David Prentice
/
Nucleo_dir_L152
Please run it on your NUCLEO-L152
MCUFRIEND_kbv/utility/mcufriend_shield.h@1:d88d2ad55fac, 2019-09-18 (annotated)
- Committer:
- davidprentice
- Date:
- Wed Sep 18 10:38:19 2019 +0000
- Revision:
- 1:d88d2ad55fac
- Parent:
- 0:b608c7f02f80
Added messages to Serial Terminal (9600 baud)
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
davidprentice | 0:b608c7f02f80 | 1 | //#define USE_SPECIAL //check for custom drivers |
davidprentice | 0:b608c7f02f80 | 2 | |
davidprentice | 0:b608c7f02f80 | 3 | #define WR_ACTIVE2 {WR_ACTIVE; WR_ACTIVE;} |
davidprentice | 0:b608c7f02f80 | 4 | #define WR_ACTIVE4 {WR_ACTIVE2; WR_ACTIVE2;} |
davidprentice | 0:b608c7f02f80 | 5 | #define WR_ACTIVE8 {WR_ACTIVE4; WR_ACTIVE4;} |
davidprentice | 0:b608c7f02f80 | 6 | #define RD_ACTIVE2 {RD_ACTIVE; RD_ACTIVE;} |
davidprentice | 0:b608c7f02f80 | 7 | #define RD_ACTIVE4 {RD_ACTIVE2; RD_ACTIVE2;} |
davidprentice | 0:b608c7f02f80 | 8 | #define RD_ACTIVE8 {RD_ACTIVE4; RD_ACTIVE4;} |
davidprentice | 0:b608c7f02f80 | 9 | #define RD_ACTIVE16 {RD_ACTIVE8; RD_ACTIVE8;} |
davidprentice | 0:b608c7f02f80 | 10 | #define WR_IDLE2 {WR_IDLE; WR_IDLE;} |
davidprentice | 0:b608c7f02f80 | 11 | #define WR_IDLE4 {WR_IDLE2; WR_IDLE2;} |
davidprentice | 0:b608c7f02f80 | 12 | #define RD_IDLE2 {RD_IDLE; RD_IDLE;} |
davidprentice | 0:b608c7f02f80 | 13 | #define RD_IDLE4 {RD_IDLE2; RD_IDLE2;} |
davidprentice | 0:b608c7f02f80 | 14 | |
davidprentice | 0:b608c7f02f80 | 15 | #if defined(USE_SPECIAL) |
davidprentice | 0:b608c7f02f80 | 16 | #include "mcufriend_special.h" |
davidprentice | 0:b608c7f02f80 | 17 | #if !defined(USE_SPECIAL_FAIL) |
davidprentice | 0:b608c7f02f80 | 18 | #warning WE ARE USING A SPECIAL CUSTOM DRIVER |
davidprentice | 0:b608c7f02f80 | 19 | #endif |
davidprentice | 0:b608c7f02f80 | 20 | #endif |
davidprentice | 0:b608c7f02f80 | 21 | #if !defined(USE_SPECIAL) || defined (USE_SPECIAL_FAIL) |
davidprentice | 0:b608c7f02f80 | 22 | |
davidprentice | 0:b608c7f02f80 | 23 | #if 0 |
davidprentice | 0:b608c7f02f80 | 24 | //################################### UNO ############################## |
davidprentice | 0:b608c7f02f80 | 25 | #elif defined(__AVR_ATmega328P__) || defined(__AVR_ATmega328PB__) //regular UNO shield on UNO |
davidprentice | 0:b608c7f02f80 | 26 | #define RD_PORT PORTC |
davidprentice | 0:b608c7f02f80 | 27 | #define RD_PIN 0 |
davidprentice | 0:b608c7f02f80 | 28 | #define WR_PORT PORTC |
davidprentice | 0:b608c7f02f80 | 29 | #define WR_PIN 1 |
davidprentice | 0:b608c7f02f80 | 30 | #define CD_PORT PORTC |
davidprentice | 0:b608c7f02f80 | 31 | #define CD_PIN 2 |
davidprentice | 0:b608c7f02f80 | 32 | #define CS_PORT PORTC |
davidprentice | 0:b608c7f02f80 | 33 | #define CS_PIN 3 |
davidprentice | 0:b608c7f02f80 | 34 | #define RESET_PORT PORTC |
davidprentice | 0:b608c7f02f80 | 35 | #define RESET_PIN 4 |
davidprentice | 0:b608c7f02f80 | 36 | |
davidprentice | 0:b608c7f02f80 | 37 | #define BMASK 0x03 //more intuitive style for mixed Ports |
davidprentice | 0:b608c7f02f80 | 38 | #define DMASK 0xFC //does exactly the same as previous |
davidprentice | 0:b608c7f02f80 | 39 | #define write_8(x) { PORTB = (PORTB & ~BMASK) | ((x) & BMASK); PORTD = (PORTD & ~DMASK) | ((x) & DMASK); } |
davidprentice | 0:b608c7f02f80 | 40 | #define read_8() ( (PINB & BMASK) | (PIND & DMASK) ) |
davidprentice | 0:b608c7f02f80 | 41 | #define setWriteDir() { DDRB |= BMASK; DDRD |= DMASK; } |
davidprentice | 0:b608c7f02f80 | 42 | #define setReadDir() { DDRB &= ~BMASK; DDRD &= ~DMASK; } |
davidprentice | 0:b608c7f02f80 | 43 | #define write8(x) { write_8(x); WR_STROBE; } |
davidprentice | 0:b608c7f02f80 | 44 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
davidprentice | 0:b608c7f02f80 | 45 | #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; } |
davidprentice | 0:b608c7f02f80 | 46 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
davidprentice | 0:b608c7f02f80 | 47 | |
davidprentice | 0:b608c7f02f80 | 48 | #define PIN_LOW(p, b) (p) &= ~(1<<(b)) |
davidprentice | 0:b608c7f02f80 | 49 | #define PIN_HIGH(p, b) (p) |= (1<<(b)) |
davidprentice | 0:b608c7f02f80 | 50 | #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b)) |
davidprentice | 0:b608c7f02f80 | 51 | |
davidprentice | 0:b608c7f02f80 | 52 | //################################### MEGA2560 ############################## |
davidprentice | 0:b608c7f02f80 | 53 | #elif defined(__AVR_ATmega2560__) || defined(__AVR_ATmega1280__) //regular UNO shield on MEGA2560 |
davidprentice | 0:b608c7f02f80 | 54 | #define RD_PORT PORTF |
davidprentice | 0:b608c7f02f80 | 55 | #define RD_PIN 0 |
davidprentice | 0:b608c7f02f80 | 56 | #define WR_PORT PORTF |
davidprentice | 0:b608c7f02f80 | 57 | #define WR_PIN 1 |
davidprentice | 0:b608c7f02f80 | 58 | #define CD_PORT PORTF |
davidprentice | 0:b608c7f02f80 | 59 | #define CD_PIN 2 |
davidprentice | 0:b608c7f02f80 | 60 | #define CS_PORT PORTF |
davidprentice | 0:b608c7f02f80 | 61 | #define CS_PIN 3 |
davidprentice | 0:b608c7f02f80 | 62 | #define RESET_PORT PORTF |
davidprentice | 0:b608c7f02f80 | 63 | #define RESET_PIN 4 |
davidprentice | 0:b608c7f02f80 | 64 | |
davidprentice | 0:b608c7f02f80 | 65 | #define EMASK 0x38 |
davidprentice | 0:b608c7f02f80 | 66 | #define GMASK 0x20 |
davidprentice | 0:b608c7f02f80 | 67 | #define HMASK 0x78 |
davidprentice | 0:b608c7f02f80 | 68 | #define write_8(x) { PORTH &= ~HMASK; PORTG &= ~GMASK; PORTE &= ~EMASK; \ |
davidprentice | 0:b608c7f02f80 | 69 | PORTH |= (((x) & (3<<0)) << 5); \ |
davidprentice | 0:b608c7f02f80 | 70 | PORTE |= (((x) & (3<<2)) << 2); \ |
davidprentice | 0:b608c7f02f80 | 71 | PORTG |= (((x) & (1<<4)) << 1); \ |
davidprentice | 0:b608c7f02f80 | 72 | PORTE |= (((x) & (1<<5)) >> 2); \ |
davidprentice | 0:b608c7f02f80 | 73 | PORTH |= (((x) & (3<<6)) >> 3); \ |
davidprentice | 0:b608c7f02f80 | 74 | } |
davidprentice | 0:b608c7f02f80 | 75 | |
davidprentice | 0:b608c7f02f80 | 76 | #define read_8() ( ((PINH & (3<<5)) >> 5)\ |
davidprentice | 0:b608c7f02f80 | 77 | | ((PINE & (3<<4)) >> 2)\ |
davidprentice | 0:b608c7f02f80 | 78 | | ((PING & (1<<5)) >> 1)\ |
davidprentice | 0:b608c7f02f80 | 79 | | ((PINE & (1<<3)) << 2)\ |
davidprentice | 0:b608c7f02f80 | 80 | | ((PINH & (3<<3)) << 3)\ |
davidprentice | 0:b608c7f02f80 | 81 | ) |
davidprentice | 0:b608c7f02f80 | 82 | #define setWriteDir() { DDRH |= HMASK; DDRG |= GMASK; DDRE |= EMASK; } |
davidprentice | 0:b608c7f02f80 | 83 | #define setReadDir() { DDRH &= ~HMASK; DDRG &= ~GMASK; DDRE &= ~EMASK; } |
davidprentice | 0:b608c7f02f80 | 84 | #define write8(x) { write_8(x); WR_STROBE; } |
davidprentice | 0:b608c7f02f80 | 85 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
davidprentice | 0:b608c7f02f80 | 86 | #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; } |
davidprentice | 0:b608c7f02f80 | 87 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
davidprentice | 0:b608c7f02f80 | 88 | |
davidprentice | 0:b608c7f02f80 | 89 | #define PIN_LOW(p, b) (p) &= ~(1<<(b)) |
davidprentice | 0:b608c7f02f80 | 90 | #define PIN_HIGH(p, b) (p) |= (1<<(b)) |
davidprentice | 0:b608c7f02f80 | 91 | #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b)) |
davidprentice | 0:b608c7f02f80 | 92 | |
davidprentice | 0:b608c7f02f80 | 93 | //################################### MEGA4809 NANO_EVERY 4808 ############################## |
davidprentice | 0:b608c7f02f80 | 94 | #elif defined(__AVR_ATmega4808__) // Thinary EVERY-4808 with Nano-Shield_Adapter |
davidprentice | 0:b608c7f02f80 | 95 | #warning EVERY-4808 with Nano-Shield_Adapter |
davidprentice | 0:b608c7f02f80 | 96 | #define RD_PORT VPORTD // |
davidprentice | 0:b608c7f02f80 | 97 | #define RD_PIN 0 |
davidprentice | 0:b608c7f02f80 | 98 | #define WR_PORT VPORTD |
davidprentice | 0:b608c7f02f80 | 99 | #define WR_PIN 1 |
davidprentice | 0:b608c7f02f80 | 100 | #define CD_PORT VPORTD |
davidprentice | 0:b608c7f02f80 | 101 | #define CD_PIN 2 |
davidprentice | 0:b608c7f02f80 | 102 | #define CS_PORT VPORTD |
davidprentice | 0:b608c7f02f80 | 103 | #define CS_PIN 3 |
davidprentice | 0:b608c7f02f80 | 104 | #define RESET_PORT VPORTF |
davidprentice | 0:b608c7f02f80 | 105 | #define RESET_PIN 2 |
davidprentice | 0:b608c7f02f80 | 106 | |
davidprentice | 0:b608c7f02f80 | 107 | #define AMASK 0xFF |
davidprentice | 0:b608c7f02f80 | 108 | #define write_8(x) { VPORTA.OUT = ((x) << 6) | ((x) >> 2); } |
davidprentice | 0:b608c7f02f80 | 109 | #define read_8() ( (VPORTA.IN >> 6) | (VPORTA.IN << 2) ) |
davidprentice | 0:b608c7f02f80 | 110 | #define setWriteDir() { VPORTA_DIR |= AMASK; } |
davidprentice | 0:b608c7f02f80 | 111 | #define setReadDir() { VPORTA_DIR &= ~AMASK; } |
davidprentice | 0:b608c7f02f80 | 112 | |
davidprentice | 0:b608c7f02f80 | 113 | //#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; } //6.47s no_inline |
davidprentice | 0:b608c7f02f80 | 114 | #define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //-Os=5.43s @20MHz always_inline. (-O1=5.41s, -O3=5.25s) |
davidprentice | 0:b608c7f02f80 | 115 | #define READ_DELAY { RD_ACTIVE4; } //ID=0x7789 |
davidprentice | 0:b608c7f02f80 | 116 | #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; } |
davidprentice | 0:b608c7f02f80 | 117 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
davidprentice | 0:b608c7f02f80 | 118 | #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } |
davidprentice | 0:b608c7f02f80 | 119 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
davidprentice | 0:b608c7f02f80 | 120 | |
davidprentice | 0:b608c7f02f80 | 121 | #define PIN_LOW(p, b) (p).OUT &= ~(1<<(b)) |
davidprentice | 0:b608c7f02f80 | 122 | #define PIN_HIGH(p, b) (p).OUT |= (1<<(b)) |
davidprentice | 0:b608c7f02f80 | 123 | #define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b)) |
davidprentice | 0:b608c7f02f80 | 124 | |
davidprentice | 0:b608c7f02f80 | 125 | //################################### MEGA4809 NANO_EVERY ############################## |
davidprentice | 0:b608c7f02f80 | 126 | #elif defined(__AVR_ATmega4809__) && defined(ARDUINO_AVR_NANO_EVERY) // EVERY-4809 with Nano-Shield_Adapter |
davidprentice | 0:b608c7f02f80 | 127 | #warning EVERY-4809 with Nano-Shield_Adapter using VPORT.OUT and BLD/BST |
davidprentice | 0:b608c7f02f80 | 128 | #define RD_PORT VPORTD // |
davidprentice | 0:b608c7f02f80 | 129 | #define RD_PIN 3 |
davidprentice | 0:b608c7f02f80 | 130 | #define WR_PORT VPORTD |
davidprentice | 0:b608c7f02f80 | 131 | #define WR_PIN 2 |
davidprentice | 0:b608c7f02f80 | 132 | #define CD_PORT VPORTD |
davidprentice | 0:b608c7f02f80 | 133 | #define CD_PIN 1 |
davidprentice | 0:b608c7f02f80 | 134 | #define CS_PORT VPORTD |
davidprentice | 0:b608c7f02f80 | 135 | #define CS_PIN 0 |
davidprentice | 0:b608c7f02f80 | 136 | #define RESET_PORT VPORTF |
davidprentice | 0:b608c7f02f80 | 137 | #define RESET_PIN 2 |
davidprentice | 0:b608c7f02f80 | 138 | |
davidprentice | 0:b608c7f02f80 | 139 | #define AMASK (3<<0) |
davidprentice | 0:b608c7f02f80 | 140 | #define BMASK (5<<0) |
davidprentice | 0:b608c7f02f80 | 141 | #define CMASK (1<<6) |
davidprentice | 0:b608c7f02f80 | 142 | #define EMASK (1<<3) |
davidprentice | 0:b608c7f02f80 | 143 | #define FMASK (3<<4) |
davidprentice | 0:b608c7f02f80 | 144 | static __attribute((always_inline)) |
davidprentice | 0:b608c7f02f80 | 145 | void write_8(uint8_t val) |
davidprentice | 0:b608c7f02f80 | 146 | { |
davidprentice | 0:b608c7f02f80 | 147 | asm volatile("in __tmp_reg__,0x01" "\n\t" //VPORTA.OUT |
davidprentice | 0:b608c7f02f80 | 148 | "BST %0,2" "\n\t" "BLD __tmp_reg__,0" "\n\t" |
davidprentice | 0:b608c7f02f80 | 149 | "BST %0,7" "\n\t" "BLD __tmp_reg__,1" "\n\t" |
davidprentice | 0:b608c7f02f80 | 150 | "out 0x01,__tmp_reg__" : : "a" (val)); |
davidprentice | 0:b608c7f02f80 | 151 | asm volatile("in __tmp_reg__,0x05" "\n\t" //VPORTB.OUT |
davidprentice | 0:b608c7f02f80 | 152 | "BST %0,1" "\n\t" "BLD __tmp_reg__,0" "\n\t" |
davidprentice | 0:b608c7f02f80 | 153 | "BST %0,5" "\n\t" "BLD __tmp_reg__,2" "\n\t" |
davidprentice | 0:b608c7f02f80 | 154 | "out 0x05,__tmp_reg__" : : "a" (val)); |
davidprentice | 0:b608c7f02f80 | 155 | asm volatile("in __tmp_reg__,0x09" "\n\t" //VPORTC.OUT |
davidprentice | 0:b608c7f02f80 | 156 | "BST %0,4" "\n\t" "BLD __tmp_reg__,6" "\n\t" |
davidprentice | 0:b608c7f02f80 | 157 | "out 0x09,__tmp_reg__" : : "a" (val)); |
davidprentice | 0:b608c7f02f80 | 158 | asm volatile("in __tmp_reg__,0x11" "\n\t" //VPORTE.OUT |
davidprentice | 0:b608c7f02f80 | 159 | "BST %0,0" "\n\t" "BLD __tmp_reg__,3" "\n\t" |
davidprentice | 0:b608c7f02f80 | 160 | "out 0x11,__tmp_reg__" : : "a" (val)); |
davidprentice | 0:b608c7f02f80 | 161 | asm volatile("in __tmp_reg__,0x15" "\n\t" //VPORTF.OUT |
davidprentice | 0:b608c7f02f80 | 162 | "BST %0,3" "\n\t" "BLD __tmp_reg__,5" "\n\t" |
davidprentice | 0:b608c7f02f80 | 163 | "BST %0,6" "\n\t" "BLD __tmp_reg__,4" "\n\t" |
davidprentice | 0:b608c7f02f80 | 164 | "out 0x15,__tmp_reg__" : : "a" (val)); |
davidprentice | 0:b608c7f02f80 | 165 | } |
davidprentice | 0:b608c7f02f80 | 166 | |
davidprentice | 0:b608c7f02f80 | 167 | #define read_8() ( 0 \ |
davidprentice | 0:b608c7f02f80 | 168 | | ((VPORTA_IN & (1<<0)) << 2)\ |
davidprentice | 0:b608c7f02f80 | 169 | | ((VPORTA_IN & (1<<1)) << 6)\ |
davidprentice | 0:b608c7f02f80 | 170 | | ((VPORTB_IN & (1<<0)) << 1)\ |
davidprentice | 0:b608c7f02f80 | 171 | | ((VPORTB_IN & (1<<2)) << 3)\ |
davidprentice | 0:b608c7f02f80 | 172 | | ((VPORTC_IN & CMASK) >> 2)\ |
davidprentice | 0:b608c7f02f80 | 173 | | ((VPORTE_IN & EMASK) >> 3)\ |
davidprentice | 0:b608c7f02f80 | 174 | | ((VPORTF_IN & (1<<5)) >> 2)\ |
davidprentice | 0:b608c7f02f80 | 175 | | ((VPORTF_IN & (1<<4)) << 2)\ |
davidprentice | 0:b608c7f02f80 | 176 | ) |
davidprentice | 0:b608c7f02f80 | 177 | #define setWriteDir() { VPORTA_DIR |= AMASK; VPORTB_DIR |= BMASK; VPORTC_DIR |= CMASK; VPORTE_DIR |= EMASK; VPORTF_DIR |= FMASK; } |
davidprentice | 0:b608c7f02f80 | 178 | #define setReadDir() { VPORTA_DIR &= ~AMASK; VPORTB_DIR &= ~BMASK; VPORTC_DIR &= ~CMASK; VPORTE_DIR &= ~EMASK; VPORTF_DIR &= ~FMASK; } |
davidprentice | 0:b608c7f02f80 | 179 | |
davidprentice | 0:b608c7f02f80 | 180 | //#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; } //6.47s no_inline |
davidprentice | 0:b608c7f02f80 | 181 | #define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //-Os=5.43s @20MHz always_inline. (-O1=5.41s, -O3=5.25s) |
davidprentice | 0:b608c7f02f80 | 182 | #define READ_DELAY { RD_ACTIVE4; } //ID=0x7789 |
davidprentice | 0:b608c7f02f80 | 183 | #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; } |
davidprentice | 0:b608c7f02f80 | 184 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
davidprentice | 0:b608c7f02f80 | 185 | #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } |
davidprentice | 0:b608c7f02f80 | 186 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
davidprentice | 0:b608c7f02f80 | 187 | |
davidprentice | 0:b608c7f02f80 | 188 | #define PIN_LOW(p, b) (p).OUT &= ~(1<<(b)) |
davidprentice | 0:b608c7f02f80 | 189 | #define PIN_HIGH(p, b) (p).OUT |= (1<<(b)) |
davidprentice | 0:b608c7f02f80 | 190 | #define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b)) |
davidprentice | 0:b608c7f02f80 | 191 | |
davidprentice | 0:b608c7f02f80 | 192 | //################################### TEENSY++2.0 ############################## |
davidprentice | 0:b608c7f02f80 | 193 | #elif defined(__AVR_AT90USB1286__) //regular UNO shield on TEENSY++ 2.0 thanks tysonlt |
davidprentice | 0:b608c7f02f80 | 194 | |
davidprentice | 0:b608c7f02f80 | 195 | //LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST| |
davidprentice | 0:b608c7f02f80 | 196 | //AVR pin |PD7|PD6|PD5|PD4|PD3|PD2|PE1|PE0| |PF0|PF1|PF2|PF3|PF4| |
davidprentice | 0:b608c7f02f80 | 197 | |
davidprentice | 0:b608c7f02f80 | 198 | #define RD_PORT PORTF |
davidprentice | 0:b608c7f02f80 | 199 | #define RD_PIN 0 |
davidprentice | 0:b608c7f02f80 | 200 | #define WR_PORT PORTF |
davidprentice | 0:b608c7f02f80 | 201 | #define WR_PIN 1 |
davidprentice | 0:b608c7f02f80 | 202 | #define CD_PORT PORTF |
davidprentice | 0:b608c7f02f80 | 203 | #define CD_PIN 2 |
davidprentice | 0:b608c7f02f80 | 204 | #define CS_PORT PORTF |
davidprentice | 0:b608c7f02f80 | 205 | #define CS_PIN 3 |
davidprentice | 0:b608c7f02f80 | 206 | #define RESET_PORT PORTF |
davidprentice | 0:b608c7f02f80 | 207 | #define RESET_PIN 4 |
davidprentice | 0:b608c7f02f80 | 208 | |
davidprentice | 0:b608c7f02f80 | 209 | #define EMASK 0x03 //more intuitive style for mixed Ports |
davidprentice | 0:b608c7f02f80 | 210 | #define DMASK 0xFC //does exactly the same as previous |
davidprentice | 0:b608c7f02f80 | 211 | #define write_8(x) { PORTE = (PORTE & ~EMASK) | ((x) & EMASK); PORTD = (PORTD & ~DMASK) | ((x) & DMASK); } |
davidprentice | 0:b608c7f02f80 | 212 | #define read_8() ( (PINE & EMASK) | (PIND & DMASK) ) |
davidprentice | 0:b608c7f02f80 | 213 | #define setWriteDir() { DDRE |= EMASK; DDRD |= DMASK; } |
davidprentice | 0:b608c7f02f80 | 214 | #define setReadDir() { DDRE &= ~EMASK; DDRD &= ~DMASK; } |
davidprentice | 0:b608c7f02f80 | 215 | #define write8(x) { write_8(x); WR_STROBE; } |
davidprentice | 0:b608c7f02f80 | 216 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
davidprentice | 0:b608c7f02f80 | 217 | #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; } |
davidprentice | 0:b608c7f02f80 | 218 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
davidprentice | 0:b608c7f02f80 | 219 | |
davidprentice | 0:b608c7f02f80 | 220 | #define PIN_LOW(p, b) (p) &= ~(1<<(b)) |
davidprentice | 0:b608c7f02f80 | 221 | #define PIN_HIGH(p, b) (p) |= (1<<(b)) |
davidprentice | 0:b608c7f02f80 | 222 | #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b)) |
davidprentice | 0:b608c7f02f80 | 223 | |
davidprentice | 0:b608c7f02f80 | 224 | //################################# ZERO and M0_PRO ############################ |
davidprentice | 0:b608c7f02f80 | 225 | #elif defined(__SAMD21G18A__) //regular UNO shield on ZERO or M0_PRO |
davidprentice | 0:b608c7f02f80 | 226 | #include "sam.h" |
davidprentice | 0:b608c7f02f80 | 227 | // configure macros for the control pins |
davidprentice | 0:b608c7f02f80 | 228 | #define RD_PORT PORT->Group[0] |
davidprentice | 0:b608c7f02f80 | 229 | #define RD_PIN 2 |
davidprentice | 0:b608c7f02f80 | 230 | #define WR_PORT PORT->Group[1] |
davidprentice | 0:b608c7f02f80 | 231 | #define WR_PIN 8 |
davidprentice | 0:b608c7f02f80 | 232 | #define CD_PORT PORT->Group[1] |
davidprentice | 0:b608c7f02f80 | 233 | #define CD_PIN 9 |
davidprentice | 0:b608c7f02f80 | 234 | #define CS_PORT PORT->Group[0] |
davidprentice | 0:b608c7f02f80 | 235 | #define CS_PIN 4 |
davidprentice | 0:b608c7f02f80 | 236 | #define RESET_PORT PORT->Group[0] |
davidprentice | 0:b608c7f02f80 | 237 | #define RESET_PIN 5 |
davidprentice | 0:b608c7f02f80 | 238 | // configure macros for data bus |
davidprentice | 0:b608c7f02f80 | 239 | #define DMASK 0x0030C3C0 |
davidprentice | 0:b608c7f02f80 | 240 | // #define write_8(x) PORT->Group[0].OUT.reg = (PORT->Group[0].OUT.reg & ~DMASK)|(((x) & 0x0F) << 6)|(((x) & 0x30) << 10)|(((x) & 0xC0)<<14) |
davidprentice | 0:b608c7f02f80 | 241 | #if defined(ARDUINO_SAMD_ZERO) || defined(ARDUINO_SAMD_ZERO) // American ZERO |
davidprentice | 0:b608c7f02f80 | 242 | #define write_8(x) {\ |
davidprentice | 0:b608c7f02f80 | 243 | PORT->Group[0].OUTCLR.reg = DMASK;\ |
davidprentice | 0:b608c7f02f80 | 244 | PORT->Group[0].OUTSET.reg = (((x) & 0x0B) << 6)\ |
davidprentice | 0:b608c7f02f80 | 245 | |(((x) & (1<<2)) << 12)\ |
davidprentice | 0:b608c7f02f80 | 246 | |(((x) & (1<<4)) << 4)\ |
davidprentice | 0:b608c7f02f80 | 247 | |(((x) & (1<<5)) << 10)\ |
davidprentice | 0:b608c7f02f80 | 248 | |(((x) & 0xC0) << 14);\ |
davidprentice | 0:b608c7f02f80 | 249 | } |
davidprentice | 0:b608c7f02f80 | 250 | #define read_8() (((PORT->Group[0].IN.reg >> 6) & 0x0B)\ |
davidprentice | 0:b608c7f02f80 | 251 | |((PORT->Group[0].IN.reg >> 12) & (1<<2))\ |
davidprentice | 0:b608c7f02f80 | 252 | |((PORT->Group[0].IN.reg >> 4) & (1<<4))\ |
davidprentice | 0:b608c7f02f80 | 253 | |((PORT->Group[0].IN.reg >> 10) & (1<<5))\ |
davidprentice | 0:b608c7f02f80 | 254 | |((PORT->Group[0].IN.reg >> 14) & 0xC0)) |
davidprentice | 0:b608c7f02f80 | 255 | #else //default to an M0_PRO on v1.6.5 or 1.7.6 |
davidprentice | 0:b608c7f02f80 | 256 | #define write_8(x) {\ |
davidprentice | 0:b608c7f02f80 | 257 | PORT->Group[0].OUTCLR.reg = DMASK;\ |
davidprentice | 0:b608c7f02f80 | 258 | PORT->Group[0].OUTSET.reg = (((x) & 0x0F) << 6)\ |
davidprentice | 0:b608c7f02f80 | 259 | |(((x) & 0x30) << 10)\ |
davidprentice | 0:b608c7f02f80 | 260 | |(((x) & 0xC0) << 14);\ |
davidprentice | 0:b608c7f02f80 | 261 | } |
davidprentice | 0:b608c7f02f80 | 262 | #define read_8() (((PORT->Group[0].IN.reg >> 6) & 0x0F)|((PORT->Group[0].IN.reg >> 10) & 0x30)|((PORT->Group[0].IN.reg >> 14) & 0xC0)) |
davidprentice | 0:b608c7f02f80 | 263 | #endif |
davidprentice | 0:b608c7f02f80 | 264 | #define setWriteDir() { PORT->Group[0].DIRSET.reg = DMASK; \ |
davidprentice | 0:b608c7f02f80 | 265 | PORT->Group[0].WRCONFIG.reg = (DMASK & 0xFFFF) | (0<<22) | (1<<28) | (1<<30); \ |
davidprentice | 0:b608c7f02f80 | 266 | PORT->Group[0].WRCONFIG.reg = (DMASK>>16) | (0<<22) | (1<<28) | (1<<30) | (1<<31); \ |
davidprentice | 0:b608c7f02f80 | 267 | } |
davidprentice | 0:b608c7f02f80 | 268 | #define setReadDir() { PORT->Group[0].DIRCLR.reg = DMASK; \ |
davidprentice | 0:b608c7f02f80 | 269 | PORT->Group[0].WRCONFIG.reg = (DMASK & 0xFFFF) | (1<<17) | (1<<28) | (1<<30); \ |
davidprentice | 0:b608c7f02f80 | 270 | PORT->Group[0].WRCONFIG.reg = (DMASK>>16) | (1<<17) | (1<<28) | (1<<30) | (1<<31); \ |
davidprentice | 0:b608c7f02f80 | 271 | } |
davidprentice | 0:b608c7f02f80 | 272 | #define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; } |
davidprentice | 0:b608c7f02f80 | 273 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
davidprentice | 0:b608c7f02f80 | 274 | #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; } |
davidprentice | 0:b608c7f02f80 | 275 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
davidprentice | 0:b608c7f02f80 | 276 | // Shield Control macros. |
davidprentice | 0:b608c7f02f80 | 277 | #define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin)) |
davidprentice | 0:b608c7f02f80 | 278 | #define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin)) |
davidprentice | 0:b608c7f02f80 | 279 | #define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin)) |
davidprentice | 0:b608c7f02f80 | 280 | |
davidprentice | 0:b608c7f02f80 | 281 | //####################################### DUE ############################ |
davidprentice | 0:b608c7f02f80 | 282 | #elif defined(__SAM3X8E__) //regular UNO shield on DUE |
davidprentice | 0:b608c7f02f80 | 283 | #define WRITE_DELAY { WR_ACTIVE; } |
davidprentice | 0:b608c7f02f80 | 284 | #define IDLE_DELAY { WR_IDLE; } |
davidprentice | 0:b608c7f02f80 | 285 | #define READ_DELAY { RD_ACTIVE;} |
davidprentice | 0:b608c7f02f80 | 286 | // configure macros for the control pins |
davidprentice | 0:b608c7f02f80 | 287 | #define RD_PORT PIOA |
davidprentice | 0:b608c7f02f80 | 288 | #define RD_PIN 16 |
davidprentice | 0:b608c7f02f80 | 289 | #define WR_PORT PIOA |
davidprentice | 0:b608c7f02f80 | 290 | #define WR_PIN 24 |
davidprentice | 0:b608c7f02f80 | 291 | #define CD_PORT PIOA |
davidprentice | 0:b608c7f02f80 | 292 | #define CD_PIN 23 |
davidprentice | 0:b608c7f02f80 | 293 | #define CS_PORT PIOA |
davidprentice | 0:b608c7f02f80 | 294 | #define CS_PIN 22 |
davidprentice | 0:b608c7f02f80 | 295 | #define RESET_PORT PIOA |
davidprentice | 0:b608c7f02f80 | 296 | #define RESET_PIN 6 |
davidprentice | 0:b608c7f02f80 | 297 | // configure macros for data bus |
davidprentice | 0:b608c7f02f80 | 298 | #define BMASK (1<<25) |
davidprentice | 0:b608c7f02f80 | 299 | #define CMASK (0xBF << 21) |
davidprentice | 0:b608c7f02f80 | 300 | #define write_8(x) { PIOB->PIO_CODR = BMASK; PIOC->PIO_CODR = CMASK; \ |
davidprentice | 0:b608c7f02f80 | 301 | PIOB->PIO_SODR = (((x) & (1<<2)) << 23); \ |
davidprentice | 0:b608c7f02f80 | 302 | PIOC->PIO_SODR = (((x) & (1<<0)) << 22) \ |
davidprentice | 0:b608c7f02f80 | 303 | | (((x) & (1<<1)) << 20) \ |
davidprentice | 0:b608c7f02f80 | 304 | | (((x) & (1<<3)) << 25) \ |
davidprentice | 0:b608c7f02f80 | 305 | | (((x) & (1<<4)) << 22) \ |
davidprentice | 0:b608c7f02f80 | 306 | | (((x) & (1<<5)) << 20) \ |
davidprentice | 0:b608c7f02f80 | 307 | | (((x) & (1<<6)) << 18) \ |
davidprentice | 0:b608c7f02f80 | 308 | | (((x) & (1<<7)) << 16); \ |
davidprentice | 0:b608c7f02f80 | 309 | } |
davidprentice | 0:b608c7f02f80 | 310 | |
davidprentice | 0:b608c7f02f80 | 311 | #define read_8() ( ((PIOC->PIO_PDSR & (1<<22)) >> 22)\ |
davidprentice | 0:b608c7f02f80 | 312 | | ((PIOC->PIO_PDSR & (1<<21)) >> 20)\ |
davidprentice | 0:b608c7f02f80 | 313 | | ((PIOB->PIO_PDSR & (1<<25)) >> 23)\ |
davidprentice | 0:b608c7f02f80 | 314 | | ((PIOC->PIO_PDSR & (1<<28)) >> 25)\ |
davidprentice | 0:b608c7f02f80 | 315 | | ((PIOC->PIO_PDSR & (1<<26)) >> 22)\ |
davidprentice | 0:b608c7f02f80 | 316 | | ((PIOC->PIO_PDSR & (1<<25)) >> 20)\ |
davidprentice | 0:b608c7f02f80 | 317 | | ((PIOC->PIO_PDSR & (1<<24)) >> 18)\ |
davidprentice | 0:b608c7f02f80 | 318 | | ((PIOC->PIO_PDSR & (1<<23)) >> 16)\ |
davidprentice | 0:b608c7f02f80 | 319 | ) |
davidprentice | 0:b608c7f02f80 | 320 | #define setWriteDir() { PIOB->PIO_OER = BMASK; PIOC->PIO_OER = CMASK; } |
davidprentice | 0:b608c7f02f80 | 321 | #define setReadDir() { \ |
davidprentice | 0:b608c7f02f80 | 322 | PMC->PMC_PCER0 = (1 << ID_PIOB)|(1 << ID_PIOC);\ |
davidprentice | 0:b608c7f02f80 | 323 | PIOB->PIO_ODR = BMASK; PIOC->PIO_ODR = CMASK;\ |
davidprentice | 0:b608c7f02f80 | 324 | } |
davidprentice | 0:b608c7f02f80 | 325 | #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; IDLE_DELAY; } |
davidprentice | 0:b608c7f02f80 | 326 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
davidprentice | 0:b608c7f02f80 | 327 | #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; RD_IDLE; } |
davidprentice | 0:b608c7f02f80 | 328 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
davidprentice | 0:b608c7f02f80 | 329 | |
davidprentice | 0:b608c7f02f80 | 330 | // Shield Control macros. |
davidprentice | 0:b608c7f02f80 | 331 | #define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin)) |
davidprentice | 0:b608c7f02f80 | 332 | #define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin)) |
davidprentice | 0:b608c7f02f80 | 333 | #define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin)) |
davidprentice | 0:b608c7f02f80 | 334 | |
davidprentice | 0:b608c7f02f80 | 335 | //################################### LEONARDO ############################## |
davidprentice | 0:b608c7f02f80 | 336 | #elif defined(__AVR_ATmega32U4__) //regular UNO shield on Leonardo |
davidprentice | 0:b608c7f02f80 | 337 | #define RD_PORT PORTF |
davidprentice | 0:b608c7f02f80 | 338 | #define RD_PIN 7 |
davidprentice | 0:b608c7f02f80 | 339 | #define WR_PORT PORTF |
davidprentice | 0:b608c7f02f80 | 340 | #define WR_PIN 6 |
davidprentice | 0:b608c7f02f80 | 341 | #define CD_PORT PORTF |
davidprentice | 0:b608c7f02f80 | 342 | #define CD_PIN 5 |
davidprentice | 0:b608c7f02f80 | 343 | #define CS_PORT PORTF |
davidprentice | 0:b608c7f02f80 | 344 | #define CS_PIN 4 |
davidprentice | 0:b608c7f02f80 | 345 | #define RESET_PORT PORTF |
davidprentice | 0:b608c7f02f80 | 346 | #define RESET_PIN 1 |
davidprentice | 0:b608c7f02f80 | 347 | |
davidprentice | 0:b608c7f02f80 | 348 | #define BMASK (3<<4) |
davidprentice | 0:b608c7f02f80 | 349 | #define CMASK (1<<6) |
davidprentice | 0:b608c7f02f80 | 350 | #define DMASK ((1<<7)|(1<<4)|(3<<0)) |
davidprentice | 0:b608c7f02f80 | 351 | #define EMASK (1<<6) |
davidprentice | 0:b608c7f02f80 | 352 | static inline //hope we use r24 |
davidprentice | 0:b608c7f02f80 | 353 | void write_8(uint8_t x) |
davidprentice | 0:b608c7f02f80 | 354 | { |
davidprentice | 0:b608c7f02f80 | 355 | PORTB &= ~BMASK; |
davidprentice | 0:b608c7f02f80 | 356 | PORTC &= ~CMASK; |
davidprentice | 0:b608c7f02f80 | 357 | PORTD &= ~DMASK; |
davidprentice | 0:b608c7f02f80 | 358 | PORTE &= ~EMASK; |
davidprentice | 0:b608c7f02f80 | 359 | PORTB |= (((x) & (3 << 0)) << 4); |
davidprentice | 0:b608c7f02f80 | 360 | PORTD |= (((x) & (1 << 2)) >> 1); |
davidprentice | 0:b608c7f02f80 | 361 | PORTD |= (((x) & (1 << 3)) >> 3); |
davidprentice | 0:b608c7f02f80 | 362 | PORTD |= (((x) & (1 << 4)) << 0); |
davidprentice | 0:b608c7f02f80 | 363 | PORTC |= (((x) & (1 << 5)) << 1); |
davidprentice | 0:b608c7f02f80 | 364 | PORTD |= (((x) & (1 << 6)) << 1); |
davidprentice | 0:b608c7f02f80 | 365 | PORTE |= (((x) & (1 << 7)) >> 1); |
davidprentice | 0:b608c7f02f80 | 366 | } |
davidprentice | 0:b608c7f02f80 | 367 | |
davidprentice | 0:b608c7f02f80 | 368 | #define read_8() ( ((PINB & (3<<4)) >> 4)\ |
davidprentice | 0:b608c7f02f80 | 369 | | ((PIND & (1<<1)) << 1)\ |
davidprentice | 0:b608c7f02f80 | 370 | | ((PIND & (1<<0)) << 3)\ |
davidprentice | 0:b608c7f02f80 | 371 | | ((PIND & (1<<4)) >> 0)\ |
davidprentice | 0:b608c7f02f80 | 372 | | ((PINC & (1<<6)) >> 1)\ |
davidprentice | 0:b608c7f02f80 | 373 | | ((PIND & (1<<7)) >> 1)\ |
davidprentice | 0:b608c7f02f80 | 374 | | ((PINE & (1<<6)) << 1)\ |
davidprentice | 0:b608c7f02f80 | 375 | ) |
davidprentice | 0:b608c7f02f80 | 376 | #define setWriteDir() { DDRB |= BMASK; DDRC |= CMASK; DDRD |= DMASK; DDRE |= EMASK; } |
davidprentice | 0:b608c7f02f80 | 377 | #define setReadDir() { DDRB &= ~BMASK; DDRC &= ~CMASK; DDRD &= ~DMASK; DDRE &= ~EMASK; } |
davidprentice | 0:b608c7f02f80 | 378 | #define write8(x) { write_8(x); WR_STROBE; } |
davidprentice | 0:b608c7f02f80 | 379 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
davidprentice | 0:b608c7f02f80 | 380 | #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; } |
davidprentice | 0:b608c7f02f80 | 381 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
davidprentice | 0:b608c7f02f80 | 382 | |
davidprentice | 0:b608c7f02f80 | 383 | #define PIN_LOW(p, b) (p) &= ~(1<<(b)) |
davidprentice | 0:b608c7f02f80 | 384 | #define PIN_HIGH(p, b) (p) |= (1<<(b)) |
davidprentice | 0:b608c7f02f80 | 385 | #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b)) |
davidprentice | 0:b608c7f02f80 | 386 | |
davidprentice | 0:b608c7f02f80 | 387 | //################################### UNO SHIELD on BOBUINO ############################## |
davidprentice | 0:b608c7f02f80 | 388 | #elif defined(__AVR_ATmega1284P__) || defined(__AVR_ATmega644P__) //UNO shield on BOBUINO |
davidprentice | 0:b608c7f02f80 | 389 | #warning regular UNO shield on BOBUINO |
davidprentice | 0:b608c7f02f80 | 390 | |
davidprentice | 0:b608c7f02f80 | 391 | //LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST| |
davidprentice | 0:b608c7f02f80 | 392 | //AVR pin |PB3|PB2|PB1|PB0|PD3|PD2|PD6|PD5| |PA7|PA6|PA5|PA4|PA3| |
davidprentice | 0:b608c7f02f80 | 393 | |
davidprentice | 0:b608c7f02f80 | 394 | #define RD_PORT PORTA |
davidprentice | 0:b608c7f02f80 | 395 | #define RD_PIN 7 |
davidprentice | 0:b608c7f02f80 | 396 | #define WR_PORT PORTA |
davidprentice | 0:b608c7f02f80 | 397 | #define WR_PIN 6 |
davidprentice | 0:b608c7f02f80 | 398 | #define CD_PORT PORTA |
davidprentice | 0:b608c7f02f80 | 399 | #define CD_PIN 5 |
davidprentice | 0:b608c7f02f80 | 400 | #define CS_PORT PORTA |
davidprentice | 0:b608c7f02f80 | 401 | #define CS_PIN 4 |
davidprentice | 0:b608c7f02f80 | 402 | #define RESET_PORT PORTA |
davidprentice | 0:b608c7f02f80 | 403 | #define RESET_PIN 3 |
davidprentice | 0:b608c7f02f80 | 404 | |
davidprentice | 0:b608c7f02f80 | 405 | #define BMASK 0x0F // |
davidprentice | 0:b608c7f02f80 | 406 | #define DMASK 0x6C // |
davidprentice | 0:b608c7f02f80 | 407 | #define write_8(x) { PORTB = (PORTB & ~BMASK) | ((x) >> 4); \ |
davidprentice | 0:b608c7f02f80 | 408 | PORTD = (PORTD & ~DMASK) | ((x) & 0x0C) | (((x) & 0x03) << 5); } |
davidprentice | 0:b608c7f02f80 | 409 | #define read_8() ( (PINB << 4) | (PIND & 0x0C) | ((PIND & 0x60) >> 5) ) |
davidprentice | 0:b608c7f02f80 | 410 | #define setWriteDir() { DDRB |= BMASK; DDRD |= DMASK; } |
davidprentice | 0:b608c7f02f80 | 411 | #define setReadDir() { DDRB &= ~BMASK; DDRD &= ~DMASK; } |
davidprentice | 0:b608c7f02f80 | 412 | #define write8(x) { write_8(x); WR_STROBE; } |
davidprentice | 0:b608c7f02f80 | 413 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
davidprentice | 0:b608c7f02f80 | 414 | #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; } |
davidprentice | 0:b608c7f02f80 | 415 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
davidprentice | 0:b608c7f02f80 | 416 | |
davidprentice | 0:b608c7f02f80 | 417 | #define PIN_LOW(p, b) (p) &= ~(1<<(b)) |
davidprentice | 0:b608c7f02f80 | 418 | #define PIN_HIGH(p, b) (p) |= (1<<(b)) |
davidprentice | 0:b608c7f02f80 | 419 | #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b)) |
davidprentice | 0:b608c7f02f80 | 420 | |
davidprentice | 0:b608c7f02f80 | 421 | //####################################### TEENSY ############################ |
davidprentice | 0:b608c7f02f80 | 422 | #elif defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__) // regular UNO shield on a Teensy 3.x |
davidprentice | 0:b608c7f02f80 | 423 | #warning regular UNO shield on a Teensy 3.x |
davidprentice | 0:b608c7f02f80 | 424 | |
davidprentice | 0:b608c7f02f80 | 425 | //LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST| |
davidprentice | 0:b608c7f02f80 | 426 | //MK20 pin |PD2|PD4|PD7|PA13|PA12|PD2|PC3|PD3| |PD1|PC0|PB0|PB1|PB3| |
davidprentice | 0:b608c7f02f80 | 427 | |
davidprentice | 0:b608c7f02f80 | 428 | #if defined(__MK20DX128__) || defined(__MK20DX256__) // Teensy3.0 || 3.2 96MHz |
davidprentice | 0:b608c7f02f80 | 429 | #define WRITE_DELAY { WR_ACTIVE2; } |
davidprentice | 0:b608c7f02f80 | 430 | #define READ_DELAY { RD_ACTIVE8; RD_ACTIVE; } |
davidprentice | 0:b608c7f02f80 | 431 | #elif defined(__MK64FX512__) // Teensy3.5 120MHz thanks to PeteJohno |
davidprentice | 0:b608c7f02f80 | 432 | #define WRITE_DELAY { WR_ACTIVE4; } |
davidprentice | 0:b608c7f02f80 | 433 | #define READ_DELAY { RD_ACTIVE8; } |
davidprentice | 0:b608c7f02f80 | 434 | #elif defined(__MK66FX1M0__) // Teensy3.6 180MHz untested. delays can possibly be reduced. |
davidprentice | 0:b608c7f02f80 | 435 | #define WRITE_DELAY { WR_ACTIVE8; } |
davidprentice | 0:b608c7f02f80 | 436 | #define READ_DELAY { RD_ACTIVE16; } |
davidprentice | 0:b608c7f02f80 | 437 | #else |
davidprentice | 0:b608c7f02f80 | 438 | #error unspecified delays |
davidprentice | 0:b608c7f02f80 | 439 | #endif |
davidprentice | 0:b608c7f02f80 | 440 | |
davidprentice | 0:b608c7f02f80 | 441 | #define RD_PORT GPIOD |
davidprentice | 0:b608c7f02f80 | 442 | #define RD_PIN 1 |
davidprentice | 0:b608c7f02f80 | 443 | #define WR_PORT GPIOC |
davidprentice | 0:b608c7f02f80 | 444 | #define WR_PIN 0 |
davidprentice | 0:b608c7f02f80 | 445 | #define CD_PORT GPIOB |
davidprentice | 0:b608c7f02f80 | 446 | #define CD_PIN 0 |
davidprentice | 0:b608c7f02f80 | 447 | #define CS_PORT GPIOB |
davidprentice | 0:b608c7f02f80 | 448 | #define CS_PIN 1 |
davidprentice | 0:b608c7f02f80 | 449 | #define RESET_PORT GPIOB |
davidprentice | 0:b608c7f02f80 | 450 | #define RESET_PIN 3 |
davidprentice | 0:b608c7f02f80 | 451 | |
davidprentice | 0:b608c7f02f80 | 452 | // configure macros for the data pins |
davidprentice | 0:b608c7f02f80 | 453 | #define AMASK ((1<<12)|(1<<13)) |
davidprentice | 0:b608c7f02f80 | 454 | #define CMASK ((1<<3)) |
davidprentice | 0:b608c7f02f80 | 455 | #define DMASK ((1<<0)|(1<<2)|(1<<3)|(1<<4)|(1<<7)) |
davidprentice | 0:b608c7f02f80 | 456 | |
davidprentice | 0:b608c7f02f80 | 457 | #define write_8(d) { \ |
davidprentice | 0:b608c7f02f80 | 458 | GPIOA_PCOR = AMASK; GPIOC_PCOR = CMASK; GPIOD_PCOR = DMASK; \ |
davidprentice | 0:b608c7f02f80 | 459 | GPIOA_PSOR = (((d) & (1 << 3)) << 9) \ |
davidprentice | 0:b608c7f02f80 | 460 | | (((d) & (1 << 4)) << 9); \ |
davidprentice | 0:b608c7f02f80 | 461 | GPIOC_PSOR = (((d) & (1 << 1)) << 2); \ |
davidprentice | 0:b608c7f02f80 | 462 | GPIOD_PSOR = (((d) & (1 << 0)) << 3) \ |
davidprentice | 0:b608c7f02f80 | 463 | | (((d) & (1 << 2)) >> 2) \ |
davidprentice | 0:b608c7f02f80 | 464 | | (((d) & (1 << 5)) << 2) \ |
davidprentice | 0:b608c7f02f80 | 465 | | (((d) & (1 << 6)) >> 2) \ |
davidprentice | 0:b608c7f02f80 | 466 | | (((d) & (1 << 7)) >> 5); \ |
davidprentice | 0:b608c7f02f80 | 467 | } |
davidprentice | 0:b608c7f02f80 | 468 | #define read_8() ((((GPIOD_PDIR & (1<<3)) >> 3) \ |
davidprentice | 0:b608c7f02f80 | 469 | | ((GPIOC_PDIR & (1 << 3)) >> 2) \ |
davidprentice | 0:b608c7f02f80 | 470 | | ((GPIOD_PDIR & (1 << 0)) << 2) \ |
davidprentice | 0:b608c7f02f80 | 471 | | ((GPIOA_PDIR & (1 << 12)) >> 9) \ |
davidprentice | 0:b608c7f02f80 | 472 | | ((GPIOA_PDIR & (1 << 13)) >> 9) \ |
davidprentice | 0:b608c7f02f80 | 473 | | ((GPIOD_PDIR & (1 << 7)) >> 2) \ |
davidprentice | 0:b608c7f02f80 | 474 | | ((GPIOD_PDIR & (1 << 4)) << 2) \ |
davidprentice | 0:b608c7f02f80 | 475 | | ((GPIOD_PDIR & (1 << 2)) << 5))) |
davidprentice | 0:b608c7f02f80 | 476 | #define setWriteDir() {GPIOA_PDDR |= AMASK;GPIOC_PDDR |= CMASK;GPIOD_PDDR |= DMASK; } |
davidprentice | 0:b608c7f02f80 | 477 | #define setReadDir() {GPIOA_PDDR &= ~AMASK;GPIOC_PDDR &= ~CMASK;GPIOD_PDDR &= ~DMASK; } |
davidprentice | 0:b608c7f02f80 | 478 | #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; } //PJ adjusted |
davidprentice | 0:b608c7f02f80 | 479 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
davidprentice | 0:b608c7f02f80 | 480 | #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } //PJ adjusted |
davidprentice | 0:b608c7f02f80 | 481 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
davidprentice | 0:b608c7f02f80 | 482 | //#define GPIO_INIT() {SIM_SCGC5 |= 0x3E00;} //PORTA-PORTE |
davidprentice | 0:b608c7f02f80 | 483 | #define GPIO_INIT() {for (int i = 2; i <= 9; i++) pinMode(i, OUTPUT); for (int i = A0; i <= A4; i++) pinMode(i, OUTPUT);} |
davidprentice | 0:b608c7f02f80 | 484 | |
davidprentice | 0:b608c7f02f80 | 485 | #define PASTE(x, y) x ## y |
davidprentice | 0:b608c7f02f80 | 486 | |
davidprentice | 0:b608c7f02f80 | 487 | #define PIN_LOW(port, pin) PASTE(port, _PCOR) = (1<<(pin)) |
davidprentice | 0:b608c7f02f80 | 488 | #define PIN_HIGH(port, pin) PASTE(port, _PSOR) = (1<<(pin)) |
davidprentice | 0:b608c7f02f80 | 489 | #define PIN_OUTPUT(port, pin) PASTE(port, _PDDR) |= (1<<(pin)) |
davidprentice | 0:b608c7f02f80 | 490 | |
davidprentice | 0:b608c7f02f80 | 491 | //####################################### STM32 ############################ |
davidprentice | 0:b608c7f02f80 | 492 | // NUCLEO: ARDUINO_NUCLEO_xxxx from ST Core or ARDUINO_STM_NUCLEO_F103RB from MapleCore |
davidprentice | 0:b608c7f02f80 | 493 | // BLUEPILL: ARDUINO_NUCLEO_F103C8 / ARDUINO_BLUEPILL_F103C8 from ST Core or ARDUINO_GENERIC_STM32F103C from MapleCore |
davidprentice | 0:b608c7f02f80 | 494 | // MAPLE_REV3: n/a from ST Core or ARDUINO_MAPLE_REV3 from MapleCore |
davidprentice | 0:b608c7f02f80 | 495 | // ST Core: ARDUINO_ARCH_STM32 |
davidprentice | 0:b608c7f02f80 | 496 | // MapleCore: __STM32F1__ |
davidprentice | 0:b608c7f02f80 | 497 | #elif defined(__STM32F1__) || defined(ARDUINO_ARCH_STM32) //MapleCore or ST Core |
davidprentice | 0:b608c7f02f80 | 498 | #define IS_NUCLEO64 ( defined(ARDUINO_STM_NUCLEO_F103RB) \ |
davidprentice | 0:b608c7f02f80 | 499 | || defined(ARDUINO_NUCLEO_F030R8) || defined(ARDUINO_NUCLEO_F091RC) \ |
davidprentice | 0:b608c7f02f80 | 500 | || defined(ARDUINO_NUCLEO_F103RB) || defined(ARDUINO_NUCLEO_F303RE) \ |
davidprentice | 0:b608c7f02f80 | 501 | || defined(ARDUINO_NUCLEO_F401RE) || defined(ARDUINO_NUCLEO_F411RE) \ |
davidprentice | 0:b608c7f02f80 | 502 | || defined(ARDUINO_NUCLEO_F446RE) || defined(ARDUINO_NUCLEO_L053R8) \ |
davidprentice | 0:b608c7f02f80 | 503 | || defined(ARDUINO_NUCLEO_L152RE) || defined(ARDUINO_NUCLEO_L476RG) \ |
davidprentice | 0:b608c7f02f80 | 504 | || defined(ARDUINO_NUCLEO_F072RB) \ |
davidprentice | 0:b608c7f02f80 | 505 | ) |
davidprentice | 0:b608c7f02f80 | 506 | #define IS_NUCLEO144 ( defined(ARDUINO_NUCLEO_F207ZG) \ |
davidprentice | 0:b608c7f02f80 | 507 | || defined(ARDUINO_NUCLEO_F429ZI) || defined(ARDUINO_NUCLEO_F767ZI) \ |
davidprentice | 0:b608c7f02f80 | 508 | || defined(ARDUINO_NUCLEO_L496ZG) || defined(ARDUINO_NUCLEO_L496ZG_P) \ |
davidprentice | 0:b608c7f02f80 | 509 | || defined(ARDUINO_NUCLEO_H743ZI) \ |
davidprentice | 0:b608c7f02f80 | 510 | ) |
davidprentice | 0:b608c7f02f80 | 511 | // F1xx, F4xx, L4xx have different registers and styles. General Macros |
davidprentice | 0:b608c7f02f80 | 512 | #if defined(__STM32F1__) //weird Maple Core |
davidprentice | 0:b608c7f02f80 | 513 | #define REGS(x) regs->x |
davidprentice | 0:b608c7f02f80 | 514 | #else //regular ST Core |
davidprentice | 0:b608c7f02f80 | 515 | #define REGS(x) x |
davidprentice | 0:b608c7f02f80 | 516 | #endif |
davidprentice | 0:b608c7f02f80 | 517 | #define PIN_HIGH(port, pin) (port)-> REGS(BSRR) = (1<<(pin)) |
davidprentice | 0:b608c7f02f80 | 518 | #define PIN_LOW(port, pin) (port)-> REGS(BSRR) = (1<<((pin)+16)) |
davidprentice | 0:b608c7f02f80 | 519 | #define PIN_MODE2(reg, pin, mode) reg=(reg&~(0x3<<((pin)<<1)))|(mode<<((pin)<<1)) |
davidprentice | 0:b608c7f02f80 | 520 | #define GROUP_MODE(port, reg, mask, val) {port->REGS(reg) = (port->REGS(reg) & ~(mask)) | ((mask)&(val)); } |
davidprentice | 0:b608c7f02f80 | 521 | |
davidprentice | 0:b608c7f02f80 | 522 | // Family specific Macros. F103 needs ST and Maple compatibility |
davidprentice | 0:b608c7f02f80 | 523 | // note that ILI9320 class of controller has much slower Read cycles |
davidprentice | 0:b608c7f02f80 | 524 | #if 0 |
davidprentice | 0:b608c7f02f80 | 525 | #elif defined(__STM32F1__) || defined(ARDUINO_NUCLEO_F103C8) || defined(ARDUINO_BLUEPILL_F103C8) || defined(ARDUINO_NUCLEO_F103RB) |
davidprentice | 0:b608c7f02f80 | 526 | #define WRITE_DELAY { } |
davidprentice | 0:b608c7f02f80 | 527 | #define READ_DELAY { RD_ACTIVE; } |
davidprentice | 0:b608c7f02f80 | 528 | #if defined(__STM32F1__) //MapleCore crts.o does RCC. not understand regular syntax anyway |
davidprentice | 0:b608c7f02f80 | 529 | #define GPIO_INIT() |
davidprentice | 0:b608c7f02f80 | 530 | #else |
davidprentice | 0:b608c7f02f80 | 531 | #define GPIO_INIT() { RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | RCC_APB2ENR_AFIOEN; \ |
davidprentice | 0:b608c7f02f80 | 532 | AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_1;} |
davidprentice | 0:b608c7f02f80 | 533 | #endif |
davidprentice | 0:b608c7f02f80 | 534 | #define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333) |
davidprentice | 0:b608c7f02f80 | 535 | #define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444) |
davidprentice | 0:b608c7f02f80 | 536 | #define PIN_OUTPUT(port, pin) {\ |
davidprentice | 0:b608c7f02f80 | 537 | if (pin < 8) {GP_OUT(port, CRL, 0xF<<((pin)<<2));} \ |
davidprentice | 0:b608c7f02f80 | 538 | else {GP_OUT(port, CRH, 0xF<<((pin&7)<<2));} \ |
davidprentice | 0:b608c7f02f80 | 539 | } |
davidprentice | 0:b608c7f02f80 | 540 | #define PIN_INPUT(port, pin) { \ |
davidprentice | 0:b608c7f02f80 | 541 | if (pin < 8) { GP_INP(port, CRL, 0xF<<((pin)<<2)); } \ |
davidprentice | 0:b608c7f02f80 | 542 | else { GP_INP(port, CRH, 0xF<<((pin&7)<<2)); } \ |
davidprentice | 0:b608c7f02f80 | 543 | } |
davidprentice | 0:b608c7f02f80 | 544 | |
davidprentice | 0:b608c7f02f80 | 545 | // should be easy to add F030, F091, F303, L053, ... |
davidprentice | 0:b608c7f02f80 | 546 | #elif defined(STM32F030x8) |
davidprentice | 0:b608c7f02f80 | 547 | #define WRITE_DELAY { } |
davidprentice | 0:b608c7f02f80 | 548 | #define READ_DELAY { RD_ACTIVE; } |
davidprentice | 0:b608c7f02f80 | 549 | #define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; } |
davidprentice | 0:b608c7f02f80 | 550 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
davidprentice | 0:b608c7f02f80 | 551 | |
davidprentice | 0:b608c7f02f80 | 552 | #elif defined(STM32F072xB) |
davidprentice | 0:b608c7f02f80 | 553 | #define WRITE_DELAY { } |
davidprentice | 0:b608c7f02f80 | 554 | #define READ_DELAY { RD_ACTIVE; } |
davidprentice | 0:b608c7f02f80 | 555 | #define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; } |
davidprentice | 0:b608c7f02f80 | 556 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
davidprentice | 0:b608c7f02f80 | 557 | |
davidprentice | 0:b608c7f02f80 | 558 | #elif defined(STM32F091xC) |
davidprentice | 0:b608c7f02f80 | 559 | #define WRITE_DELAY { } |
davidprentice | 0:b608c7f02f80 | 560 | #define READ_DELAY { RD_ACTIVE; } |
davidprentice | 0:b608c7f02f80 | 561 | #define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; } |
davidprentice | 0:b608c7f02f80 | 562 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
davidprentice | 0:b608c7f02f80 | 563 | |
davidprentice | 0:b608c7f02f80 | 564 | #elif defined(STM32F207xx) |
davidprentice | 0:b608c7f02f80 | 565 | #warning DELAY macros untested yet |
davidprentice | 0:b608c7f02f80 | 566 | #define WRITE_DELAY { WR_ACTIVE8; } //120MHz |
davidprentice | 0:b608c7f02f80 | 567 | #define IDLE_DELAY { WR_IDLE2;WR_IDLE; } |
davidprentice | 0:b608c7f02f80 | 568 | #define READ_DELAY { RD_ACTIVE16;} |
davidprentice | 0:b608c7f02f80 | 569 | #define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN; } |
davidprentice | 0:b608c7f02f80 | 570 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
davidprentice | 0:b608c7f02f80 | 571 | |
davidprentice | 0:b608c7f02f80 | 572 | #elif defined(STM32F303xE) |
davidprentice | 0:b608c7f02f80 | 573 | #define WRITE_DELAY { } |
davidprentice | 0:b608c7f02f80 | 574 | #define READ_DELAY { RD_ACTIVE8; } //thanks MasterT |
davidprentice | 0:b608c7f02f80 | 575 | #define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; \ |
davidprentice | 0:b608c7f02f80 | 576 | /* AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_1; */ } |
davidprentice | 0:b608c7f02f80 | 577 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) //thanks fpiSTM |
davidprentice | 0:b608c7f02f80 | 578 | |
davidprentice | 0:b608c7f02f80 | 579 | #elif defined(STM32F401xE) |
davidprentice | 0:b608c7f02f80 | 580 | #define WRITE_DELAY { WR_ACTIVE2; } //84MHz |
davidprentice | 0:b608c7f02f80 | 581 | #define READ_DELAY { RD_ACTIVE4; } |
davidprentice | 0:b608c7f02f80 | 582 | #define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN; } |
davidprentice | 0:b608c7f02f80 | 583 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
davidprentice | 0:b608c7f02f80 | 584 | |
davidprentice | 0:b608c7f02f80 | 585 | #elif defined(STM32F411xE) |
davidprentice | 0:b608c7f02f80 | 586 | #define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //100MHz |
davidprentice | 0:b608c7f02f80 | 587 | #define READ_DELAY { RD_ACTIVE4; RD_ACTIVE2; } |
davidprentice | 0:b608c7f02f80 | 588 | #define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN; } |
davidprentice | 0:b608c7f02f80 | 589 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
davidprentice | 0:b608c7f02f80 | 590 | |
davidprentice | 0:b608c7f02f80 | 591 | #elif defined(STM32F429xx) |
davidprentice | 0:b608c7f02f80 | 592 | #warning DELAY macros untested yet |
davidprentice | 0:b608c7f02f80 | 593 | #define WRITE_DELAY { WR_ACTIVE8; } //180MHz |
davidprentice | 0:b608c7f02f80 | 594 | #define IDLE_DELAY { WR_IDLE2;WR_IDLE; } |
davidprentice | 0:b608c7f02f80 | 595 | #define READ_DELAY { RD_ACTIVE16;} |
davidprentice | 0:b608c7f02f80 | 596 | #define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN; } |
davidprentice | 0:b608c7f02f80 | 597 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
davidprentice | 0:b608c7f02f80 | 598 | |
davidprentice | 0:b608c7f02f80 | 599 | #elif defined(STM32F446xx) |
davidprentice | 0:b608c7f02f80 | 600 | #define WRITE_DELAY { WR_ACTIVE8; } //180MHz |
davidprentice | 0:b608c7f02f80 | 601 | #define IDLE_DELAY { WR_IDLE2;WR_IDLE; } |
davidprentice | 0:b608c7f02f80 | 602 | #define READ_DELAY { RD_ACTIVE16;} |
davidprentice | 0:b608c7f02f80 | 603 | #define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN; } |
davidprentice | 0:b608c7f02f80 | 604 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
davidprentice | 0:b608c7f02f80 | 605 | |
davidprentice | 0:b608c7f02f80 | 606 | #elif defined(STM32F767xx) |
davidprentice | 0:b608c7f02f80 | 607 | #warning DELAY macros untested yet |
davidprentice | 0:b608c7f02f80 | 608 | #define WRITE_DELAY { WR_ACTIVE8;WR_ACTIVE2; } //216MHz |
davidprentice | 0:b608c7f02f80 | 609 | #define IDLE_DELAY { WR_IDLE2;WR_IDLE; } |
davidprentice | 0:b608c7f02f80 | 610 | #define READ_DELAY { RD_ACTIVE16;RD_ACTIVE16;RD_ACTIVE4;} |
davidprentice | 0:b608c7f02f80 | 611 | #define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN; } |
davidprentice | 0:b608c7f02f80 | 612 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
davidprentice | 0:b608c7f02f80 | 613 | |
davidprentice | 0:b608c7f02f80 | 614 | #elif defined(STM32H743xx) // thanks MagicianT |
davidprentice | 0:b608c7f02f80 | 615 | #warning STM32H743xx< DELAY macros untested yet |
davidprentice | 0:b608c7f02f80 | 616 | #define WRITE_DELAY { WR_ACTIVE8;WR_ACTIVE2; } //F_CPU=400MHz |
davidprentice | 0:b608c7f02f80 | 617 | #define IDLE_DELAY { WR_IDLE2;WR_IDLE; } |
davidprentice | 0:b608c7f02f80 | 618 | #define READ_DELAY { RD_ACTIVE16;RD_ACTIVE16;RD_ACTIVE4;} |
davidprentice | 0:b608c7f02f80 | 619 | #define GPIO_INIT() { RCC->AHB4ENR |= RCC_AHB4ENR_GPIOAEN | RCC_AHB4ENR_GPIOCEN | RCC_AHB4ENR_GPIODEN | RCC_AHB4ENR_GPIOEEN | RCC_AHB4ENR_GPIOFEN; } |
davidprentice | 0:b608c7f02f80 | 620 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
davidprentice | 0:b608c7f02f80 | 621 | |
davidprentice | 0:b608c7f02f80 | 622 | #elif defined(STM32L053xx) |
davidprentice | 0:b608c7f02f80 | 623 | #define WRITE_DELAY { } //32MHz M0+ |
davidprentice | 0:b608c7f02f80 | 624 | #define READ_DELAY { RD_ACTIVE; } |
davidprentice | 0:b608c7f02f80 | 625 | #define GPIO_INIT() { RCC->IOPENR |= RCC_IOPENR_GPIOAEN | RCC_IOPENR_GPIOBEN | RCC_IOPENR_GPIOCEN; } |
davidprentice | 0:b608c7f02f80 | 626 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
davidprentice | 0:b608c7f02f80 | 627 | |
davidprentice | 0:b608c7f02f80 | 628 | #elif defined(STM32L152xE) |
davidprentice | 0:b608c7f02f80 | 629 | #define WRITE_DELAY { } //32MHz M3 |
davidprentice | 0:b608c7f02f80 | 630 | #define READ_DELAY { RD_ACTIVE; } |
davidprentice | 0:b608c7f02f80 | 631 | #define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; } |
davidprentice | 0:b608c7f02f80 | 632 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
davidprentice | 0:b608c7f02f80 | 633 | |
davidprentice | 0:b608c7f02f80 | 634 | #elif defined(STM32L476xx) |
davidprentice | 0:b608c7f02f80 | 635 | #define WRITE_DELAY { WR_ACTIVE2; } //80MHz |
davidprentice | 0:b608c7f02f80 | 636 | #define READ_DELAY { RD_ACTIVE4; RD_ACTIVE; } |
davidprentice | 0:b608c7f02f80 | 637 | #define GPIO_INIT() { RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | RCC_AHB2ENR_GPIOCEN; } |
davidprentice | 0:b608c7f02f80 | 638 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
davidprentice | 0:b608c7f02f80 | 639 | |
davidprentice | 0:b608c7f02f80 | 640 | #elif defined(STM32L496xx) |
davidprentice | 0:b608c7f02f80 | 641 | #warning DELAY macros untested yet |
davidprentice | 0:b608c7f02f80 | 642 | #define WRITE_DELAY { WR_ACTIVE2; } //80MHz |
davidprentice | 0:b608c7f02f80 | 643 | #define READ_DELAY { RD_ACTIVE4; RD_ACTIVE; } |
davidprentice | 0:b608c7f02f80 | 644 | #define GPIO_INIT() { RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOCEN | RCC_AHB2ENR_GPIODEN | RCC_AHB2ENR_GPIOEEN | RCC_AHB2ENR_GPIOFEN; } |
davidprentice | 0:b608c7f02f80 | 645 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
davidprentice | 0:b608c7f02f80 | 646 | |
davidprentice | 0:b608c7f02f80 | 647 | #else |
davidprentice | 0:b608c7f02f80 | 648 | #error unsupported STM32 |
davidprentice | 0:b608c7f02f80 | 649 | #endif |
davidprentice | 0:b608c7f02f80 | 650 | |
davidprentice | 0:b608c7f02f80 | 651 | #if 0 |
davidprentice | 0:b608c7f02f80 | 652 | #elif defined(ARDUINO_GENERIC_STM32F103C) || defined(ARDUINO_NUCLEO_F103C8) || defined(ARDUINO_BLUEPILL_F103C8) |
davidprentice | 0:b608c7f02f80 | 653 | #warning Uno Shield on BLUEPILL |
davidprentice | 0:b608c7f02f80 | 654 | |
davidprentice | 0:b608c7f02f80 | 655 | //LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST| |SD_SS|SD_DI|SD_DO|SD_SCK| |
davidprentice | 0:b608c7f02f80 | 656 | //STM32 pin |PA7|PA6|PA5|PA4|PA3|PA2|PA1|PA0| |PB0|PB6|PB7|PB8|PB9| |PA15 |PB5 |PB4 |PB3 | **ALT-SPI1** |
davidprentice | 0:b608c7f02f80 | 657 | |
davidprentice | 0:b608c7f02f80 | 658 | #define RD_PORT GPIOB |
davidprentice | 0:b608c7f02f80 | 659 | //#define RD_PIN 5 |
davidprentice | 0:b608c7f02f80 | 660 | #define RD_PIN 0 //hardware mod to Adapter. Allows use of PB5 for SD Card |
davidprentice | 0:b608c7f02f80 | 661 | #define WR_PORT GPIOB |
davidprentice | 0:b608c7f02f80 | 662 | #define WR_PIN 6 |
davidprentice | 0:b608c7f02f80 | 663 | #define CD_PORT GPIOB |
davidprentice | 0:b608c7f02f80 | 664 | #define CD_PIN 7 |
davidprentice | 0:b608c7f02f80 | 665 | #define CS_PORT GPIOB |
davidprentice | 0:b608c7f02f80 | 666 | #define CS_PIN 8 |
davidprentice | 0:b608c7f02f80 | 667 | #define RESET_PORT GPIOB |
davidprentice | 0:b608c7f02f80 | 668 | #define RESET_PIN 9 |
davidprentice | 0:b608c7f02f80 | 669 | |
davidprentice | 0:b608c7f02f80 | 670 | // configure macros for the data pins |
davidprentice | 0:b608c7f02f80 | 671 | #define write_8(d) { GPIOA->REGS(BSRR) = 0x00FF << 16; GPIOA->REGS(BSRR) = (d) & 0xFF; } |
davidprentice | 0:b608c7f02f80 | 672 | #define read_8() (GPIOA->REGS(IDR) & 0xFF) |
davidprentice | 0:b608c7f02f80 | 673 | // PA7 ..PA0 |
davidprentice | 0:b608c7f02f80 | 674 | #define setWriteDir() {GP_OUT(GPIOA, CRL, 0xFFFFFFFF); } |
davidprentice | 0:b608c7f02f80 | 675 | #define setReadDir() {GP_INP(GPIOA, CRL, 0xFFFFFFFF); } |
davidprentice | 0:b608c7f02f80 | 676 | |
davidprentice | 0:b608c7f02f80 | 677 | #elif IS_NUCLEO64 // Uno Shield on NUCLEO-64 |
davidprentice | 0:b608c7f02f80 | 678 | #warning Uno Shield on NUCLEO-64 |
davidprentice | 0:b608c7f02f80 | 679 | #define RD_PORT GPIOA //PA0 |
davidprentice | 0:b608c7f02f80 | 680 | #define RD_PIN 0 |
davidprentice | 0:b608c7f02f80 | 681 | #define WR_PORT GPIOA //PA1 |
davidprentice | 0:b608c7f02f80 | 682 | #define WR_PIN 1 |
davidprentice | 0:b608c7f02f80 | 683 | #define CD_PORT GPIOA //PA4 |
davidprentice | 0:b608c7f02f80 | 684 | #define CD_PIN 4 |
davidprentice | 0:b608c7f02f80 | 685 | #define CS_PORT GPIOB //PB0 |
davidprentice | 0:b608c7f02f80 | 686 | #define CS_PIN 0 |
davidprentice | 0:b608c7f02f80 | 687 | #define RESET_PORT GPIOC //PC1 |
davidprentice | 0:b608c7f02f80 | 688 | #define RESET_PIN 1 |
davidprentice | 0:b608c7f02f80 | 689 | |
davidprentice | 0:b608c7f02f80 | 690 | // configure macros for the data pins |
davidprentice | 0:b608c7f02f80 | 691 | #define AMASK ((1<<9)|(1<<10)|(1<<8)) //#0, #2, #7 |
davidprentice | 0:b608c7f02f80 | 692 | #define BMASK ((1<<3)|(1<<5)|(1<<4)|(1<<10)) //#3, #4, #5, #6 |
davidprentice | 0:b608c7f02f80 | 693 | #define CMASK ((1<<7)) //#1 |
davidprentice | 0:b608c7f02f80 | 694 | |
davidprentice | 0:b608c7f02f80 | 695 | #define write_8(d) { \ |
davidprentice | 0:b608c7f02f80 | 696 | GPIOA->REGS(BSRR) = AMASK << 16; \ |
davidprentice | 0:b608c7f02f80 | 697 | GPIOB->REGS(BSRR) = BMASK << 16; \ |
davidprentice | 0:b608c7f02f80 | 698 | GPIOC->REGS(BSRR) = CMASK << 16; \ |
davidprentice | 0:b608c7f02f80 | 699 | GPIOA->REGS(BSRR) = ( ((d) & (1<<0)) << 9) \ |
davidprentice | 0:b608c7f02f80 | 700 | | (((d) & (1<<2)) << 8) \ |
davidprentice | 0:b608c7f02f80 | 701 | | (((d) & (1<<7)) << 1); \ |
davidprentice | 0:b608c7f02f80 | 702 | GPIOB->REGS(BSRR) = ( ((d) & (1<<3)) << 0) \ |
davidprentice | 0:b608c7f02f80 | 703 | | (((d) & (1<<4)) << 1) \ |
davidprentice | 0:b608c7f02f80 | 704 | | (((d) & (1<<5)) >> 1) \ |
davidprentice | 0:b608c7f02f80 | 705 | | (((d) & (1<<6)) << 4); \ |
davidprentice | 0:b608c7f02f80 | 706 | GPIOC->REGS(BSRR) = ( ((d) & (1<<1)) << 6); \ |
davidprentice | 0:b608c7f02f80 | 707 | } |
davidprentice | 0:b608c7f02f80 | 708 | |
davidprentice | 0:b608c7f02f80 | 709 | #define read_8() ( ( ( (GPIOA->REGS(IDR) & (1<<9)) >> 9) \ |
davidprentice | 0:b608c7f02f80 | 710 | | ((GPIOC->REGS(IDR) & (1<<7)) >> 6) \ |
davidprentice | 0:b608c7f02f80 | 711 | | ((GPIOA->REGS(IDR) & (1<<10)) >> 8) \ |
davidprentice | 0:b608c7f02f80 | 712 | | ((GPIOB->REGS(IDR) & (1<<3)) >> 0) \ |
davidprentice | 0:b608c7f02f80 | 713 | | ((GPIOB->REGS(IDR) & (1<<5)) >> 1) \ |
davidprentice | 0:b608c7f02f80 | 714 | | ((GPIOB->REGS(IDR) & (1<<4)) << 1) \ |
davidprentice | 0:b608c7f02f80 | 715 | | ((GPIOB->REGS(IDR) & (1<<10)) >> 4) \ |
davidprentice | 0:b608c7f02f80 | 716 | | ((GPIOA->REGS(IDR) & (1<<8)) >> 1))) |
davidprentice | 0:b608c7f02f80 | 717 | |
davidprentice | 0:b608c7f02f80 | 718 | |
davidprentice | 0:b608c7f02f80 | 719 | #if defined(ARDUINO_NUCLEO_F103RB) || defined(ARDUINO_STM_NUCLEO_F103RB) //F103 has unusual GPIO modes |
davidprentice | 0:b608c7f02f80 | 720 | // PA10,PA9,PA8 PB10 PB5,PB4,PB3 PC7 |
davidprentice | 0:b608c7f02f80 | 721 | #define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOB, CRH, 0xF00); GP_OUT(GPIOB, CRL, 0xFFF000); GP_OUT(GPIOC, CRL, 0xF0000000); } |
davidprentice | 0:b608c7f02f80 | 722 | #define setReadDir() {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOB, CRH, 0xF00); GP_INP(GPIOB, CRL, 0xFFF000); GP_INP(GPIOC, CRL, 0xF0000000); } |
davidprentice | 0:b608c7f02f80 | 723 | #else //F0xx, F3xx, F4xx, L0xx, L1xx, L4xx use MODER |
davidprentice | 0:b608c7f02f80 | 724 | // PA10,PA9,PA8 PB10,PB5,PB4,PB3 PC7 |
davidprentice | 0:b608c7f02f80 | 725 | #define setWriteDir() { setReadDir(); \ |
davidprentice | 0:b608c7f02f80 | 726 | GPIOA->MODER |= 0x150000; GPIOB->MODER |= 0x100540; GPIOC->MODER |= 0x4000; } |
davidprentice | 0:b608c7f02f80 | 727 | #define setReadDir() { GPIOA->MODER &= ~0x3F0000; GPIOB->MODER &= ~0x300FC0; GPIOC->MODER &= ~0xC000; } |
davidprentice | 0:b608c7f02f80 | 728 | #endif |
davidprentice | 0:b608c7f02f80 | 729 | |
davidprentice | 0:b608c7f02f80 | 730 | #elif IS_NUCLEO144 // Uno Shield on NUCLEO-144 |
davidprentice | 0:b608c7f02f80 | 731 | #warning Uno Shield on NUCLEO-144 |
davidprentice | 0:b608c7f02f80 | 732 | #define RD_PORT GPIOA //PA3 |
davidprentice | 0:b608c7f02f80 | 733 | #define RD_PIN 3 |
davidprentice | 0:b608c7f02f80 | 734 | #define WR_PORT GPIOC //PC0 |
davidprentice | 0:b608c7f02f80 | 735 | #define WR_PIN 0 |
davidprentice | 0:b608c7f02f80 | 736 | #define CD_PORT GPIOC //PC3 |
davidprentice | 0:b608c7f02f80 | 737 | #define CD_PIN 3 |
davidprentice | 0:b608c7f02f80 | 738 | #define CS_PORT GPIOF //PF3 |
davidprentice | 0:b608c7f02f80 | 739 | #define CS_PIN 3 |
davidprentice | 0:b608c7f02f80 | 740 | #define RESET_PORT GPIOF //PF5 |
davidprentice | 0:b608c7f02f80 | 741 | #define RESET_PIN 5 |
davidprentice | 0:b608c7f02f80 | 742 | |
davidprentice | 0:b608c7f02f80 | 743 | // configure macros for the data pins |
davidprentice | 0:b608c7f02f80 | 744 | #define DMASK ((1<<15)) //#1 |
davidprentice | 0:b608c7f02f80 | 745 | #define EMASK ((1<<13)|(1<<11)|(1<<9)) //#3, #5, #6 |
davidprentice | 0:b608c7f02f80 | 746 | #define FMASK ((1<<12)|(1<<15)|(1<<14)|(1<<13)) //#0, #2, #4, #7 |
davidprentice | 0:b608c7f02f80 | 747 | |
davidprentice | 0:b608c7f02f80 | 748 | #define write_8(d) { \ |
davidprentice | 0:b608c7f02f80 | 749 | GPIOD->REGS(BSRR) = DMASK << 16; \ |
davidprentice | 0:b608c7f02f80 | 750 | GPIOE->REGS(BSRR) = EMASK << 16; \ |
davidprentice | 0:b608c7f02f80 | 751 | GPIOF->REGS(BSRR) = FMASK << 16; \ |
davidprentice | 0:b608c7f02f80 | 752 | GPIOD->REGS(BSRR) = ( ((d) & (1<<1)) << 14); \ |
davidprentice | 0:b608c7f02f80 | 753 | GPIOE->REGS(BSRR) = ( ((d) & (1<<3)) << 10) \ |
davidprentice | 0:b608c7f02f80 | 754 | | (((d) & (1<<5)) << 6) \ |
davidprentice | 0:b608c7f02f80 | 755 | | (((d) & (1<<6)) << 3); \ |
davidprentice | 0:b608c7f02f80 | 756 | GPIOF->REGS(BSRR) = ( ((d) & (1<<0)) << 12) \ |
davidprentice | 0:b608c7f02f80 | 757 | | (((d) & (1<<2)) << 13) \ |
davidprentice | 0:b608c7f02f80 | 758 | | (((d) & (1<<4)) << 10) \ |
davidprentice | 0:b608c7f02f80 | 759 | | (((d) & (1<<7)) << 6); \ |
davidprentice | 0:b608c7f02f80 | 760 | } |
davidprentice | 0:b608c7f02f80 | 761 | |
davidprentice | 0:b608c7f02f80 | 762 | #define read_8() ( ( ( (GPIOF->REGS(IDR) & (1<<12)) >> 12) \ |
davidprentice | 0:b608c7f02f80 | 763 | | ((GPIOD->REGS(IDR) & (1<<15)) >> 14) \ |
davidprentice | 0:b608c7f02f80 | 764 | | ((GPIOF->REGS(IDR) & (1<<15)) >> 13) \ |
davidprentice | 0:b608c7f02f80 | 765 | | ((GPIOE->REGS(IDR) & (1<<13)) >> 10) \ |
davidprentice | 0:b608c7f02f80 | 766 | | ((GPIOF->REGS(IDR) & (1<<14)) >> 10) \ |
davidprentice | 0:b608c7f02f80 | 767 | | ((GPIOE->REGS(IDR) & (1<<11)) >> 6) \ |
davidprentice | 0:b608c7f02f80 | 768 | | ((GPIOE->REGS(IDR) & (1<<9)) >> 3) \ |
davidprentice | 0:b608c7f02f80 | 769 | | ((GPIOF->REGS(IDR) & (1<<13)) >> 6))) |
davidprentice | 0:b608c7f02f80 | 770 | |
davidprentice | 0:b608c7f02f80 | 771 | |
davidprentice | 0:b608c7f02f80 | 772 | // PD15 PE13,PE11,PE9 PF15,PF14,PF13,PF12 |
davidprentice | 0:b608c7f02f80 | 773 | #define setWriteDir() { setReadDir(); \ |
davidprentice | 0:b608c7f02f80 | 774 | GPIOD->MODER |= 0x40000000; GPIOE->MODER |= 0x04440000; GPIOF->MODER |= 0x55000000; } |
davidprentice | 0:b608c7f02f80 | 775 | #define setReadDir() { GPIOD->MODER &= ~0xC0000000; GPIOE->MODER &= ~0x0CCC0000; GPIOF->MODER &= ~0xFF000000; } |
davidprentice | 0:b608c7f02f80 | 776 | |
davidprentice | 0:b608c7f02f80 | 777 | #elif defined(ARDUINO_MAPLE_REV3) // Uno Shield on MAPLE_REV3 board |
davidprentice | 0:b608c7f02f80 | 778 | #warning Uno Shield on MAPLE_REV3 board |
davidprentice | 0:b608c7f02f80 | 779 | #define RD_PORT GPIOC |
davidprentice | 0:b608c7f02f80 | 780 | #define RD_PIN 0 |
davidprentice | 0:b608c7f02f80 | 781 | #define WR_PORT GPIOC |
davidprentice | 0:b608c7f02f80 | 782 | #define WR_PIN 1 |
davidprentice | 0:b608c7f02f80 | 783 | #define CD_PORT GPIOC |
davidprentice | 0:b608c7f02f80 | 784 | #define CD_PIN 2 |
davidprentice | 0:b608c7f02f80 | 785 | #define CS_PORT GPIOC |
davidprentice | 0:b608c7f02f80 | 786 | #define CS_PIN 3 |
davidprentice | 0:b608c7f02f80 | 787 | #define RESET_PORT GPIOC |
davidprentice | 0:b608c7f02f80 | 788 | #define RESET_PIN 4 |
davidprentice | 0:b608c7f02f80 | 789 | |
davidprentice | 0:b608c7f02f80 | 790 | // configure macros for the data pins |
davidprentice | 0:b608c7f02f80 | 791 | #define write_8(d) { \ |
davidprentice | 0:b608c7f02f80 | 792 | GPIOA->REGS(BSRR) = 0x0703 << 16; \ |
davidprentice | 0:b608c7f02f80 | 793 | GPIOB->REGS(BSRR) = 0x00E0 << 16; \ |
davidprentice | 0:b608c7f02f80 | 794 | GPIOA->REGS(BSRR) = ( ((d) & (1<<0)) << 10) \ |
davidprentice | 0:b608c7f02f80 | 795 | | (((d) & (1<<2)) >> 2) \ |
davidprentice | 0:b608c7f02f80 | 796 | | (((d) & (1<<3)) >> 2) \ |
davidprentice | 0:b608c7f02f80 | 797 | | (((d) & (1<<6)) << 2) \ |
davidprentice | 0:b608c7f02f80 | 798 | | (((d) & (1<<7)) << 2); \ |
davidprentice | 0:b608c7f02f80 | 799 | GPIOB->REGS(BSRR) = ( ((d) & (1<<1)) << 6) \ |
davidprentice | 0:b608c7f02f80 | 800 | | (((d) & (1<<4)) << 1) \ |
davidprentice | 0:b608c7f02f80 | 801 | | (((d) & (1<<5)) << 1); \ |
davidprentice | 0:b608c7f02f80 | 802 | } |
davidprentice | 0:b608c7f02f80 | 803 | |
davidprentice | 0:b608c7f02f80 | 804 | #define read_8() ( ( ( (GPIOA->REGS(IDR) & (1<<10)) >> 10) \ |
davidprentice | 0:b608c7f02f80 | 805 | | ((GPIOB->REGS(IDR) & (1<<7)) >> 6) \ |
davidprentice | 0:b608c7f02f80 | 806 | | ((GPIOA->REGS(IDR) & (1<<0)) << 2) \ |
davidprentice | 0:b608c7f02f80 | 807 | | ((GPIOA->REGS(IDR) & (1<<1)) << 2) \ |
davidprentice | 0:b608c7f02f80 | 808 | | ((GPIOB->REGS(IDR) & (1<<5)) >> 1) \ |
davidprentice | 0:b608c7f02f80 | 809 | | ((GPIOB->REGS(IDR) & (1<<6)) >> 1) \ |
davidprentice | 0:b608c7f02f80 | 810 | | ((GPIOA->REGS(IDR) & (1<<8)) >> 2) \ |
davidprentice | 0:b608c7f02f80 | 811 | | ((GPIOA->REGS(IDR) & (1<<9)) >> 2))) |
davidprentice | 0:b608c7f02f80 | 812 | |
davidprentice | 0:b608c7f02f80 | 813 | // PA10,PA9,PA8 PA1,PA0 PB7,PB6,PB5 |
davidprentice | 0:b608c7f02f80 | 814 | #define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOA, CRL, 0xFF); GP_OUT(GPIOB, CRL, 0xFFF00000); } |
davidprentice | 0:b608c7f02f80 | 815 | #define setReadDir() {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOA, CRL, 0xFF); GP_INP(GPIOB, CRL, 0xFFF00000); } |
davidprentice | 0:b608c7f02f80 | 816 | |
davidprentice | 0:b608c7f02f80 | 817 | #else |
davidprentice | 0:b608c7f02f80 | 818 | #error REGS group |
davidprentice | 0:b608c7f02f80 | 819 | #endif |
davidprentice | 0:b608c7f02f80 | 820 | |
davidprentice | 0:b608c7f02f80 | 821 | #ifndef IDLE_DELAY |
davidprentice | 0:b608c7f02f80 | 822 | #define IDLE_DELAY { WR_IDLE; } |
davidprentice | 0:b608c7f02f80 | 823 | #endif |
davidprentice | 0:b608c7f02f80 | 824 | |
davidprentice | 0:b608c7f02f80 | 825 | #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; IDLE_DELAY; } |
davidprentice | 0:b608c7f02f80 | 826 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
davidprentice | 0:b608c7f02f80 | 827 | #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE2; RD_IDLE; } |
davidprentice | 0:b608c7f02f80 | 828 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
davidprentice | 0:b608c7f02f80 | 829 | |
davidprentice | 0:b608c7f02f80 | 830 | //################################### ESP32 ############################## |
davidprentice | 0:b608c7f02f80 | 831 | #elif defined(ESP32) //regular UNO shield on TTGO D1 R32 (ESP32) |
davidprentice | 0:b608c7f02f80 | 832 | #define LCD_RD 2 //LED |
davidprentice | 0:b608c7f02f80 | 833 | #define LCD_WR 4 |
davidprentice | 0:b608c7f02f80 | 834 | #define LCD_RS 15 //hard-wired to A2 (GPIO35) |
davidprentice | 0:b608c7f02f80 | 835 | #define LCD_CS 33 //hard-wired to A3 (GPIO34) |
davidprentice | 0:b608c7f02f80 | 836 | #define LCD_RST 32 //hard-wired to A4 (GPIO36) |
davidprentice | 0:b608c7f02f80 | 837 | |
davidprentice | 0:b608c7f02f80 | 838 | #define LCD_D0 12 |
davidprentice | 0:b608c7f02f80 | 839 | #define LCD_D1 13 |
davidprentice | 0:b608c7f02f80 | 840 | #define LCD_D2 26 |
davidprentice | 0:b608c7f02f80 | 841 | #define LCD_D3 25 |
davidprentice | 0:b608c7f02f80 | 842 | #define LCD_D4 17 |
davidprentice | 0:b608c7f02f80 | 843 | #define LCD_D5 16 |
davidprentice | 0:b608c7f02f80 | 844 | #define LCD_D6 27 |
davidprentice | 0:b608c7f02f80 | 845 | #define LCD_D7 14 |
davidprentice | 0:b608c7f02f80 | 846 | |
davidprentice | 0:b608c7f02f80 | 847 | #define RD_PORT GPIO.out |
davidprentice | 0:b608c7f02f80 | 848 | #define RD_PIN LCD_RD |
davidprentice | 0:b608c7f02f80 | 849 | #define WR_PORT GPIO.out |
davidprentice | 0:b608c7f02f80 | 850 | #define WR_PIN LCD_WR |
davidprentice | 0:b608c7f02f80 | 851 | #define CD_PORT GPIO.out |
davidprentice | 0:b608c7f02f80 | 852 | #define CD_PIN LCD_RS |
davidprentice | 0:b608c7f02f80 | 853 | #define CS_PORT GPIO.out1.val |
davidprentice | 0:b608c7f02f80 | 854 | #define CS_PIN LCD_CS |
davidprentice | 0:b608c7f02f80 | 855 | #define RESET_PORT GPIO.out1.val |
davidprentice | 0:b608c7f02f80 | 856 | #define RESET_PIN LCD_RST |
davidprentice | 0:b608c7f02f80 | 857 | |
davidprentice | 0:b608c7f02f80 | 858 | static inline uint32_t map_8(uint32_t d) |
davidprentice | 0:b608c7f02f80 | 859 | { |
davidprentice | 0:b608c7f02f80 | 860 | return ( |
davidprentice | 0:b608c7f02f80 | 861 | 0 |
davidprentice | 0:b608c7f02f80 | 862 | | ((d & (1 << 0)) << (LCD_D0 - 0)) |
davidprentice | 0:b608c7f02f80 | 863 | | ((d & (1 << 1)) << (LCD_D1 - 1)) |
davidprentice | 0:b608c7f02f80 | 864 | | ((d & (1 << 2)) << (LCD_D2 - 2)) |
davidprentice | 0:b608c7f02f80 | 865 | | ((d & (1 << 3)) << (LCD_D3 - 3)) |
davidprentice | 0:b608c7f02f80 | 866 | | ((d & (1 << 4)) << (LCD_D4 - 4)) |
davidprentice | 0:b608c7f02f80 | 867 | | ((d & (1 << 5)) << (LCD_D5 - 5)) |
davidprentice | 0:b608c7f02f80 | 868 | | ((d & (1 << 6)) << (LCD_D6 - 6)) |
davidprentice | 0:b608c7f02f80 | 869 | | ((d & (1 << 7)) << (LCD_D7 - 7)) |
davidprentice | 0:b608c7f02f80 | 870 | ); |
davidprentice | 0:b608c7f02f80 | 871 | } |
davidprentice | 0:b608c7f02f80 | 872 | |
davidprentice | 0:b608c7f02f80 | 873 | static inline uint8_t map_32(uint32_t d) |
davidprentice | 0:b608c7f02f80 | 874 | { |
davidprentice | 0:b608c7f02f80 | 875 | return ( |
davidprentice | 0:b608c7f02f80 | 876 | 0 |
davidprentice | 0:b608c7f02f80 | 877 | | ((d & (1 << LCD_D0)) >> (LCD_D0 - 0)) |
davidprentice | 0:b608c7f02f80 | 878 | | ((d & (1 << LCD_D1)) >> (LCD_D1 - 1)) |
davidprentice | 0:b608c7f02f80 | 879 | | ((d & (1 << LCD_D2)) >> (LCD_D2 - 2)) |
davidprentice | 0:b608c7f02f80 | 880 | | ((d & (1 << LCD_D3)) >> (LCD_D3 - 3)) |
davidprentice | 0:b608c7f02f80 | 881 | | ((d & (1 << LCD_D4)) >> (LCD_D4 - 4)) |
davidprentice | 0:b608c7f02f80 | 882 | | ((d & (1 << LCD_D5)) >> (LCD_D5 - 5)) |
davidprentice | 0:b608c7f02f80 | 883 | | ((d & (1 << LCD_D6)) >> (LCD_D6 - 6)) |
davidprentice | 0:b608c7f02f80 | 884 | | ((d & (1 << LCD_D7)) >> (LCD_D7 - 7)) |
davidprentice | 0:b608c7f02f80 | 885 | ); |
davidprentice | 0:b608c7f02f80 | 886 | } |
davidprentice | 0:b608c7f02f80 | 887 | |
davidprentice | 0:b608c7f02f80 | 888 | static inline void write_8(uint16_t data) |
davidprentice | 0:b608c7f02f80 | 889 | { |
davidprentice | 0:b608c7f02f80 | 890 | GPIO.out_w1tc = map_8(0xFF); //could define once as DMASK |
davidprentice | 0:b608c7f02f80 | 891 | GPIO.out_w1ts = map_8(data); |
davidprentice | 0:b608c7f02f80 | 892 | } |
davidprentice | 0:b608c7f02f80 | 893 | |
davidprentice | 0:b608c7f02f80 | 894 | static inline uint8_t read_8() |
davidprentice | 0:b608c7f02f80 | 895 | { |
davidprentice | 0:b608c7f02f80 | 896 | return map_32(GPIO.in); |
davidprentice | 0:b608c7f02f80 | 897 | } |
davidprentice | 0:b608c7f02f80 | 898 | static void setWriteDir() |
davidprentice | 0:b608c7f02f80 | 899 | { |
davidprentice | 0:b608c7f02f80 | 900 | pinMode(LCD_D0, OUTPUT); |
davidprentice | 0:b608c7f02f80 | 901 | pinMode(LCD_D1, OUTPUT); |
davidprentice | 0:b608c7f02f80 | 902 | pinMode(LCD_D2, OUTPUT); |
davidprentice | 0:b608c7f02f80 | 903 | pinMode(LCD_D3, OUTPUT); |
davidprentice | 0:b608c7f02f80 | 904 | pinMode(LCD_D4, OUTPUT); |
davidprentice | 0:b608c7f02f80 | 905 | pinMode(LCD_D5, OUTPUT); |
davidprentice | 0:b608c7f02f80 | 906 | pinMode(LCD_D6, OUTPUT); |
davidprentice | 0:b608c7f02f80 | 907 | pinMode(LCD_D7, OUTPUT); |
davidprentice | 0:b608c7f02f80 | 908 | } |
davidprentice | 0:b608c7f02f80 | 909 | |
davidprentice | 0:b608c7f02f80 | 910 | static void setReadDir() |
davidprentice | 0:b608c7f02f80 | 911 | { |
davidprentice | 0:b608c7f02f80 | 912 | pinMode(LCD_D0, INPUT); |
davidprentice | 0:b608c7f02f80 | 913 | pinMode(LCD_D1, INPUT); |
davidprentice | 0:b608c7f02f80 | 914 | pinMode(LCD_D2, INPUT); |
davidprentice | 0:b608c7f02f80 | 915 | pinMode(LCD_D3, INPUT); |
davidprentice | 0:b608c7f02f80 | 916 | pinMode(LCD_D4, INPUT); |
davidprentice | 0:b608c7f02f80 | 917 | pinMode(LCD_D5, INPUT); |
davidprentice | 0:b608c7f02f80 | 918 | pinMode(LCD_D6, INPUT); |
davidprentice | 0:b608c7f02f80 | 919 | pinMode(LCD_D7, INPUT); |
davidprentice | 0:b608c7f02f80 | 920 | } |
davidprentice | 0:b608c7f02f80 | 921 | |
davidprentice | 0:b608c7f02f80 | 922 | #define WRITE_DELAY { } |
davidprentice | 0:b608c7f02f80 | 923 | #define READ_DELAY { } |
davidprentice | 0:b608c7f02f80 | 924 | |
davidprentice | 0:b608c7f02f80 | 925 | #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; } |
davidprentice | 0:b608c7f02f80 | 926 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
davidprentice | 0:b608c7f02f80 | 927 | #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } |
davidprentice | 0:b608c7f02f80 | 928 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
davidprentice | 0:b608c7f02f80 | 929 | |
davidprentice | 0:b608c7f02f80 | 930 | #define PIN_LOW(p, b) (digitalWrite(b, LOW)) |
davidprentice | 0:b608c7f02f80 | 931 | #define PIN_HIGH(p, b) (digitalWrite(b, HIGH)) |
davidprentice | 0:b608c7f02f80 | 932 | #define PIN_OUTPUT(p, b) (pinMode(b, OUTPUT)) |
davidprentice | 0:b608c7f02f80 | 933 | |
davidprentice | 0:b608c7f02f80 | 934 | #else |
davidprentice | 0:b608c7f02f80 | 935 | #error MCU unsupported |
davidprentice | 0:b608c7f02f80 | 936 | #endif // regular UNO shields on Arduino boards |
davidprentice | 0:b608c7f02f80 | 937 | |
davidprentice | 0:b608c7f02f80 | 938 | #endif //!defined(USE_SPECIAL) || defined (USE_SPECIAL_FAIL) |
davidprentice | 0:b608c7f02f80 | 939 | |
davidprentice | 0:b608c7f02f80 | 940 | #define RD_ACTIVE PIN_LOW(RD_PORT, RD_PIN) |
davidprentice | 0:b608c7f02f80 | 941 | #define RD_IDLE PIN_HIGH(RD_PORT, RD_PIN) |
davidprentice | 0:b608c7f02f80 | 942 | #define RD_OUTPUT PIN_OUTPUT(RD_PORT, RD_PIN) |
davidprentice | 0:b608c7f02f80 | 943 | #define WR_ACTIVE PIN_LOW(WR_PORT, WR_PIN) |
davidprentice | 0:b608c7f02f80 | 944 | #define WR_IDLE PIN_HIGH(WR_PORT, WR_PIN) |
davidprentice | 0:b608c7f02f80 | 945 | #define WR_OUTPUT PIN_OUTPUT(WR_PORT, WR_PIN) |
davidprentice | 0:b608c7f02f80 | 946 | #define CD_COMMAND PIN_LOW(CD_PORT, CD_PIN) |
davidprentice | 0:b608c7f02f80 | 947 | #define CD_DATA PIN_HIGH(CD_PORT, CD_PIN) |
davidprentice | 0:b608c7f02f80 | 948 | #define CD_OUTPUT PIN_OUTPUT(CD_PORT, CD_PIN) |
davidprentice | 0:b608c7f02f80 | 949 | #define CS_ACTIVE PIN_LOW(CS_PORT, CS_PIN) |
davidprentice | 0:b608c7f02f80 | 950 | #define CS_IDLE PIN_HIGH(CS_PORT, CS_PIN) |
davidprentice | 0:b608c7f02f80 | 951 | #define CS_OUTPUT PIN_OUTPUT(CS_PORT, CS_PIN) |
davidprentice | 0:b608c7f02f80 | 952 | #define RESET_ACTIVE PIN_LOW(RESET_PORT, RESET_PIN) |
davidprentice | 0:b608c7f02f80 | 953 | #define RESET_IDLE PIN_HIGH(RESET_PORT, RESET_PIN) |
davidprentice | 0:b608c7f02f80 | 954 | #define RESET_OUTPUT PIN_OUTPUT(RESET_PORT, RESET_PIN) |
davidprentice | 0:b608c7f02f80 | 955 | |
davidprentice | 0:b608c7f02f80 | 956 | // General macros. IOCLR registers are 1 cycle when optimised. |
davidprentice | 0:b608c7f02f80 | 957 | #define WR_STROBE { WR_ACTIVE; WR_IDLE; } //PWLW=TWRL=50ns |
davidprentice | 0:b608c7f02f80 | 958 | #define RD_STROBE RD_IDLE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE //PWLR=TRDL=150ns, tDDR=100ns |
davidprentice | 0:b608c7f02f80 | 959 | |
davidprentice | 0:b608c7f02f80 | 960 | #if !defined(GPIO_INIT) |
davidprentice | 0:b608c7f02f80 | 961 | #define GPIO_INIT() |
davidprentice | 0:b608c7f02f80 | 962 | #endif |
davidprentice | 0:b608c7f02f80 | 963 | #define CTL_INIT() { GPIO_INIT(); RD_OUTPUT; WR_OUTPUT; CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; } |
davidprentice | 0:b608c7f02f80 | 964 | #define WriteCmd(x) { CD_COMMAND; write16(x); CD_DATA; } |
davidprentice | 0:b608c7f02f80 | 965 | #define WriteData(x) { write16(x); } |