David Prentice / Mbed 2 deprecated Nucleo_dir_L152

Please run it on your NUCLEO-L152

Dependencies:   mbed

MCUFRIEND_kbv/utility/mcufriend_serial.h@1:d88d2ad55fac, 2019-09-18 (annotated)

Committer:
davidprentice
Date:
Wed Sep 18 10:38:19 2019 +0000
Revision:
1:d88d2ad55fac
Parent:
0:b608c7f02f80 
Added messages to Serial Terminal (9600 baud)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
davidprentice 0:b608c7f02f80 1 #if ARDUINO >= 165
davidprentice 0:b608c7f02f80 2 #include <SPI.h>
davidprentice 0:b608c7f02f80 3 #endif
davidprentice 0:b608c7f02f80 4
davidprentice 0:b608c7f02f80 5 #if 0
davidprentice 0:b608c7f02f80 6 #elif defined(__AVR_ATmega328P__)
davidprentice 0:b608c7f02f80 7
davidprentice 0:b608c7f02f80 8 #define SPI_INIT() { DDRB |= (1<<5)|(1<<3)|(1<<2); SPCR = (1<<SPE)|(1<<MSTR); SPSR = (1<<SPI2X); SPSR; SPDR; }
davidprentice 0:b608c7f02f80 9 static inline uint8_t spi_xfer(uint8_t c)
davidprentice 0:b608c7f02f80 10 {
davidprentice 0:b608c7f02f80 11 SPDR = c;
davidprentice 0:b608c7f02f80 12 while ((SPSR & (1<<SPIF)) == 0) ;
davidprentice 0:b608c7f02f80 13 return SPDR;
davidprentice 0:b608c7f02f80 14 }
davidprentice 0:b608c7f02f80 15 extern uint8_t running;
davidprentice 0:b608c7f02f80 16 static inline void write8(uint8_t x) {
davidprentice 0:b608c7f02f80 17 if (running) {
davidprentice 0:b608c7f02f80 18 while ((SPSR & 0x80) == 0);
davidprentice 0:b608c7f02f80 19 SPDR;
davidprentice 0:b608c7f02f80 20 }
davidprentice 0:b608c7f02f80 21 SPDR = x;
davidprentice 0:b608c7f02f80 22 running = 1;
davidprentice 0:b608c7f02f80 23 }
davidprentice 0:b608c7f02f80 24 static inline uint8_t read8(void) {
davidprentice 0:b608c7f02f80 25 if (running) while ((SPSR & 0x80) == 0);
davidprentice 0:b608c7f02f80 26 running = 0;
davidprentice 0:b608c7f02f80 27 return SPDR;
davidprentice 0:b608c7f02f80 28 }
davidprentice 0:b608c7f02f80 29 static inline uint8_t xchg8(uint8_t x) { write8(x); return read8(); }
davidprentice 0:b608c7f02f80 30 static inline void flush(void) {
davidprentice 0:b608c7f02f80 31 if (running) {
davidprentice 0:b608c7f02f80 32 while ((SPSR & 0x80) == 0);
davidprentice 0:b608c7f02f80 33 }
davidprentice 0:b608c7f02f80 34 running = 0;
davidprentice 0:b608c7f02f80 35 SPDR;
davidprentice 0:b608c7f02f80 36 }
davidprentice 0:b608c7f02f80 37
davidprentice 0:b608c7f02f80 38 #if defined(SUPPORT_8347D)
davidprentice 0:b608c7f02f80 39 #warning using HX8347D hardware
davidprentice 0:b608c7f02f80 40 #define CD_PORT PORTD
davidprentice 0:b608c7f02f80 41 #define CD_PIN PD7
davidprentice 0:b608c7f02f80 42 #define CS_PORT PORTB
davidprentice 0:b608c7f02f80 43 #define CS_PIN PB2
davidprentice 0:b608c7f02f80 44 #define RESET_PORT PORTB
davidprentice 0:b608c7f02f80 45 #define RESET_PIN PB1
davidprentice 0:b608c7f02f80 46 #define SD_PIN PD5
davidprentice 0:b608c7f02f80 47 #define XPT_PIN PD4
davidprentice 0:b608c7f02f80 48 #define RD_IDLE
davidprentice 0:b608c7f02f80 49 #define WR_IDLE
davidprentice 0:b608c7f02f80 50 #else
davidprentice 0:b608c7f02f80 51 #warning using regular SPI hardware
davidprentice 0:b608c7f02f80 52 #define CD_PORT PORTB
davidprentice 0:b608c7f02f80 53 #define CD_PIN 1
davidprentice 0:b608c7f02f80 54 #define CS_PORT PORTB
davidprentice 0:b608c7f02f80 55 #define CS_PIN 2
davidprentice 0:b608c7f02f80 56 #define RESET_PORT PORTB
davidprentice 0:b608c7f02f80 57 #define RESET_PIN 0
davidprentice 0:b608c7f02f80 58 #define RD_IDLE
davidprentice 0:b608c7f02f80 59 #define WR_IDLE
davidprentice 0:b608c7f02f80 60 #endif
davidprentice 0:b608c7f02f80 61
davidprentice 0:b608c7f02f80 62 #define setWriteDir() { }
davidprentice 0:b608c7f02f80 63 #define setReadDir() { }
davidprentice 0:b608c7f02f80 64 //#define write8(x) spi_xfer(x)
davidprentice 0:b608c7f02f80 65 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
davidprentice 0:b608c7f02f80 66 #define READ_8(dst) { dst = xchg8(0); }
davidprentice 0:b608c7f02f80 67 #define READ_16(dst) { dst = xchg8(0); dst = (dst << 8) | xchg8(0); }
davidprentice 0:b608c7f02f80 68
davidprentice 0:b608c7f02f80 69 #define PIN_LOW(p, b) (p) &= ~(1<<(b))
davidprentice 0:b608c7f02f80 70 #define PIN_HIGH(p, b) (p) |= (1<<(b))
davidprentice 0:b608c7f02f80 71 #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
davidprentice 0:b608c7f02f80 72 #elif defined(__SAMD21G18A__)
davidprentice 0:b608c7f02f80 73
davidprentice 0:b608c7f02f80 74 #define SPI_INIT() { SPI.begin(); SPI.setDataMode(SPI_MODE0); SPI.setClockDivider(6); }
davidprentice 0:b608c7f02f80 75
davidprentice 0:b608c7f02f80 76 #define CD_PORT PORT->Group[0]
davidprentice 0:b608c7f02f80 77 #define CD_PIN 7
davidprentice 0:b608c7f02f80 78 #define CS_PORT PORT->Group[0]
davidprentice 0:b608c7f02f80 79 #define CS_PIN 18
davidprentice 0:b608c7f02f80 80 #define RESET_PORT PORT->Group[0]
davidprentice 0:b608c7f02f80 81 #define RESET_PIN 6
davidprentice 0:b608c7f02f80 82 #define RD_IDLE
davidprentice 0:b608c7f02f80 83 #define WR_IDLE
davidprentice 0:b608c7f02f80 84
davidprentice 0:b608c7f02f80 85
davidprentice 0:b608c7f02f80 86 uint8_t running;
davidprentice 0:b608c7f02f80 87 static inline void write8(uint8_t c)
davidprentice 0:b608c7f02f80 88 {
davidprentice 0:b608c7f02f80 89 running = 1;
davidprentice 0:b608c7f02f80 90 while( SERCOM1->SPI.INTFLAG.bit.DRE == 0) ;
davidprentice 0:b608c7f02f80 91 SERCOM1->SPI.DATA.bit.DATA = c; // Writing data into Data register
davidprentice 0:b608c7f02f80 92 }
davidprentice 0:b608c7f02f80 93
davidprentice 0:b608c7f02f80 94 static inline void flush(void)
davidprentice 0:b608c7f02f80 95 {
davidprentice 0:b608c7f02f80 96 if (running) while( SERCOM1->SPI.INTFLAG.bit.TXC == 0) ;
davidprentice 0:b608c7f02f80 97 running = 0;
davidprentice 0:b608c7f02f80 98 }
davidprentice 0:b608c7f02f80 99
davidprentice 0:b608c7f02f80 100 static inline uint8_t xchg8(uint8_t c)
davidprentice 0:b608c7f02f80 101 {
davidprentice 0:b608c7f02f80 102 // flush();
davidprentice 0:b608c7f02f80 103 while( SERCOM1->SPI.INTFLAG.bit.RXC != 0) SERCOM1->SPI.DATA.bit.DATA; //eat up
davidprentice 0:b608c7f02f80 104 while( SERCOM1->SPI.INTFLAG.bit.DRE == 0) ;
davidprentice 0:b608c7f02f80 105 SERCOM1->SPI.DATA.bit.DATA = c; // Writing data into Data register
davidprentice 0:b608c7f02f80 106 while( SERCOM1->SPI.INTFLAG.bit.RXC == 0) ;
davidprentice 0:b608c7f02f80 107 return SERCOM1->SPI.DATA.bit.DATA;
davidprentice 0:b608c7f02f80 108 }
davidprentice 0:b608c7f02f80 109
davidprentice 0:b608c7f02f80 110
davidprentice 0:b608c7f02f80 111 #define setWriteDir() { }
davidprentice 0:b608c7f02f80 112 #define setReadDir() { }
davidprentice 0:b608c7f02f80 113 //#define flush()
davidprentice 0:b608c7f02f80 114 //#define write8(x) xchg8(x)
davidprentice 0:b608c7f02f80 115 //#define xchg8(x) SPI.transfer(x)
davidprentice 0:b608c7f02f80 116 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
davidprentice 0:b608c7f02f80 117 #define READ_8(dst) { dst = xchg8(0); }
davidprentice 0:b608c7f02f80 118 #define READ_16(dst) { dst = xchg8(0); dst = (dst << 8) | xchg8(0); }
davidprentice 0:b608c7f02f80 119
davidprentice 0:b608c7f02f80 120 // Shield Control macros.
davidprentice 0:b608c7f02f80 121 #define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin))
davidprentice 0:b608c7f02f80 122 #define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin))
davidprentice 0:b608c7f02f80 123 #define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin))
davidprentice 0:b608c7f02f80 124
davidprentice 0:b608c7f02f80 125 #elif defined(__AVR_ATxmega128A1__) //3.49s @ 32MHz -O2
davidprentice 0:b608c7f02f80 126 #define CD_PORT VPORT2
davidprentice 0:b608c7f02f80 127 #define CD_PIN 1
davidprentice 0:b608c7f02f80 128 #define CS_PORT VPORT3
davidprentice 0:b608c7f02f80 129 #define CS_PIN 4
davidprentice 0:b608c7f02f80 130 #define RESET_PORT VPORT2
davidprentice 0:b608c7f02f80 131 #define RESET_PIN 0
davidprentice 0:b608c7f02f80 132 #define SPCRVAL (USART_CLK2X_bm | USART_RXEN_bm | USART_TXEN_bm)
davidprentice 0:b608c7f02f80 133 #define SETDDR {VPORT3.DIR |= (1<<4)|(1<<5)|(1<<7); VPORT2.DIR |= 0x03; }
davidprentice 0:b608c7f02f80 134 #define SPI_INIT() { PORTCFG.VPCTRLB=PORTCFG_VP3MAP_PORTF_gc | PORTCFG_VP2MAP_PORTC_gc; CS_IDLE; RESET_IDLE; SETDDR; spi_init(); }
davidprentice 0:b608c7f02f80 135
davidprentice 0:b608c7f02f80 136 void spi_init(void)
davidprentice 0:b608c7f02f80 137 {
davidprentice 0:b608c7f02f80 138 SPIF.CTRL=SPI_ENABLE_bm | SPI_MODE_3_gc | (1<<SPI_MASTER_bp) | (1<<SPI_CLK2X_bp);
davidprentice 0:b608c7f02f80 139 }
davidprentice 0:b608c7f02f80 140
davidprentice 0:b608c7f02f80 141 #define write8(x) {\
davidprentice 0:b608c7f02f80 142 SPIF.DATA=x;\
davidprentice 0:b608c7f02f80 143 while ((SPIF.STATUS & SPI_IF_bm)==0);\
davidprentice 0:b608c7f02f80 144 SPIF.DATA;\
davidprentice 0:b608c7f02f80 145 }
davidprentice 0:b608c7f02f80 146 #define flush() {\
davidprentice 0:b608c7f02f80 147 }
davidprentice 0:b608c7f02f80 148
davidprentice 0:b608c7f02f80 149 #define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
davidprentice 0:b608c7f02f80 150 #define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
davidprentice 0:b608c7f02f80 151 #define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
davidprentice 0:b608c7f02f80 152
davidprentice 0:b608c7f02f80 153 #elif defined(__AVR_ATxmega32A4U__) //3.49s @ 32MHz -O2.
davidprentice 0:b608c7f02f80 154 // 100ns/150ns for ILI9341 W/R cycle. 100ns/200ns for ILI920. 20ns/150ns HX8347
davidprentice 0:b608c7f02f80 155 // Xmega @ 60MHz i.e. 30MHz SCK works with 9341.
davidprentice 0:b608c7f02f80 156 #warning Using ATxmega32A4U USART_MSPI
davidprentice 0:b608c7f02f80 157 #define CD_PORT VPORT2
davidprentice 0:b608c7f02f80 158 #define CD_PIN 1
davidprentice 0:b608c7f02f80 159 #define CS_PORT VPORT3
davidprentice 0:b608c7f02f80 160 #define CS_PIN 0
davidprentice 0:b608c7f02f80 161 #define RESET_PORT VPORT2
davidprentice 0:b608c7f02f80 162 #define RESET_PIN 0
davidprentice 0:b608c7f02f80 163 #define SD_PORT PORTC
davidprentice 0:b608c7f02f80 164 #define SD_PIN 4
davidprentice 0:b608c7f02f80 165 #define SPCRVAL (USART_CLK2X_bm | USART_RXEN_bm | USART_TXEN_bm)
davidprentice 0:b608c7f02f80 166 #define SETDDR {PORTCFG.VPCTRLB=PORTCFG_VP13MAP_PORTD_gc | PORTCFG_VP02MAP_PORTC_gc; VPORT3.DIR |= (1<<0)|(1<<1)|(1<<3); VPORT2.DIR |= 0x03; PIN_HIGH(SD_PORT, SD_PIN); SD_PORT.DIR |= (1<<SD_PIN); }
davidprentice 0:b608c7f02f80 167 #define SPI_INIT() { CS_IDLE; RESET_IDLE; SETDDR; spi_init(); }
davidprentice 0:b608c7f02f80 168
davidprentice 0:b608c7f02f80 169 static inline void spi_init(void)
davidprentice 0:b608c7f02f80 170 {
davidprentice 0:b608c7f02f80 171 USARTD0.CTRLB = SPCRVAL;
davidprentice 0:b608c7f02f80 172 USARTD0.CTRLC = USART_CMODE_MSPI_gc | 0x00 | 0x00; //mode #0
davidprentice 0:b608c7f02f80 173 // PORTD.PIN1CTRL |= PORT_INVEN_bm; //CPOL
davidprentice 0:b608c7f02f80 174 USARTD0.BAUDCTRLA = 0x00; //F_CPU/2
davidprentice 0:b608c7f02f80 175 USARTD0.BAUDCTRLB = ((0x00 << USART_BSCALE_gp) & USART_BSCALE_gm) | 0x00;
davidprentice 0:b608c7f02f80 176 USARTD0.DATA;
davidprentice 0:b608c7f02f80 177 }
davidprentice 0:b608c7f02f80 178
davidprentice 0:b608c7f02f80 179 extern uint8_t running;
davidprentice 0:b608c7f02f80 180
davidprentice 0:b608c7f02f80 181 #define write8(x) {\
davidprentice 0:b608c7f02f80 182 while ((USARTD0.STATUS & USART_DREIF_bm) == 0) ;\
davidprentice 0:b608c7f02f80 183 asm("cli");\
davidprentice 0:b608c7f02f80 184 USARTD0.DATA = x;\
davidprentice 0:b608c7f02f80 185 USARTD0.STATUS = USART_TXCIF_bm;\
davidprentice 0:b608c7f02f80 186 asm("sei");\
davidprentice 0:b608c7f02f80 187 running = 1;\
davidprentice 0:b608c7f02f80 188 }
davidprentice 0:b608c7f02f80 189 static inline uint8_t read8(void) {
davidprentice 0:b608c7f02f80 190 if (running) while ((USARTD0.STATUS & USART_RXCIF_bm) == 0) ;
davidprentice 0:b608c7f02f80 191 return USARTD0.DATA;
davidprentice 0:b608c7f02f80 192 }
davidprentice 0:b608c7f02f80 193 #define flush() {\
davidprentice 0:b608c7f02f80 194 if (running) while ((USARTD0.STATUS & USART_TXCIF_bm) == 0) ;\
davidprentice 0:b608c7f02f80 195 while ((USARTD0.STATUS & USART_RXCIF_bm) != 0) USARTD0.DATA;\
davidprentice 0:b608c7f02f80 196 running = 0;\
davidprentice 0:b608c7f02f80 197 }
davidprentice 0:b608c7f02f80 198 static inline uint8_t xchg8(uint8_t x) {
davidprentice 0:b608c7f02f80 199 USARTD0.DATA = x;
davidprentice 0:b608c7f02f80 200 while ((USARTD0.STATUS & USART_RXCIF_bm) == 0) ;
davidprentice 0:b608c7f02f80 201 return USARTD0.DATA;
davidprentice 0:b608c7f02f80 202 }
davidprentice 0:b608c7f02f80 203 /*
davidprentice 0:b608c7f02f80 204 #define write8(x) {\
davidprentice 0:b608c7f02f80 205 while ((USARTD0.STATUS & USART_DREIF_bm) == 0) ;\
davidprentice 0:b608c7f02f80 206 USARTD0.DATA = x;\
davidprentice 0:b608c7f02f80 207 while ((USARTD0.STATUS & USART_RXCIF_bm) == 0) ;\
davidprentice 0:b608c7f02f80 208 USARTD0.DATA;\
davidprentice 0:b608c7f02f80 209 }
davidprentice 0:b608c7f02f80 210 #define flush()
davidprentice 0:b608c7f02f80 211 */
davidprentice 0:b608c7f02f80 212
davidprentice 0:b608c7f02f80 213 #define RD_IDLE
davidprentice 0:b608c7f02f80 214 #define WR_IDLE
davidprentice 0:b608c7f02f80 215 //#define SPI_INIT() spi_init()
davidprentice 0:b608c7f02f80 216 #define setWriteDir() { }
davidprentice 0:b608c7f02f80 217 #define setReadDir() { }
davidprentice 0:b608c7f02f80 218 //#define write8(x) spi_xfer(x)
davidprentice 0:b608c7f02f80 219 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
davidprentice 0:b608c7f02f80 220 #define READ_8(dst) { dst = xchg8(0); }
davidprentice 0:b608c7f02f80 221 #define READ_16(dst) { dst = xchg8(0); dst = (dst << 8) | xchg8(0); }
davidprentice 0:b608c7f02f80 222
davidprentice 0:b608c7f02f80 223 #define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
davidprentice 0:b608c7f02f80 224 #define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
davidprentice 0:b608c7f02f80 225 #define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
davidprentice 0:b608c7f02f80 226
davidprentice 0:b608c7f02f80 227 #endif
davidprentice 0:b608c7f02f80 228
davidprentice 0:b608c7f02f80 229 #define CD_COMMAND {flush(); PIN_LOW(CD_PORT, CD_PIN); }
davidprentice 0:b608c7f02f80 230 #define CD_DATA {flush(); PIN_HIGH(CD_PORT, CD_PIN); }
davidprentice 0:b608c7f02f80 231 #define CD_OUTPUT PIN_OUTPUT(CD_PORT, CD_PIN)
davidprentice 0:b608c7f02f80 232 #define CS_ACTIVE PIN_LOW(CS_PORT, CS_PIN)
davidprentice 0:b608c7f02f80 233 #define CS_IDLE {flush(); PIN_HIGH(CS_PORT, CS_PIN); }
davidprentice 0:b608c7f02f80 234 #define CS_OUTPUT PIN_OUTPUT(CS_PORT, CS_PIN)
davidprentice 0:b608c7f02f80 235 #define RESET_ACTIVE PIN_LOW(RESET_PORT, RESET_PIN)
davidprentice 0:b608c7f02f80 236 #define RESET_IDLE PIN_HIGH(RESET_PORT, RESET_PIN)
davidprentice 0:b608c7f02f80 237 #define RESET_OUTPUT PIN_OUTPUT(RESET_PORT, RESET_PIN)
davidprentice 0:b608c7f02f80 238
davidprentice 0:b608c7f02f80 239 // General macros. IOCLR registers are 1 cycle when optimised.
davidprentice 0:b608c7f02f80 240
davidprentice 0:b608c7f02f80 241 #define CTL_INIT() { CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; SPI_INIT(); }
davidprentice 0:b608c7f02f80 242 #define WriteCmd(x) { CD_COMMAND; write8(x); }
davidprentice 0:b608c7f02f80 243 #define WriteData(x) { CD_DATA; write16(x); }