David Prentice / Mbed 2 deprecated Nucleo_dir_L152

Please run it on your NUCLEO-L152

Dependencies:   mbed

MCUFRIEND_kbv/utility/mcufriend_keil.h@0:b608c7f02f80, 2019-09-18 (annotated)

Committer:
davidprentice
Date:
Wed Sep 18 10:26:00 2019 +0000
Revision:
0:b608c7f02f80
add L152 to utility/pin_shield_?.h; otherwise MCUFRIEND_kbv from Beta on GitHub

Who changed what in which revision?

UserRevisionLine numberNew contents of line
davidprentice 0:b608c7f02f80 1 #ifndef MCUFRIEND_KEIL_H_
davidprentice 0:b608c7f02f80 2 #define MCUFRIEND_KEIL_H_
davidprentice 0:b608c7f02f80 3
davidprentice 0:b608c7f02f80 4 #if defined(USE_SERIAL)
davidprentice 0:b608c7f02f80 5 #include "mcufriend_keil_spi.h"
davidprentice 0:b608c7f02f80 6 #else
davidprentice 0:b608c7f02f80 7 #include "pin_shield_1.h" //shield pin macros e.g. A2_PORT, PIN_OUTPUT()
davidprentice 0:b608c7f02f80 8 #include "pin_shield_8.h" //macros for write_8(), read_8(), setWriteDir(), ...
davidprentice 0:b608c7f02f80 9
davidprentice 0:b608c7f02f80 10 // control pins as used in MCUFRIEND shields
davidprentice 0:b608c7f02f80 11 #define RD_PORT A0_PORT
davidprentice 0:b608c7f02f80 12 #define RD_PIN A0_PIN
davidprentice 0:b608c7f02f80 13 #define WR_PORT A1_PORT
davidprentice 0:b608c7f02f80 14 #define WR_PIN A1_PIN
davidprentice 0:b608c7f02f80 15 #define CD_PORT A2_PORT
davidprentice 0:b608c7f02f80 16 #define CD_PIN A2_PIN
davidprentice 0:b608c7f02f80 17 #define CS_PORT A3_PORT
davidprentice 0:b608c7f02f80 18 #define CS_PIN A3_PIN
davidprentice 0:b608c7f02f80 19 #define RESET_PORT A4_PORT
davidprentice 0:b608c7f02f80 20 #define RESET_PIN A4_PIN
davidprentice 0:b608c7f02f80 21
davidprentice 0:b608c7f02f80 22 // general purpose pin macros
davidprentice 0:b608c7f02f80 23 #define RD_ACTIVE PIN_LOW(RD_PORT, RD_PIN)
davidprentice 0:b608c7f02f80 24 #define RD_IDLE PIN_HIGH(RD_PORT, RD_PIN)
davidprentice 0:b608c7f02f80 25 #define RD_OUTPUT PIN_OUTPUT(RD_PORT, RD_PIN)
davidprentice 0:b608c7f02f80 26 #define WR_ACTIVE PIN_LOW(WR_PORT, WR_PIN)
davidprentice 0:b608c7f02f80 27 #define WR_IDLE PIN_HIGH(WR_PORT, WR_PIN)
davidprentice 0:b608c7f02f80 28 #define WR_OUTPUT PIN_OUTPUT(WR_PORT, WR_PIN)
davidprentice 0:b608c7f02f80 29 #define CD_COMMAND PIN_LOW(CD_PORT, CD_PIN)
davidprentice 0:b608c7f02f80 30 #define CD_DATA PIN_HIGH(CD_PORT, CD_PIN)
davidprentice 0:b608c7f02f80 31 #define CD_OUTPUT PIN_OUTPUT(CD_PORT, CD_PIN)
davidprentice 0:b608c7f02f80 32 #define CS_ACTIVE PIN_LOW(CS_PORT, CS_PIN)
davidprentice 0:b608c7f02f80 33 #define CS_IDLE PIN_HIGH(CS_PORT, CS_PIN)
davidprentice 0:b608c7f02f80 34 #define CS_OUTPUT PIN_OUTPUT(CS_PORT, CS_PIN)
davidprentice 0:b608c7f02f80 35 #define RESET_ACTIVE PIN_LOW(RESET_PORT, RESET_PIN)
davidprentice 0:b608c7f02f80 36 #define RESET_IDLE PIN_HIGH(RESET_PORT, RESET_PIN)
davidprentice 0:b608c7f02f80 37 #define RESET_OUTPUT PIN_OUTPUT(RESET_PORT, RESET_PIN)
davidprentice 0:b608c7f02f80 38
davidprentice 0:b608c7f02f80 39 #define WR_ACTIVE2 {WR_ACTIVE; WR_ACTIVE;}
davidprentice 0:b608c7f02f80 40 #define WR_ACTIVE4 {WR_ACTIVE2; WR_ACTIVE2;}
davidprentice 0:b608c7f02f80 41 #define WR_ACTIVE8 {WR_ACTIVE4; WR_ACTIVE4;}
davidprentice 0:b608c7f02f80 42 #define RD_ACTIVE2 {RD_ACTIVE; RD_ACTIVE;}
davidprentice 0:b608c7f02f80 43 #define RD_ACTIVE4 {RD_ACTIVE2; RD_ACTIVE2;}
davidprentice 0:b608c7f02f80 44 #define RD_ACTIVE8 {RD_ACTIVE4; RD_ACTIVE4;}
davidprentice 0:b608c7f02f80 45 #define RD_ACTIVE16 {RD_ACTIVE8; RD_ACTIVE8;}
davidprentice 0:b608c7f02f80 46 #define WR_IDLE2 {WR_IDLE; WR_IDLE;}
davidprentice 0:b608c7f02f80 47 #define WR_IDLE4 {WR_IDLE2; WR_IDLE2;}
davidprentice 0:b608c7f02f80 48 #define RD_IDLE2 {RD_IDLE; RD_IDLE;}
davidprentice 0:b608c7f02f80 49 #define RD_IDLE4 {RD_IDLE2; RD_IDLE2;}
davidprentice 0:b608c7f02f80 50
davidprentice 0:b608c7f02f80 51 // General macros. IOCLR registers are 1 cycle when optimised.
davidprentice 0:b608c7f02f80 52 #define WR_STROBE { WR_ACTIVE; WR_IDLE; } //PWLW=TWRL=50ns
davidprentice 0:b608c7f02f80 53 #define RD_STROBE RD_IDLE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE //PWLR=TRDL=150ns
davidprentice 0:b608c7f02f80 54
davidprentice 0:b608c7f02f80 55 #if defined(TEENSY) || defined(__ARM_ARCH_7EM__) // -O2: F411@100MHz = 1.44s
davidprentice 0:b608c7f02f80 56 //#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; }
davidprentice 0:b608c7f02f80 57 //#define READ_DELAY { RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; }
davidprentice 0:b608c7f02f80 58 #if 0
davidprentice 0:b608c7f02f80 59 #elif defined(STM32F401xx)
davidprentice 0:b608c7f02f80 60 #warning 84MHz
davidprentice 0:b608c7f02f80 61 #define WRITE_DELAY { WR_ACTIVE2; } //100MHz
davidprentice 0:b608c7f02f80 62 #define READ_DELAY { RD_ACTIVE4; }
davidprentice 0:b608c7f02f80 63 #elif defined(STM32F411xx)
davidprentice 0:b608c7f02f80 64 #define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //100MHz
davidprentice 0:b608c7f02f80 65 #define READ_DELAY { RD_ACTIVE4; RD_ACTIVE2; }
davidprentice 0:b608c7f02f80 66 #elif defined(STM32F446xx)
davidprentice 0:b608c7f02f80 67 #warning 180MHz
davidprentice 0:b608c7f02f80 68 #define WRITE_DELAY { WR_ACTIVE8; } //180MHz
davidprentice 0:b608c7f02f80 69 #define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
davidprentice 0:b608c7f02f80 70 #define READ_DELAY { RD_ACTIVE16;}
davidprentice 0:b608c7f02f80 71 #elif defined(STM32F767xx)
davidprentice 0:b608c7f02f80 72 #warning 216MHz
davidprentice 0:b608c7f02f80 73 #define WRITE_DELAY { WR_ACTIVE8; WR_ACTIVE8; } //216MHz
davidprentice 0:b608c7f02f80 74 #define IDLE_DELAY { WR_IDLE4;WR_IDLE4; }
davidprentice 0:b608c7f02f80 75 #define READ_DELAY { RD_ACTIVE16;RD_ACTIVE16;RD_ACTIVE16;}
davidprentice 0:b608c7f02f80 76 #elif defined(STM32H743xx) //STM32H743 GPIO needs testing
davidprentice 0:b608c7f02f80 77 #define WRITE_DELAY { WR_ACTIVE8;WR_ACTIVE2; } //F_CPU=400MHz
davidprentice 0:b608c7f02f80 78 #define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
davidprentice 0:b608c7f02f80 79 #define READ_DELAY { RD_ACTIVE16;RD_ACTIVE16;RD_ACTIVE4;}
davidprentice 0:b608c7f02f80 80 #else
davidprentice 0:b608c7f02f80 81 #error check specific STM32
davidprentice 0:b608c7f02f80 82 #endif
davidprentice 0:b608c7f02f80 83 #elif defined(__ARM_ARCH_7M__) // -O2: F103@72MHz = 2.68s
davidprentice 0:b608c7f02f80 84 #define WRITE_DELAY { }
davidprentice 0:b608c7f02f80 85 #define READ_DELAY { RD_ACTIVE; }
davidprentice 0:b608c7f02f80 86 #elif defined(__ARM_ARCH_6M__) // -O2: F072@48MHz = 5.03s
davidprentice 0:b608c7f02f80 87 #define WRITE_DELAY { }
davidprentice 0:b608c7f02f80 88 #define READ_DELAY { }
davidprentice 0:b608c7f02f80 89 #endif
davidprentice 0:b608c7f02f80 90
davidprentice 0:b608c7f02f80 91 #ifndef IDLE_DELAY
davidprentice 0:b608c7f02f80 92 #define IDLE_DELAY { WR_IDLE; }
davidprentice 0:b608c7f02f80 93 #endif
davidprentice 0:b608c7f02f80 94
davidprentice 0:b608c7f02f80 95 #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; IDLE_DELAY; }
davidprentice 0:b608c7f02f80 96 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
davidprentice 0:b608c7f02f80 97 #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE2; RD_IDLE; } // read 250ns after RD_ACTIVE goes low
davidprentice 0:b608c7f02f80 98 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
davidprentice 0:b608c7f02f80 99
davidprentice 0:b608c7f02f80 100 #define CTL_INIT() { RD_OUTPUT; WR_OUTPUT; CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; }
davidprentice 0:b608c7f02f80 101 #define WriteCmd(x) { CD_COMMAND; write16(x); CD_DATA; }
davidprentice 0:b608c7f02f80 102 #define WriteData(x) { write16(x); }
davidprentice 0:b608c7f02f80 103
davidprentice 0:b608c7f02f80 104 #endif //!USE_SERIAL
davidprentice 0:b608c7f02f80 105 #endif //MCUFRIEND_KEIL_H_