david childs / FT800_3

updated for FT810 and 800x480 display

Dependents:   FT810_RGB_demo FT81x_TripComp_test FT810_LoadJPG

Fork of FT800_2 by Peter Drescher

FT_Gpu_Hal.cpp@7:a69ac4d39afd, 2016-02-24 (annotated)

Committer:
davidchilds
Date:
Wed Feb 24 14:04:34 2016 +0000
Revision:
7:a69ac4d39afd
Parent:
6:16e22c789f7d 
The updated library for FT810 with 800x480 display; Thanks to FTDI and Peter Drescher for getting this far

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dreschpe 2:ab74a9a05970 1 /* mbed Library for FTDI FT800 Enbedded Video Engine "EVE"
dreschpe 3:392d2c733c68 2 * based on Original Code Sample from FTDI
dreschpe 2:ab74a9a05970 3 * ported to mbed by Peter Drescher, DC2PD 2014
dreschpe 3:392d2c733c68 4 * Released under the MIT License: http://mbed.org/license/mit
dreschpe 3:392d2c733c68 5 * 19.09.14 changed to shorter function names
dreschpe 3:392d2c733c68 6 * FTDI was using very long names.
dreschpe 3:392d2c733c68 7 * Ft_App_Flush_Co_Buffer -> Flush_Co_Buffer ... */
dreschpe 3:392d2c733c68 8
dreschpe 0:5e013296b353 9 #include "FT_Platform.h"
dreschpe 0:5e013296b353 10 #include "mbed.h"
dreschpe 0:5e013296b353 11 #include "FT_LCD_Type.h"
davidchilds 7:a69ac4d39afd 12 Serial pc(USBTX, USBRX);
dreschpe 0:5e013296b353 13
dreschpe 0:5e013296b353 14 FT800::FT800(PinName mosi,
dreschpe 0:5e013296b353 15 PinName miso,
dreschpe 0:5e013296b353 16 PinName sck,
dreschpe 0:5e013296b353 17 PinName ss,
dreschpe 0:5e013296b353 18 PinName intr,
dreschpe 0:5e013296b353 19 PinName pd)
dreschpe 3:392d2c733c68 20 :
dreschpe 3:392d2c733c68 21 _spi(mosi, miso, sck),
dreschpe 0:5e013296b353 22 _ss(ss),
dreschpe 3:392d2c733c68 23 _pd(pd),
dreschpe 3:392d2c733c68 24 _f800_isr(InterruptIn(intr))
dreschpe 0:5e013296b353 25 {
dreschpe 0:5e013296b353 26 _spi.format(8,0); // 8 bit spi mode 0
davidchilds 7:a69ac4d39afd 27 _spi.frequency(1000000); // start with 10 Mhz SPI clock
dreschpe 0:5e013296b353 28 _ss = 1; // cs high
dreschpe 3:392d2c733c68 29 _pd = 1; // PD high
dreschpe 3:392d2c733c68 30 Bootup();
dreschpe 0:5e013296b353 31 }
dreschpe 0:5e013296b353 32
dreschpe 0:5e013296b353 33
dreschpe 0:5e013296b353 34 ft_bool_t FT800::Bootup(void){
dreschpe 3:392d2c733c68 35 Open();
dreschpe 0:5e013296b353 36 BootupConfig();
dreschpe 3:392d2c733c68 37
dreschpe 0:5e013296b353 38 return(1);
dreschpe 0:5e013296b353 39 }
dreschpe 3:392d2c733c68 40
dreschpe 0:5e013296b353 41
dreschpe 0:5e013296b353 42 ft_void_t FT800::BootupConfig(void){
dreschpe 0:5e013296b353 43 ft_uint8_t chipid;
dreschpe 0:5e013296b353 44 /* Do a power cycle for safer side */
dreschpe 3:392d2c733c68 45 Powercycle( FT_TRUE);
dreschpe 0:5e013296b353 46
dreschpe 0:5e013296b353 47 /* Set the clk to external clock */
dreschpe 3:392d2c733c68 48 HostCommand( FT_GPU_EXTERNAL_OSC);
dreschpe 3:392d2c733c68 49 Sleep(10);
davidchilds 7:a69ac4d39afd 50
davidchilds 7:a69ac4d39afd 51 /* Access address 0 to wake up the FT800 */
davidchilds 7:a69ac4d39afd 52 HostCommand( FT_GPU_ACTIVE_M);
davidchilds 7:a69ac4d39afd 53 Sleep(500);
dreschpe 0:5e013296b353 54
dreschpe 0:5e013296b353 55 /* Switch PLL output to 48MHz */
davidchilds 7:a69ac4d39afd 56 // HostCommand( FT_GPU_PLL_48M);
dreschpe 3:392d2c733c68 57 Sleep(10);
dreschpe 0:5e013296b353 58
dreschpe 0:5e013296b353 59 /* Do a core reset for safer side */
dreschpe 3:392d2c733c68 60 HostCommand( FT_GPU_CORE_RESET);
davidchilds 7:a69ac4d39afd 61 Sleep(500);
dreschpe 3:392d2c733c68 62 //Read Register ID to check if FT800 is ready.
dreschpe 3:392d2c733c68 63 chipid = Rd8( REG_ID);
davidchilds 7:a69ac4d39afd 64 // chipid = Rd8(0x0C0000);
davidchilds 7:a69ac4d39afd 65 pc.printf("ID%08X\n", chipid);
dreschpe 0:5e013296b353 66 while(chipid != 0x7C)
dreschpe 3:392d2c733c68 67
dreschpe 0:5e013296b353 68
dreschpe 3:392d2c733c68 69 // Speed up
davidchilds 7:a69ac4d39afd 70 // _spi.frequency(20000000); // 20 Mhz SPI clock DC
davidchilds 7:a69ac4d39afd 71 _spi.frequency(12000000); // 20 Mhz SPI clock
dreschpe 0:5e013296b353 72 /* Configuration of LCD display */
dreschpe 3:392d2c733c68 73 DispHCycle = my_DispHCycle;
dreschpe 3:392d2c733c68 74 Wr16( REG_HCYCLE, DispHCycle);
dreschpe 3:392d2c733c68 75 DispHOffset = my_DispHOffset;
dreschpe 3:392d2c733c68 76 Wr16( REG_HOFFSET, DispHOffset);
dreschpe 3:392d2c733c68 77 DispWidth = my_DispWidth;
dreschpe 3:392d2c733c68 78 Wr16( REG_HSIZE, DispWidth);
dreschpe 3:392d2c733c68 79 DispHSync0 = my_DispHSync0;
dreschpe 3:392d2c733c68 80 Wr16( REG_HSYNC0, DispHSync0);
dreschpe 3:392d2c733c68 81 DispHSync1 = my_DispHSync1;
dreschpe 3:392d2c733c68 82 Wr16( REG_HSYNC1, DispHSync1);
dreschpe 3:392d2c733c68 83 DispVCycle = my_DispVCycle;
dreschpe 3:392d2c733c68 84 Wr16( REG_VCYCLE, DispVCycle);
dreschpe 3:392d2c733c68 85 DispVOffset = my_DispVOffset;
dreschpe 3:392d2c733c68 86 Wr16( REG_VOFFSET, DispVOffset);
dreschpe 3:392d2c733c68 87 DispHeight = my_DispHeight;
dreschpe 3:392d2c733c68 88 Wr16( REG_VSIZE, DispHeight);
dreschpe 3:392d2c733c68 89 DispVSync0 = my_DispVSync0;
dreschpe 3:392d2c733c68 90 Wr16( REG_VSYNC0, DispVSync0);
dreschpe 3:392d2c733c68 91 DispVSync1 = my_DispVSync1;
dreschpe 3:392d2c733c68 92 Wr16( REG_VSYNC1, DispVSync1);
dreschpe 3:392d2c733c68 93 DispSwizzle = my_DispSwizzle;
dreschpe 4:363ec27cdfaa 94 Wr8( REG_SWIZZLE, DispSwizzle);
dreschpe 3:392d2c733c68 95 DispPCLKPol = my_DispPCLKPol;
dreschpe 4:363ec27cdfaa 96 Wr8( REG_PCLK_POL, DispPCLKPol);
dreschpe 4:363ec27cdfaa 97 Wr8( REG_CSPREAD, 1);
dreschpe 3:392d2c733c68 98 DispPCLK = my_DispPCLK;
dreschpe 4:363ec27cdfaa 99 Wr8( REG_PCLK, DispPCLK);//after this display is visible on the LCD
dreschpe 0:5e013296b353 100
dreschpe 3:392d2c733c68 101 Wr16( REG_PWM_HZ, 1000);
dreschpe 3:392d2c733c68 102
dreschpe 3:392d2c733c68 103 #ifdef Inv_Backlite // turn on backlite
dreschpe 3:392d2c733c68 104 Wr16( REG_PWM_DUTY, 0);
dreschpe 0:5e013296b353 105 #else
dreschpe 3:392d2c733c68 106 Wr16( REG_PWM_DUTY, 100);
dreschpe 3:392d2c733c68 107 #endif
dreschpe 3:392d2c733c68 108
dreschpe 3:392d2c733c68 109 Wr8( REG_GPIO_DIR,0x82); //| Rd8( REG_GPIO_DIR));
dreschpe 3:392d2c733c68 110 Wr8( REG_GPIO,0x080); //| Rd8( REG_GPIO));
dreschpe 3:392d2c733c68 111
dreschpe 3:392d2c733c68 112 Wr32( RAM_DL, CLEAR(1,1,1));
dreschpe 3:392d2c733c68 113 Wr32( RAM_DL+4, DISPLAY());
dreschpe 3:392d2c733c68 114 Wr32( REG_DLSWAP,1);
dreschpe 3:392d2c733c68 115
dreschpe 3:392d2c733c68 116 Wr16( REG_PCLK, DispPCLK);
dreschpe 3:392d2c733c68 117
dreschpe 0:5e013296b353 118 /* Touch configuration - configure the resistance value to 1200 - this value is specific to customer requirement and derived by experiment */
dreschpe 3:392d2c733c68 119 Wr16( REG_TOUCH_RZTHRESH,1200);
dreschpe 0:5e013296b353 120
dreschpe 0:5e013296b353 121 }
dreschpe 0:5e013296b353 122
dreschpe 0:5e013296b353 123
dreschpe 0:5e013296b353 124
dreschpe 0:5e013296b353 125 /* API to initialize the SPI interface */
dreschpe 3:392d2c733c68 126 ft_bool_t FT800::Init()
dreschpe 0:5e013296b353 127 {
dreschpe 0:5e013296b353 128 // is done in constructor
dreschpe 0:5e013296b353 129 return 1;
dreschpe 0:5e013296b353 130 }
dreschpe 0:5e013296b353 131
dreschpe 0:5e013296b353 132
dreschpe 3:392d2c733c68 133 ft_bool_t FT800::Open()
dreschpe 0:5e013296b353 134 {
dreschpe 3:392d2c733c68 135 cmd_fifo_wp = dl_buff_wp = 0;
dreschpe 3:392d2c733c68 136 status = OPENED;
dreschpe 0:5e013296b353 137 return 1;
dreschpe 0:5e013296b353 138 }
dreschpe 0:5e013296b353 139
dreschpe 3:392d2c733c68 140 ft_void_t FT800::Close( )
dreschpe 0:5e013296b353 141 {
dreschpe 3:392d2c733c68 142 status = CLOSED;
dreschpe 0:5e013296b353 143 }
dreschpe 0:5e013296b353 144
dreschpe 3:392d2c733c68 145 ft_void_t FT800::DeInit()
dreschpe 0:5e013296b353 146 {
dreschpe 0:5e013296b353 147
dreschpe 0:5e013296b353 148 }
dreschpe 0:5e013296b353 149
dreschpe 0:5e013296b353 150 /*The APIs for reading/writing transfer continuously only with small buffer system*/
dreschpe 3:392d2c733c68 151 ft_void_t FT800::StartTransfer( FT_GPU_TRANSFERDIR_T rw,ft_uint32_t addr)
dreschpe 0:5e013296b353 152 {
dreschpe 0:5e013296b353 153 if (FT_GPU_READ == rw){
dreschpe 0:5e013296b353 154 _ss = 0; // cs low
dreschpe 0:5e013296b353 155 _spi.write(addr >> 16);
dreschpe 0:5e013296b353 156 _spi.write(addr >> 8);
dreschpe 0:5e013296b353 157 _spi.write(addr & 0xff);
dreschpe 0:5e013296b353 158 _spi.write(0); //Dummy Read Byte
dreschpe 3:392d2c733c68 159 status = READING;
dreschpe 0:5e013296b353 160 }else{
dreschpe 0:5e013296b353 161 _ss = 0; // cs low
dreschpe 0:5e013296b353 162 _spi.write(0x80 | (addr >> 16));
dreschpe 0:5e013296b353 163 _spi.write(addr >> 8);
dreschpe 0:5e013296b353 164 _spi.write(addr & 0xff);
dreschpe 3:392d2c733c68 165 status = WRITING;
dreschpe 0:5e013296b353 166 }
dreschpe 0:5e013296b353 167 }
dreschpe 0:5e013296b353 168
dreschpe 0:5e013296b353 169
dreschpe 0:5e013296b353 170 /*The APIs for writing transfer continuously only*/
dreschpe 3:392d2c733c68 171 ft_void_t FT800::StartCmdTransfer( FT_GPU_TRANSFERDIR_T rw, ft_uint16_t count)
dreschpe 0:5e013296b353 172 {
dreschpe 3:392d2c733c68 173 StartTransfer( rw, cmd_fifo_wp + RAM_CMD);
dreschpe 0:5e013296b353 174 }
dreschpe 0:5e013296b353 175
dreschpe 3:392d2c733c68 176 ft_uint8_t FT800::TransferString( const ft_char8_t *string)
dreschpe 0:5e013296b353 177 {
dreschpe 0:5e013296b353 178 ft_uint16_t length = strlen(string);
dreschpe 0:5e013296b353 179 while(length --){
dreschpe 3:392d2c733c68 180 Transfer8( *string);
dreschpe 0:5e013296b353 181 string ++;
dreschpe 0:5e013296b353 182 }
dreschpe 0:5e013296b353 183 //Append one null as ending flag
dreschpe 3:392d2c733c68 184 Transfer8( 0);
dreschpe 3:392d2c733c68 185 return(1);
dreschpe 0:5e013296b353 186 }
dreschpe 0:5e013296b353 187
dreschpe 0:5e013296b353 188
dreschpe 3:392d2c733c68 189 ft_uint8_t FT800::Transfer8( ft_uint8_t value)
dreschpe 0:5e013296b353 190 {
dreschpe 3:392d2c733c68 191 return _spi.write(value);
dreschpe 0:5e013296b353 192 }
dreschpe 0:5e013296b353 193
dreschpe 0:5e013296b353 194
dreschpe 3:392d2c733c68 195 ft_uint16_t FT800::Transfer16( ft_uint16_t value)
dreschpe 0:5e013296b353 196 {
dreschpe 0:5e013296b353 197 ft_uint16_t retVal = 0;
dreschpe 0:5e013296b353 198
dreschpe 3:392d2c733c68 199 if (status == WRITING){
dreschpe 3:392d2c733c68 200 Transfer8( value & 0xFF);//LSB first
dreschpe 3:392d2c733c68 201 Transfer8( (value >> 8) & 0xFF);
dreschpe 0:5e013296b353 202 }else{
dreschpe 3:392d2c733c68 203 retVal = Transfer8( 0);
dreschpe 3:392d2c733c68 204 retVal |= (ft_uint16_t)Transfer8( 0) << 8;
dreschpe 0:5e013296b353 205 }
dreschpe 0:5e013296b353 206
dreschpe 0:5e013296b353 207 return retVal;
dreschpe 0:5e013296b353 208 }
dreschpe 0:5e013296b353 209
dreschpe 3:392d2c733c68 210 ft_uint32_t FT800::Transfer32( ft_uint32_t value)
dreschpe 0:5e013296b353 211 {
dreschpe 0:5e013296b353 212 ft_uint32_t retVal = 0;
dreschpe 3:392d2c733c68 213 if (status == WRITING){
dreschpe 3:392d2c733c68 214 Transfer16( value & 0xFFFF);//LSB first
dreschpe 3:392d2c733c68 215 Transfer16( (value >> 16) & 0xFFFF);
dreschpe 0:5e013296b353 216 }else{
dreschpe 3:392d2c733c68 217 retVal = Transfer16( 0);
dreschpe 3:392d2c733c68 218 retVal |= (ft_uint32_t)Transfer16( 0) << 16;
dreschpe 0:5e013296b353 219 }
dreschpe 0:5e013296b353 220 return retVal;
dreschpe 0:5e013296b353 221 }
dreschpe 0:5e013296b353 222
dreschpe 3:392d2c733c68 223 ft_void_t FT800::EndTransfer( )
dreschpe 0:5e013296b353 224 {
dreschpe 3:392d2c733c68 225 _ss = 1;
dreschpe 3:392d2c733c68 226 status = OPENED;
dreschpe 0:5e013296b353 227 }
dreschpe 0:5e013296b353 228
dreschpe 0:5e013296b353 229
dreschpe 3:392d2c733c68 230 ft_uint8_t FT800::Rd8( ft_uint32_t addr)
dreschpe 0:5e013296b353 231 {
dreschpe 0:5e013296b353 232 ft_uint8_t value;
dreschpe 3:392d2c733c68 233 StartTransfer( FT_GPU_READ,addr);
dreschpe 3:392d2c733c68 234 value = Transfer8( 0);
dreschpe 3:392d2c733c68 235 EndTransfer( );
dreschpe 0:5e013296b353 236 return value;
dreschpe 0:5e013296b353 237 }
dreschpe 3:392d2c733c68 238 ft_uint16_t FT800::Rd16( ft_uint32_t addr)
dreschpe 0:5e013296b353 239 {
dreschpe 0:5e013296b353 240 ft_uint16_t value;
dreschpe 3:392d2c733c68 241 StartTransfer( FT_GPU_READ,addr);
dreschpe 3:392d2c733c68 242 value = Transfer16( 0);
dreschpe 3:392d2c733c68 243 EndTransfer( );
dreschpe 0:5e013296b353 244 return value;
dreschpe 0:5e013296b353 245 }
dreschpe 3:392d2c733c68 246 ft_uint32_t FT800::Rd32( ft_uint32_t addr)
dreschpe 0:5e013296b353 247 {
dreschpe 0:5e013296b353 248 ft_uint32_t value;
dreschpe 3:392d2c733c68 249 StartTransfer( FT_GPU_READ,addr);
dreschpe 3:392d2c733c68 250 value = Transfer32( 0);
dreschpe 3:392d2c733c68 251 EndTransfer( );
dreschpe 0:5e013296b353 252 return value;
dreschpe 0:5e013296b353 253 }
dreschpe 0:5e013296b353 254
dreschpe 3:392d2c733c68 255 ft_void_t FT800::Wr8( ft_uint32_t addr, ft_uint8_t v)
dreschpe 3:392d2c733c68 256 {
dreschpe 3:392d2c733c68 257 StartTransfer( FT_GPU_WRITE,addr);
dreschpe 3:392d2c733c68 258 Transfer8( v);
dreschpe 3:392d2c733c68 259 EndTransfer( );
dreschpe 0:5e013296b353 260 }
dreschpe 3:392d2c733c68 261 ft_void_t FT800::Wr16( ft_uint32_t addr, ft_uint16_t v)
dreschpe 0:5e013296b353 262 {
dreschpe 3:392d2c733c68 263 StartTransfer( FT_GPU_WRITE,addr);
dreschpe 3:392d2c733c68 264 Transfer16( v);
dreschpe 3:392d2c733c68 265 EndTransfer( );
dreschpe 0:5e013296b353 266 }
dreschpe 3:392d2c733c68 267 ft_void_t FT800::Wr32( ft_uint32_t addr, ft_uint32_t v)
dreschpe 0:5e013296b353 268 {
dreschpe 3:392d2c733c68 269 StartTransfer( FT_GPU_WRITE,addr);
dreschpe 3:392d2c733c68 270 Transfer32( v);
dreschpe 3:392d2c733c68 271 EndTransfer( );
dreschpe 0:5e013296b353 272 }
dreschpe 0:5e013296b353 273
dreschpe 3:392d2c733c68 274 ft_void_t FT800::HostCommand( ft_uint8_t cmd)
dreschpe 0:5e013296b353 275 {
dreschpe 0:5e013296b353 276 _ss = 0;
dreschpe 0:5e013296b353 277 _spi.write(cmd);
dreschpe 0:5e013296b353 278 _spi.write(0);
dreschpe 0:5e013296b353 279 _spi.write(0);
dreschpe 0:5e013296b353 280 _ss = 1;
dreschpe 0:5e013296b353 281 }
dreschpe 0:5e013296b353 282
dreschpe 3:392d2c733c68 283 ft_void_t FT800::ClockSelect( FT_GPU_PLL_SOURCE_T pllsource)
dreschpe 0:5e013296b353 284 {
dreschpe 3:392d2c733c68 285 HostCommand( pllsource);
dreschpe 0:5e013296b353 286 }
dreschpe 0:5e013296b353 287
dreschpe 3:392d2c733c68 288 ft_void_t FT800::PLL_FreqSelect( FT_GPU_PLL_FREQ_T freq)
dreschpe 0:5e013296b353 289 {
dreschpe 3:392d2c733c68 290 HostCommand( freq);
dreschpe 0:5e013296b353 291 }
dreschpe 0:5e013296b353 292
dreschpe 3:392d2c733c68 293 ft_void_t FT800::PowerModeSwitch( FT_GPU_POWER_MODE_T pwrmode)
dreschpe 0:5e013296b353 294 {
dreschpe 3:392d2c733c68 295 HostCommand( pwrmode);
dreschpe 0:5e013296b353 296 }
dreschpe 0:5e013296b353 297
dreschpe 3:392d2c733c68 298 ft_void_t FT800::CoreReset( )
dreschpe 0:5e013296b353 299 {
dreschpe 3:392d2c733c68 300 HostCommand( 0x68);
dreschpe 0:5e013296b353 301 }
dreschpe 0:5e013296b353 302
dreschpe 0:5e013296b353 303
dreschpe 3:392d2c733c68 304 ft_void_t FT800::Updatecmdfifo( ft_uint16_t count)
dreschpe 0:5e013296b353 305 {
dreschpe 3:392d2c733c68 306 cmd_fifo_wp = ( cmd_fifo_wp + count) & 4095;
dreschpe 0:5e013296b353 307 //4 byte alignment
dreschpe 3:392d2c733c68 308 cmd_fifo_wp = ( cmd_fifo_wp + 3) & 0xffc;
dreschpe 3:392d2c733c68 309 Wr16( REG_CMD_WRITE, cmd_fifo_wp);
dreschpe 0:5e013296b353 310 }
dreschpe 0:5e013296b353 311
dreschpe 0:5e013296b353 312
dreschpe 3:392d2c733c68 313 ft_uint16_t FT800::fifo_Freespace( )
dreschpe 0:5e013296b353 314 {
dreschpe 0:5e013296b353 315 ft_uint16_t fullness,retval;
dreschpe 0:5e013296b353 316
dreschpe 3:392d2c733c68 317 fullness = ( cmd_fifo_wp - Rd16( REG_CMD_READ)) & 4095;
dreschpe 0:5e013296b353 318 retval = (FT_CMD_FIFO_SIZE - 4) - fullness;
dreschpe 0:5e013296b353 319 return (retval);
dreschpe 0:5e013296b353 320 }
dreschpe 0:5e013296b353 321
dreschpe 3:392d2c733c68 322 ft_void_t FT800::WrCmdBuf( ft_uint8_t *buffer,ft_uint16_t count)
dreschpe 0:5e013296b353 323 {
dreschpe 3:392d2c733c68 324 ft_uint32_t length =0, SizeTransfered = 0;
dreschpe 0:5e013296b353 325
dreschpe 3:392d2c733c68 326 #define MAX_CMD_FIFO_TRANSFER fifo_Freespace( )
dreschpe 3:392d2c733c68 327 do {
dreschpe 0:5e013296b353 328 length = count;
dreschpe 0:5e013296b353 329 if (length > MAX_CMD_FIFO_TRANSFER){
dreschpe 0:5e013296b353 330 length = MAX_CMD_FIFO_TRANSFER;
dreschpe 0:5e013296b353 331 }
dreschpe 3:392d2c733c68 332 CheckCmdBuffer( length);
dreschpe 0:5e013296b353 333
dreschpe 3:392d2c733c68 334 StartCmdTransfer( FT_GPU_WRITE,length);
dreschpe 0:5e013296b353 335
dreschpe 0:5e013296b353 336 SizeTransfered = 0;
dreschpe 0:5e013296b353 337 while (length--) {
dreschpe 3:392d2c733c68 338 Transfer8( *buffer);
dreschpe 0:5e013296b353 339 buffer++;
dreschpe 0:5e013296b353 340 SizeTransfered ++;
dreschpe 0:5e013296b353 341 }
dreschpe 0:5e013296b353 342 length = SizeTransfered;
dreschpe 0:5e013296b353 343
dreschpe 3:392d2c733c68 344 EndTransfer( );
dreschpe 3:392d2c733c68 345 Updatecmdfifo( length);
dreschpe 0:5e013296b353 346
dreschpe 3:392d2c733c68 347 WaitCmdfifo_empty( );
dreschpe 0:5e013296b353 348
dreschpe 0:5e013296b353 349 count -= length;
dreschpe 0:5e013296b353 350 }while (count > 0);
dreschpe 0:5e013296b353 351 }
dreschpe 0:5e013296b353 352
dreschpe 0:5e013296b353 353
dreschpe 3:392d2c733c68 354 ft_void_t FT800::WrCmdBufFromFlash( FT_PROGMEM ft_prog_uchar8_t *buffer,ft_uint16_t count)
dreschpe 0:5e013296b353 355 {
dreschpe 3:392d2c733c68 356 ft_uint32_t length =0, SizeTransfered = 0;
dreschpe 0:5e013296b353 357
dreschpe 3:392d2c733c68 358 #define MAX_CMD_FIFO_TRANSFER fifo_Freespace( )
dreschpe 3:392d2c733c68 359 do {
dreschpe 0:5e013296b353 360 length = count;
dreschpe 0:5e013296b353 361 if (length > MAX_CMD_FIFO_TRANSFER){
dreschpe 0:5e013296b353 362 length = MAX_CMD_FIFO_TRANSFER;
dreschpe 0:5e013296b353 363 }
dreschpe 3:392d2c733c68 364 CheckCmdBuffer( length);
dreschpe 0:5e013296b353 365
dreschpe 3:392d2c733c68 366 StartCmdTransfer( FT_GPU_WRITE,length);
dreschpe 0:5e013296b353 367
dreschpe 0:5e013296b353 368
dreschpe 0:5e013296b353 369 SizeTransfered = 0;
dreschpe 0:5e013296b353 370 while (length--) {
dreschpe 3:392d2c733c68 371 Transfer8( ft_pgm_read_byte_near(buffer));
dreschpe 0:5e013296b353 372 buffer++;
dreschpe 0:5e013296b353 373 SizeTransfered ++;
dreschpe 0:5e013296b353 374 }
dreschpe 0:5e013296b353 375 length = SizeTransfered;
dreschpe 0:5e013296b353 376
dreschpe 3:392d2c733c68 377 EndTransfer( );
dreschpe 3:392d2c733c68 378 Updatecmdfifo( length);
dreschpe 0:5e013296b353 379
dreschpe 3:392d2c733c68 380 WaitCmdfifo_empty( );
dreschpe 0:5e013296b353 381
dreschpe 0:5e013296b353 382 count -= length;
dreschpe 0:5e013296b353 383 }while (count > 0);
dreschpe 0:5e013296b353 384 }
dreschpe 0:5e013296b353 385
dreschpe 0:5e013296b353 386
dreschpe 3:392d2c733c68 387 ft_void_t FT800::CheckCmdBuffer( ft_uint16_t count)
dreschpe 0:5e013296b353 388 {
dreschpe 0:5e013296b353 389 ft_uint16_t getfreespace;
dreschpe 0:5e013296b353 390 do{
dreschpe 3:392d2c733c68 391 getfreespace = fifo_Freespace( );
dreschpe 0:5e013296b353 392 }while(getfreespace < count);
dreschpe 0:5e013296b353 393 }
dreschpe 0:5e013296b353 394
dreschpe 3:392d2c733c68 395 ft_void_t FT800::WaitCmdfifo_empty( )
dreschpe 0:5e013296b353 396 {
dreschpe 3:392d2c733c68 397 while(Rd16( REG_CMD_READ) != Rd16( REG_CMD_WRITE));
dreschpe 3:392d2c733c68 398
dreschpe 3:392d2c733c68 399 cmd_fifo_wp = Rd16( REG_CMD_WRITE);
dreschpe 0:5e013296b353 400 }
dreschpe 0:5e013296b353 401
dreschpe 3:392d2c733c68 402 ft_void_t FT800::WaitLogo_Finish( )
dreschpe 0:5e013296b353 403 {
dreschpe 0:5e013296b353 404 ft_int16_t cmdrdptr,cmdwrptr;
dreschpe 0:5e013296b353 405
dreschpe 0:5e013296b353 406 do{
dreschpe 3:392d2c733c68 407 cmdrdptr = Rd16( REG_CMD_READ);
dreschpe 3:392d2c733c68 408 cmdwrptr = Rd16( REG_CMD_WRITE);
dreschpe 0:5e013296b353 409 }while ((cmdwrptr != cmdrdptr) || (cmdrdptr != 0));
dreschpe 3:392d2c733c68 410 cmd_fifo_wp = 0;
dreschpe 0:5e013296b353 411 }
dreschpe 0:5e013296b353 412
dreschpe 0:5e013296b353 413
dreschpe 3:392d2c733c68 414 ft_void_t FT800::ResetCmdFifo( )
dreschpe 0:5e013296b353 415 {
dreschpe 3:392d2c733c68 416 cmd_fifo_wp = 0;
dreschpe 0:5e013296b353 417 }
dreschpe 0:5e013296b353 418
dreschpe 0:5e013296b353 419
dreschpe 3:392d2c733c68 420 ft_void_t FT800::WrCmd32( ft_uint32_t cmd)
dreschpe 0:5e013296b353 421 {
dreschpe 3:392d2c733c68 422 CheckCmdBuffer( sizeof(cmd));
dreschpe 3:392d2c733c68 423
dreschpe 3:392d2c733c68 424 Wr32( RAM_CMD + cmd_fifo_wp,cmd);
dreschpe 3:392d2c733c68 425
dreschpe 3:392d2c733c68 426 Updatecmdfifo( sizeof(cmd));
dreschpe 0:5e013296b353 427 }
dreschpe 0:5e013296b353 428
dreschpe 0:5e013296b353 429
dreschpe 3:392d2c733c68 430 ft_void_t FT800::ResetDLBuffer( )
dreschpe 0:5e013296b353 431 {
dreschpe 3:392d2c733c68 432 dl_buff_wp = 0;
dreschpe 0:5e013296b353 433 }
dreschpe 0:5e013296b353 434
dreschpe 0:5e013296b353 435 /* Toggle PD_N pin of FT800 board for a power cycle*/
dreschpe 3:392d2c733c68 436 ft_void_t FT800::Powercycle( ft_bool_t up)
dreschpe 0:5e013296b353 437 {
dreschpe 0:5e013296b353 438 if (up)
dreschpe 0:5e013296b353 439 {
dreschpe 3:392d2c733c68 440 //Toggle PD_N from low to high for power up switch
dreschpe 3:392d2c733c68 441 _pd = 0;
dreschpe 3:392d2c733c68 442 Sleep(20);
dreschpe 0:5e013296b353 443
dreschpe 0:5e013296b353 444 _pd = 1;
dreschpe 3:392d2c733c68 445 Sleep(20);
dreschpe 0:5e013296b353 446 }else
dreschpe 0:5e013296b353 447 {
dreschpe 0:5e013296b353 448 //Toggle PD_N from high to low for power down switch
dreschpe 0:5e013296b353 449 _pd = 1;
dreschpe 3:392d2c733c68 450 Sleep(20);
dreschpe 3:392d2c733c68 451
dreschpe 0:5e013296b353 452 _pd = 0;
dreschpe 3:392d2c733c68 453 Sleep(20);
dreschpe 0:5e013296b353 454 }
dreschpe 0:5e013296b353 455 }
dreschpe 0:5e013296b353 456
dreschpe 3:392d2c733c68 457 ft_void_t FT800::WrMemFromFlash( ft_uint32_t addr,const ft_prog_uchar8_t *buffer, ft_uint32_t length)
dreschpe 0:5e013296b353 458 {
dreschpe 3:392d2c733c68 459 //ft_uint32_t SizeTransfered = 0;
dreschpe 0:5e013296b353 460
dreschpe 3:392d2c733c68 461 StartTransfer( FT_GPU_WRITE,addr);
dreschpe 0:5e013296b353 462
dreschpe 0:5e013296b353 463 while (length--) {
dreschpe 3:392d2c733c68 464 Transfer8( ft_pgm_read_byte_near(buffer));
dreschpe 0:5e013296b353 465 buffer++;
dreschpe 0:5e013296b353 466 }
dreschpe 0:5e013296b353 467
dreschpe 3:392d2c733c68 468 EndTransfer( );
dreschpe 0:5e013296b353 469 }
dreschpe 0:5e013296b353 470
dreschpe 3:392d2c733c68 471 ft_void_t FT800::WrMem( ft_uint32_t addr,const ft_uint8_t *buffer, ft_uint32_t length)
dreschpe 0:5e013296b353 472 {
dreschpe 3:392d2c733c68 473 //ft_uint32_t SizeTransfered = 0;
dreschpe 0:5e013296b353 474
dreschpe 3:392d2c733c68 475 StartTransfer( FT_GPU_WRITE,addr);
dreschpe 0:5e013296b353 476
dreschpe 0:5e013296b353 477 while (length--) {
dreschpe 3:392d2c733c68 478 Transfer8( *buffer);
dreschpe 0:5e013296b353 479 buffer++;
dreschpe 0:5e013296b353 480 }
dreschpe 0:5e013296b353 481
dreschpe 3:392d2c733c68 482 EndTransfer( );
dreschpe 0:5e013296b353 483 }
dreschpe 0:5e013296b353 484
dreschpe 0:5e013296b353 485
dreschpe 3:392d2c733c68 486 ft_void_t FT800::RdMem( ft_uint32_t addr, ft_uint8_t *buffer, ft_uint32_t length)
dreschpe 0:5e013296b353 487 {
dreschpe 3:392d2c733c68 488 //ft_uint32_t SizeTransfered = 0;
dreschpe 0:5e013296b353 489
dreschpe 3:392d2c733c68 490 StartTransfer( FT_GPU_READ,addr);
dreschpe 0:5e013296b353 491
dreschpe 0:5e013296b353 492 while (length--) {
dreschpe 3:392d2c733c68 493 *buffer = Transfer8( 0);
dreschpe 0:5e013296b353 494 buffer++;
dreschpe 0:5e013296b353 495 }
dreschpe 0:5e013296b353 496
dreschpe 3:392d2c733c68 497 EndTransfer( );
dreschpe 0:5e013296b353 498 }
dreschpe 0:5e013296b353 499
dreschpe 3:392d2c733c68 500 ft_int32_t FT800::Dec2Ascii(ft_char8_t *pSrc,ft_int32_t value)
dreschpe 0:5e013296b353 501 {
dreschpe 0:5e013296b353 502 ft_int16_t Length;
dreschpe 0:5e013296b353 503 ft_char8_t *pdst,charval;
dreschpe 0:5e013296b353 504 ft_int32_t CurrVal = value,tmpval,i;
dreschpe 0:5e013296b353 505 ft_char8_t tmparray[16],idx = 0;
dreschpe 0:5e013296b353 506
dreschpe 0:5e013296b353 507 Length = strlen(pSrc);
dreschpe 0:5e013296b353 508 pdst = pSrc + Length;
dreschpe 0:5e013296b353 509
dreschpe 0:5e013296b353 510 if(0 == value)
dreschpe 0:5e013296b353 511 {
dreschpe 0:5e013296b353 512 *pdst++ = '0';
dreschpe 0:5e013296b353 513 *pdst++ = '\0';
dreschpe 0:5e013296b353 514 return 0;
dreschpe 0:5e013296b353 515 }
dreschpe 0:5e013296b353 516
dreschpe 0:5e013296b353 517 if(CurrVal < 0)
dreschpe 0:5e013296b353 518 {
dreschpe 0:5e013296b353 519 *pdst++ = '-';
dreschpe 0:5e013296b353 520 CurrVal = - CurrVal;
dreschpe 0:5e013296b353 521 }
dreschpe 0:5e013296b353 522 /* insert the value */
dreschpe 0:5e013296b353 523 while(CurrVal > 0){
dreschpe 0:5e013296b353 524 tmpval = CurrVal;
dreschpe 0:5e013296b353 525 CurrVal /= 10;
dreschpe 0:5e013296b353 526 tmpval = tmpval - CurrVal*10;
dreschpe 0:5e013296b353 527 charval = '0' + tmpval;
dreschpe 0:5e013296b353 528 tmparray[idx++] = charval;
dreschpe 0:5e013296b353 529 }
dreschpe 0:5e013296b353 530
dreschpe 0:5e013296b353 531 for(i=0;i<idx;i++)
dreschpe 0:5e013296b353 532 {
dreschpe 0:5e013296b353 533 *pdst++ = tmparray[idx - i - 1];
dreschpe 0:5e013296b353 534 }
dreschpe 0:5e013296b353 535 *pdst++ = '\0';
dreschpe 0:5e013296b353 536
dreschpe 0:5e013296b353 537 return 0;
dreschpe 0:5e013296b353 538 }
dreschpe 0:5e013296b353 539
dreschpe 0:5e013296b353 540
dreschpe 3:392d2c733c68 541 ft_void_t FT800::Sleep(ft_uint16_t ms)
dreschpe 0:5e013296b353 542 {
dreschpe 0:5e013296b353 543 wait_ms(ms);
dreschpe 0:5e013296b353 544 }
dreschpe 0:5e013296b353 545
dreschpe 3:392d2c733c68 546 ft_void_t FT800::Sound_ON(){
dreschpe 3:392d2c733c68 547 Wr8( REG_GPIO, 0x02 | Rd8( REG_GPIO));
dreschpe 1:bd671a31e765 548 }
dreschpe 1:bd671a31e765 549
dreschpe 3:392d2c733c68 550 ft_void_t FT800::Sound_OFF(){
dreschpe 3:392d2c733c68 551 Wr8( REG_GPIO, 0xFD & Rd8( REG_GPIO));
dreschpe 1:bd671a31e765 552 }
dreschpe 0:5e013296b353 553
dreschpe 0:5e013296b353 554
dreschpe 0:5e013296b353 555
dreschpe 1:bd671a31e765 556