Dave Van Wagner / USBHOST

ST/USBHOST forked to add another HID handler for raw keyboard data to get more detail not available with current handlers (all pressed keys, all releases, and periodic updates)

Dependents:   C64-stm429_discovery

USBHost/USBHostTypes.h@7:9dc1cb9d5e12, 2020-04-13 (annotated)

Committer:
davervw
Date:
Mon Apr 13 05:25:10 2020 +0000
Revision:
7:9dc1cb9d5e12
Parent:
5:fc157e6bd5a5 
Added handler to USBHostHID/USBHostKeyboard.cpp:;    void (*onKeyData)(uint8_t len, uint8_t* data);; so can get raw keyboard data for all keys simultaneously pressed, and all releases and periodic data

Who changed what in which revision?

UserRevisionLine numberNew contents of line
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 1 /* mbed USBHost Library
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 2 * Copyright (c) 2006-2013 ARM Limited
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 3 *
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 4 * Licensed under the Apache License, Version 2.0 (the "License");
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 5 * you may not use this file except in compliance with the License.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 6 * You may obtain a copy of the License at
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 7 *
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 8 * http://www.apache.org/licenses/LICENSE-2.0
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 9 *
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 10 * Unless required by applicable law or agreed to in writing, software
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 11 * distributed under the License is distributed on an "AS IS" BASIS,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 13 * See the License for the specific language governing permissions and
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 14 * limitations under the License.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 15 */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 16
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 17 #ifndef USB_INC_H
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 18 #define USB_INC_H
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 19
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 20 #include "mbed.h"
frq08711@LMECWL0871.LME.ST.COM 5:fc157e6bd5a5 21 #include "mbed_toolchain.h"
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 22
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 23 enum USB_TYPE {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 24 USB_TYPE_OK = 0,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 25
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 26 // completion code
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 27 USB_TYPE_CRC_ERROR = 1,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 28 USB_TYPE_BIT_STUFFING_ERROR = 2,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 29 USB_TYPE_DATA_TOGGLE_MISMATCH_ERROR = 3,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 30 USB_TYPE_STALL_ERROR = 4,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 31 USB_TYPE_DEVICE_NOT_RESPONDING_ERROR = 5,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 32 USB_TYPE_PID_CHECK_FAILURE_ERROR = 6,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 33 USB_TYPE_UNEXPECTED_PID_ERROR = 7,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 34 USB_TYPE_DATA_OVERRUN_ERROR = 8,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 35 USB_TYPE_DATA_UNDERRUN_ERROR = 9,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 36 USB_TYPE_RESERVED = 9,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 37 USB_TYPE_RESERVED_ = 10,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 38 USB_TYPE_BUFFER_OVERRUN_ERROR = 12,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 39 USB_TYPE_BUFFER_UNDERRUN_ERROR = 13,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 40
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 41 // general usb state
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 42 USB_TYPE_DISCONNECTED = 14,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 43 USB_TYPE_FREE = 15,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 44 USB_TYPE_IDLE = 16,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 45 USB_TYPE_PROCESSING = 17,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 46
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 47 USB_TYPE_ERROR = 18,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 48 };
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 49
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 50
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 51 enum ENDPOINT_DIRECTION {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 52 OUT = 1,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 53 IN
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 54 };
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 55
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 56 enum ENDPOINT_TYPE {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 57 CONTROL_ENDPOINT = 0,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 58 ISOCHRONOUS_ENDPOINT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 59 BULK_ENDPOINT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 60 INTERRUPT_ENDPOINT
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 61 };
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 62
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 63 #define AUDIO_CLASS 0x01
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 64 #define CDC_CLASS 0x02
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 65 #define HID_CLASS 0x03
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 66 #define MSD_CLASS 0x08
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 67 #define HUB_CLASS 0x09
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 68 #define SERIAL_CLASS 0x0A
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 69
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 70 #if !defined(USBHOST_OTHER)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 71 // ------------------ HcControl Register ---------------------
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 72 #define OR_CONTROL_PLE 0x00000004
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 73 #define OR_CONTROL_CLE 0x00000010
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 74 #define OR_CONTROL_BLE 0x00000020
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 75 #define OR_CONTROL_HCFS 0x000000C0
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 76 #define OR_CONTROL_HC_RSET 0x00000000
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 77 #define OR_CONTROL_HC_RES 0x00000040
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 78 #define OR_CONTROL_HC_OPER 0x00000080
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 79 #define OR_CONTROL_HC_SUSP 0x000000C0
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 80 // ----------------- HcCommandStatus Register -----------------
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 81 #define OR_CMD_STATUS_HCR 0x00000001
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 82 #define OR_CMD_STATUS_CLF 0x00000002
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 83 #define OR_CMD_STATUS_BLF 0x00000004
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 84 // --------------- HcInterruptStatus Register -----------------
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 85 #define OR_INTR_STATUS_WDH 0x00000002
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 86 #define OR_INTR_STATUS_RHSC 0x00000040
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 87 #define OR_INTR_STATUS_UE 0x00000010
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 88 // --------------- HcInterruptEnable Register -----------------
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 89 #define OR_INTR_ENABLE_WDH 0x00000002
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 90 #define OR_INTR_ENABLE_RHSC 0x00000040
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 91 #define OR_INTR_ENABLE_MIE 0x80000000
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 92 // ---------------- HcRhDescriptorA Register ------------------
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 93 #define OR_RH_STATUS_LPSC 0x00010000
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 94 #define OR_RH_STATUS_DRWE 0x00008000
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 95 // -------------- HcRhPortStatus[1:NDP] Register --------------
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 96 #define OR_RH_PORT_CCS 0x00000001
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 97 #define OR_RH_PORT_PRS 0x00000010
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 98 #define OR_RH_PORT_CSC 0x00010000
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 99 #define OR_RH_PORT_PRSC 0x00100000
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 100 #define OR_RH_PORT_LSDA 0x00000200
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 101 #define OR_RH_PORT_PESC 0x00020000
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 102 #define OR_RH_PORT_OCIC 0x00080000
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 103
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 104 #define FI 0x2EDF // 12000 bits per frame (-1)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 105 #define DEFAULT_FMINTERVAL ((((6 * (FI - 210)) / 7) << 16) | FI)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 106
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 107 #define ED_SKIP (uint32_t) (0x00001000) // Skip this ep in queue
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 108
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 109 #define TD_ROUNDING (uint32_t) (0x00040000) // Buffer Rounding
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 110 #define TD_SETUP (uint32_t)(0) // Direction of Setup Packet
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 111 #define TD_IN (uint32_t)(0x00100000) // Direction In
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 112 #define TD_OUT (uint32_t)(0x00080000) // Direction Out
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 113 #define TD_DELAY_INT(x) (uint32_t)((x) << 21) // Delay Interrupt
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 114 #define TD_TOGGLE_0 (uint32_t)(0x02000000) // Toggle 0
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 115 #define TD_TOGGLE_1 (uint32_t)(0x03000000) // Toggle 1
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 116 #define TD_CC (uint32_t)(0xF0000000) // Completion Code
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 117
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 118 #else
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 119
frq08711@LMECWL0871.LME.ST.COM 5:fc157e6bd5a5 120 #define TD_TIMEOUT_CTRL 100
frq08711@LMECWL0871.LME.ST.COM 5:fc157e6bd5a5 121 #define TD_TIMEOUT 2000
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 122 #define TD_SETUP (uint32_t)(0) // Direction of Setup Packet
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 123 #define TD_IN (uint32_t)(0x00100000) // Direction In
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 124 #define TD_OUT (uint32_t)(0x00080000) // Direction Out
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 125
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 126 #endif
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 127 #define DEVICE_DESCRIPTOR (1)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 128 #define CONFIGURATION_DESCRIPTOR (2)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 129 #define INTERFACE_DESCRIPTOR (4)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 130 #define ENDPOINT_DESCRIPTOR (5)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 131 #define HID_DESCRIPTOR (33)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 132
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 133 // ----------- Control RequestType Fields -----------
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 134 #define USB_DEVICE_TO_HOST 0x80
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 135 #define USB_HOST_TO_DEVICE 0x00
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 136 #define USB_REQUEST_TYPE_CLASS 0x20
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 137 #define USB_REQUEST_TYPE_STANDARD 0x00
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 138 #define USB_RECIPIENT_DEVICE 0x00
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 139 #define USB_RECIPIENT_INTERFACE 0x01
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 140 #define USB_RECIPIENT_ENDPOINT 0x02
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 141
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 142 // -------------- USB Standard Requests --------------
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 143 #define SET_ADDRESS 0x05
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 144 #define GET_DESCRIPTOR 0x06
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 145 #define SET_CONFIGURATION 0x09
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 146 #define SET_INTERFACE 0x0b
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 147 #define CLEAR_FEATURE 0x01
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 148
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 149 // -------------- USB Descriptor Length --------------
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 150 #define DEVICE_DESCRIPTOR_LENGTH 0x12
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 151 #define CONFIGURATION_DESCRIPTOR_LENGTH 0x09
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 152
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 153 // ------------ HostController Transfer Descriptor ------------
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 154 #if defined(USBHOST_OTHER)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 155
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 156 typedef struct hcTd {
frq08711@LMECWL0871.LME.ST.COM 3:1c76b46ad779 157 __IO uint32_t state;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 158 __IO uint8_t * currBufPtr; // Physical address of current buffer pointer
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 159 __IO hcTd * nextTD; // Physical pointer to next Transfer Descriptor
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 160 __IO uint32_t size; // size of buffer
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 161 void * ep; // ep address where a td is linked in
frq08711@LMECWL0871.LME.ST.COM 3:1c76b46ad779 162 __IO uint32_t retry;
frq08711@LMECWL0871.LME.ST.COM 5:fc157e6bd5a5 163 __IO uint32_t setup;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 164 } PACKED HCTD;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 165 // ----------- HostController EndPoint Descriptor -------------
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 166 typedef struct hcEd {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 167 uint8_t ch_num;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 168 void *hhcd;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 169 } PACKED HCED;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 170 // ----------- Host Controller Communication Area ------------
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 171 #define HCCA void
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 172
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 173
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 174 #else
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 175 // -------------OHCI register --------------------------------
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 176 // ------------ HostController Transfer Descriptor ------------
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 177 typedef struct hcTd {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 178 __IO uint32_t control; // Transfer descriptor control
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 179 __IO uint8_t * currBufPtr; // Physical address of current buffer pointer
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 180 __IO hcTd * nextTD; // Physical pointer to next Transfer Descriptor
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 181 __IO uint8_t * bufEnd; // Physical address of end of buffer
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 182 void * ep; // ep address where a td is linked in
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 183 uint32_t dummy[3]; // padding
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 184 } PACKED HCTD;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 185 // ----------- HostController EndPoint Descriptor -------------
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 186 typedef struct hcEd {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 187 __IO uint32_t control; // Endpoint descriptor control
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 188 __IO HCTD * tailTD; // Physical address of tail in Transfer descriptor list
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 189 __IO HCTD * headTD; // Physcial address of head in Transfer descriptor list
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 190 __IO hcEd * nextED; // Physical address of next Endpoint descriptor
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 191 } PACKED HCED;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 192 // ----------- Host Controller Communication Area ------------
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 193 typedef struct hcca {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 194 __IO uint32_t IntTable[32]; // Interrupt Table
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 195 __IO uint32_t FrameNumber; // Frame Number
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 196 __IO uint32_t DoneHead; // Done Head
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 197 volatile uint8_t Reserved[116]; // Reserved for future use
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 198 volatile uint8_t Unknown[4]; // Unused
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 199 } PACKED HCCA;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 200 #endif
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 201
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 202 typedef struct {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 203 uint8_t bLength;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 204 uint8_t bDescriptorType;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 205 uint16_t bcdUSB;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 206 uint8_t bDeviceClass;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 207 uint8_t bDeviceSubClass;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 208 uint8_t bDeviceProtocol;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 209 uint8_t bMaxPacketSize;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 210 uint16_t idVendor;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 211 uint16_t idProduct;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 212 uint16_t bcdDevice;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 213 uint8_t iManufacturer;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 214 uint8_t iProduct;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 215 uint8_t iSerialNumber;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 216 uint8_t bNumConfigurations;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 217 } PACKED DeviceDescriptor;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 218
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 219 typedef struct {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 220 uint8_t bLength;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 221 uint8_t bDescriptorType;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 222 uint16_t wTotalLength;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 223 uint8_t bNumInterfaces;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 224 uint8_t bConfigurationValue;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 225 uint8_t iConfiguration;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 226 uint8_t bmAttributes;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 227 uint8_t bMaxPower;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 228 } PACKED ConfigurationDescriptor;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 229
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 230 typedef struct {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 231 uint8_t bLength;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 232 uint8_t bDescriptorType;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 233 uint8_t bInterfaceNumber;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 234 uint8_t bAlternateSetting;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 235 uint8_t bNumEndpoints;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 236 uint8_t bInterfaceClass;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 237 uint8_t bInterfaceSubClass;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 238 uint8_t bInterfaceProtocol;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 239 uint8_t iInterface;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 240 } InterfaceDescriptor;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 241
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 242 typedef struct {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 243 uint8_t bLength;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 244 uint8_t bDescriptorType;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 245 uint8_t bEndpointAddress;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 246 uint8_t bmAttributes;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 247 uint16_t wMaxPacketSize;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 248 uint8_t bInterval;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 249 } EndpointDescriptor;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 250
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 251 typedef struct {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 252 uint8_t bDescLength;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 253 uint8_t bDescriptorType;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 254 uint8_t bNbrPorts;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 255 uint16_t wHubCharacteristics;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 256 uint8_t bPwrOn2PwrGood;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 257 uint8_t bHubContrCurrent;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 258 uint8_t DeviceRemovable;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 259 uint8_t PortPweCtrlMak;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 260 } HubDescriptor;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 261
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 262 #endif