Jumpei Oguro / Mbed 2 deprecated windmeter4receive_1

wind logger

Dependencies:   SDFileSystem TextLCD mbed

Fork of windmeter4receive by Jumpei Oguro

PowerControl/PowerControl.h@1:4810436d9e48, 2014-08-08 (annotated)

Committer:
data37
Date:
Fri Aug 08 10:25:27 2014 +0000
Revision:
1:4810436d9e48
Parent:
0:36c080f46ab1 
wind logger

Who changed what in which revision?

UserRevisionLine numberNew contents of line
data37 0:36c080f46ab1 1 /* mbed PowerControl Library
data37 0:36c080f46ab1 2 * Copyright (c) 2010 Michael Wei
data37 0:36c080f46ab1 3 */
data37 0:36c080f46ab1 4
data37 0:36c080f46ab1 5 #ifndef MBED_POWERCONTROL_H
data37 0:36c080f46ab1 6 #define MBED_POWERCONTROL_H
data37 0:36c080f46ab1 7
data37 0:36c080f46ab1 8 //shouldn't have to include, but fixes weird problems with defines
data37 0:36c080f46ab1 9 //#include "LPC1768/LPC17xx.h"
data37 0:36c080f46ab1 10
data37 0:36c080f46ab1 11 //System Control Register
data37 0:36c080f46ab1 12 // bit 0: Reserved
data37 0:36c080f46ab1 13 // bit 1: Sleep on Exit
data37 0:36c080f46ab1 14 #define LPC1768_SCR_SLEEPONEXIT 0x2
data37 0:36c080f46ab1 15 // bit 2: Deep Sleep
data37 0:36c080f46ab1 16 #define LPC1768_SCR_SLEEPDEEP 0x4
data37 0:36c080f46ab1 17 // bit 3: Resereved
data37 0:36c080f46ab1 18 // bit 4: Send on Pending
data37 0:36c080f46ab1 19 #define LPC1768_SCR_SEVONPEND 0x10
data37 0:36c080f46ab1 20 // bit 5-31: Reserved
data37 0:36c080f46ab1 21
data37 0:36c080f46ab1 22 //Power Control Register
data37 0:36c080f46ab1 23 // bit 0: Power mode control bit 0 (power-down mode)
data37 0:36c080f46ab1 24 #define LPC1768_PCON_PM0 0x1
data37 0:36c080f46ab1 25 // bit 1: Power mode control bit 1 (deep power-down mode)
data37 0:36c080f46ab1 26 #define LPC1768_PCON_PM1 0x2
data37 0:36c080f46ab1 27 // bit 2: Brown-out reduced power mode
data37 0:36c080f46ab1 28 #define LPC1768_PCON_BODRPM 0x4
data37 0:36c080f46ab1 29 // bit 3: Brown-out global disable
data37 0:36c080f46ab1 30 #define LPC1768_PCON_BOGD 0x8
data37 0:36c080f46ab1 31 // bit 4: Brown-out reset disable
data37 0:36c080f46ab1 32 #define LPC1768_PCON_BORD 0x10
data37 0:36c080f46ab1 33 // bit 5-7 : Reserved
data37 0:36c080f46ab1 34 // bit 8: Sleep Mode Entry Flag
data37 0:36c080f46ab1 35 #define LPC1768_PCON_SMFLAG 0x100
data37 0:36c080f46ab1 36 // bit 9: Deep Sleep Entry Flag
data37 0:36c080f46ab1 37 #define LPC1768_PCON_DSFLAG 0x200
data37 0:36c080f46ab1 38 // bit 10: Power Down Entry Flag
data37 0:36c080f46ab1 39 #define LPC1768_PCON_PDFLAG 0x400
data37 0:36c080f46ab1 40 // bit 11: Deep Power Down Entry Flag
data37 0:36c080f46ab1 41 #define LPC1768_PCON_DPDFLAG 0x800
data37 0:36c080f46ab1 42 // bit 12-31: Reserved
data37 0:36c080f46ab1 43
data37 0:36c080f46ab1 44 //"Sleep Mode" (WFI).
data37 0:36c080f46ab1 45 inline void Sleep(void)
data37 0:36c080f46ab1 46 {
data37 0:36c080f46ab1 47 __WFI();
data37 0:36c080f46ab1 48 }
data37 0:36c080f46ab1 49
data37 0:36c080f46ab1 50 //"Deep Sleep" Mode
data37 0:36c080f46ab1 51 inline void DeepSleep(void)
data37 0:36c080f46ab1 52 {
data37 0:36c080f46ab1 53 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
data37 0:36c080f46ab1 54 __WFI();
data37 0:36c080f46ab1 55 }
data37 0:36c080f46ab1 56
data37 0:36c080f46ab1 57 //"Power-Down" Mode
data37 0:36c080f46ab1 58 inline void PowerDown(void)
data37 0:36c080f46ab1 59 {
data37 0:36c080f46ab1 60 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
data37 0:36c080f46ab1 61 LPC_SC->PCON &= ~LPC1768_PCON_PM1;
data37 0:36c080f46ab1 62 LPC_SC->PCON |= LPC1768_PCON_PM0;
data37 0:36c080f46ab1 63 __WFI();
data37 0:36c080f46ab1 64 //reset back to normal
data37 0:36c080f46ab1 65 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
data37 0:36c080f46ab1 66 }
data37 0:36c080f46ab1 67
data37 0:36c080f46ab1 68 //"Deep Power-Down" Mode
data37 0:36c080f46ab1 69 inline void DeepPowerDown(void)
data37 0:36c080f46ab1 70 {
data37 0:36c080f46ab1 71 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
data37 0:36c080f46ab1 72 LPC_SC->PCON |= LPC1768_PCON_PM1 | LPC1768_PCON_PM0;
data37 0:36c080f46ab1 73 __WFI();
data37 0:36c080f46ab1 74 //reset back to normal
data37 0:36c080f46ab1 75 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
data37 0:36c080f46ab1 76 }
data37 0:36c080f46ab1 77
data37 0:36c080f46ab1 78 //shut down BOD during power-down/deep sleep
data37 0:36c080f46ab1 79 inline void BrownOut_ReducedPowerMode_Enable(void)
data37 0:36c080f46ab1 80 {
data37 0:36c080f46ab1 81 LPC_SC->PCON |= LPC1768_PCON_BODRPM;
data37 0:36c080f46ab1 82 }
data37 0:36c080f46ab1 83
data37 0:36c080f46ab1 84 //turn on BOD during power-down/deep sleep
data37 0:36c080f46ab1 85 inline void BrownOut_ReducedPowerMode_Disable(void)
data37 0:36c080f46ab1 86 {
data37 0:36c080f46ab1 87 LPC_SC->PCON &= ~LPC1768_PCON_BODRPM;
data37 0:36c080f46ab1 88 }
data37 0:36c080f46ab1 89
data37 0:36c080f46ab1 90 //turn off brown out circutry
data37 0:36c080f46ab1 91 inline void BrownOut_Global_Disable(void)
data37 0:36c080f46ab1 92 {
data37 0:36c080f46ab1 93 LPC_SC->PCON |= LPC1768_PCON_BOGD;
data37 0:36c080f46ab1 94 }
data37 0:36c080f46ab1 95
data37 0:36c080f46ab1 96 //turn on brown out circutry
data37 0:36c080f46ab1 97 inline void BrownOut_Global_Enable(void)
data37 0:36c080f46ab1 98 {
data37 0:36c080f46ab1 99 LPC_SC->PCON &= !LPC1768_PCON_BOGD;
data37 0:36c080f46ab1 100 }
data37 0:36c080f46ab1 101
data37 0:36c080f46ab1 102 //turn off brown out reset circutry
data37 0:36c080f46ab1 103 inline void BrownOut_Reset_Disable(void)
data37 0:36c080f46ab1 104 {
data37 0:36c080f46ab1 105 LPC_SC->PCON |= LPC1768_PCON_BORD;
data37 0:36c080f46ab1 106 }
data37 0:36c080f46ab1 107
data37 0:36c080f46ab1 108 //turn on brown outreset circutry
data37 0:36c080f46ab1 109 inline void BrownOut_Reset_Enable(void)
data37 0:36c080f46ab1 110 {
data37 0:36c080f46ab1 111 LPC_SC->PCON &= ~LPC1768_PCON_BORD;
data37 0:36c080f46ab1 112 }
data37 0:36c080f46ab1 113 //Peripheral Control Register
data37 0:36c080f46ab1 114 // bit 0: Reserved
data37 0:36c080f46ab1 115 // bit 1: PCTIM0: Timer/Counter 0 power/clock enable
data37 0:36c080f46ab1 116 #define LPC1768_PCONP_PCTIM0 0x2
data37 0:36c080f46ab1 117 // bit 2: PCTIM1: Timer/Counter 1 power/clock enable
data37 0:36c080f46ab1 118 #define LPC1768_PCONP_PCTIM1 0x4
data37 0:36c080f46ab1 119 // bit 3: PCUART0: UART 0 power/clock enable
data37 0:36c080f46ab1 120 #define LPC1768_PCONP_PCUART0 0x8
data37 0:36c080f46ab1 121 // bit 4: PCUART1: UART 1 power/clock enable
data37 0:36c080f46ab1 122 #define LPC1768_PCONP_PCUART1 0x10
data37 0:36c080f46ab1 123 // bit 5: Reserved
data37 0:36c080f46ab1 124 // bit 6: PCPWM1: PWM 1 power/clock enable
data37 0:36c080f46ab1 125 #define LPC1768_PCONP_PCPWM1 0x40
data37 0:36c080f46ab1 126 // bit 7: PCI2C0: I2C interface 0 power/clock enable
data37 0:36c080f46ab1 127 #define LPC1768_PCONP_PCI2C0 0x80
data37 0:36c080f46ab1 128 // bit 8: PCSPI: SPI interface power/clock enable
data37 0:36c080f46ab1 129 #define LPC1768_PCONP_PCSPI 0x100
data37 0:36c080f46ab1 130 // bit 9: PCRTC: RTC power/clock enable
data37 0:36c080f46ab1 131 #define LPC1768_PCONP_PCRTC 0x200
data37 0:36c080f46ab1 132 // bit 10: PCSSP1: SSP interface 1 power/clock enable
data37 0:36c080f46ab1 133 #define LPC1768_PCONP_PCSSP1 0x400
data37 0:36c080f46ab1 134 // bit 11: Reserved
data37 0:36c080f46ab1 135 // bit 12: PCADC: A/D converter power/clock enable
data37 0:36c080f46ab1 136 #define LPC1768_PCONP_PCADC 0x1000
data37 0:36c080f46ab1 137 // bit 13: PCCAN1: CAN controller 1 power/clock enable
data37 0:36c080f46ab1 138 #define LPC1768_PCONP_PCCAN1 0x2000
data37 0:36c080f46ab1 139 // bit 14: PCCAN2: CAN controller 2 power/clock enable
data37 0:36c080f46ab1 140 #define LPC1768_PCONP_PCCAN2 0x4000
data37 0:36c080f46ab1 141 // bit 15: PCGPIO: GPIOs power/clock enable
data37 0:36c080f46ab1 142 #define LPC1768_PCONP_PCGPIO 0x8000
data37 0:36c080f46ab1 143 // bit 16: PCRIT: Repetitive interrupt timer power/clock enable
data37 0:36c080f46ab1 144 #define LPC1768_PCONP_PCRIT 0x10000
data37 0:36c080f46ab1 145 // bit 17: PCMCPWM: Motor control PWM power/clock enable
data37 0:36c080f46ab1 146 #define LPC1768_PCONP_PCMCPWM 0x20000
data37 0:36c080f46ab1 147 // bit 18: PCQEI: Quadrature encoder interface power/clock enable
data37 0:36c080f46ab1 148 #define LPC1768_PCONP_PCQEI 0x40000
data37 0:36c080f46ab1 149 // bit 19: PCI2C1: I2C interface 1 power/clock enable
data37 0:36c080f46ab1 150 #define LPC1768_PCONP_PCI2C1 0x80000
data37 0:36c080f46ab1 151 // bit 20: Reserved
data37 0:36c080f46ab1 152 // bit 21: PCSSP0: SSP interface 0 power/clock enable
data37 0:36c080f46ab1 153 #define LPC1768_PCONP_PCSSP0 0x200000
data37 0:36c080f46ab1 154 // bit 22: PCTIM2: Timer 2 power/clock enable
data37 0:36c080f46ab1 155 #define LPC1768_PCONP_PCTIM2 0x400000
data37 0:36c080f46ab1 156 // bit 23: PCTIM3: Timer 3 power/clock enable
data37 0:36c080f46ab1 157 #define LPC1768_PCONP_PCQTIM3 0x800000
data37 0:36c080f46ab1 158 // bit 24: PCUART2: UART 2 power/clock enable
data37 0:36c080f46ab1 159 #define LPC1768_PCONP_PCUART2 0x1000000
data37 0:36c080f46ab1 160 // bit 25: PCUART3: UART 3 power/clock enable
data37 0:36c080f46ab1 161 #define LPC1768_PCONP_PCUART3 0x2000000
data37 0:36c080f46ab1 162 // bit 26: PCI2C2: I2C interface 2 power/clock enable
data37 0:36c080f46ab1 163 #define LPC1768_PCONP_PCI2C2 0x4000000
data37 0:36c080f46ab1 164 // bit 27: PCI2S: I2S interface power/clock enable
data37 0:36c080f46ab1 165 #define LPC1768_PCONP_PCI2S 0x8000000
data37 0:36c080f46ab1 166 // bit 28: Reserved
data37 0:36c080f46ab1 167 // bit 29: PCGPDMA: GP DMA function power/clock enable
data37 0:36c080f46ab1 168 #define LPC1768_PCONP_PCGPDMA 0x20000000
data37 0:36c080f46ab1 169 // bit 30: PCENET: Ethernet block power/clock enable
data37 0:36c080f46ab1 170 #define LPC1768_PCONP_PCENET 0x40000000
data37 0:36c080f46ab1 171 // bit 31: PCUSB: USB interface power/clock enable
data37 0:36c080f46ab1 172 #define LPC1768_PCONP_PCUSB 0x80000000
data37 0:36c080f46ab1 173
data37 0:36c080f46ab1 174 //Powers Up specified Peripheral(s)
data37 0:36c080f46ab1 175 inline unsigned int Peripheral_PowerUp(unsigned int bitMask)
data37 0:36c080f46ab1 176 {
data37 0:36c080f46ab1 177 return LPC_SC->PCONP |= bitMask;
data37 0:36c080f46ab1 178 }
data37 0:36c080f46ab1 179
data37 0:36c080f46ab1 180 //Powers Down specified Peripheral(s)
data37 0:36c080f46ab1 181 inline unsigned int Peripheral_PowerDown(unsigned int bitMask)
data37 0:36c080f46ab1 182 {
data37 0:36c080f46ab1 183 return LPC_SC->PCONP &= ~bitMask;
data37 0:36c080f46ab1 184 }
data37 0:36c080f46ab1 185
data37 0:36c080f46ab1 186 //returns if the peripheral is on or off
data37 0:36c080f46ab1 187 inline bool Peripheral_GetStatus(unsigned int peripheral)
data37 0:36c080f46ab1 188 {
data37 0:36c080f46ab1 189 return (LPC_SC->PCONP & peripheral) ? true : false;
data37 0:36c080f46ab1 190 }
data37 0:36c080f46ab1 191
data37 0:36c080f46ab1 192 #endif