Jumpei Oguro
wind logger
Dependencies: SDFileSystem TextLCD mbed
Revision 0:36c080f46ab1, committed 2014-08-08
- Comitter:
- data37
- Date:
- Fri Aug 08 08:41:02 2014 +0000
- Commit message:
- tsrp wind logger
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/PowerControl/EthernetPowerControl.cpp Fri Aug 08 08:41:02 2014 +0000
@@ -0,0 +1,138 @@
+#include "EthernetPowerControl.h"
+
+static void write_PHY (unsigned int PhyReg, unsigned short Value) {
+ /* Write a data 'Value' to PHY register 'PhyReg'. */
+ unsigned int tout;
+ /* Hardware MII Management for LPC176x devices. */
+ LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+ LPC_EMAC->MWTD = Value;
+
+ /* Wait utill operation completed */
+ for (tout = 0; tout < MII_WR_TOUT; tout++) {
+ if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
+ break;
+ }
+ }
+}
+
+static unsigned short read_PHY (unsigned int PhyReg) {
+ /* Read a PHY register 'PhyReg'. */
+ unsigned int tout, val;
+
+ LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+ LPC_EMAC->MCMD = MCMD_READ;
+
+ /* Wait until operation completed */
+ for (tout = 0; tout < MII_RD_TOUT; tout++) {
+ if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
+ break;
+ }
+ }
+ LPC_EMAC->MCMD = 0;
+ val = LPC_EMAC->MRDD;
+
+ return (val);
+}
+
+void EMAC_Init()
+{
+ unsigned int tout,regv;
+ /* Power Up the EMAC controller. */
+ Peripheral_PowerUp(LPC1768_PCONP_PCENET);
+
+ LPC_PINCON->PINSEL2 = 0x50150105;
+ LPC_PINCON->PINSEL3 &= ~0x0000000F;
+ LPC_PINCON->PINSEL3 |= 0x00000005;
+
+ /* Reset all EMAC internal modules. */
+ LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
+ MAC1_SIM_RES | MAC1_SOFT_RES;
+ LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
+
+ /* A short delay after reset. */
+ for (tout = 100; tout; tout--);
+
+ /* Initialize MAC control registers. */
+ LPC_EMAC->MAC1 = MAC1_PASS_ALL;
+ LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
+ LPC_EMAC->MAXF = ETH_MAX_FLEN;
+ LPC_EMAC->CLRT = CLRT_DEF;
+ LPC_EMAC->IPGR = IPGR_DEF;
+
+ /* Enable Reduced MII interface. */
+ LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
+
+ /* Reset Reduced MII Logic. */
+ LPC_EMAC->SUPP = SUPP_RES_RMII;
+ for (tout = 100; tout; tout--);
+ LPC_EMAC->SUPP = 0;
+
+ /* Put the DP83848C in reset mode */
+ write_PHY (PHY_REG_BMCR, 0x8000);
+
+ /* Wait for hardware reset to end. */
+ for (tout = 0; tout < 0x100000; tout++) {
+ regv = read_PHY (PHY_REG_BMCR);
+ if (!(regv & 0x8000)) {
+ /* Reset complete */
+ break;
+ }
+ }
+}
+
+
+void PHY_PowerDown()
+{
+ if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
+ EMAC_Init(); //init EMAC if it is not already init'd
+
+ unsigned int regv;
+ regv = read_PHY(PHY_REG_BMCR);
+ write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
+ regv = read_PHY(PHY_REG_BMCR);
+
+ //shouldn't need the EMAC now.
+ Peripheral_PowerDown(LPC1768_PCONP_PCENET);
+
+ //and turn off the PHY OSC
+ LPC_GPIO1->FIODIR |= 0x8000000;
+ LPC_GPIO1->FIOCLR = 0x8000000;
+}
+
+void PHY_PowerUp()
+{
+ if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
+ EMAC_Init(); //init EMAC if it is not already init'd
+
+ LPC_GPIO1->FIODIR |= 0x8000000;
+ LPC_GPIO1->FIOSET = 0x8000000;
+
+ //wait for osc to be stable
+ wait_ms(200);
+
+ unsigned int regv;
+ regv = read_PHY(PHY_REG_BMCR);
+ write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
+ regv = read_PHY(PHY_REG_BMCR);
+}
+
+void PHY_EnergyDetect_Enable()
+{
+ if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
+ EMAC_Init(); //init EMAC if it is not already init'd
+
+ unsigned int regv;
+ regv = read_PHY(PHY_REG_EDCR);
+ write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
+ regv = read_PHY(PHY_REG_EDCR);
+}
+
+void PHY_EnergyDetect_Disable()
+{
+ if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
+ EMAC_Init(); //init EMAC if it is not already init'd
+ unsigned int regv;
+ regv = read_PHY(PHY_REG_EDCR);
+ write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
+ regv = read_PHY(PHY_REG_EDCR);
+}
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/PowerControl/EthernetPowerControl.h Fri Aug 08 08:41:02 2014 +0000 @@ -0,0 +1,299 @@ +/* mbed PowerControl Library + * Copyright (c) 2010 Michael Wei + */ + +#ifndef MBED_POWERCONTROL_ETH_H +#define MBED_POWERCONTROL_ETH_H + +#include "mbed.h" +#include "PowerControl.h" + +#define PHY_REG_BMCR_POWERDOWN 0xB +#define PHY_REG_EDCR_ENABLE 0xF + + +void EMAC_Init(); +static unsigned short read_PHY (unsigned int PhyReg); +static void write_PHY (unsigned int PhyReg, unsigned short Value); + +void PHY_PowerDown(void); +void PHY_PowerUp(void); +void PHY_EnergyDetect_Enable(void); +void PHY_EnergyDetect_Disable(void); + +//From NXP Sample Code .... Probably from KEIL sample code +/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ +#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ +#define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */ +#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ + +#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ + +/* EMAC variables located in 16K Ethernet SRAM */ +#define RX_DESC_BASE 0x20080000 +#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8) +#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8) +#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8) +#define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4) +#define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE) + +/* RX and TX descriptor and status definitions. */ +#define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i)) +#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i)) +#define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i)) +#define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i)) +#define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i)) +#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i)) +#define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i)) +#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i) +#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i) + +/* MAC Configuration Register 1 */ +#define MAC1_REC_EN 0x00000001 /* Receive Enable */ +#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ +#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ +#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ +#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ +#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ +#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ +#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ +#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ +#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ +#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ + +/* MAC Configuration Register 2 */ +#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ +#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ +#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ +#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ +#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ +#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ +#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ +#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ +#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ +#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ +#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ +#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ +#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ + +/* Back-to-Back Inter-Packet-Gap Register */ +#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ +#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ + +/* Non Back-to-Back Inter-Packet-Gap Register */ +#define IPGR_DEF 0x00000012 /* Recommended value */ + +/* Collision Window/Retry Register */ +#define CLRT_DEF 0x0000370F /* Default value */ + +/* PHY Support Register */ +#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ +#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ + +/* Test Register */ +#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ +#define TEST_TST_PAUSE 0x00000002 /* Test Pause */ +#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ + +/* MII Management Configuration Register */ +#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ +#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ +#define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */ +#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ + +/* MII Management Command Register */ +#define MCMD_READ 0x00000001 /* MII Read */ +#define MCMD_SCAN 0x00000002 /* MII Scan continuously */ + +#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ +#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ + +/* MII Management Address Register */ +#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ +#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ + +/* MII Management Indicators Register */ +#define MIND_BUSY 0x00000001 /* MII is Busy */ +#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ +#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ +#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ + +/* Command Register */ +#define CR_RX_EN 0x00000001 /* Enable Receive */ +#define CR_TX_EN 0x00000002 /* Enable Transmit */ +#define CR_REG_RES 0x00000008 /* Reset Host Registers */ +#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ +#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ +#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ +#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ +#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ +#define CR_RMII 0x00000200 /* Reduced MII Interface */ +#define CR_FULL_DUP 0x00000400 /* Full Duplex */ + +/* Status Register */ +#define SR_RX_EN 0x00000001 /* Enable Receive */ +#define SR_TX_EN 0x00000002 /* Enable Transmit */ + +/* Transmit Status Vector 0 Register */ +#define TSV0_CRC_ERR 0x00000001 /* CRC error */ +#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ +#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ +#define TSV0_DONE 0x00000008 /* Tramsmission Completed */ +#define TSV0_MCAST 0x00000010 /* Multicast Destination */ +#define TSV0_BCAST 0x00000020 /* Broadcast Destination */ +#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ +#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ +#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ +#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ +#define TSV0_GIANT 0x00000400 /* Giant Frame */ +#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ +#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ +#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ +#define TSV0_PAUSE 0x20000000 /* Pause Frame */ +#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ +#define TSV0_VLAN 0x80000000 /* VLAN Frame */ + +/* Transmit Status Vector 1 Register */ +#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ +#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ + +/* Receive Status Vector Register */ +#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ +#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ +#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ +#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ +#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ +#define RSV_CRC_ERR 0x00100000 /* CRC Error */ +#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ +#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ +#define RSV_REC_OK 0x00800000 /* Frame Received OK */ +#define RSV_MCAST 0x01000000 /* Multicast Frame */ +#define RSV_BCAST 0x02000000 /* Broadcast Frame */ +#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ +#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ +#define RSV_PAUSE 0x10000000 /* Pause Frame */ +#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ +#define RSV_VLAN 0x40000000 /* VLAN Frame */ + +/* Flow Control Counter Register */ +#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ +#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ + +/* Flow Control Status Register */ +#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ + +/* Receive Filter Control Register */ +#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ +#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ +#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ +#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ +#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ +#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ +#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ +#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ + +/* Receive Filter WoL Status/Clear Registers */ +#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ +#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ +#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ +#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ +#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ +#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ +#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ +#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ + +/* Interrupt Status/Enable/Clear/Set Registers */ +#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ +#define INT_RX_ERR 0x00000002 /* Receive Error */ +#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ +#define INT_RX_DONE 0x00000008 /* Receive Done */ +#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ +#define INT_TX_ERR 0x00000020 /* Transmit Error */ +#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ +#define INT_TX_DONE 0x00000080 /* Transmit Done */ +#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ +#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ + +/* Power Down Register */ +#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ + +/* RX Descriptor Control Word */ +#define RCTRL_SIZE 0x000007FF /* Buffer size mask */ +#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ + +/* RX Status Hash CRC Word */ +#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ +#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ + +/* RX Status Information Word */ +#define RINFO_SIZE 0x000007FF /* Data size in bytes */ +#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ +#define RINFO_VLAN 0x00080000 /* VLAN Frame */ +#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ +#define RINFO_MCAST 0x00200000 /* Multicast Frame */ +#define RINFO_BCAST 0x00400000 /* Broadcast Frame */ +#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ +#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ +#define RINFO_LEN_ERR 0x02000000 /* Length Error */ +#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ +#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ +#define RINFO_OVERRUN 0x10000000 /* Receive overrun */ +#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ +#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ +#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \ + RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) + +/* TX Descriptor Control Word */ +#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ +#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ +#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ +#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ +#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ +#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ +#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ + +/* TX Status Information Word */ +#define TINFO_COL_CNT 0x01E00000 /* Collision Count */ +#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ +#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ +#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ +#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ +#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ +#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ +#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +/* DP83848C PHY Registers */ +#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ +#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ +#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ +#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ +#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ +#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ +#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ +#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ + +/* PHY Extended Registers */ +#define PHY_REG_STS 0x10 /* Status Register */ +#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ +#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ +#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ +#define PHY_REG_RECR 0x15 /* Receive Error Counter */ +#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ +#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ +#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ +#define PHY_REG_PHYCR 0x19 /* PHY Control Register */ +#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ +#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ +#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ + +#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ +#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ +#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ +#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ +#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ + +#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ +#define DP83848C_ID 0x20005C90 /* PHY Identifier */ +#endif \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/PowerControl/PowerControl.h Fri Aug 08 08:41:02 2014 +0000
@@ -0,0 +1,192 @@
+/* mbed PowerControl Library
+ * Copyright (c) 2010 Michael Wei
+ */
+
+#ifndef MBED_POWERCONTROL_H
+#define MBED_POWERCONTROL_H
+
+//shouldn't have to include, but fixes weird problems with defines
+//#include "LPC1768/LPC17xx.h"
+
+//System Control Register
+// bit 0: Reserved
+// bit 1: Sleep on Exit
+#define LPC1768_SCR_SLEEPONEXIT 0x2
+// bit 2: Deep Sleep
+#define LPC1768_SCR_SLEEPDEEP 0x4
+// bit 3: Resereved
+// bit 4: Send on Pending
+#define LPC1768_SCR_SEVONPEND 0x10
+// bit 5-31: Reserved
+
+//Power Control Register
+// bit 0: Power mode control bit 0 (power-down mode)
+#define LPC1768_PCON_PM0 0x1
+// bit 1: Power mode control bit 1 (deep power-down mode)
+#define LPC1768_PCON_PM1 0x2
+// bit 2: Brown-out reduced power mode
+#define LPC1768_PCON_BODRPM 0x4
+// bit 3: Brown-out global disable
+#define LPC1768_PCON_BOGD 0x8
+// bit 4: Brown-out reset disable
+#define LPC1768_PCON_BORD 0x10
+// bit 5-7 : Reserved
+// bit 8: Sleep Mode Entry Flag
+#define LPC1768_PCON_SMFLAG 0x100
+// bit 9: Deep Sleep Entry Flag
+#define LPC1768_PCON_DSFLAG 0x200
+// bit 10: Power Down Entry Flag
+#define LPC1768_PCON_PDFLAG 0x400
+// bit 11: Deep Power Down Entry Flag
+#define LPC1768_PCON_DPDFLAG 0x800
+// bit 12-31: Reserved
+
+//"Sleep Mode" (WFI).
+inline void Sleep(void)
+{
+ __WFI();
+}
+
+//"Deep Sleep" Mode
+inline void DeepSleep(void)
+{
+ SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
+ __WFI();
+}
+
+//"Power-Down" Mode
+inline void PowerDown(void)
+{
+ SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
+ LPC_SC->PCON &= ~LPC1768_PCON_PM1;
+ LPC_SC->PCON |= LPC1768_PCON_PM0;
+ __WFI();
+ //reset back to normal
+ LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
+}
+
+//"Deep Power-Down" Mode
+inline void DeepPowerDown(void)
+{
+ SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
+ LPC_SC->PCON |= LPC1768_PCON_PM1 | LPC1768_PCON_PM0;
+ __WFI();
+ //reset back to normal
+ LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
+}
+
+//shut down BOD during power-down/deep sleep
+inline void BrownOut_ReducedPowerMode_Enable(void)
+{
+ LPC_SC->PCON |= LPC1768_PCON_BODRPM;
+}
+
+//turn on BOD during power-down/deep sleep
+inline void BrownOut_ReducedPowerMode_Disable(void)
+{
+ LPC_SC->PCON &= ~LPC1768_PCON_BODRPM;
+}
+
+//turn off brown out circutry
+inline void BrownOut_Global_Disable(void)
+{
+ LPC_SC->PCON |= LPC1768_PCON_BOGD;
+}
+
+//turn on brown out circutry
+inline void BrownOut_Global_Enable(void)
+{
+ LPC_SC->PCON &= !LPC1768_PCON_BOGD;
+}
+
+//turn off brown out reset circutry
+inline void BrownOut_Reset_Disable(void)
+{
+ LPC_SC->PCON |= LPC1768_PCON_BORD;
+}
+
+//turn on brown outreset circutry
+inline void BrownOut_Reset_Enable(void)
+{
+ LPC_SC->PCON &= ~LPC1768_PCON_BORD;
+}
+//Peripheral Control Register
+// bit 0: Reserved
+// bit 1: PCTIM0: Timer/Counter 0 power/clock enable
+#define LPC1768_PCONP_PCTIM0 0x2
+// bit 2: PCTIM1: Timer/Counter 1 power/clock enable
+#define LPC1768_PCONP_PCTIM1 0x4
+// bit 3: PCUART0: UART 0 power/clock enable
+#define LPC1768_PCONP_PCUART0 0x8
+// bit 4: PCUART1: UART 1 power/clock enable
+#define LPC1768_PCONP_PCUART1 0x10
+// bit 5: Reserved
+// bit 6: PCPWM1: PWM 1 power/clock enable
+#define LPC1768_PCONP_PCPWM1 0x40
+// bit 7: PCI2C0: I2C interface 0 power/clock enable
+#define LPC1768_PCONP_PCI2C0 0x80
+// bit 8: PCSPI: SPI interface power/clock enable
+#define LPC1768_PCONP_PCSPI 0x100
+// bit 9: PCRTC: RTC power/clock enable
+#define LPC1768_PCONP_PCRTC 0x200
+// bit 10: PCSSP1: SSP interface 1 power/clock enable
+#define LPC1768_PCONP_PCSSP1 0x400
+// bit 11: Reserved
+// bit 12: PCADC: A/D converter power/clock enable
+#define LPC1768_PCONP_PCADC 0x1000
+// bit 13: PCCAN1: CAN controller 1 power/clock enable
+#define LPC1768_PCONP_PCCAN1 0x2000
+// bit 14: PCCAN2: CAN controller 2 power/clock enable
+#define LPC1768_PCONP_PCCAN2 0x4000
+// bit 15: PCGPIO: GPIOs power/clock enable
+#define LPC1768_PCONP_PCGPIO 0x8000
+// bit 16: PCRIT: Repetitive interrupt timer power/clock enable
+#define LPC1768_PCONP_PCRIT 0x10000
+// bit 17: PCMCPWM: Motor control PWM power/clock enable
+#define LPC1768_PCONP_PCMCPWM 0x20000
+// bit 18: PCQEI: Quadrature encoder interface power/clock enable
+#define LPC1768_PCONP_PCQEI 0x40000
+// bit 19: PCI2C1: I2C interface 1 power/clock enable
+#define LPC1768_PCONP_PCI2C1 0x80000
+// bit 20: Reserved
+// bit 21: PCSSP0: SSP interface 0 power/clock enable
+#define LPC1768_PCONP_PCSSP0 0x200000
+// bit 22: PCTIM2: Timer 2 power/clock enable
+#define LPC1768_PCONP_PCTIM2 0x400000
+// bit 23: PCTIM3: Timer 3 power/clock enable
+#define LPC1768_PCONP_PCQTIM3 0x800000
+// bit 24: PCUART2: UART 2 power/clock enable
+#define LPC1768_PCONP_PCUART2 0x1000000
+// bit 25: PCUART3: UART 3 power/clock enable
+#define LPC1768_PCONP_PCUART3 0x2000000
+// bit 26: PCI2C2: I2C interface 2 power/clock enable
+#define LPC1768_PCONP_PCI2C2 0x4000000
+// bit 27: PCI2S: I2S interface power/clock enable
+#define LPC1768_PCONP_PCI2S 0x8000000
+// bit 28: Reserved
+// bit 29: PCGPDMA: GP DMA function power/clock enable
+#define LPC1768_PCONP_PCGPDMA 0x20000000
+// bit 30: PCENET: Ethernet block power/clock enable
+#define LPC1768_PCONP_PCENET 0x40000000
+// bit 31: PCUSB: USB interface power/clock enable
+#define LPC1768_PCONP_PCUSB 0x80000000
+
+//Powers Up specified Peripheral(s)
+inline unsigned int Peripheral_PowerUp(unsigned int bitMask)
+{
+ return LPC_SC->PCONP |= bitMask;
+}
+
+//Powers Down specified Peripheral(s)
+inline unsigned int Peripheral_PowerDown(unsigned int bitMask)
+{
+ return LPC_SC->PCONP &= ~bitMask;
+}
+
+//returns if the peripheral is on or off
+inline bool Peripheral_GetStatus(unsigned int peripheral)
+{
+ return (LPC_SC->PCONP & peripheral) ? true : false;
+}
+
+#endif
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/SDFileSystem.lib Fri Aug 08 08:41:02 2014 +0000 @@ -0,0 +1,1 @@ +http://mbed.org/users/mbed_official/code/SDFileSystem/#c8f66dc765d4
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TextLCD.lib Fri Aug 08 08:41:02 2014 +0000 @@ -0,0 +1,1 @@ +http://mbed.org/users/simon/code/TextLCD/#e4cb7ddee0d3
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/main.cpp Fri Aug 08 08:41:02 2014 +0000
@@ -0,0 +1,219 @@
+#include "mbed.h"
+#include "TextLCD.h"
+#include "PowerControl/PowerControl.h"
+#include "PowerControl/EthernetPowerControl.h"
+#include "SDFileSystem.h"
+// wind data receiver (not SDcard logger)
+DigitalOut myled1(LED1);
+DigitalOut myled2(LED2);
+DigitalOut myled3(LED3);
+DigitalOut myled4(LED4);
+SDFileSystem sd(p5, p6, p7, p8, "sd");
+TextLCD lcd(p24, p26, p27, p28, p29, p30); // rs, e, d4-d7
+
+Serial pc(USBTX, USBRX);
+Serial xbee(p13,p14);
+
+#define PI 3.1415926535
+
+int main() {
+ PHY_PowerDown();
+ myled1=1;
+ myled2=0;
+ myled3=0;
+ myled4=0;
+
+ pc.baud(9600);
+ xbee.baud(9600);
+
+
+ //wind data value
+ char wind_data[256];
+ float windvel_5min_ave,windvel_5sec_ave;
+ float winddeg_5sec_ave=0.0,winddeg_5min_ave=0.0;
+ char winddeg_5min_ave_c[4],winddeg_5sec_ave_c[4];
+ //strcpy(winddeg_5sec_ave_c," ");
+ //strcpy(winddeg_5min_ave_c," ");
+ //float year,month,day;
+ //char time[8];
+ //float pre,temp;
+ int i=0;
+ int j=0;
+ int h=0;
+ char k[2];
+
+ //Value
+ long dt = 1000000; //1 Hz (1000000 us, 1000 ms)
+ //float time = 0.0;
+ Timer ti;
+ long tminus = 0;
+
+
+ //LCD startup
+ lcd.cls();
+
+ lcd.locate(0,0);
+ lcd.printf("-Windmeter LCD!-");
+
+ lcd.locate(0,1);
+ lcd.printf("-----Ready!-----");
+ wait(2);
+ //uint8_t buf[128];
+ lcd.cls();
+ lcd.locate(0,0);
+ lcd.printf("------Wait------");
+ lcd.locate(0,1);
+ lcd.printf("----no data!----");
+ ti.reset();
+
+ //wind parameter set
+ char wind_data[256];
+ //char winddeg_c[4];
+ char winddeg_5sec_ave_c[4],winddeg_5min_ave_c[4];
+ float winddeg,windvel;
+ float windvel_5sec[6],windvel_5min[301];
+ float winddeg_5sec[6],winddeg_5min[301];
+ float windvel_5sec_ave=0.0,windvel_5min_ave=0.0;
+ float winddeg_5sec_ave=0.0,winddeg_5min_ave=0.0;
+ for(i=0; i<=5; i++){windvel_5sec[i]=0.0; winddeg_5sec[i]=0.0;}
+ for(i=0; i<=300; i++){windvel_5min[i]=0.0; winddeg_5min[i]=0.0;}
+
+ char idir[14] = "/sd/";
+ char time_c[7],date_c[9];
+
+ sprintf(date_c,"%4d%2d%2d",y_date,m_date,d_date);
+ sprintf(time_c,"%2d%2d%2d",h_time,m_time,s_time);
+
+ char filename[15] = "";
+ strcat(filename,date_c);
+ strcat(filename,time_c);
+
+ char dir[100] = "";
+ strcat(idir,date_c);
+ mkdir(idir, 0777);
+
+ strcat(dir,idir);
+ strcat(dir,"/");
+ strcat(dir,filename);
+ strcat(dir,".csv");
+
+ FILE *fp = fopen(dir, "w");
+ if(fp == NULL) {
+ error("Could not open file for write\r\n");
+ myled3 = 1;
+ }
+ //fprintf(fp, "Year,Month,Day,hh:mm:ss,wind_velocity[m/s],wind_velocity_5sec[m/s],wind_velocity_5min[m/s],wind_direction[deg],wind_direction_5sec[deg],wind_direction_5min[deg],Atmospheric Pressure[Pa],Temperature[degC]\n");
+ fprintf(fp, "Year,Month,Day,hh:mm:ss,wind_velocity[m/s],wind_direction[deg],wind_velocity_5sec[m/s],wind_direction_5sec[deg],wind_velocity_5min[m/s],wind_direction_5min[deg]\n");
+
+ fclose(fp);
+
+ while(1){
+ ti.start();
+ myled1=0;
+ i=0;
+ while(xbee.getc()!='Q'){
+ lcd.locate(0,16);
+ lcd.printf("i");
+ }
+ myled1 = 1;
+ i=0;
+ while( (wind_data[i]=xbee.getc()) != '\r'){
+ i++;
+ if(i==256){
+ //lcd.locate(0,1);
+ //lcd.printf("Data read Error");
+ i=255;
+ break;
+ }
+ }
+ myled1 = 0;
+ wind_data[i]='\0';
+ if(i<=256){
+ //if( sscanf(wind_data, "WAPT,%f,%f,%c,%f",&year,&month,&day,&time,&windvel_5sec_ave,&winddeg_5sec_ave_c,&windvel_5min_ave,&winddeg_5min_ave_c,&pre,&temp) >= 1)
+ //if( sscanf(wind_data, "WAPT,%f,%f,%f,%f,%s",&windvel_5sec_ave,&winddeg_5sec_ave,&windvel_5min_ave,&winddeg_5min_ave,&k) >= 1)
+ if( sscanf(wind_data, ",%f,%f,%c,%f",&winddeg,&windvel,&ms,&check) >= 1){
+ if( check == 0 ){
+ windvel_5sec[j] = windvel;
+ winddeg_5sec[j] = winddeg;
+ windvel_5min[k] = windvel;
+ winddeg_5min[k] = winddeg;
+
+ j++;
+ k++;
+
+ if(j==5){j=1;}
+ if(k==300){k=1;}
+
+ for(i=1; i<=5; i++){windvel_5sec_ave +=windvel_5sec[i];}
+ for(i=1; i<=5; i++){winddeg_5sec_ave +=winddeg_5sec[i];}
+ windvel_5sec_ave /= 5.0;
+ winddeg_5sec_ave /= 5.0;
+ for(i=1; i<=300; i++){windvel_5min_ave +=windvel_5min[i];}
+ for(i=1; i<=300; i++){winddeg_5min_ave +=winddeg_5min[i];}
+ windvel_5min_ave /= 300.0;
+ winddeg_5min_ave /= 300.0;
+ if(winddeg_5sec_ave>348.75 || winddeg_5sec_ave<=11.25){strcpy(winddeg_5sec_ave_c,"N ");}
+ if(winddeg_5sec_ave>11.25 && winddeg_5sec_ave<=33.75){strcpy(winddeg_5sec_ave_c,"NNE");}
+ if(winddeg_5sec_ave>33.75 && winddeg_5sec_ave<=56.25){strcpy(winddeg_5sec_ave_c,"NE ");}
+ if(winddeg_5sec_ave>56.25 && winddeg_5sec_ave<=78.75){strcpy(winddeg_5sec_ave_c,"ENE");}
+ if(winddeg_5sec_ave>78.75 && winddeg_5sec_ave<=101.25){strcpy(winddeg_5sec_ave_c,"E ");}
+ if(winddeg_5sec_ave>101.25 && winddeg_5sec_ave<=123.75){strcpy(winddeg_5sec_ave_c,"ESE");}
+ if(winddeg_5sec_ave>123.75 && winddeg_5sec_ave<=146.25){strcpy(winddeg_5sec_ave_c,"SE ");}
+ if(winddeg_5sec_ave>146.25 && winddeg_5sec_ave<=168.75){strcpy(winddeg_5sec_ave_c,"SSE");}
+ if(winddeg_5sec_ave>168.75 && winddeg_5sec_ave<=191.25){strcpy(winddeg_5sec_ave_c,"S ");}
+ if(winddeg_5sec_ave>191.25 && winddeg_5sec_ave<=213.75){strcpy(winddeg_5sec_ave_c,"SSW");}
+ if(winddeg_5sec_ave>213.75 && winddeg_5sec_ave<=236.25){strcpy(winddeg_5sec_ave_c,"SW ");}
+ if(winddeg_5sec_ave>236.25 && winddeg_5sec_ave<=258.75){strcpy(winddeg_5sec_ave_c,"WSW");}
+ if(winddeg_5sec_ave>258.75 && winddeg_5sec_ave<=281.25){strcpy(winddeg_5sec_ave_c,"W ");}
+ if(winddeg_5sec_ave>281.25 && winddeg_5sec_ave<=303.75){strcpy(winddeg_5sec_ave_c,"WNW");}
+ if(winddeg_5sec_ave>303.75 && winddeg_5sec_ave<=326.25){strcpy(winddeg_5sec_ave_c,"NW ");}
+ if(winddeg_5sec_ave>326.25 && winddeg_5sec_ave<=348.75){strcpy(winddeg_5sec_ave_c,"NNW");}
+
+ if(winddeg_5min_ave>348.75 || winddeg_5min_ave<=11.25){strcpy(winddeg_5min_ave_c,"N ");}
+ if(winddeg_5min_ave>11.25 && winddeg_5min_ave<=33.75){strcpy(winddeg_5min_ave_c,"NNE");}
+ if(winddeg_5min_ave>33.75 && winddeg_5min_ave<=56.25){strcpy(winddeg_5min_ave_c,"NE ");}
+ if(winddeg_5min_ave>56.25 && winddeg_5min_ave<=78.75){strcpy(winddeg_5min_ave_c,"ENE");}
+ if(winddeg_5min_ave>78.75 && winddeg_5min_ave<=101.25){strcpy(winddeg_5min_ave_c,"E ");}
+ if(winddeg_5min_ave>101.25 && winddeg_5min_ave<=123.75){strcpy(winddeg_5min_ave_c,"ESE");}
+ if(winddeg_5min_ave>123.75 && winddeg_5min_ave<=146.25){strcpy(winddeg_5min_ave_c,"SE ");}
+ if(winddeg_5min_ave>146.25 && winddeg_5min_ave<=168.75){strcpy(winddeg_5min_ave_c,"SSE");}
+ if(winddeg_5min_ave>168.75 && winddeg_5min_ave<=191.25){strcpy(winddeg_5min_ave_c,"S ");}
+ if(winddeg_5min_ave>191.25 && winddeg_5min_ave<=213.75){strcpy(winddeg_5min_ave_c,"SSW");}
+ if(winddeg_5min_ave>213.75 && winddeg_5min_ave<=236.25){strcpy(winddeg_5min_ave_c,"SW ");}
+ if(winddeg_5min_ave>236.25 && winddeg_5min_ave<=258.75){strcpy(winddeg_5min_ave_c,"WSW");}
+ if(winddeg_5min_ave>258.75 && winddeg_5min_ave<=281.25){strcpy(winddeg_5min_ave_c,"W ");}
+ if(winddeg_5min_ave>281.25 && winddeg_5min_ave<=303.75){strcpy(winddeg_5min_ave_c,"WNW");}
+ if(winddeg_5min_ave>303.75 && winddeg_5min_ave<=326.25){strcpy(winddeg_5min_ave_c,"NW ");}
+ if(winddeg_5min_ave>326.25 && winddeg_5min_ave<=348.75){strcpy(winddeg_5min_ave_c,"NNW");}
+
+ if(h>=9) {h=0;}
+ else {h++;}
+ lcd.cls();
+ lcd.locate(0,0);
+ lcd.printf("5s:%5.2fm/s %s",windvel_5sec_ave,winddeg_5sec_ave_c);
+ lcd.locate(0,1);
+ lcd.printf("5m:%5.2fm/s %s%d",windvel_5min_ave,winddeg_5min_ave_c,h);
+ //lcd.locate(0,1);
+ //lcd.printf("%6.2f hPa %4.2f ",Press[0]/100.0,Press[1]);
+ }
+ else
+ {
+ lcd.cls();
+ lcd.locate(0,0);
+ lcd.printf("-Windmeter LCD!-");
+ lcd.locate(0,1);
+ lcd.printf("Data read Error");
+ }
+ }
+ strcpy(winddeg_5sec_ave_c," ");
+ strcpy(winddeg_5min_ave_c," ");
+ for(i=0; i<=256; i++) wind_data[i] = 0;
+ }
+
+ while(1) {
+ myled1 = 1;
+ wait(0.2);
+ myled1 = 0;
+ wait(0.2);
+ }
+}
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed.bld Fri Aug 08 08:41:02 2014 +0000 @@ -0,0 +1,1 @@ +http://mbed.org/users/mbed_official/code/mbed/builds/5798e58a58b1 \ No newline at end of file