FYPFinalizeProgram -

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Daryl Tan Wei Guang / Mbed 2 deprecated FYPFinalizeProgram

Dependencies: keypad SDHCFileSystem mbed FPointer wave_player

scmRTOS/CortexM3/OS_Target.h@0:879af6e11219, 2012-02-20 (annotated)

Committer:: daryl2110
Date:: Mon Feb 20 07:36:06 2012 +0000
Revision:: 0:879af6e11219

Who changed what in which revision?

User	Revision	Line number	New contents of line
daryl2110	0:879af6e11219	1	//******************************************************************************
daryl2110	0:879af6e11219	2	//*
daryl2110	0:879af6e11219	3	//* FULLNAME: Single-Chip Microcontroller Real-Time Operating System
daryl2110	0:879af6e11219	4	//*
daryl2110	0:879af6e11219	5	//* NICKNAME: scmRTOS
daryl2110	0:879af6e11219	6	//*
daryl2110	0:879af6e11219	7	//* PROCESSOR: ARM Cortex-M3
daryl2110	0:879af6e11219	8	//*
daryl2110	0:879af6e11219	9	//* TOOLKIT: RVCT (ARM)
daryl2110	0:879af6e11219	10	//*
daryl2110	0:879af6e11219	11	//* PURPOSE: Target Dependent Stuff Header. Declarations And Definitions
daryl2110	0:879af6e11219	12	//*
daryl2110	0:879af6e11219	13	//* Version: 3.10
daryl2110	0:879af6e11219	14	//*
daryl2110	0:879af6e11219	15	//* $Revision: 195 $
daryl2110	0:879af6e11219	16	//* $Date:: 2008-06-19 #$
daryl2110	0:879af6e11219	17	//*
daryl2110	0:879af6e11219	18	//* Copyright (c) 2003-2010, Harry E. Zhurov
daryl2110	0:879af6e11219	19	//*
daryl2110	0:879af6e11219	20	//* Permission is hereby granted, free of charge, to any person
daryl2110	0:879af6e11219	21	//* obtaining a copy of this software and associated documentation
daryl2110	0:879af6e11219	22	//* files (the "Software"), to deal in the Software without restriction,
daryl2110	0:879af6e11219	23	//* including without limitation the rights to use, copy, modify, merge,
daryl2110	0:879af6e11219	24	//* publish, distribute, sublicense, and/or sell copies of the Software,
daryl2110	0:879af6e11219	25	//* and to permit persons to whom the Software is furnished to do so,
daryl2110	0:879af6e11219	26	//* subject to the following conditions:
daryl2110	0:879af6e11219	27	//*
daryl2110	0:879af6e11219	28	//* The above copyright notice and this permission notice shall be included
daryl2110	0:879af6e11219	29	//* in all copies or substantial portions of the Software.
daryl2110	0:879af6e11219	30	//*
daryl2110	0:879af6e11219	31	//* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
daryl2110	0:879af6e11219	32	//* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
daryl2110	0:879af6e11219	33	//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
daryl2110	0:879af6e11219	34	//* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
daryl2110	0:879af6e11219	35	//* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
daryl2110	0:879af6e11219	36	//* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH
daryl2110	0:879af6e11219	37	//* THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
daryl2110	0:879af6e11219	38	//*
daryl2110	0:879af6e11219	39	//* =================================================================
daryl2110	0:879af6e11219	40	//* See http://scmrtos.sourceforge.net for documentation, latest
daryl2110	0:879af6e11219	41	//* information, license and contact details.
daryl2110	0:879af6e11219	42	//* =================================================================
daryl2110	0:879af6e11219	43	//*
daryl2110	0:879af6e11219	44	//******************************************************************************
daryl2110	0:879af6e11219	45	//* Ported by Andrey Chuikin, Copyright (c) 2008-2010
daryl2110	0:879af6e11219	46
daryl2110	0:879af6e11219	47	#ifndef scmRTOS_CORTEXM3_H
daryl2110	0:879af6e11219	48	#define scmRTOS_CORTEXM3_H
daryl2110	0:879af6e11219	49
daryl2110	0:879af6e11219	50	#include <commdefs.h>
daryl2110	0:879af6e11219	51
daryl2110	0:879af6e11219	52	//------------------------------------------------------------------------------
daryl2110	0:879af6e11219	53	//
daryl2110	0:879af6e11219	54	// Compiler and Target checks
daryl2110	0:879af6e11219	55	//
daryl2110	0:879af6e11219	56	//
daryl2110	0:879af6e11219	57	#ifndef __ARMCC_VERSION
daryl2110	0:879af6e11219	58	#error "This file should only be compiled with ARM RVCT Compiler"
daryl2110	0:879af6e11219	59	#endif // __ARMCC_VERSION
daryl2110	0:879af6e11219	60
daryl2110	0:879af6e11219	61	#if __TARGET_ARCH_ARM != 0 \|\| __TARGET_ARCH_THUMB != 4
daryl2110	0:879af6e11219	62	#error "This file must be compiled for ARMv7-M (Cortex-M3) processor only."
daryl2110	0:879af6e11219	63	#endif
daryl2110	0:879af6e11219	64
daryl2110	0:879af6e11219	65	//------------------------------------------------------------------------------
daryl2110	0:879af6e11219	66	//
daryl2110	0:879af6e11219	67	// Target specific types
daryl2110	0:879af6e11219	68	//
daryl2110	0:879af6e11219	69	//
daryl2110	0:879af6e11219	70	typedef dword TStackItem;
daryl2110	0:879af6e11219	71	typedef dword TStatusReg;
daryl2110	0:879af6e11219	72
daryl2110	0:879af6e11219	73	//-----------------------------------------------------------------------------
daryl2110	0:879af6e11219	74	//
daryl2110	0:879af6e11219	75	// Configuration macros
daryl2110	0:879af6e11219	76	//
daryl2110	0:879af6e11219	77	//
daryl2110	0:879af6e11219	78	#define OS_PROCESS __attribute__((__noreturn__))
daryl2110	0:879af6e11219	79	#define OS_INTERRUPT
daryl2110	0:879af6e11219	80	#define DUMMY_INSTR() __NOP()
daryl2110	0:879af6e11219	81	#define INLINE_PROCESS_CTOR INLINE inline
daryl2110	0:879af6e11219	82
daryl2110	0:879af6e11219	83	//-----------------------------------------------------------------------------
daryl2110	0:879af6e11219	84	//
daryl2110	0:879af6e11219	85	// Uncomment macro value below for SystemTimer() run in critical section
daryl2110	0:879af6e11219	86	//
daryl2110	0:879af6e11219	87	// This is useful (and necessary) when target processor has hardware
daryl2110	0:879af6e11219	88	// enabled nested interrups. Cortex-M3 have such interrupts.
daryl2110	0:879af6e11219	89	//
daryl2110	0:879af6e11219	90	#define SYS_TIMER_CRIT_SECT() TCritSect cs
daryl2110	0:879af6e11219	91
daryl2110	0:879af6e11219	92	//-----------------------------------------------------------------------------
daryl2110	0:879af6e11219	93	// Separate return stack not required
daryl2110	0:879af6e11219	94	#define SEPARATE_RETURN_STACK 0
daryl2110	0:879af6e11219	95
daryl2110	0:879af6e11219	96	//-----------------------------------------------------------------------------
daryl2110	0:879af6e11219	97	// Software interrupt stack switching not supported in Cortex-M3 port
daryl2110	0:879af6e11219	98	// because processor implements hardware stack switching.
daryl2110	0:879af6e11219	99	// So, system timer isr wrapper can't be choosen at project level
daryl2110	0:879af6e11219	100	//
daryl2110	0:879af6e11219	101	#define scmRTOS_ISRW_TYPE TISRW
daryl2110	0:879af6e11219	102
daryl2110	0:879af6e11219	103	//-----------------------------------------------------------------------------
daryl2110	0:879af6e11219	104	//
daryl2110	0:879af6e11219	105	// scmRTOS Context Switch Scheme
daryl2110	0:879af6e11219	106	//
daryl2110	0:879af6e11219	107	// The macro defines a context switch manner. Value 0 sets direct context
daryl2110	0:879af6e11219	108	// switch in the scheduler and in the OS ISRs. This is the primary method.
daryl2110	0:879af6e11219	109	// Value 1 sets the second way to switch context - by using of software
daryl2110	0:879af6e11219	110	// interrupt. See documentation fo details.
daryl2110	0:879af6e11219	111	// Cortex-M3 port supports software interrupt switch method only.
daryl2110	0:879af6e11219	112	//
daryl2110	0:879af6e11219	113	#define scmRTOS_CONTEXT_SWITCH_SCHEME 1
daryl2110	0:879af6e11219	114
daryl2110	0:879af6e11219	115	//-----------------------------------------------------------------------------
daryl2110	0:879af6e11219	116	//
daryl2110	0:879af6e11219	117	// Include project-level configurations
daryl2110	0:879af6e11219	118	// !!! The order of includes is important !!!
daryl2110	0:879af6e11219	119	//
daryl2110	0:879af6e11219	120	#include "../../scmRTOS_config.h"
daryl2110	0:879af6e11219	121	#include "../scmRTOS_TARGET_CFG.h"
daryl2110	0:879af6e11219	122	#include <scmRTOS_defs.h>
daryl2110	0:879af6e11219	123	#include <LPC17xx.h>
daryl2110	0:879af6e11219	124
daryl2110	0:879af6e11219	125	//-----------------------------------------------------------------------------
daryl2110	0:879af6e11219	126	//
daryl2110	0:879af6e11219	127	// The Critital Section Wrapper
daryl2110	0:879af6e11219	128	//
daryl2110	0:879af6e11219	129	//
daryl2110	0:879af6e11219	130	#define __enable_interrupt() __enable_irq()
daryl2110	0:879af6e11219	131	#define __disable_interrupt() __disable_irq()
daryl2110	0:879af6e11219	132
daryl2110	0:879af6e11219	133	#define __set_interrupt_state(status) __set_PRIMASK(status)
daryl2110	0:879af6e11219	134	#define __get_interrupt_state() __get_PRIMASK()
daryl2110	0:879af6e11219	135
daryl2110	0:879af6e11219	136	class TCritSect
daryl2110	0:879af6e11219	137	{
daryl2110	0:879af6e11219	138	public:
daryl2110	0:879af6e11219	139	TCritSect () : StatusReg(__get_interrupt_state()) { __disable_interrupt(); }
daryl2110	0:879af6e11219	140	~TCritSect() { __set_interrupt_state(StatusReg); }
daryl2110	0:879af6e11219	141
daryl2110	0:879af6e11219	142	private:
daryl2110	0:879af6e11219	143	TStatusReg StatusReg;
daryl2110	0:879af6e11219	144	};
daryl2110	0:879af6e11219	145	//-----------------------------------------------------------------------------
daryl2110	0:879af6e11219	146
daryl2110	0:879af6e11219	147	//-----------------------------------------------------------------------------
daryl2110	0:879af6e11219	148	//
daryl2110	0:879af6e11219	149	// Priority stuff
daryl2110	0:879af6e11219	150	//
daryl2110	0:879af6e11219	151	//
daryl2110	0:879af6e11219	152	namespace OS
daryl2110	0:879af6e11219	153	{
daryl2110	0:879af6e11219	154	INLINE inline OS::TProcessMap GetPrioTag(const byte pr) { return static_cast<OS::TProcessMap> (1 << pr); }
daryl2110	0:879af6e11219	155
daryl2110	0:879af6e11219	156	#if scmRTOS_PRIORITY_ORDER == 0
daryl2110	0:879af6e11219	157	INLINE inline byte GetHighPriority(TProcessMap pm)
daryl2110	0:879af6e11219	158	{
daryl2110	0:879af6e11219	159	byte pr = 0;
daryl2110	0:879af6e11219	160
daryl2110	0:879af6e11219	161	while( !(pm & 0x0001) )
daryl2110	0:879af6e11219	162	{
daryl2110	0:879af6e11219	163	pr++;
daryl2110	0:879af6e11219	164	pm >>= 1;
daryl2110	0:879af6e11219	165	}
daryl2110	0:879af6e11219	166	return pr;
daryl2110	0:879af6e11219	167	}
daryl2110	0:879af6e11219	168	#else
daryl2110	0:879af6e11219	169	INLINE inline byte GetHighPriority(TProcessMap pm) { return (31 - __clz(pm)); }
daryl2110	0:879af6e11219	170	#endif // scmRTOS_PRIORITY_ORDER
daryl2110	0:879af6e11219	171	}
daryl2110	0:879af6e11219	172
daryl2110	0:879af6e11219	173	//-----------------------------------------------------------------------------
daryl2110	0:879af6e11219	174	//
daryl2110	0:879af6e11219	175	// Interrupt and Interrupt Service Routines support
daryl2110	0:879af6e11219	176	//
daryl2110	0:879af6e11219	177	INLINE inline TStatusReg GetInterruptState( ) { return __get_interrupt_state(); }
daryl2110	0:879af6e11219	178	INLINE inline void SetInterruptState(TStatusReg sr) { __set_interrupt_state(sr); }
daryl2110	0:879af6e11219	179
daryl2110	0:879af6e11219	180	INLINE inline void EnableInterrupts() { __enable_interrupt(); }
daryl2110	0:879af6e11219	181	INLINE inline void DisableInterrupts() { __disable_interrupt(); }
daryl2110	0:879af6e11219	182
daryl2110	0:879af6e11219	183
daryl2110	0:879af6e11219	184	namespace OS
daryl2110	0:879af6e11219	185	{
daryl2110	0:879af6e11219	186	INLINE inline void EnableContextSwitch() { EnableInterrupts(); }
daryl2110	0:879af6e11219	187	INLINE inline void DisableContextSwitch() { DisableInterrupts(); }
daryl2110	0:879af6e11219	188	}
daryl2110	0:879af6e11219	189
daryl2110	0:879af6e11219	190	#include <OS_Kernel.h>
daryl2110	0:879af6e11219	191
daryl2110	0:879af6e11219	192	namespace OS
daryl2110	0:879af6e11219	193	{
daryl2110	0:879af6e11219	194	//--------------------------------------------------------------------------
daryl2110	0:879af6e11219	195	//
daryl2110	0:879af6e11219	196	// NAME : OS ISR support
daryl2110	0:879af6e11219	197	//
daryl2110	0:879af6e11219	198	// PURPOSE : Implements common actions on interrupt enter and exit
daryl2110	0:879af6e11219	199	// under the OS
daryl2110	0:879af6e11219	200	//
daryl2110	0:879af6e11219	201	// DESCRIPTION:
daryl2110	0:879af6e11219	202	//
daryl2110	0:879af6e11219	203	//
daryl2110	0:879af6e11219	204	class TISRW
daryl2110	0:879af6e11219	205	{
daryl2110	0:879af6e11219	206	public:
daryl2110	0:879af6e11219	207	INLINE TISRW() { ISR_Enter(); }
daryl2110	0:879af6e11219	208	INLINE ~TISRW() { ISR_Exit(); }
daryl2110	0:879af6e11219	209
daryl2110	0:879af6e11219	210	private:
daryl2110	0:879af6e11219	211	//-----------------------------------------------------
daryl2110	0:879af6e11219	212	INLINE void ISR_Enter()
daryl2110	0:879af6e11219	213	{
daryl2110	0:879af6e11219	214	TCritSect cs;
daryl2110	0:879af6e11219	215	Kernel.ISR_NestCount++;
daryl2110	0:879af6e11219	216	}
daryl2110	0:879af6e11219	217	//-----------------------------------------------------
daryl2110	0:879af6e11219	218	INLINE void ISR_Exit()
daryl2110	0:879af6e11219	219	{
daryl2110	0:879af6e11219	220	TCritSect cs;
daryl2110	0:879af6e11219	221	if(--Kernel.ISR_NestCount) return;
daryl2110	0:879af6e11219	222	Kernel.SchedISR();
daryl2110	0:879af6e11219	223	}
daryl2110	0:879af6e11219	224	//-----------------------------------------------------
daryl2110	0:879af6e11219	225	};
daryl2110	0:879af6e11219	226
daryl2110	0:879af6e11219	227	// No software interrupt stack switching provided,
daryl2110	0:879af6e11219	228	// TISRW_SS declared to be the same as TISRW for porting compability
daryl2110	0:879af6e11219	229	#define TISRW_SS TISRW
daryl2110	0:879af6e11219	230
daryl2110	0:879af6e11219	231	} // ns OS
daryl2110	0:879af6e11219	232	//-----------------------------------------------------------------------------
daryl2110	0:879af6e11219	233
daryl2110	0:879af6e11219	234	#endif // scmRTOS_CORTEXM3_H
daryl2110	0:879af6e11219	235	//-----------------------------------------------------------------------------
daryl2110	0:879af6e11219	236

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	20 Feb 2012
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	5
Followers:	1

scmRTOS/CortexM3/OS_Target.h@0:879af6e11219, 2012-02-20 (annotated)

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