Darien Figueroa / Mbed 2 deprecated repo3

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Dependencies:   mbed MAX14720 MAX30205 USBDevice

e4a10ed6eb92/HSP/Interfaces/QuadSpiInterface.cpp@20:6d2af70c92ab, 2021-04-06 (annotated)

Committer:
darienf
Date:
Tue Apr 06 06:41:40 2021 +0000
Revision:
20:6d2af70c92ab
another repo

Who changed what in which revision?

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darienf 20:6d2af70c92ab 1 /*******************************************************************************
darienf 20:6d2af70c92ab 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
darienf 20:6d2af70c92ab 3 *
darienf 20:6d2af70c92ab 4 * Permission is hereby granted, free of charge, to any person obtaining a
darienf 20:6d2af70c92ab 5 * copy of this software and associated documentation files (the "Software"),
darienf 20:6d2af70c92ab 6 * to deal in the Software without restriction, including without limitation
darienf 20:6d2af70c92ab 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
darienf 20:6d2af70c92ab 8 * and/or sell copies of the Software, and to permit persons to whom the
darienf 20:6d2af70c92ab 9 * Software is furnished to do so, subject to the following conditions:
darienf 20:6d2af70c92ab 10 *
darienf 20:6d2af70c92ab 11 * The above copyright notice and this permission notice shall be included
darienf 20:6d2af70c92ab 12 * in all copies or substantial portions of the Software.
darienf 20:6d2af70c92ab 13 *
darienf 20:6d2af70c92ab 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
darienf 20:6d2af70c92ab 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
darienf 20:6d2af70c92ab 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
darienf 20:6d2af70c92ab 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
darienf 20:6d2af70c92ab 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
darienf 20:6d2af70c92ab 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
darienf 20:6d2af70c92ab 20 * OTHER DEALINGS IN THE SOFTWARE.
darienf 20:6d2af70c92ab 21 *
darienf 20:6d2af70c92ab 22 * Except as contained in this notice, the name of Maxim Integrated
darienf 20:6d2af70c92ab 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
darienf 20:6d2af70c92ab 24 * Products, Inc. Branding Policy.
darienf 20:6d2af70c92ab 25 *
darienf 20:6d2af70c92ab 26 * The mere transfer of this software does not imply any licenses
darienf 20:6d2af70c92ab 27 * of trade secrets, proprietary technology, copyrights, patents,
darienf 20:6d2af70c92ab 28 * trademarks, maskwork rights, or any other form of intellectual
darienf 20:6d2af70c92ab 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
darienf 20:6d2af70c92ab 30 * ownership rights.
darienf 20:6d2af70c92ab 31 *******************************************************************************
darienf 20:6d2af70c92ab 32 */
darienf 20:6d2af70c92ab 33 #include "QuadSpiInterface.h"
darienf 20:6d2af70c92ab 34
darienf 20:6d2af70c92ab 35 /**
darienf 20:6d2af70c92ab 36 * @brief Constructor that accepts pin names for the QUAD SPI interface
darienf 20:6d2af70c92ab 37 * @param mosi master out slave in pin name
darienf 20:6d2af70c92ab 38 * @param miso master in slave out pin name
darienf 20:6d2af70c92ab 39 * @param sclk serial clock pin name
darienf 20:6d2af70c92ab 40 * @param cs chip select pin name
darienf 20:6d2af70c92ab 41 */
darienf 20:6d2af70c92ab 42 QuadSpiInterface::QuadSpiInterface(PinName mosi, PinName miso, PinName sclk,
darienf 20:6d2af70c92ab 43 PinName cs)
darienf 20:6d2af70c92ab 44 : spi(mosi, miso, sclk), csPin(cs) {
darienf 20:6d2af70c92ab 45
darienf 20:6d2af70c92ab 46 }
darienf 20:6d2af70c92ab 47
darienf 20:6d2af70c92ab 48 /**
darienf 20:6d2af70c92ab 49 * @brief Transmit and recieve QUAD SPI data
darienf 20:6d2af70c92ab 50 * @param tx_buf pointer to transmit byte buffer
darienf 20:6d2af70c92ab 51 * @param tx_size number of bytes to transmit
darienf 20:6d2af70c92ab 52 * @param rx_buf pointer to the recieve buffer
darienf 20:6d2af70c92ab 53 * @param rx_size number of bytes to recieve
darienf 20:6d2af70c92ab 54 * @param last flag to indicate if this is the last QUAD SPI transaction for the
darienf 20:6d2af70c92ab 55 * current chip select cycle
darienf 20:6d2af70c92ab 56 */
darienf 20:6d2af70c92ab 57 int QuadSpiInterface::SPI_Transmit(const uint8_t *tx_buf, uint32_t tx_size,
darienf 20:6d2af70c92ab 58 uint8_t *rx_buf, uint32_t rx_size,
darienf 20:6d2af70c92ab 59 int last) {
darienf 20:6d2af70c92ab 60 uint32_t i;
darienf 20:6d2af70c92ab 61 int result = 0;
darienf 20:6d2af70c92ab 62 int index = 0;
darienf 20:6d2af70c92ab 63 // lower chip select
darienf 20:6d2af70c92ab 64 csPin = 0;
darienf 20:6d2af70c92ab 65 // write bytes out QUAD SPI
darienf 20:6d2af70c92ab 66 spi.setQuadMode();
darienf 20:6d2af70c92ab 67 for (i = 0; i < tx_size; i++) {
darienf 20:6d2af70c92ab 68 rx_buf[index] = spi.write((int)tx_buf[i]);
darienf 20:6d2af70c92ab 69 index++;
darienf 20:6d2af70c92ab 70 }
darienf 20:6d2af70c92ab 71 // read in bytes from QUAD SPI
darienf 20:6d2af70c92ab 72 for (i = 0; i < rx_size; i++) {
darienf 20:6d2af70c92ab 73 rx_buf[index] = (uint8_t)spi.read();
darienf 20:6d2af70c92ab 74 index++;
darienf 20:6d2af70c92ab 75 }
darienf 20:6d2af70c92ab 76 // raise chip select if this is the last transaction
darienf 20:6d2af70c92ab 77 if (last) csPin = 1;
darienf 20:6d2af70c92ab 78 return result;
darienf 20:6d2af70c92ab 79 }
darienf 20:6d2af70c92ab 80
darienf 20:6d2af70c92ab 81 /**
darienf 20:6d2af70c92ab 82 * @brief Transmit and recieve QUAD SPI data
darienf 20:6d2af70c92ab 83 * @param tx_buf pointer to transmit byte buffer
darienf 20:6d2af70c92ab 84 * @param tx_size number of bytes to transmit
darienf 20:6d2af70c92ab 85 * @param rx_buf pointer to the recieve buffer
darienf 20:6d2af70c92ab 86 * @param rx_size number of bytes to recieve
darienf 20:6d2af70c92ab 87 * @param last flag to indicate if this is the last QUAD SPI transaction for the
darienf 20:6d2af70c92ab 88 * current chip select cycle
darienf 20:6d2af70c92ab 89 */
darienf 20:6d2af70c92ab 90 int QuadSpiInterface::SPI_Transmit4Wire(const uint8_t *tx_buf, uint32_t tx_size,
darienf 20:6d2af70c92ab 91 uint8_t *rx_buf, uint32_t rx_size,
darienf 20:6d2af70c92ab 92 int last) {
darienf 20:6d2af70c92ab 93 uint32_t i;
darienf 20:6d2af70c92ab 94 int result = 0;
darienf 20:6d2af70c92ab 95 int index = 0;
darienf 20:6d2af70c92ab 96 // lower chip select
darienf 20:6d2af70c92ab 97 csPin = 0;
darienf 20:6d2af70c92ab 98 // write bytes out Single SPI
darienf 20:6d2af70c92ab 99 spi.setSingleMode();
darienf 20:6d2af70c92ab 100 for (i = 0; i < tx_size; i++) {
darienf 20:6d2af70c92ab 101 rx_buf[index] = spi.write((int)tx_buf[i]);
darienf 20:6d2af70c92ab 102 index++;
darienf 20:6d2af70c92ab 103 }
darienf 20:6d2af70c92ab 104 // raise chip select if this is the last transaction
darienf 20:6d2af70c92ab 105 if (last) csPin = 1;
darienf 20:6d2af70c92ab 106 return result;
darienf 20:6d2af70c92ab 107 }