Daniel Sygut / Application

lol

Dependencies:   MMA8451Q

Fork of Application by Mateusz Kowalik

mbed-dev/targets/TARGET_STM/stm_spi_api.c@10:41552d038a69, 2017-01-10 (annotated)

Committer:
Zaitsev
Date:
Tue Jan 10 20:42:26 2017 +0000
Revision:
10:41552d038a69
USB Serial bi-directional bridge

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Zaitsev 10:41552d038a69 1 /* mbed Microcontroller Library
Zaitsev 10:41552d038a69 2 *******************************************************************************
Zaitsev 10:41552d038a69 3 * Copyright (c) 2015, STMicroelectronics
Zaitsev 10:41552d038a69 4 * All rights reserved.
Zaitsev 10:41552d038a69 5 *
Zaitsev 10:41552d038a69 6 * Redistribution and use in source and binary forms, with or without
Zaitsev 10:41552d038a69 7 * modification, are permitted provided that the following conditions are met:
Zaitsev 10:41552d038a69 8 *
Zaitsev 10:41552d038a69 9 * 1. Redistributions of source code must retain the above copyright notice,
Zaitsev 10:41552d038a69 10 * this list of conditions and the following disclaimer.
Zaitsev 10:41552d038a69 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
Zaitsev 10:41552d038a69 12 * this list of conditions and the following disclaimer in the documentation
Zaitsev 10:41552d038a69 13 * and/or other materials provided with the distribution.
Zaitsev 10:41552d038a69 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Zaitsev 10:41552d038a69 15 * may be used to endorse or promote products derived from this software
Zaitsev 10:41552d038a69 16 * without specific prior written permission.
Zaitsev 10:41552d038a69 17 *
Zaitsev 10:41552d038a69 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Zaitsev 10:41552d038a69 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Zaitsev 10:41552d038a69 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Zaitsev 10:41552d038a69 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Zaitsev 10:41552d038a69 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Zaitsev 10:41552d038a69 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Zaitsev 10:41552d038a69 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Zaitsev 10:41552d038a69 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Zaitsev 10:41552d038a69 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Zaitsev 10:41552d038a69 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Zaitsev 10:41552d038a69 28 *******************************************************************************
Zaitsev 10:41552d038a69 29 */
Zaitsev 10:41552d038a69 30 #include "mbed_assert.h"
Zaitsev 10:41552d038a69 31 #include "mbed_error.h"
Zaitsev 10:41552d038a69 32 #include "spi_api.h"
Zaitsev 10:41552d038a69 33
Zaitsev 10:41552d038a69 34 #if DEVICE_SPI
Zaitsev 10:41552d038a69 35 #include <stdbool.h>
Zaitsev 10:41552d038a69 36 #include <math.h>
Zaitsev 10:41552d038a69 37 #include <string.h>
Zaitsev 10:41552d038a69 38 #include "cmsis.h"
Zaitsev 10:41552d038a69 39 #include "pinmap.h"
Zaitsev 10:41552d038a69 40 #include "PeripheralPins.h"
Zaitsev 10:41552d038a69 41
Zaitsev 10:41552d038a69 42 #if DEVICE_SPI_ASYNCH
Zaitsev 10:41552d038a69 43 #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi.spi))
Zaitsev 10:41552d038a69 44 #else
Zaitsev 10:41552d038a69 45 #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi))
Zaitsev 10:41552d038a69 46 #endif
Zaitsev 10:41552d038a69 47
Zaitsev 10:41552d038a69 48 #if DEVICE_SPI_ASYNCH
Zaitsev 10:41552d038a69 49 #define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
Zaitsev 10:41552d038a69 50 #else
Zaitsev 10:41552d038a69 51 #define SPI_S(obj) (( struct spi_s *)(obj))
Zaitsev 10:41552d038a69 52 #endif
Zaitsev 10:41552d038a69 53
Zaitsev 10:41552d038a69 54 #ifndef DEBUG_STDIO
Zaitsev 10:41552d038a69 55 # define DEBUG_STDIO 0
Zaitsev 10:41552d038a69 56 #endif
Zaitsev 10:41552d038a69 57
Zaitsev 10:41552d038a69 58 #if DEBUG_STDIO
Zaitsev 10:41552d038a69 59 # include <stdio.h>
Zaitsev 10:41552d038a69 60 # define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
Zaitsev 10:41552d038a69 61 #else
Zaitsev 10:41552d038a69 62 # define DEBUG_PRINTF(...) {}
Zaitsev 10:41552d038a69 63 #endif
Zaitsev 10:41552d038a69 64
Zaitsev 10:41552d038a69 65 void init_spi(spi_t *obj)
Zaitsev 10:41552d038a69 66 {
Zaitsev 10:41552d038a69 67 struct spi_s *spiobj = SPI_S(obj);
Zaitsev 10:41552d038a69 68 SPI_HandleTypeDef *handle = &(spiobj->handle);
Zaitsev 10:41552d038a69 69
Zaitsev 10:41552d038a69 70 __HAL_SPI_DISABLE(handle);
Zaitsev 10:41552d038a69 71
Zaitsev 10:41552d038a69 72 DEBUG_PRINTF("init_spi: instance=0x%8X\r\n", (int)handle->Instance);
Zaitsev 10:41552d038a69 73 if (HAL_SPI_Init(handle) != HAL_OK) {
Zaitsev 10:41552d038a69 74 error("Cannot initialize SPI");
Zaitsev 10:41552d038a69 75 }
Zaitsev 10:41552d038a69 76
Zaitsev 10:41552d038a69 77 __HAL_SPI_ENABLE(handle);
Zaitsev 10:41552d038a69 78 }
Zaitsev 10:41552d038a69 79
Zaitsev 10:41552d038a69 80 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
Zaitsev 10:41552d038a69 81 {
Zaitsev 10:41552d038a69 82 struct spi_s *spiobj = SPI_S(obj);
Zaitsev 10:41552d038a69 83 SPI_HandleTypeDef *handle = &(spiobj->handle);
Zaitsev 10:41552d038a69 84
Zaitsev 10:41552d038a69 85 // Determine the SPI to use
Zaitsev 10:41552d038a69 86 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
Zaitsev 10:41552d038a69 87 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
Zaitsev 10:41552d038a69 88 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
Zaitsev 10:41552d038a69 89 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
Zaitsev 10:41552d038a69 90
Zaitsev 10:41552d038a69 91 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
Zaitsev 10:41552d038a69 92 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
Zaitsev 10:41552d038a69 93
Zaitsev 10:41552d038a69 94 spiobj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
Zaitsev 10:41552d038a69 95 MBED_ASSERT(spiobj->spi != (SPIName)NC);
Zaitsev 10:41552d038a69 96
Zaitsev 10:41552d038a69 97 #if defined SPI1_BASE
Zaitsev 10:41552d038a69 98 // Enable SPI clock
Zaitsev 10:41552d038a69 99 if (spiobj->spi == SPI_1) {
Zaitsev 10:41552d038a69 100 __HAL_RCC_SPI1_CLK_ENABLE();
Zaitsev 10:41552d038a69 101 spiobj->spiIRQ = SPI1_IRQn;
Zaitsev 10:41552d038a69 102 }
Zaitsev 10:41552d038a69 103 #endif
Zaitsev 10:41552d038a69 104
Zaitsev 10:41552d038a69 105 #if defined SPI2_BASE
Zaitsev 10:41552d038a69 106 if (spiobj->spi == SPI_2) {
Zaitsev 10:41552d038a69 107 __HAL_RCC_SPI2_CLK_ENABLE();
Zaitsev 10:41552d038a69 108 spiobj->spiIRQ = SPI2_IRQn;
Zaitsev 10:41552d038a69 109 }
Zaitsev 10:41552d038a69 110 #endif
Zaitsev 10:41552d038a69 111
Zaitsev 10:41552d038a69 112 #if defined SPI3_BASE
Zaitsev 10:41552d038a69 113 if (spiobj->spi == SPI_3) {
Zaitsev 10:41552d038a69 114 __HAL_RCC_SPI3_CLK_ENABLE();
Zaitsev 10:41552d038a69 115 spiobj->spiIRQ = SPI3_IRQn;
Zaitsev 10:41552d038a69 116 }
Zaitsev 10:41552d038a69 117 #endif
Zaitsev 10:41552d038a69 118
Zaitsev 10:41552d038a69 119 #if defined SPI4_BASE
Zaitsev 10:41552d038a69 120 if (spiobj->spi == SPI_4) {
Zaitsev 10:41552d038a69 121 __HAL_RCC_SPI4_CLK_ENABLE();
Zaitsev 10:41552d038a69 122 spiobj->spiIRQ = SPI4_IRQn;
Zaitsev 10:41552d038a69 123 }
Zaitsev 10:41552d038a69 124 #endif
Zaitsev 10:41552d038a69 125
Zaitsev 10:41552d038a69 126 #if defined SPI5_BASE
Zaitsev 10:41552d038a69 127 if (spiobj->spi == SPI_5) {
Zaitsev 10:41552d038a69 128 __HAL_RCC_SPI5_CLK_ENABLE();
Zaitsev 10:41552d038a69 129 spiobj->spiIRQ = SPI5_IRQn;
Zaitsev 10:41552d038a69 130 }
Zaitsev 10:41552d038a69 131 #endif
Zaitsev 10:41552d038a69 132
Zaitsev 10:41552d038a69 133 #if defined SPI6_BASE
Zaitsev 10:41552d038a69 134 if (spiobj->spi == SPI_6) {
Zaitsev 10:41552d038a69 135 __HAL_RCC_SPI6_CLK_ENABLE();
Zaitsev 10:41552d038a69 136 spiobj->spiIRQ = SPI6_IRQn;
Zaitsev 10:41552d038a69 137 }
Zaitsev 10:41552d038a69 138 #endif
Zaitsev 10:41552d038a69 139
Zaitsev 10:41552d038a69 140 // Configure the SPI pins
Zaitsev 10:41552d038a69 141 pinmap_pinout(mosi, PinMap_SPI_MOSI);
Zaitsev 10:41552d038a69 142 pinmap_pinout(miso, PinMap_SPI_MISO);
Zaitsev 10:41552d038a69 143 pinmap_pinout(sclk, PinMap_SPI_SCLK);
Zaitsev 10:41552d038a69 144 spiobj->pin_miso = miso;
Zaitsev 10:41552d038a69 145 spiobj->pin_mosi = mosi;
Zaitsev 10:41552d038a69 146 spiobj->pin_sclk = sclk;
Zaitsev 10:41552d038a69 147 spiobj->pin_ssel = ssel;
Zaitsev 10:41552d038a69 148 if (ssel != NC) {
Zaitsev 10:41552d038a69 149 pinmap_pinout(ssel, PinMap_SPI_SSEL);
Zaitsev 10:41552d038a69 150 } else {
Zaitsev 10:41552d038a69 151 handle->Init.NSS = SPI_NSS_SOFT;
Zaitsev 10:41552d038a69 152 }
Zaitsev 10:41552d038a69 153
Zaitsev 10:41552d038a69 154 /* Fill default value */
Zaitsev 10:41552d038a69 155 handle->Instance = SPI_INST(obj);
Zaitsev 10:41552d038a69 156 handle->Init.Mode = SPI_MODE_MASTER;
Zaitsev 10:41552d038a69 157 handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
Zaitsev 10:41552d038a69 158 handle->Init.Direction = SPI_DIRECTION_2LINES;
Zaitsev 10:41552d038a69 159 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
Zaitsev 10:41552d038a69 160 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
Zaitsev 10:41552d038a69 161 handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
Zaitsev 10:41552d038a69 162 handle->Init.CRCPolynomial = 7;
Zaitsev 10:41552d038a69 163 handle->Init.DataSize = SPI_DATASIZE_8BIT;
Zaitsev 10:41552d038a69 164 handle->Init.FirstBit = SPI_FIRSTBIT_MSB;
Zaitsev 10:41552d038a69 165 handle->Init.TIMode = SPI_TIMODE_DISABLED;
Zaitsev 10:41552d038a69 166
Zaitsev 10:41552d038a69 167 init_spi(obj);
Zaitsev 10:41552d038a69 168 }
Zaitsev 10:41552d038a69 169
Zaitsev 10:41552d038a69 170 void spi_free(spi_t *obj)
Zaitsev 10:41552d038a69 171 {
Zaitsev 10:41552d038a69 172 struct spi_s *spiobj = SPI_S(obj);
Zaitsev 10:41552d038a69 173 SPI_HandleTypeDef *handle = &(spiobj->handle);
Zaitsev 10:41552d038a69 174
Zaitsev 10:41552d038a69 175 DEBUG_PRINTF("spi_free\r\n");
Zaitsev 10:41552d038a69 176
Zaitsev 10:41552d038a69 177 __HAL_SPI_DISABLE(handle);
Zaitsev 10:41552d038a69 178 HAL_SPI_DeInit(handle);
Zaitsev 10:41552d038a69 179
Zaitsev 10:41552d038a69 180 #if defined SPI1_BASE
Zaitsev 10:41552d038a69 181 // Reset SPI and disable clock
Zaitsev 10:41552d038a69 182 if (spiobj->spi == SPI_1) {
Zaitsev 10:41552d038a69 183 __HAL_RCC_SPI1_FORCE_RESET();
Zaitsev 10:41552d038a69 184 __HAL_RCC_SPI1_RELEASE_RESET();
Zaitsev 10:41552d038a69 185 __HAL_RCC_SPI1_CLK_DISABLE();
Zaitsev 10:41552d038a69 186 }
Zaitsev 10:41552d038a69 187 #endif
Zaitsev 10:41552d038a69 188 #if defined SPI2_BASE
Zaitsev 10:41552d038a69 189 if (spiobj->spi == SPI_2) {
Zaitsev 10:41552d038a69 190 __HAL_RCC_SPI2_FORCE_RESET();
Zaitsev 10:41552d038a69 191 __HAL_RCC_SPI2_RELEASE_RESET();
Zaitsev 10:41552d038a69 192 __HAL_RCC_SPI2_CLK_DISABLE();
Zaitsev 10:41552d038a69 193 }
Zaitsev 10:41552d038a69 194 #endif
Zaitsev 10:41552d038a69 195
Zaitsev 10:41552d038a69 196 #if defined SPI3_BASE
Zaitsev 10:41552d038a69 197 if (spiobj->spi == SPI_3) {
Zaitsev 10:41552d038a69 198 __HAL_RCC_SPI3_FORCE_RESET();
Zaitsev 10:41552d038a69 199 __HAL_RCC_SPI3_RELEASE_RESET();
Zaitsev 10:41552d038a69 200 __HAL_RCC_SPI3_CLK_DISABLE();
Zaitsev 10:41552d038a69 201 }
Zaitsev 10:41552d038a69 202 #endif
Zaitsev 10:41552d038a69 203
Zaitsev 10:41552d038a69 204 #if defined SPI4_BASE
Zaitsev 10:41552d038a69 205 if (spiobj->spi == SPI_4) {
Zaitsev 10:41552d038a69 206 __HAL_RCC_SPI4_FORCE_RESET();
Zaitsev 10:41552d038a69 207 __HAL_RCC_SPI4_RELEASE_RESET();
Zaitsev 10:41552d038a69 208 __HAL_RCC_SPI4_CLK_DISABLE();
Zaitsev 10:41552d038a69 209 }
Zaitsev 10:41552d038a69 210 #endif
Zaitsev 10:41552d038a69 211
Zaitsev 10:41552d038a69 212 #if defined SPI5_BASE
Zaitsev 10:41552d038a69 213 if (spiobj->spi == SPI_5) {
Zaitsev 10:41552d038a69 214 __HAL_RCC_SPI5_FORCE_RESET();
Zaitsev 10:41552d038a69 215 __HAL_RCC_SPI5_RELEASE_RESET();
Zaitsev 10:41552d038a69 216 __HAL_RCC_SPI5_CLK_DISABLE();
Zaitsev 10:41552d038a69 217 }
Zaitsev 10:41552d038a69 218 #endif
Zaitsev 10:41552d038a69 219
Zaitsev 10:41552d038a69 220 #if defined SPI6_BASE
Zaitsev 10:41552d038a69 221 if (spiobj->spi == SPI_6) {
Zaitsev 10:41552d038a69 222 __HAL_RCC_SPI6_FORCE_RESET();
Zaitsev 10:41552d038a69 223 __HAL_RCC_SPI6_RELEASE_RESET();
Zaitsev 10:41552d038a69 224 __HAL_RCC_SPI6_CLK_DISABLE();
Zaitsev 10:41552d038a69 225 }
Zaitsev 10:41552d038a69 226 #endif
Zaitsev 10:41552d038a69 227
Zaitsev 10:41552d038a69 228 // Configure GPIOs
Zaitsev 10:41552d038a69 229 pin_function(spiobj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
Zaitsev 10:41552d038a69 230 pin_function(spiobj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
Zaitsev 10:41552d038a69 231 pin_function(spiobj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
Zaitsev 10:41552d038a69 232 if (handle->Init.NSS != SPI_NSS_SOFT) {
Zaitsev 10:41552d038a69 233 pin_function(spiobj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
Zaitsev 10:41552d038a69 234 }
Zaitsev 10:41552d038a69 235 }
Zaitsev 10:41552d038a69 236
Zaitsev 10:41552d038a69 237 void spi_format(spi_t *obj, int bits, int mode, int slave)
Zaitsev 10:41552d038a69 238 {
Zaitsev 10:41552d038a69 239 struct spi_s *spiobj = SPI_S(obj);
Zaitsev 10:41552d038a69 240 SPI_HandleTypeDef *handle = &(spiobj->handle);
Zaitsev 10:41552d038a69 241
Zaitsev 10:41552d038a69 242 DEBUG_PRINTF("spi_format, bits:%d, mode:%d, slave?:%d\r\n", bits, mode, slave);
Zaitsev 10:41552d038a69 243
Zaitsev 10:41552d038a69 244 // Save new values
Zaitsev 10:41552d038a69 245 handle->Init.DataSize = (bits == 16) ? SPI_DATASIZE_16BIT : SPI_DATASIZE_8BIT;
Zaitsev 10:41552d038a69 246
Zaitsev 10:41552d038a69 247 switch (mode) {
Zaitsev 10:41552d038a69 248 case 0:
Zaitsev 10:41552d038a69 249 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
Zaitsev 10:41552d038a69 250 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
Zaitsev 10:41552d038a69 251 break;
Zaitsev 10:41552d038a69 252 case 1:
Zaitsev 10:41552d038a69 253 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
Zaitsev 10:41552d038a69 254 handle->Init.CLKPhase = SPI_PHASE_2EDGE;
Zaitsev 10:41552d038a69 255 break;
Zaitsev 10:41552d038a69 256 case 2:
Zaitsev 10:41552d038a69 257 handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
Zaitsev 10:41552d038a69 258 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
Zaitsev 10:41552d038a69 259 break;
Zaitsev 10:41552d038a69 260 default:
Zaitsev 10:41552d038a69 261 handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
Zaitsev 10:41552d038a69 262 handle->Init.CLKPhase = SPI_PHASE_2EDGE;
Zaitsev 10:41552d038a69 263 break;
Zaitsev 10:41552d038a69 264 }
Zaitsev 10:41552d038a69 265
Zaitsev 10:41552d038a69 266 if (handle->Init.NSS != SPI_NSS_SOFT) {
Zaitsev 10:41552d038a69 267 handle->Init.NSS = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
Zaitsev 10:41552d038a69 268 }
Zaitsev 10:41552d038a69 269
Zaitsev 10:41552d038a69 270 handle->Init.Mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
Zaitsev 10:41552d038a69 271
Zaitsev 10:41552d038a69 272 init_spi(obj);
Zaitsev 10:41552d038a69 273 }
Zaitsev 10:41552d038a69 274
Zaitsev 10:41552d038a69 275 /*
Zaitsev 10:41552d038a69 276 * Only the IP clock input is family dependant so it computed
Zaitsev 10:41552d038a69 277 * separately in spi_get_clock_freq
Zaitsev 10:41552d038a69 278 */
Zaitsev 10:41552d038a69 279 extern int spi_get_clock_freq(spi_t *obj);
Zaitsev 10:41552d038a69 280
Zaitsev 10:41552d038a69 281 static const uint16_t baudrate_prescaler_table[] = {SPI_BAUDRATEPRESCALER_2,
Zaitsev 10:41552d038a69 282 SPI_BAUDRATEPRESCALER_4,
Zaitsev 10:41552d038a69 283 SPI_BAUDRATEPRESCALER_8,
Zaitsev 10:41552d038a69 284 SPI_BAUDRATEPRESCALER_16,
Zaitsev 10:41552d038a69 285 SPI_BAUDRATEPRESCALER_32,
Zaitsev 10:41552d038a69 286 SPI_BAUDRATEPRESCALER_64,
Zaitsev 10:41552d038a69 287 SPI_BAUDRATEPRESCALER_128,
Zaitsev 10:41552d038a69 288 SPI_BAUDRATEPRESCALER_256};
Zaitsev 10:41552d038a69 289
Zaitsev 10:41552d038a69 290 void spi_frequency(spi_t *obj, int hz) {
Zaitsev 10:41552d038a69 291 struct spi_s *spiobj = SPI_S(obj);
Zaitsev 10:41552d038a69 292 int spi_hz = 0;
Zaitsev 10:41552d038a69 293 uint8_t prescaler_rank = 0;
Zaitsev 10:41552d038a69 294 SPI_HandleTypeDef *handle = &(spiobj->handle);
Zaitsev 10:41552d038a69 295
Zaitsev 10:41552d038a69 296 /* Get the clock of the peripheral */
Zaitsev 10:41552d038a69 297 spi_hz = spi_get_clock_freq(obj);
Zaitsev 10:41552d038a69 298
Zaitsev 10:41552d038a69 299 /* Define pre-scaler in order to get highest available frequency below requested frequency */
Zaitsev 10:41552d038a69 300 while ((spi_hz > hz) && (prescaler_rank < sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0]))){
Zaitsev 10:41552d038a69 301 spi_hz = spi_hz / 2;
Zaitsev 10:41552d038a69 302 prescaler_rank++;
Zaitsev 10:41552d038a69 303 }
Zaitsev 10:41552d038a69 304
Zaitsev 10:41552d038a69 305 if (prescaler_rank <= sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) {
Zaitsev 10:41552d038a69 306 handle->Init.BaudRatePrescaler = baudrate_prescaler_table[prescaler_rank-1];
Zaitsev 10:41552d038a69 307 } else {
Zaitsev 10:41552d038a69 308 error("Couldn't setup requested SPI frequency");
Zaitsev 10:41552d038a69 309 }
Zaitsev 10:41552d038a69 310
Zaitsev 10:41552d038a69 311 init_spi(obj);
Zaitsev 10:41552d038a69 312 }
Zaitsev 10:41552d038a69 313
Zaitsev 10:41552d038a69 314 static inline int ssp_readable(spi_t *obj)
Zaitsev 10:41552d038a69 315 {
Zaitsev 10:41552d038a69 316 int status;
Zaitsev 10:41552d038a69 317 struct spi_s *spiobj = SPI_S(obj);
Zaitsev 10:41552d038a69 318 SPI_HandleTypeDef *handle = &(spiobj->handle);
Zaitsev 10:41552d038a69 319
Zaitsev 10:41552d038a69 320 // Check if data is received
Zaitsev 10:41552d038a69 321 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
Zaitsev 10:41552d038a69 322 return status;
Zaitsev 10:41552d038a69 323 }
Zaitsev 10:41552d038a69 324
Zaitsev 10:41552d038a69 325 static inline int ssp_writeable(spi_t *obj)
Zaitsev 10:41552d038a69 326 {
Zaitsev 10:41552d038a69 327 int status;
Zaitsev 10:41552d038a69 328 struct spi_s *spiobj = SPI_S(obj);
Zaitsev 10:41552d038a69 329 SPI_HandleTypeDef *handle = &(spiobj->handle);
Zaitsev 10:41552d038a69 330
Zaitsev 10:41552d038a69 331 // Check if data is transmitted
Zaitsev 10:41552d038a69 332 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
Zaitsev 10:41552d038a69 333 return status;
Zaitsev 10:41552d038a69 334 }
Zaitsev 10:41552d038a69 335
Zaitsev 10:41552d038a69 336 static inline int ssp_busy(spi_t *obj)
Zaitsev 10:41552d038a69 337 {
Zaitsev 10:41552d038a69 338 int status;
Zaitsev 10:41552d038a69 339 struct spi_s *spiobj = SPI_S(obj);
Zaitsev 10:41552d038a69 340 SPI_HandleTypeDef *handle = &(spiobj->handle);
Zaitsev 10:41552d038a69 341 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
Zaitsev 10:41552d038a69 342 return status;
Zaitsev 10:41552d038a69 343 }
Zaitsev 10:41552d038a69 344
Zaitsev 10:41552d038a69 345 int spi_master_write(spi_t *obj, int value)
Zaitsev 10:41552d038a69 346 {
Zaitsev 10:41552d038a69 347 uint16_t size, Rx, ret;
Zaitsev 10:41552d038a69 348 struct spi_s *spiobj = SPI_S(obj);
Zaitsev 10:41552d038a69 349 SPI_HandleTypeDef *handle = &(spiobj->handle);
Zaitsev 10:41552d038a69 350
Zaitsev 10:41552d038a69 351 size = (handle->Init.DataSize == SPI_DATASIZE_16BIT) ? 2 : 1;
Zaitsev 10:41552d038a69 352
Zaitsev 10:41552d038a69 353 /* Use 10ms timeout */
Zaitsev 10:41552d038a69 354 ret = HAL_SPI_TransmitReceive(handle,(uint8_t*)&value,(uint8_t*)&Rx,size,10);
Zaitsev 10:41552d038a69 355
Zaitsev 10:41552d038a69 356 if(ret == HAL_OK) {
Zaitsev 10:41552d038a69 357 return Rx;
Zaitsev 10:41552d038a69 358 } else {
Zaitsev 10:41552d038a69 359 DEBUG_PRINTF("SPI inst=0x%8X ERROR in write\r\n", (int)handle->Instance);
Zaitsev 10:41552d038a69 360 return -1;
Zaitsev 10:41552d038a69 361 }
Zaitsev 10:41552d038a69 362 }
Zaitsev 10:41552d038a69 363
Zaitsev 10:41552d038a69 364 int spi_slave_receive(spi_t *obj)
Zaitsev 10:41552d038a69 365 {
Zaitsev 10:41552d038a69 366 return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
Zaitsev 10:41552d038a69 367 };
Zaitsev 10:41552d038a69 368
Zaitsev 10:41552d038a69 369 int spi_slave_read(spi_t *obj)
Zaitsev 10:41552d038a69 370 {
Zaitsev 10:41552d038a69 371 SPI_TypeDef *spi = SPI_INST(obj);
Zaitsev 10:41552d038a69 372 struct spi_s *spiobj = SPI_S(obj);
Zaitsev 10:41552d038a69 373 SPI_HandleTypeDef *handle = &(spiobj->handle);
Zaitsev 10:41552d038a69 374 while (!ssp_readable(obj));
Zaitsev 10:41552d038a69 375 if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
Zaitsev 10:41552d038a69 376 // Force 8-bit access to the data register
Zaitsev 10:41552d038a69 377 uint8_t *p_spi_dr = 0;
Zaitsev 10:41552d038a69 378 p_spi_dr = (uint8_t *) & (spi->DR);
Zaitsev 10:41552d038a69 379 return (int)(*p_spi_dr);
Zaitsev 10:41552d038a69 380 } else {
Zaitsev 10:41552d038a69 381 return (int)spi->DR;
Zaitsev 10:41552d038a69 382 }
Zaitsev 10:41552d038a69 383 }
Zaitsev 10:41552d038a69 384
Zaitsev 10:41552d038a69 385 void spi_slave_write(spi_t *obj, int value)
Zaitsev 10:41552d038a69 386 {
Zaitsev 10:41552d038a69 387 SPI_TypeDef *spi = SPI_INST(obj);
Zaitsev 10:41552d038a69 388 struct spi_s *spiobj = SPI_S(obj);
Zaitsev 10:41552d038a69 389 SPI_HandleTypeDef *handle = &(spiobj->handle);
Zaitsev 10:41552d038a69 390 while (!ssp_writeable(obj));
Zaitsev 10:41552d038a69 391 if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
Zaitsev 10:41552d038a69 392 // Force 8-bit access to the data register
Zaitsev 10:41552d038a69 393 uint8_t *p_spi_dr = 0;
Zaitsev 10:41552d038a69 394 p_spi_dr = (uint8_t *) & (spi->DR);
Zaitsev 10:41552d038a69 395 *p_spi_dr = (uint8_t)value;
Zaitsev 10:41552d038a69 396 } else { // SPI_DATASIZE_16BIT
Zaitsev 10:41552d038a69 397 spi->DR = (uint16_t)value;
Zaitsev 10:41552d038a69 398 }
Zaitsev 10:41552d038a69 399 }
Zaitsev 10:41552d038a69 400
Zaitsev 10:41552d038a69 401 int spi_busy(spi_t *obj)
Zaitsev 10:41552d038a69 402 {
Zaitsev 10:41552d038a69 403 return ssp_busy(obj);
Zaitsev 10:41552d038a69 404 }
Zaitsev 10:41552d038a69 405
Zaitsev 10:41552d038a69 406 #ifdef DEVICE_SPI_ASYNCH
Zaitsev 10:41552d038a69 407 typedef enum {
Zaitsev 10:41552d038a69 408 SPI_TRANSFER_TYPE_NONE = 0,
Zaitsev 10:41552d038a69 409 SPI_TRANSFER_TYPE_TX = 1,
Zaitsev 10:41552d038a69 410 SPI_TRANSFER_TYPE_RX = 2,
Zaitsev 10:41552d038a69 411 SPI_TRANSFER_TYPE_TXRX = 3,
Zaitsev 10:41552d038a69 412 } transfer_type_t;
Zaitsev 10:41552d038a69 413
Zaitsev 10:41552d038a69 414
Zaitsev 10:41552d038a69 415 /// @returns the number of bytes transferred, or `0` if nothing transferred
Zaitsev 10:41552d038a69 416 static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer_type, const void *tx, void *rx, size_t length)
Zaitsev 10:41552d038a69 417 {
Zaitsev 10:41552d038a69 418 struct spi_s *spiobj = SPI_S(obj);
Zaitsev 10:41552d038a69 419 SPI_HandleTypeDef *handle = &(spiobj->handle);
Zaitsev 10:41552d038a69 420 bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
Zaitsev 10:41552d038a69 421 // the HAL expects number of transfers instead of number of bytes
Zaitsev 10:41552d038a69 422 // so for 16 bit transfer width the count needs to be halved
Zaitsev 10:41552d038a69 423 size_t words;
Zaitsev 10:41552d038a69 424
Zaitsev 10:41552d038a69 425 DEBUG_PRINTF("SPI inst=0x%8X Start: %u, %u\r\n", (int)handle->Instance, transfer_type, length);
Zaitsev 10:41552d038a69 426
Zaitsev 10:41552d038a69 427 obj->spi.transfer_type = transfer_type;
Zaitsev 10:41552d038a69 428
Zaitsev 10:41552d038a69 429 if (is16bit) {
Zaitsev 10:41552d038a69 430 words = length / 2;
Zaitsev 10:41552d038a69 431 } else {
Zaitsev 10:41552d038a69 432 words = length;
Zaitsev 10:41552d038a69 433 }
Zaitsev 10:41552d038a69 434
Zaitsev 10:41552d038a69 435 // enable the interrupt
Zaitsev 10:41552d038a69 436 IRQn_Type irq_n = spiobj->spiIRQ;
Zaitsev 10:41552d038a69 437 NVIC_DisableIRQ(irq_n);
Zaitsev 10:41552d038a69 438 NVIC_ClearPendingIRQ(irq_n);
Zaitsev 10:41552d038a69 439 NVIC_SetPriority(irq_n, 1);
Zaitsev 10:41552d038a69 440 NVIC_EnableIRQ(irq_n);
Zaitsev 10:41552d038a69 441
Zaitsev 10:41552d038a69 442 // enable the right hal transfer
Zaitsev 10:41552d038a69 443 int rc = 0;
Zaitsev 10:41552d038a69 444 switch(transfer_type) {
Zaitsev 10:41552d038a69 445 case SPI_TRANSFER_TYPE_TXRX:
Zaitsev 10:41552d038a69 446 rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t*)tx, (uint8_t*)rx, words);
Zaitsev 10:41552d038a69 447 break;
Zaitsev 10:41552d038a69 448 case SPI_TRANSFER_TYPE_TX:
Zaitsev 10:41552d038a69 449 rc = HAL_SPI_Transmit_IT(handle, (uint8_t*)tx, words);
Zaitsev 10:41552d038a69 450 break;
Zaitsev 10:41552d038a69 451 case SPI_TRANSFER_TYPE_RX:
Zaitsev 10:41552d038a69 452 // the receive function also "transmits" the receive buffer so in order
Zaitsev 10:41552d038a69 453 // to guarantee that 0xff is on the line, we explicitly memset it here
Zaitsev 10:41552d038a69 454 memset(rx, SPI_FILL_WORD, length);
Zaitsev 10:41552d038a69 455 rc = HAL_SPI_Receive_IT(handle, (uint8_t*)rx, words);
Zaitsev 10:41552d038a69 456 break;
Zaitsev 10:41552d038a69 457 default:
Zaitsev 10:41552d038a69 458 length = 0;
Zaitsev 10:41552d038a69 459 }
Zaitsev 10:41552d038a69 460
Zaitsev 10:41552d038a69 461 if (rc) {
Zaitsev 10:41552d038a69 462 DEBUG_PRINTF("SPI: RC=%u\n", rc);
Zaitsev 10:41552d038a69 463 length = 0;
Zaitsev 10:41552d038a69 464 }
Zaitsev 10:41552d038a69 465
Zaitsev 10:41552d038a69 466 return length;
Zaitsev 10:41552d038a69 467 }
Zaitsev 10:41552d038a69 468
Zaitsev 10:41552d038a69 469 // asynchronous API
Zaitsev 10:41552d038a69 470 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
Zaitsev 10:41552d038a69 471 {
Zaitsev 10:41552d038a69 472 struct spi_s *spiobj = SPI_S(obj);
Zaitsev 10:41552d038a69 473 SPI_HandleTypeDef *handle = &(spiobj->handle);
Zaitsev 10:41552d038a69 474
Zaitsev 10:41552d038a69 475 // TODO: DMA usage is currently ignored
Zaitsev 10:41552d038a69 476 (void) hint;
Zaitsev 10:41552d038a69 477
Zaitsev 10:41552d038a69 478 // check which use-case we have
Zaitsev 10:41552d038a69 479 bool use_tx = (tx != NULL && tx_length > 0);
Zaitsev 10:41552d038a69 480 bool use_rx = (rx != NULL && rx_length > 0);
Zaitsev 10:41552d038a69 481 bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
Zaitsev 10:41552d038a69 482
Zaitsev 10:41552d038a69 483 // don't do anything, if the buffers aren't valid
Zaitsev 10:41552d038a69 484 if (!use_tx && !use_rx)
Zaitsev 10:41552d038a69 485 return;
Zaitsev 10:41552d038a69 486
Zaitsev 10:41552d038a69 487 // copy the buffers to the SPI object
Zaitsev 10:41552d038a69 488 obj->tx_buff.buffer = (void *) tx;
Zaitsev 10:41552d038a69 489 obj->tx_buff.length = tx_length;
Zaitsev 10:41552d038a69 490 obj->tx_buff.pos = 0;
Zaitsev 10:41552d038a69 491 obj->tx_buff.width = is16bit ? 16 : 8;
Zaitsev 10:41552d038a69 492
Zaitsev 10:41552d038a69 493 obj->rx_buff.buffer = rx;
Zaitsev 10:41552d038a69 494 obj->rx_buff.length = rx_length;
Zaitsev 10:41552d038a69 495 obj->rx_buff.pos = 0;
Zaitsev 10:41552d038a69 496 obj->rx_buff.width = obj->tx_buff.width;
Zaitsev 10:41552d038a69 497
Zaitsev 10:41552d038a69 498 obj->spi.event = event;
Zaitsev 10:41552d038a69 499
Zaitsev 10:41552d038a69 500 DEBUG_PRINTF("SPI: Transfer: %u, %u\n", tx_length, rx_length);
Zaitsev 10:41552d038a69 501
Zaitsev 10:41552d038a69 502 // register the thunking handler
Zaitsev 10:41552d038a69 503 IRQn_Type irq_n = spiobj->spiIRQ;
Zaitsev 10:41552d038a69 504 NVIC_SetVector(irq_n, (uint32_t)handler);
Zaitsev 10:41552d038a69 505
Zaitsev 10:41552d038a69 506 // enable the right hal transfer
Zaitsev 10:41552d038a69 507 if (use_tx && use_rx) {
Zaitsev 10:41552d038a69 508 // we cannot manage different rx / tx sizes, let's use smaller one
Zaitsev 10:41552d038a69 509 size_t size = (tx_length < rx_length)? tx_length : rx_length;
Zaitsev 10:41552d038a69 510 if(tx_length != rx_length) {
Zaitsev 10:41552d038a69 511 DEBUG_PRINTF("SPI: Full duplex transfer only 1 size: %d\n", size);
Zaitsev 10:41552d038a69 512 obj->tx_buff.length = size;
Zaitsev 10:41552d038a69 513 obj->rx_buff.length = size;
Zaitsev 10:41552d038a69 514 }
Zaitsev 10:41552d038a69 515 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TXRX, tx, rx, size);
Zaitsev 10:41552d038a69 516 } else if (use_tx) {
Zaitsev 10:41552d038a69 517 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TX, tx, NULL, tx_length);
Zaitsev 10:41552d038a69 518 } else if (use_rx) {
Zaitsev 10:41552d038a69 519 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_RX, NULL, rx, rx_length);
Zaitsev 10:41552d038a69 520 }
Zaitsev 10:41552d038a69 521 }
Zaitsev 10:41552d038a69 522
Zaitsev 10:41552d038a69 523 inline uint32_t spi_irq_handler_asynch(spi_t *obj)
Zaitsev 10:41552d038a69 524 {
Zaitsev 10:41552d038a69 525 int event = 0;
Zaitsev 10:41552d038a69 526
Zaitsev 10:41552d038a69 527 // call the CubeF4 handler, this will update the handle
Zaitsev 10:41552d038a69 528 HAL_SPI_IRQHandler(&obj->spi.handle);
Zaitsev 10:41552d038a69 529
Zaitsev 10:41552d038a69 530 if (obj->spi.handle.State == HAL_SPI_STATE_READY) {
Zaitsev 10:41552d038a69 531 // When HAL SPI is back to READY state, check if there was an error
Zaitsev 10:41552d038a69 532 int error = obj->spi.handle.ErrorCode;
Zaitsev 10:41552d038a69 533 if(error != HAL_SPI_ERROR_NONE) {
Zaitsev 10:41552d038a69 534 // something went wrong and the transfer has definitely completed
Zaitsev 10:41552d038a69 535 event = SPI_EVENT_ERROR | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
Zaitsev 10:41552d038a69 536
Zaitsev 10:41552d038a69 537 if (error & HAL_SPI_ERROR_OVR) {
Zaitsev 10:41552d038a69 538 // buffer overrun
Zaitsev 10:41552d038a69 539 event |= SPI_EVENT_RX_OVERFLOW;
Zaitsev 10:41552d038a69 540 }
Zaitsev 10:41552d038a69 541 } else {
Zaitsev 10:41552d038a69 542 // else we're done
Zaitsev 10:41552d038a69 543 event = SPI_EVENT_COMPLETE | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
Zaitsev 10:41552d038a69 544 }
Zaitsev 10:41552d038a69 545 // enable the interrupt
Zaitsev 10:41552d038a69 546 NVIC_DisableIRQ(obj->spi.spiIRQ);
Zaitsev 10:41552d038a69 547 NVIC_ClearPendingIRQ(obj->spi.spiIRQ);
Zaitsev 10:41552d038a69 548 }
Zaitsev 10:41552d038a69 549
Zaitsev 10:41552d038a69 550
Zaitsev 10:41552d038a69 551 return (event & (obj->spi.event | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE));
Zaitsev 10:41552d038a69 552 }
Zaitsev 10:41552d038a69 553
Zaitsev 10:41552d038a69 554 uint8_t spi_active(spi_t *obj)
Zaitsev 10:41552d038a69 555 {
Zaitsev 10:41552d038a69 556 struct spi_s *spiobj = SPI_S(obj);
Zaitsev 10:41552d038a69 557 SPI_HandleTypeDef *handle = &(spiobj->handle);
Zaitsev 10:41552d038a69 558 HAL_SPI_StateTypeDef state = HAL_SPI_GetState(handle);
Zaitsev 10:41552d038a69 559
Zaitsev 10:41552d038a69 560 switch(state) {
Zaitsev 10:41552d038a69 561 case HAL_SPI_STATE_RESET:
Zaitsev 10:41552d038a69 562 case HAL_SPI_STATE_READY:
Zaitsev 10:41552d038a69 563 case HAL_SPI_STATE_ERROR:
Zaitsev 10:41552d038a69 564 return 0;
Zaitsev 10:41552d038a69 565 default:
Zaitsev 10:41552d038a69 566 return 1;
Zaitsev 10:41552d038a69 567 }
Zaitsev 10:41552d038a69 568 }
Zaitsev 10:41552d038a69 569
Zaitsev 10:41552d038a69 570 void spi_abort_asynch(spi_t *obj)
Zaitsev 10:41552d038a69 571 {
Zaitsev 10:41552d038a69 572 struct spi_s *spiobj = SPI_S(obj);
Zaitsev 10:41552d038a69 573 SPI_HandleTypeDef *handle = &(spiobj->handle);
Zaitsev 10:41552d038a69 574
Zaitsev 10:41552d038a69 575 // disable interrupt
Zaitsev 10:41552d038a69 576 IRQn_Type irq_n = spiobj->spiIRQ;
Zaitsev 10:41552d038a69 577 NVIC_ClearPendingIRQ(irq_n);
Zaitsev 10:41552d038a69 578 NVIC_DisableIRQ(irq_n);
Zaitsev 10:41552d038a69 579
Zaitsev 10:41552d038a69 580 // clean-up
Zaitsev 10:41552d038a69 581 __HAL_SPI_DISABLE(handle);
Zaitsev 10:41552d038a69 582 HAL_SPI_DeInit(handle);
Zaitsev 10:41552d038a69 583 HAL_SPI_Init(handle);
Zaitsev 10:41552d038a69 584 __HAL_SPI_ENABLE(handle);
Zaitsev 10:41552d038a69 585 }
Zaitsev 10:41552d038a69 586
Zaitsev 10:41552d038a69 587 #endif //DEVICE_SPI_ASYNCH
Zaitsev 10:41552d038a69 588
Zaitsev 10:41552d038a69 589 #endif