Daniel Sygut / Application

lol

Dependencies:   MMA8451Q

Fork of Application by Mateusz Kowalik

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c@12:3a30cdffa27c, 2018-01-21 (annotated)

Committer:
danix
Date:
Sun Jan 21 22:28:30 2018 +0000
Revision:
12:3a30cdffa27c
Parent:
10:41552d038a69 
Working acelerometer and mouse

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Zaitsev 10:41552d038a69 1 /**
Zaitsev 10:41552d038a69 2 ***************************************************************************
Zaitsev 10:41552d038a69 3 * @file ncs36510_init.c
Zaitsev 10:41552d038a69 4 * @brief Initialization of Orion SoC
Zaitsev 10:41552d038a69 5 * @internal
Zaitsev 10:41552d038a69 6 * @author ON Semiconductor
Zaitsev 10:41552d038a69 7 * $Rev:
Zaitsev 10:41552d038a69 8 * $Date: $
Zaitsev 10:41552d038a69 9 ******************************************************************************
Zaitsev 10:41552d038a69 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
Zaitsev 10:41552d038a69 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
Zaitsev 10:41552d038a69 12 * under limited terms and conditions. The terms and conditions pertaining to the software
Zaitsev 10:41552d038a69 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
Zaitsev 10:41552d038a69 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
Zaitsev 10:41552d038a69 15 * if applicable the software license agreement. Do not use this software and/or
Zaitsev 10:41552d038a69 16 * documentation unless you have carefully read and you agree to the limited terms and
Zaitsev 10:41552d038a69 17 * conditions. By using this software and/or documentation, you agree to the limited
Zaitsev 10:41552d038a69 18 * terms and conditions.
Zaitsev 10:41552d038a69 19 *
Zaitsev 10:41552d038a69 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
Zaitsev 10:41552d038a69 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
Zaitsev 10:41552d038a69 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
Zaitsev 10:41552d038a69 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
Zaitsev 10:41552d038a69 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
Zaitsev 10:41552d038a69 25 * @endinternal
Zaitsev 10:41552d038a69 26 *
Zaitsev 10:41552d038a69 27 * @ingroup main
Zaitsev 10:41552d038a69 28 *
Zaitsev 10:41552d038a69 29 * @details
Zaitsev 10:41552d038a69 30 */
Zaitsev 10:41552d038a69 31
Zaitsev 10:41552d038a69 32 /*************************************************************************************************
Zaitsev 10:41552d038a69 33 * *
Zaitsev 10:41552d038a69 34 * Header files *
Zaitsev 10:41552d038a69 35 * *
Zaitsev 10:41552d038a69 36 *************************************************************************************************/
Zaitsev 10:41552d038a69 37 #include "ncs36510Init.h"
Zaitsev 10:41552d038a69 38
Zaitsev 10:41552d038a69 39 void fPmuInit(void);
Zaitsev 10:41552d038a69 40
Zaitsev 10:41552d038a69 41 /**
Zaitsev 10:41552d038a69 42 * @brief
Zaitsev 10:41552d038a69 43 * Hardware trimming function
Zaitsev 10:41552d038a69 44 * This function copies trim codes from specific flash location
Zaitsev 10:41552d038a69 45 * where they are stored to proper hw registers.
Zaitsev 10:41552d038a69 46 */
Zaitsev 10:41552d038a69 47 boolean fTrim()
Zaitsev 10:41552d038a69 48 {
Zaitsev 10:41552d038a69 49 boolean status = False;
Zaitsev 10:41552d038a69 50
Zaitsev 10:41552d038a69 51 /**- Check if trim values are present */
Zaitsev 10:41552d038a69 52 /**- If Trim data is present. Only trim if valid trim values are present. */
Zaitsev 10:41552d038a69 53 /**- Copy trims in registers */
Zaitsev 10:41552d038a69 54 if (TRIMREG->REVISION_CODE != 0xFFFFFFFF) {
Zaitsev 10:41552d038a69 55
Zaitsev 10:41552d038a69 56 if ( TRIMREG->MAC_ADDR_LOW != 0xFFFFFFFF ) {
Zaitsev 10:41552d038a69 57 MACHWREG->LONG_ADDRESS_LOW = TRIMREG->MAC_ADDR_LOW;
Zaitsev 10:41552d038a69 58 }
Zaitsev 10:41552d038a69 59
Zaitsev 10:41552d038a69 60 if ( TRIMREG->MAC_ADDR_HIGH != 0xFFFFFFFF ) {
Zaitsev 10:41552d038a69 61 MACHWREG->LONG_ADDRESS_HIGH = TRIMREG->MAC_ADDR_HIGH;
Zaitsev 10:41552d038a69 62 }
Zaitsev 10:41552d038a69 63
Zaitsev 10:41552d038a69 64 /**- board specific clock trims may only be done when present, writing all 1's is not good */
Zaitsev 10:41552d038a69 65 if ((TRIMREG->TRIM_32K_EXT & 0xFFFF0000) != 0xFFFF0000) {
Zaitsev 10:41552d038a69 66 CLOCKREG->TRIM_32K_EXT.WORD = TRIMREG->TRIM_32K_EXT;
Zaitsev 10:41552d038a69 67 }
Zaitsev 10:41552d038a69 68
Zaitsev 10:41552d038a69 69 if ((TRIMREG->TRIM_32M_EXT & 0xFFFF0000) != 0xFFFF0000) {
Zaitsev 10:41552d038a69 70 CLOCKREG->TRIM_32M_EXT.WORD = TRIMREG->TRIM_32M_EXT;
Zaitsev 10:41552d038a69 71 }
Zaitsev 10:41552d038a69 72
Zaitsev 10:41552d038a69 73 MACHWREG->TX_LENGTH.BITS.TX_PRE_CHIPS = TRIMREG->TX_PRE_CHIPS;
Zaitsev 10:41552d038a69 74
Zaitsev 10:41552d038a69 75 if ((TRIMREG->TX_TRIM & 0xFFFF0000) != 0xFFFF0000) {
Zaitsev 10:41552d038a69 76 RFANATRIMREG->TX_TRIM.WORD = TRIMREG->TX_TRIM;
Zaitsev 10:41552d038a69 77 }
Zaitsev 10:41552d038a69 78 RFANATRIMREG->PLL_VCO_TAP_LOCATION = TRIMREG->PLL_VCO_TAP_LOCATION;
Zaitsev 10:41552d038a69 79 RFANATRIMREG->PLL_TRIM.WORD = TRIMREG->PLL_TRIM;
Zaitsev 10:41552d038a69 80
Zaitsev 10:41552d038a69 81 /**- board specific RSSI trims may only be done when present, writing all 1's is not good */
Zaitsev 10:41552d038a69 82 if ((TRIMREG->RSSI_OFFSET & 0xFFFF0000) != 0xFFFF0000) {
Zaitsev 10:41552d038a69 83 DMDREG->DMD_CONTROL2.BITS.RSSI_OFFSET = TRIMREG->RSSI_OFFSET;
Zaitsev 10:41552d038a69 84 }
Zaitsev 10:41552d038a69 85
Zaitsev 10:41552d038a69 86 RFANATRIMREG->RX_CHAIN_TRIM = TRIMREG->RX_CHAIN_TRIM;
Zaitsev 10:41552d038a69 87 RFANATRIMREG->PMU_TRIM = TRIMREG->PMU_TRIM;
Zaitsev 10:41552d038a69 88 RANDREG->WR_SEED_RD_RAND = TRIMREG->WR_SEED_RD_RAND;
Zaitsev 10:41552d038a69 89
Zaitsev 10:41552d038a69 90 /* High side injection settings */
Zaitsev 10:41552d038a69 91 RFANATRIMREG->RX_VCO_TRIM_LUT1 = TRIMREG->RX_VCO_LUT1.WORD;;
Zaitsev 10:41552d038a69 92 RFANATRIMREG->RX_VCO_TRIM_LUT2 = TRIMREG->RX_VCO_LUT2.WORD;;
Zaitsev 10:41552d038a69 93
Zaitsev 10:41552d038a69 94 RFANATRIMREG->TX_VCO_TRIM_LUT1 = TRIMREG->TX_VCO_LUT1.WORD;;
Zaitsev 10:41552d038a69 95 RFANATRIMREG->TX_VCO_TRIM_LUT2 = TRIMREG->TX_VCO_LUT2.WORD;;
Zaitsev 10:41552d038a69 96
Zaitsev 10:41552d038a69 97 status = True;
Zaitsev 10:41552d038a69 98
Zaitsev 10:41552d038a69 99 } else {
Zaitsev 10:41552d038a69 100
Zaitsev 10:41552d038a69 101 return(False);
Zaitsev 10:41552d038a69 102 }
Zaitsev 10:41552d038a69 103
Zaitsev 10:41552d038a69 104 /** Read in user trim values programmed in the flash memory
Zaitsev 10:41552d038a69 105 The user trim values take precedence over factory trim for MAC address
Zaitsev 10:41552d038a69 106 */
Zaitsev 10:41552d038a69 107 if (( USERTRIMREG->MAC_ADDRESS_LOW != 0xFFFFFFFF ) &&
Zaitsev 10:41552d038a69 108 (USERTRIMREG->MAC_ADDRESS_HIGH != 0xFFFFFFFF)) {
Zaitsev 10:41552d038a69 109
Zaitsev 10:41552d038a69 110 MACHWREG->LONG_ADDRESS_LOW = USERTRIMREG->MAC_ADDRESS_LOW;
Zaitsev 10:41552d038a69 111 MACHWREG->LONG_ADDRESS_HIGH = USERTRIMREG->MAC_ADDRESS_HIGH;
Zaitsev 10:41552d038a69 112 }
Zaitsev 10:41552d038a69 113
Zaitsev 10:41552d038a69 114 if (USERTRIMREG->TRIM_32K_EXT != 0xFFFFFFFF) {
Zaitsev 10:41552d038a69 115 CLOCKREG->TRIM_32K_EXT.WORD = (USERTRIMREG->TRIM_32K_EXT & 0x00000FFF);
Zaitsev 10:41552d038a69 116 }
Zaitsev 10:41552d038a69 117
Zaitsev 10:41552d038a69 118 if (USERTRIMREG->TRIM_32K_EXT != 0xFFFFFFFF) {
Zaitsev 10:41552d038a69 119 CLOCKREG->TRIM_32K_EXT.WORD = (USERTRIMREG->TRIM_32K_EXT & 0x00000FFF);
Zaitsev 10:41552d038a69 120 }
Zaitsev 10:41552d038a69 121
Zaitsev 10:41552d038a69 122 if (USERTRIMREG->RSSI_OFFSET != 0xFFFFFFFF) {
Zaitsev 10:41552d038a69 123 DMDREG->DMD_CONTROL2.BITS.RSSI_OFFSET = (USERTRIMREG->RSSI_OFFSET & 0x0000003F);
Zaitsev 10:41552d038a69 124 }
Zaitsev 10:41552d038a69 125
Zaitsev 10:41552d038a69 126 if (USERTRIMREG->TX_TRIM != 0xFFFFFFFF) {
Zaitsev 10:41552d038a69 127 RFANATRIMREG->TX_TRIM.BITS.TX_TUNE = (USERTRIMREG->TX_TRIM & 0x0000000F);
Zaitsev 10:41552d038a69 128 }
Zaitsev 10:41552d038a69 129 return(status);
Zaitsev 10:41552d038a69 130 }
Zaitsev 10:41552d038a69 131
Zaitsev 10:41552d038a69 132 /* See clock.h for documentation. */
Zaitsev 10:41552d038a69 133 void fClockInit()
Zaitsev 10:41552d038a69 134 {
Zaitsev 10:41552d038a69 135
Zaitsev 10:41552d038a69 136 /** Enable external 32MHz oscillator */
Zaitsev 10:41552d038a69 137 CLOCKREG->CCR.BITS.OSC_SEL = 1;
Zaitsev 10:41552d038a69 138
Zaitsev 10:41552d038a69 139 /** - Wait external 32MHz oscillator to be ready */
Zaitsev 10:41552d038a69 140 while(CLOCKREG->CSR.BITS.XTAL32M != 1) {} /* If you get stuck here, something is wrong with board or trim values */
Zaitsev 10:41552d038a69 141
Zaitsev 10:41552d038a69 142 /** Internal 32MHz calibration \n *//** - Enable internal 32MHz clock */
Zaitsev 10:41552d038a69 143 PMUREG->CONTROL.BITS.INT32M = 0;
Zaitsev 10:41552d038a69 144
Zaitsev 10:41552d038a69 145 /** - Wait 5 uSec for clock to stabilize */
Zaitsev 10:41552d038a69 146 volatile uint8_t Timer;
Zaitsev 10:41552d038a69 147 for(Timer = 0; Timer < 10; Timer++);
Zaitsev 10:41552d038a69 148
Zaitsev 10:41552d038a69 149 /** - Enable calibration */
Zaitsev 10:41552d038a69 150 CLOCKREG->CCR.BITS.CAL32M = True;
Zaitsev 10:41552d038a69 151
Zaitsev 10:41552d038a69 152 /** - Wait calibration to be completed */
Zaitsev 10:41552d038a69 153 while(CLOCKREG->CSR.BITS.CAL32MDONE == False); /* If you stuck here, issue with internal 32M calibration */
Zaitsev 10:41552d038a69 154
Zaitsev 10:41552d038a69 155 /** - Check calibration status */
Zaitsev 10:41552d038a69 156 while(CLOCKREG->CSR.BITS.CAL32MFAIL == True); /* If you stuck here, issue with internal 32M calibration */
Zaitsev 10:41552d038a69 157
Zaitsev 10:41552d038a69 158 /** - Power down internal 32MHz osc */
Zaitsev 10:41552d038a69 159 PMUREG->CONTROL.BITS.INT32M = 1;
Zaitsev 10:41552d038a69 160
Zaitsev 10:41552d038a69 161 /** Internal 32KHz calibration \n */ /** - Enable internal 32KHz clock */
Zaitsev 10:41552d038a69 162 PMUREG->CONTROL.BITS.INT32K = 0;
Zaitsev 10:41552d038a69 163
Zaitsev 10:41552d038a69 164 /** - Wait 5 uSec for clock to stabilize */
Zaitsev 10:41552d038a69 165 for(Timer = 0; Timer < 10; Timer++);
Zaitsev 10:41552d038a69 166
Zaitsev 10:41552d038a69 167 /** - Enable calibration */
Zaitsev 10:41552d038a69 168 CLOCKREG->CCR.BITS.CAL32K = True;
Zaitsev 10:41552d038a69 169
Zaitsev 10:41552d038a69 170 /** - Wait calibration to be completed */
Zaitsev 10:41552d038a69 171 while(CLOCKREG->CSR.BITS.DONE32K == False); /* If you stuck here, issue with internal 32K calibration */
Zaitsev 10:41552d038a69 172
Zaitsev 10:41552d038a69 173 /** - Check calibration status */
Zaitsev 10:41552d038a69 174 while(CLOCKREG->CSR.BITS.CAL32K == True); /* If you stuck here, issue with internal 32M calibration */
Zaitsev 10:41552d038a69 175
Zaitsev 10:41552d038a69 176 /** - Power down external 32KHz osc */
Zaitsev 10:41552d038a69 177 PMUREG->CONTROL.BITS.EXT32K = 1;
Zaitsev 10:41552d038a69 178
Zaitsev 10:41552d038a69 179 /** Disable all peripheral clocks by default */
Zaitsev 10:41552d038a69 180 CLOCKREG->PDIS.WORD = 0xFFFFFFFF;
Zaitsev 10:41552d038a69 181
Zaitsev 10:41552d038a69 182 /** Set core frequency */
Zaitsev 10:41552d038a69 183 CLOCKREG->FDIV = CPU_CLOCK_DIV - 1;
Zaitsev 10:41552d038a69 184 }
Zaitsev 10:41552d038a69 185
Zaitsev 10:41552d038a69 186 /* Initializes PMU module */
Zaitsev 10:41552d038a69 187 void fPmuInit()
Zaitsev 10:41552d038a69 188 {
Zaitsev 10:41552d038a69 189 /** Enable the clock for PMU peripheral device */
Zaitsev 10:41552d038a69 190 CLOCK_ENABLE(CLOCK_PMU);
Zaitsev 10:41552d038a69 191
Zaitsev 10:41552d038a69 192 /** Unset wakeup on pending (only enabled irq can wakeup) */
Zaitsev 10:41552d038a69 193 SCB->SCR &= ~SCB_SCR_SEVONPEND_Msk;
Zaitsev 10:41552d038a69 194
Zaitsev 10:41552d038a69 195 /** Unset auto sleep when returning from wakeup irq */
Zaitsev 10:41552d038a69 196 SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
Zaitsev 10:41552d038a69 197
Zaitsev 10:41552d038a69 198 /** Set regulator timings */
Zaitsev 10:41552d038a69 199 PMUREG->FVDD_TSETTLE = 160;
Zaitsev 10:41552d038a69 200 PMUREG->FVDD_TSTARTUP = 400;
Zaitsev 10:41552d038a69 201
Zaitsev 10:41552d038a69 202
Zaitsev 10:41552d038a69 203 /** Keep SRAMA & SRAMB powered in coma mode */
Zaitsev 10:41552d038a69 204 PMUREG->CONTROL.BITS.SRAMA = False;
Zaitsev 10:41552d038a69 205 PMUREG->CONTROL.BITS.SRAMB = False;
Zaitsev 10:41552d038a69 206
Zaitsev 10:41552d038a69 207 PMUREG->CONTROL.BITS.N1V1 = True; /* Enable ACTIVE mode switching regulator */
Zaitsev 10:41552d038a69 208 PMUREG->CONTROL.BITS.C1V1 = True; /* Enable COMA mode switching regulator */
Zaitsev 10:41552d038a69 209
Zaitsev 10:41552d038a69 210 /** Disable the clock for PMU peripheral device, all settings are done */
Zaitsev 10:41552d038a69 211 CLOCK_DISABLE(CLOCK_PMU);
Zaitsev 10:41552d038a69 212 }
Zaitsev 10:41552d038a69 213
Zaitsev 10:41552d038a69 214 /* See clock.h for documentation. */
Zaitsev 10:41552d038a69 215 uint32_t fClockGetPeriphClockfrequency()
Zaitsev 10:41552d038a69 216 {
Zaitsev 10:41552d038a69 217 return (CPU_CLOCK_ROOT_HZ / CPU_CLOCK_DIV);
Zaitsev 10:41552d038a69 218 }
Zaitsev 10:41552d038a69 219
Zaitsev 10:41552d038a69 220
Zaitsev 10:41552d038a69 221 /**
Zaitsev 10:41552d038a69 222 * @brief
Zaitsev 10:41552d038a69 223 * Hardware initialization function
Zaitsev 10:41552d038a69 224 * This function initializes hardware at application start up prior
Zaitsev 10:41552d038a69 225 * to other initializations or OS operations.
Zaitsev 10:41552d038a69 226 */
Zaitsev 10:41552d038a69 227 static void fHwInit(void)
Zaitsev 10:41552d038a69 228 {
Zaitsev 10:41552d038a69 229
Zaitsev 10:41552d038a69 230 /* Trim register settings */
Zaitsev 10:41552d038a69 231 fTrim();
Zaitsev 10:41552d038a69 232
Zaitsev 10:41552d038a69 233 /* Clock setting */
Zaitsev 10:41552d038a69 234 /** - Initialize clock */
Zaitsev 10:41552d038a69 235 fClockInit();
Zaitsev 10:41552d038a69 236
Zaitsev 10:41552d038a69 237 /** - Initialize pmu */
Zaitsev 10:41552d038a69 238 fPmuInit();
Zaitsev 10:41552d038a69 239
Zaitsev 10:41552d038a69 240 /** Orion has 4 interrupt bits in interrupt priority register
Zaitsev 10:41552d038a69 241 * The lowest 4 bits are not used.
Zaitsev 10:41552d038a69 242 *
Zaitsev 10:41552d038a69 243 @verbatim
Zaitsev 10:41552d038a69 244 +-----+-----+-----+-----+-----+-----+-----+-----+
Zaitsev 10:41552d038a69 245 |bit 7|bit 6|bit 5|bit 4|bit 3|bit 2|bit 1|bit 0|
Zaitsev 10:41552d038a69 246 | | | | | 0 | 0 | 0 | 0 |
Zaitsev 10:41552d038a69 247 +-----+-----+-----+-----+-----+-----+-----+-----+
Zaitsev 10:41552d038a69 248 |
Zaitsev 10:41552d038a69 249 INTERRUPT PRIORITY | NOT IMPLEMENTED,
Zaitsev 10:41552d038a69 250 | read as 0
Zaitsev 10:41552d038a69 251 Valid priorities are 0x00, 0x10, 0x20, 0x30
Zaitsev 10:41552d038a69 252 0x40, 0x50, 0x60, 0x70
Zaitsev 10:41552d038a69 253 0x80, 0x90, 0xA0, 0xB0
Zaitsev 10:41552d038a69 254 0xC0, 0xD0, 0xE0, 0xF0
Zaitsev 10:41552d038a69 255 @endverbatim
Zaitsev 10:41552d038a69 256 * Lowest number is highest priority
Zaitsev 10:41552d038a69 257 *
Zaitsev 10:41552d038a69 258 *
Zaitsev 10:41552d038a69 259 * This range is defined by
Zaitsev 10:41552d038a69 260 * configKERNEL_INTERRUPT_PRIORITY (lowest)
Zaitsev 10:41552d038a69 261 * and configMAX_SYSCALL_INTERRUPT_PRIORITY (highest). All interrupt
Zaitsev 10:41552d038a69 262 * priorities need to fall in that range.
Zaitsev 10:41552d038a69 263 *
Zaitsev 10:41552d038a69 264 * To be future safe, the LSbits of the priority are set to 0xF.
Zaitsev 10:41552d038a69 265 * This wil lmake sure that if more interrupt bits are used, the
Zaitsev 10:41552d038a69 266 * priority is maintained.
Zaitsev 10:41552d038a69 267 */
Zaitsev 10:41552d038a69 268
Zaitsev 10:41552d038a69 269 /** - Set IRQs priorities */
Zaitsev 10:41552d038a69 270 NVIC_SetPriority(Tim0_IRQn, 14);
Zaitsev 10:41552d038a69 271 NVIC_SetPriority(Tim1_IRQn, 14);
Zaitsev 10:41552d038a69 272 NVIC_SetPriority(Tim2_IRQn, 14);
Zaitsev 10:41552d038a69 273 NVIC_SetPriority(Uart1_IRQn,14);
Zaitsev 10:41552d038a69 274 NVIC_SetPriority(Spi_IRQn, 14);
Zaitsev 10:41552d038a69 275 NVIC_SetPriority(I2C_IRQn, 14);
Zaitsev 10:41552d038a69 276 NVIC_SetPriority(Gpio_IRQn, 14);
Zaitsev 10:41552d038a69 277 NVIC_SetPriority(Rtc_IRQn, 14);
Zaitsev 10:41552d038a69 278 NVIC_SetPriority(MacHw_IRQn, 13);
Zaitsev 10:41552d038a69 279 NVIC_SetPriority(Aes_IRQn, 13);
Zaitsev 10:41552d038a69 280 NVIC_SetPriority(Adc_IRQn, 14);
Zaitsev 10:41552d038a69 281 NVIC_SetPriority(ClockCal_IRQn, 14);
Zaitsev 10:41552d038a69 282 NVIC_SetPriority(Uart2_IRQn, 14);
Zaitsev 10:41552d038a69 283 NVIC_SetPriority(Dma_IRQn, 14);
Zaitsev 10:41552d038a69 284 NVIC_SetPriority(Uvi_IRQn, 14);
Zaitsev 10:41552d038a69 285 NVIC_SetPriority(DbgPwrUp_IRQn, 14);
Zaitsev 10:41552d038a69 286 NVIC_SetPriority(Spi2_IRQn, 14);
Zaitsev 10:41552d038a69 287 NVIC_SetPriority(I2C2_IRQn, 14);
Zaitsev 10:41552d038a69 288 }
Zaitsev 10:41552d038a69 289
Zaitsev 10:41552d038a69 290 extern void __Vectors;
Zaitsev 10:41552d038a69 291
Zaitsev 10:41552d038a69 292 void fNcs36510Init(void)
Zaitsev 10:41552d038a69 293 {
Zaitsev 10:41552d038a69 294 /** Setting this register is helping to debug imprecise bus access faults
Zaitsev 10:41552d038a69 295 * making them precise bus access faults. It has an impact on application
Zaitsev 10:41552d038a69 296 * performance. */
Zaitsev 10:41552d038a69 297 // SCnSCB->ACTLR |= SCnSCB_ACTLR_DISDEFWBUF_Msk;
Zaitsev 10:41552d038a69 298
Zaitsev 10:41552d038a69 299 /** This main function implements: */
Zaitsev 10:41552d038a69 300 /**- Disable all interrupts */
Zaitsev 10:41552d038a69 301 NVIC->ICER[0] = 0x1F;
Zaitsev 10:41552d038a69 302
Zaitsev 10:41552d038a69 303 /**- Clear all Pending interrupts */
Zaitsev 10:41552d038a69 304 NVIC->ICPR[0] = 0x1F;
Zaitsev 10:41552d038a69 305
Zaitsev 10:41552d038a69 306 /**- Clear all pending SV and systick */
Zaitsev 10:41552d038a69 307 SCB->ICSR = (uint32_t)0x0A000000;
Zaitsev 10:41552d038a69 308 SCB->VTOR = (uint32_t) (&__Vectors);
Zaitsev 10:41552d038a69 309
Zaitsev 10:41552d038a69 310 /**- Initialize hardware */
Zaitsev 10:41552d038a69 311 fHwInit();
Zaitsev 10:41552d038a69 312 }