Daniel Sygut / Application

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Dependencies:   MMA8451Q

Fork of Application by Mateusz Kowalik

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c@10:41552d038a69, 2017-01-10 (annotated)

Committer:
Zaitsev
Date:
Tue Jan 10 20:42:26 2017 +0000
Revision:
10:41552d038a69
USB Serial bi-directional bridge

Who changed what in which revision?

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Zaitsev 10:41552d038a69 1 /**
Zaitsev 10:41552d038a69 2 ******************************************************************************
Zaitsev 10:41552d038a69 3 * @file rfAna.c
Zaitsev 10:41552d038a69 4 * @brief Implementation of rfAna hw module functions
Zaitsev 10:41552d038a69 5 * @internal
Zaitsev 10:41552d038a69 6 * @author ON Semiconductor
Zaitsev 10:41552d038a69 7 * $Rev: 3445 $
Zaitsev 10:41552d038a69 8 * $Date: 2015-06-22 13:51:24 +0530 (Mon, 22 Jun 2015) $
Zaitsev 10:41552d038a69 9 ******************************************************************************
Zaitsev 10:41552d038a69 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
Zaitsev 10:41552d038a69 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
Zaitsev 10:41552d038a69 12 * under limited terms and conditions. The terms and conditions pertaining to the software
Zaitsev 10:41552d038a69 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
Zaitsev 10:41552d038a69 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
Zaitsev 10:41552d038a69 15 * if applicable the software license agreement. Do not use this software and/or
Zaitsev 10:41552d038a69 16 * documentation unless you have carefully read and you agree to the limited terms and
Zaitsev 10:41552d038a69 17 * conditions. By using this software and/or documentation, you agree to the limited
Zaitsev 10:41552d038a69 18 * terms and conditions.
Zaitsev 10:41552d038a69 19 *
Zaitsev 10:41552d038a69 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
Zaitsev 10:41552d038a69 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
Zaitsev 10:41552d038a69 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
Zaitsev 10:41552d038a69 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
Zaitsev 10:41552d038a69 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
Zaitsev 10:41552d038a69 25 * @endinternal
Zaitsev 10:41552d038a69 26 *
Zaitsev 10:41552d038a69 27 * @ingroup rfAna
Zaitsev 10:41552d038a69 28 *
Zaitsev 10:41552d038a69 29 * @details
Zaitsev 10:41552d038a69 30 *
Zaitsev 10:41552d038a69 31 * <h1> Reference document(s) </h1>
Zaitsev 10:41552d038a69 32 */
Zaitsev 10:41552d038a69 33
Zaitsev 10:41552d038a69 34 /*************************************************************************************************
Zaitsev 10:41552d038a69 35 * *
Zaitsev 10:41552d038a69 36 * Header files *
Zaitsev 10:41552d038a69 37 * *
Zaitsev 10:41552d038a69 38 *************************************************************************************************/
Zaitsev 10:41552d038a69 39
Zaitsev 10:41552d038a69 40 #include "memory_map.h"
Zaitsev 10:41552d038a69 41 #include "rfAna.h"
Zaitsev 10:41552d038a69 42 #include "clock.h"
Zaitsev 10:41552d038a69 43
Zaitsev 10:41552d038a69 44 /*************************************************************************************************
Zaitsev 10:41552d038a69 45 * *
Zaitsev 10:41552d038a69 46 * Global variables *
Zaitsev 10:41552d038a69 47 * *
Zaitsev 10:41552d038a69 48 *************************************************************************************************/
Zaitsev 10:41552d038a69 49
Zaitsev 10:41552d038a69 50 /** Rf channel and tx power lookup tables (constant)
Zaitsev 10:41552d038a69 51 * @details
Zaitsev 10:41552d038a69 52 *
Zaitsev 10:41552d038a69 53 * The rf channel table is used to program internal hardware register for different 15.4 rf channels.
Zaitsev 10:41552d038a69 54 * It has 16 entries corresponding to 16 15.4 channels.
Zaitsev 10:41552d038a69 55 * Entry 1 <-> Channel 11
Zaitsev 10:41552d038a69 56 * ...
Zaitsev 10:41552d038a69 57 * Entry 16 <-> Channel 26
Zaitsev 10:41552d038a69 58 *
Zaitsev 10:41552d038a69 59 * Each entry is compound of 4 items.
Zaitsev 10:41552d038a69 60 * Item 0: Rx Frequency integer divide portion
Zaitsev 10:41552d038a69 61 * Item 1: Rx Frequency fractional divide portion
Zaitsev 10:41552d038a69 62 * Item 2: Tx Frequency integer divide portion
Zaitsev 10:41552d038a69 63 * Item 3: Tx Frequency fractional divide portion
Zaitsev 10:41552d038a69 64 *
Zaitsev 10:41552d038a69 65 * The tx power table is used to program internal hardware register for different 15.4 tx power levels.
Zaitsev 10:41552d038a69 66 * It has 43 entries corresponding to tx power levels from -32dBm to +10dBm.
Zaitsev 10:41552d038a69 67 * Entry 1 <-> -32dB
Zaitsev 10:41552d038a69 68 * Entry 2 <-> -31dB
Zaitsev 10:41552d038a69 69 * ...
Zaitsev 10:41552d038a69 70 * Entry 2 <-> 9dB
Zaitsev 10:41552d038a69 71 * Entry 43 <-> +10dB
Zaitsev 10:41552d038a69 72 *
Zaitsev 10:41552d038a69 73 * Each entry is compound of 1 byte.
Zaitsev 10:41552d038a69 74 */
Zaitsev 10:41552d038a69 75
Zaitsev 10:41552d038a69 76 // RR: Making high side injection changes to RevD
Zaitsev 10:41552d038a69 77
Zaitsev 10:41552d038a69 78 /** This rf LUT is built for high side injection, using low side injection
Zaitsev 10:41552d038a69 79 * would requiere to change this LUT. */
Zaitsev 10:41552d038a69 80 const uint32_t rfLut[16][4] = {{0x50,0x00D4A7,0x4B,0x00A000},
Zaitsev 10:41552d038a69 81 {0x50,0x017F52,0x4B,0x014001},
Zaitsev 10:41552d038a69 82 {0x51,0xFE29FB,0x4B,0x01E001},
Zaitsev 10:41552d038a69 83 {0x51,0xFED4A6,0x4C,0xFE7FFF},
Zaitsev 10:41552d038a69 84 {0x51,0xFF7F51,0x4C,0xFF1FFF},
Zaitsev 10:41552d038a69 85 {0x51,0x0029FC,0x4C,0xFFC000},
Zaitsev 10:41552d038a69 86 {0x51,0x00D4A7,0x4C,0x006000},
Zaitsev 10:41552d038a69 87 {0x51,0x017F52,0x4C,0x010001},
Zaitsev 10:41552d038a69 88 {0x52,0xFE29FB,0x4C,0x01A001},
Zaitsev 10:41552d038a69 89 {0x52,0xFED4A6,0x4D,0xFE3FFF},
Zaitsev 10:41552d038a69 90 {0x52,0xFF7F51,0x4D,0xFEDFFF},
Zaitsev 10:41552d038a69 91 {0x52,0x0029FC,0x4D,0xFF8000},
Zaitsev 10:41552d038a69 92 {0x52,0x00D4A7,0x4D,0x002000},
Zaitsev 10:41552d038a69 93 {0x52,0x017F52,0x4D,0x00C001},
Zaitsev 10:41552d038a69 94 {0x53,0xFE29FB,0x4D,0x016001},
Zaitsev 10:41552d038a69 95 {0x53,0xFED4A6,0x4E,0xFDFFFE}
Zaitsev 10:41552d038a69 96 };
Zaitsev 10:41552d038a69 97
Zaitsev 10:41552d038a69 98 const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
Zaitsev 10:41552d038a69 99 0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
Zaitsev 10:41552d038a69 100 0,0,0,0,0,0,0,0,1,2, // -19dBm to -10dBm
Zaitsev 10:41552d038a69 101 3,4,5,6,7,8,9,10,11,12, // -9dBm to 0dBm
Zaitsev 10:41552d038a69 102 13,14,15,16,17,18,19,20,20,20
Zaitsev 10:41552d038a69 103 }; // +1dBm to +10 dBm
Zaitsev 10:41552d038a69 104
Zaitsev 10:41552d038a69 105 /*************************************************************************************************
Zaitsev 10:41552d038a69 106 * *
Zaitsev 10:41552d038a69 107 * Functions *
Zaitsev 10:41552d038a69 108 * *
Zaitsev 10:41552d038a69 109 *************************************************************************************************/
Zaitsev 10:41552d038a69 110
Zaitsev 10:41552d038a69 111 void fRfAnaInit()
Zaitsev 10:41552d038a69 112 {
Zaitsev 10:41552d038a69 113 // Enable rfana clock
Zaitsev 10:41552d038a69 114 CLOCK_ENABLE(CLOCK_RFANA);
Zaitsev 10:41552d038a69 115
Zaitsev 10:41552d038a69 116 // Set PLL timing
Zaitsev 10:41552d038a69 117 RFANAREG->PLL_TIMING.BITS.PLL_RESET_TIME = 0x1E; // 30us
Zaitsev 10:41552d038a69 118 RFANAREG->PLL_TIMING.BITS.PLL_LOCK_TIME = 0x2F; // 47us
Zaitsev 10:41552d038a69 119
Zaitsev 10:41552d038a69 120 // Set other parameters
Zaitsev 10:41552d038a69 121 RFANAREG->RX_CONTROL.BITS.LNA_GAIN_MODE = 0x1; // High Gain mode
Zaitsev 10:41552d038a69 122 RFANAREG->RX_CONTROL.BITS.ADC_DITHER_MODE = 0x0; // Dither mode disabled
Zaitsev 10:41552d038a69 123 }
Zaitsev 10:41552d038a69 124
Zaitsev 10:41552d038a69 125 boolean fRfAnaIoctl (uint32_t request, void *argument)
Zaitsev 10:41552d038a69 126 {
Zaitsev 10:41552d038a69 127 uint8_t channel, txPower;
Zaitsev 10:41552d038a69 128
Zaitsev 10:41552d038a69 129 // Enable rfana clock (in case fRfAnaIoctl is used before call of fRfAnaInit)
Zaitsev 10:41552d038a69 130 CLOCK_ENABLE(CLOCK_RFANA);
Zaitsev 10:41552d038a69 131
Zaitsev 10:41552d038a69 132 switch(request) {
Zaitsev 10:41552d038a69 133 case SET_RF_CHANNEL:
Zaitsev 10:41552d038a69 134 channel = *(uint8_t*)argument;
Zaitsev 10:41552d038a69 135
Zaitsev 10:41552d038a69 136 // Set tx/rx integer/fractional divide portions
Zaitsev 10:41552d038a69 137 RFANAREG->TX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][3];
Zaitsev 10:41552d038a69 138 RFANAREG->TX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][2];
Zaitsev 10:41552d038a69 139 RFANAREG->RX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][1];
Zaitsev 10:41552d038a69 140 RFANAREG->RX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][0];
Zaitsev 10:41552d038a69 141
Zaitsev 10:41552d038a69 142 // Set tx/rx vco trims
Zaitsev 10:41552d038a69 143 /** REVD is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
Zaitsev 10:41552d038a69 144 * from trims stored in dedicated registers available in digital.*/
Zaitsev 10:41552d038a69 145 if (channel < 19) {
Zaitsev 10:41552d038a69 146 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
Zaitsev 10:41552d038a69 147 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
Zaitsev 10:41552d038a69 148 } else {
Zaitsev 10:41552d038a69 149 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
Zaitsev 10:41552d038a69 150 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
Zaitsev 10:41552d038a69 151 }
Zaitsev 10:41552d038a69 152 break;
Zaitsev 10:41552d038a69 153 case SET_TX_POWER:
Zaitsev 10:41552d038a69 154 txPower = *(uint8_t*)argument;
Zaitsev 10:41552d038a69 155
Zaitsev 10:41552d038a69 156 // Set tx power register
Zaitsev 10:41552d038a69 157 if ((txPower & 0x20) == 0) {
Zaitsev 10:41552d038a69 158 RFANAREG->TX_POWER = (txPowerLut[txPower + 32] & 0xFF);
Zaitsev 10:41552d038a69 159 } else {
Zaitsev 10:41552d038a69 160 RFANAREG->TX_POWER = (txPowerLut[txPower - 32] & 0xFF);
Zaitsev 10:41552d038a69 161 }
Zaitsev 10:41552d038a69 162
Zaitsev 10:41552d038a69 163 break;
Zaitsev 10:41552d038a69 164 default:
Zaitsev 10:41552d038a69 165 return False;
Zaitsev 10:41552d038a69 166 }
Zaitsev 10:41552d038a69 167 return True;
Zaitsev 10:41552d038a69 168 }