Daniel Sygut / Application

lol

Dependencies:   MMA8451Q

Fork of Application by Mateusz Kowalik

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/objects.h@10:41552d038a69, 2017-01-10 (annotated)

Committer:
Zaitsev
Date:
Tue Jan 10 20:42:26 2017 +0000
Revision:
10:41552d038a69
USB Serial bi-directional bridge

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Zaitsev 10:41552d038a69 1 /**
Zaitsev 10:41552d038a69 2 ******************************************************************************
Zaitsev 10:41552d038a69 3 * @file Objects.h
Zaitsev 10:41552d038a69 4 * @brief Implements an assertion.
Zaitsev 10:41552d038a69 5 * @internal
Zaitsev 10:41552d038a69 6 * @author ON Semiconductor
Zaitsev 10:41552d038a69 7 * $Rev: 0.1 $
Zaitsev 10:41552d038a69 8 * $Date: 2015-11-06 $
Zaitsev 10:41552d038a69 9 ******************************************************************************
Zaitsev 10:41552d038a69 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
Zaitsev 10:41552d038a69 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
Zaitsev 10:41552d038a69 12 * under limited terms and conditions. The terms and conditions pertaining to the software
Zaitsev 10:41552d038a69 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
Zaitsev 10:41552d038a69 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
Zaitsev 10:41552d038a69 15 * if applicable the software license agreement. Do not use this software and/or
Zaitsev 10:41552d038a69 16 * documentation unless you have carefully read and you agree to the limited terms and
Zaitsev 10:41552d038a69 17 * conditions. By using this software and/or documentation, you agree to the limited
Zaitsev 10:41552d038a69 18 * terms and conditions.
Zaitsev 10:41552d038a69 19 *
Zaitsev 10:41552d038a69 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
Zaitsev 10:41552d038a69 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
Zaitsev 10:41552d038a69 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
Zaitsev 10:41552d038a69 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
Zaitsev 10:41552d038a69 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
Zaitsev 10:41552d038a69 25 * @endinternal
Zaitsev 10:41552d038a69 26 *
Zaitsev 10:41552d038a69 27 * @ingroup debug
Zaitsev 10:41552d038a69 28 */
Zaitsev 10:41552d038a69 29 #ifndef OBJECTS_H_
Zaitsev 10:41552d038a69 30 #define OBJECTS_H_
Zaitsev 10:41552d038a69 31
Zaitsev 10:41552d038a69 32
Zaitsev 10:41552d038a69 33 #ifdef __cplusplus
Zaitsev 10:41552d038a69 34 extern "C" {
Zaitsev 10:41552d038a69 35 #endif
Zaitsev 10:41552d038a69 36
Zaitsev 10:41552d038a69 37 #include "gpio_map.h"
Zaitsev 10:41552d038a69 38 #include "uart_16c550_map.h"
Zaitsev 10:41552d038a69 39 #include "PinNames.h"
Zaitsev 10:41552d038a69 40 #include "PortNames.h"
Zaitsev 10:41552d038a69 41 #include "PeripheralNames.h"
Zaitsev 10:41552d038a69 42 #include "target_config.h"
Zaitsev 10:41552d038a69 43 #include "spi.h"
Zaitsev 10:41552d038a69 44
Zaitsev 10:41552d038a69 45 typedef enum {
Zaitsev 10:41552d038a69 46 FlowControlNone_1,
Zaitsev 10:41552d038a69 47 FlowControlRTS_1,
Zaitsev 10:41552d038a69 48 FlowControlCTS_1,
Zaitsev 10:41552d038a69 49 FlowControlRTSCTS_1
Zaitsev 10:41552d038a69 50 } FlowControl_1;
Zaitsev 10:41552d038a69 51
Zaitsev 10:41552d038a69 52 struct serial_s {
Zaitsev 10:41552d038a69 53 Uart16C550Reg_pt UARTREG;
Zaitsev 10:41552d038a69 54 FlowControl_1 FlowCtrl;
Zaitsev 10:41552d038a69 55 IRQn_Type IRQType;
Zaitsev 10:41552d038a69 56 int index;
Zaitsev 10:41552d038a69 57 };
Zaitsev 10:41552d038a69 58
Zaitsev 10:41552d038a69 59 typedef struct _gpio_t {
Zaitsev 10:41552d038a69 60 GpioReg_pt GPIOMEMBASE;
Zaitsev 10:41552d038a69 61 PinName gpioPin;
Zaitsev 10:41552d038a69 62 uint32_t gpioMask;
Zaitsev 10:41552d038a69 63
Zaitsev 10:41552d038a69 64 } gpio_t;
Zaitsev 10:41552d038a69 65
Zaitsev 10:41552d038a69 66
Zaitsev 10:41552d038a69 67 /* TODO: This is currently a dummy structure; implementation will be done along
Zaitsev 10:41552d038a69 68 * with the sleep API implementation
Zaitsev 10:41552d038a69 69 */
Zaitsev 10:41552d038a69 70 typedef struct sleep_s {
Zaitsev 10:41552d038a69 71 uint32_t timeToSleep; /* 0: Use sleep type variable to select low power mode; Noz-zero: Selects sleep type based on timeToSleep duration using table 1. sleep below */
Zaitsev 10:41552d038a69 72 uint8_t SleepType; /* 0: Sleep; 1: DeepSleep; 2: Coma */
Zaitsev 10:41552d038a69 73 } sleep_t;
Zaitsev 10:41552d038a69 74
Zaitsev 10:41552d038a69 75 /* Table 1. Sleep
Zaitsev 10:41552d038a69 76 ___________________________________________________________________________________
Zaitsev 10:41552d038a69 77 | Sleep duration | Sleep Type |
Zaitsev 10:41552d038a69 78 |-------------------------------------------------------------------|---------------|
Zaitsev 10:41552d038a69 79 | > Zero AND <= SLEEP_DURATION_SLEEP_MAX | sleep |
Zaitsev 10:41552d038a69 80 | > SLEEP_DURATION_SLEEP_MAX AND <= SLEEP_DURATION_DEEPSLEEP_MAX | deepsleep |
Zaitsev 10:41552d038a69 81 | > SLEEP_DURATION_DEEPSLEEP_MAX | coma |
Zaitsev 10:41552d038a69 82 |___________________________________________________________________|_______________|
Zaitsev 10:41552d038a69 83
Zaitsev 10:41552d038a69 84 */
Zaitsev 10:41552d038a69 85
Zaitsev 10:41552d038a69 86 struct gpio_irq_s {
Zaitsev 10:41552d038a69 87 uint32_t pin;
Zaitsev 10:41552d038a69 88 uint32_t pinMask;
Zaitsev 10:41552d038a69 89 GpioReg_pt GPIOMEMBASE;
Zaitsev 10:41552d038a69 90 };
Zaitsev 10:41552d038a69 91
Zaitsev 10:41552d038a69 92 typedef struct {
Zaitsev 10:41552d038a69 93
Zaitsev 10:41552d038a69 94 /* options to configure the ADC */
Zaitsev 10:41552d038a69 95 uint8_t interruptConfig; /**< 1= interrupt Enable 0=Interrupt Disable */
Zaitsev 10:41552d038a69 96 uint8_t PrescaleVal; /**< Prescaler: Sets the converter clock frequency. Fclk = 32 MHz/(prescaler + 1) where prescaler is the value of this register segment. The minimum tested value is 07 (4 MHz clock) */
Zaitsev 10:41552d038a69 97 uint8_t measurementType; /**< 1= Absolute 0= Differential */
Zaitsev 10:41552d038a69 98 uint8_t mode; /**< 1= Continuous Conversion 0= Single Shot */
Zaitsev 10:41552d038a69 99 uint8_t referenceCh; /**< Selects 1 to 8 channels for reference channel */
Zaitsev 10:41552d038a69 100 uint8_t convCh; /**< Selects 1 or 8 channels to do a conversion on.*/
Zaitsev 10:41552d038a69 101 uint8_t inputScale; /**< Sets the input scale, 000 ? 1.0, 001 ? 0.6923, 010 ? 0.5294, 011 ? 0.4286, 100 ? 0.3600, 101 ? 0.3103, 110 ? 0.2728, 111 ? 0.2432 */
Zaitsev 10:41552d038a69 102 uint8_t samplingTime; /**< Sample Time. Sets the measure time in units of PCLKperiod * (Prescale + 1).*/
Zaitsev 10:41552d038a69 103 uint8_t WarmUpTime; /**< The number of converter clock cycles that the state machine dwells in the warm or warm_meas state */
Zaitsev 10:41552d038a69 104 uint16_t samplingRate; /**< Sets the sample rate in units of PCLKperiod * (Prescale + 1). */
Zaitsev 10:41552d038a69 105
Zaitsev 10:41552d038a69 106 } analog_config_s;
Zaitsev 10:41552d038a69 107
Zaitsev 10:41552d038a69 108 struct analogin_s {
Zaitsev 10:41552d038a69 109
Zaitsev 10:41552d038a69 110 analog_config_s *adcConf;
Zaitsev 10:41552d038a69 111 AdcReg_pt adcReg;
Zaitsev 10:41552d038a69 112 PinName pin;
Zaitsev 10:41552d038a69 113 uint8_t pinFlag;
Zaitsev 10:41552d038a69 114 uint32_t ADC_Offset_Value;
Zaitsev 10:41552d038a69 115 };
Zaitsev 10:41552d038a69 116
Zaitsev 10:41552d038a69 117 struct pwmout_s {
Zaitsev 10:41552d038a69 118
Zaitsev 10:41552d038a69 119 PwmReg_pt pwmReg;
Zaitsev 10:41552d038a69 120 };
Zaitsev 10:41552d038a69 121
Zaitsev 10:41552d038a69 122 struct port_s {
Zaitsev 10:41552d038a69 123 GpioReg_pt GPIOMEMBASE;
Zaitsev 10:41552d038a69 124 PortName port;
Zaitsev 10:41552d038a69 125 uint32_t mask;
Zaitsev 10:41552d038a69 126 };
Zaitsev 10:41552d038a69 127
Zaitsev 10:41552d038a69 128 typedef enum {
Zaitsev 10:41552d038a69 129 littleEndian = 0,
Zaitsev 10:41552d038a69 130 bigEndian
Zaitsev 10:41552d038a69 131 } spi_ipc7207_endian_t, *spi_ipc7207_endian_pt;
Zaitsev 10:41552d038a69 132
Zaitsev 10:41552d038a69 133 /** Type for the clock polarity. */
Zaitsev 10:41552d038a69 134 typedef enum {
Zaitsev 10:41552d038a69 135 activeLow = 0,
Zaitsev 10:41552d038a69 136 activeHigh
Zaitsev 10:41552d038a69 137 } spi_clockPolarity_t, *spi_clockPolarity_pt;
Zaitsev 10:41552d038a69 138
Zaitsev 10:41552d038a69 139 /** Type for the clock phase. */
Zaitsev 10:41552d038a69 140 typedef enum {
Zaitsev 10:41552d038a69 141 risingEdge = 0,
Zaitsev 10:41552d038a69 142 fallingEdge
Zaitsev 10:41552d038a69 143 } spi_clockPhase_t, *spi_clockPhase_pt;
Zaitsev 10:41552d038a69 144
Zaitsev 10:41552d038a69 145 struct spi_s {
Zaitsev 10:41552d038a69 146 SpiIpc7207Reg_pt membase; /* Register address */
Zaitsev 10:41552d038a69 147 IRQn_Type irq; /* IRQ number of the IRQ associated to the device. */
Zaitsev 10:41552d038a69 148 uint8_t irqEnable; /* IRQ enables for 8 IRQ sources:
Zaitsev 10:41552d038a69 149 * - bit 7 = Receive FIFO Full
Zaitsev 10:41552d038a69 150 * - bit 6 = Receive FIFO 'Half' Full (watermark level)
Zaitsev 10:41552d038a69 151 * - bit 5 = Receive FIFO Not Empty
Zaitsev 10:41552d038a69 152 * - bit 4 = Transmit FIFO Not Full
Zaitsev 10:41552d038a69 153 * - bit 3 = Transmit FIFO 'Half' Empty (watermark level)
Zaitsev 10:41552d038a69 154 * - bit 2 = Transmit FIFO Empty
Zaitsev 10:41552d038a69 155 * - bit 1 = Transfer Error
Zaitsev 10:41552d038a69 156 * - bit 0 = ssIn (conditionally inverted and synchronized to PCLK)
Zaitsev 10:41552d038a69 157 * (unused option in current implementation / irq 6 and 7 used) */
Zaitsev 10:41552d038a69 158 uint8_t slaveSelectEnable; /* Slave Select enables (x4):
Zaitsev 10:41552d038a69 159 * - 0 (x4) = Slave select enable
Zaitsev 10:41552d038a69 160 * - 1 (x4) = Slave select disable */
Zaitsev 10:41552d038a69 161 uint8_t slaveSelectBurst; /* Slave Select burst mode:
Zaitsev 10:41552d038a69 162 * - NO_BURST_MODE = Burst mode disable
Zaitsev 10:41552d038a69 163 * - BURST_MODE = Burst mode enable */
Zaitsev 10:41552d038a69 164 uint8_t slaveSelectPolarity; /* Slave Select polarity (x4) for up to 4 slaves:
Zaitsev 10:41552d038a69 165 * - 0 (x4) = Slave select is active low
Zaitsev 10:41552d038a69 166 * - 1 (x4) = Slave select is active high */
Zaitsev 10:41552d038a69 167 uint8_t txWatermark; /* Transmit FIFO Watermark: Defines level of RX Half Full Flag
Zaitsev 10:41552d038a69 168 * - Value between 1 and 15
Zaitsev 10:41552d038a69 169 * (unused option in current implementation / not txWatermark irq used) */
Zaitsev 10:41552d038a69 170 uint8_t rxWatermark; /* Receive FIFO Watermark: Defines level of TX Half Full Flag:
Zaitsev 10:41552d038a69 171 * - Value between 1 and 15
Zaitsev 10:41552d038a69 172 * * (unused option in current implementation / rxWatermark fixed to 1) */
Zaitsev 10:41552d038a69 173 spi_ipc7207_endian_t endian; /* Bits endianness:
Zaitsev 10:41552d038a69 174 * - LITTLE_ENDIAN = LSB first
Zaitsev 10:41552d038a69 175 * - BIG_ENDIAN = MSB first */
Zaitsev 10:41552d038a69 176 uint8_t samplingEdge; /* SDI sampling edge (relative to SDO sampling edge):
Zaitsev 10:41552d038a69 177 * - 0 = opposite to SDO sampling edge
Zaitsev 10:41552d038a69 178 * - 1 = same as SDO sampling edge */
Zaitsev 10:41552d038a69 179 uint32_t baudrate; /* The expected baud rate. */
Zaitsev 10:41552d038a69 180 spi_clockPolarity_t clockPolarity; /* The clock polarity (active high or low). */
Zaitsev 10:41552d038a69 181 spi_clockPhase_t clockPhase; /* The clock phase (sample on rising or falling edge). */
Zaitsev 10:41552d038a69 182 uint8_t wordSize; /* The size word size in number of bits. */
Zaitsev 10:41552d038a69 183 uint8_t Mode;
Zaitsev 10:41552d038a69 184 uint32_t event;
Zaitsev 10:41552d038a69 185 };
Zaitsev 10:41552d038a69 186
Zaitsev 10:41552d038a69 187 struct i2c_s {
Zaitsev 10:41552d038a69 188 uint32_t baudrate; /**< The expected baud rate. */
Zaitsev 10:41552d038a69 189 uint32_t I2cStatusFromInt;
Zaitsev 10:41552d038a69 190 uint8_t ClockSource; /**< I2C clock source, 0 – clkI2C pin, 1 – PCLK */
Zaitsev 10:41552d038a69 191 uint8_t irqEnable; /**< IRQs to be enabled */
Zaitsev 10:41552d038a69 192 I2cIpc7208Reg_pt membase; /**< The memory base for the device's registers. */
Zaitsev 10:41552d038a69 193 IRQn_Type irq; /**< The IRQ number of the IRQ associated to the device. */
Zaitsev 10:41552d038a69 194 //queue_pt rxQueue; /**< The receive queue for the device instance. */
Zaitsev 10:41552d038a69 195 };
Zaitsev 10:41552d038a69 196
Zaitsev 10:41552d038a69 197 struct trng_s {
Zaitsev 10:41552d038a69 198 RandReg_pt membase; /**< The memory base for the device's registers. */
Zaitsev 10:41552d038a69 199 };
Zaitsev 10:41552d038a69 200
Zaitsev 10:41552d038a69 201 #ifdef __cplusplus
Zaitsev 10:41552d038a69 202 }
Zaitsev 10:41552d038a69 203 #endif
Zaitsev 10:41552d038a69 204
Zaitsev 10:41552d038a69 205 #endif //OBJECTS_H_