Daniel Sygut / Application

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Dependencies:   MMA8451Q

Fork of Application by Mateusz Kowalik

mbed-dev/targets/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.c@10:41552d038a69, 2017-01-10 (annotated)

Committer:
Zaitsev
Date:
Tue Jan 10 20:42:26 2017 +0000
Revision:
10:41552d038a69
USB Serial bi-directional bridge

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Zaitsev 10:41552d038a69 1 /*******************************************************************************
Zaitsev 10:41552d038a69 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
Zaitsev 10:41552d038a69 3 *
Zaitsev 10:41552d038a69 4 * Permission is hereby granted, free of charge, to any person obtaining a
Zaitsev 10:41552d038a69 5 * copy of this software and associated documentation files (the "Software"),
Zaitsev 10:41552d038a69 6 * to deal in the Software without restriction, including without limitation
Zaitsev 10:41552d038a69 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Zaitsev 10:41552d038a69 8 * and/or sell copies of the Software, and to permit persons to whom the
Zaitsev 10:41552d038a69 9 * Software is furnished to do so, subject to the following conditions:
Zaitsev 10:41552d038a69 10 *
Zaitsev 10:41552d038a69 11 * The above copyright notice and this permission notice shall be included
Zaitsev 10:41552d038a69 12 * in all copies or substantial portions of the Software.
Zaitsev 10:41552d038a69 13 *
Zaitsev 10:41552d038a69 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Zaitsev 10:41552d038a69 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Zaitsev 10:41552d038a69 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Zaitsev 10:41552d038a69 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Zaitsev 10:41552d038a69 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Zaitsev 10:41552d038a69 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Zaitsev 10:41552d038a69 20 * OTHER DEALINGS IN THE SOFTWARE.
Zaitsev 10:41552d038a69 21 *
Zaitsev 10:41552d038a69 22 * Except as contained in this notice, the name of Maxim Integrated
Zaitsev 10:41552d038a69 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Zaitsev 10:41552d038a69 24 * Products, Inc. Branding Policy.
Zaitsev 10:41552d038a69 25 *
Zaitsev 10:41552d038a69 26 * The mere transfer of this software does not imply any licenses
Zaitsev 10:41552d038a69 27 * of trade secrets, proprietary technology, copyrights, patents,
Zaitsev 10:41552d038a69 28 * trademarks, maskwork rights, or any other form of intellectual
Zaitsev 10:41552d038a69 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
Zaitsev 10:41552d038a69 30 * ownership rights.
Zaitsev 10:41552d038a69 31 *******************************************************************************
Zaitsev 10:41552d038a69 32 */
Zaitsev 10:41552d038a69 33
Zaitsev 10:41552d038a69 34 #include "device.h"
Zaitsev 10:41552d038a69 35 #include "PeripheralPins.h"
Zaitsev 10:41552d038a69 36 #include "ioman_regs.h"
Zaitsev 10:41552d038a69 37
Zaitsev 10:41552d038a69 38 /*
Zaitsev 10:41552d038a69 39 * To select a peripheral function on Maxim microcontrollers, multiple
Zaitsev 10:41552d038a69 40 * configurations must be made. The mbed PinMap structure only includes one
Zaitsev 10:41552d038a69 41 * data member to hold this information. To extend the configuration storage,
Zaitsev 10:41552d038a69 42 * the "function" data member is used as a pointer to a pin_function_t
Zaitsev 10:41552d038a69 43 * structure. This structure is defined in objects.h. The definitions below
Zaitsev 10:41552d038a69 44 * include the creation of the pin_function_t structures and the assignment of
Zaitsev 10:41552d038a69 45 * the pointers to the "function" data members.
Zaitsev 10:41552d038a69 46 */
Zaitsev 10:41552d038a69 47
Zaitsev 10:41552d038a69 48 #ifdef TOOLCHAIN_ARM_STD
Zaitsev 10:41552d038a69 49 #pragma diag_suppress 1296
Zaitsev 10:41552d038a69 50 #endif
Zaitsev 10:41552d038a69 51
Zaitsev 10:41552d038a69 52 /************I2C***************/
Zaitsev 10:41552d038a69 53 const PinMap PinMap_I2C_SDA[] = {
Zaitsev 10:41552d038a69 54 { P0_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev 10:41552d038a69 55 { P0_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_H | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev 10:41552d038a69 56 { NC, NC, 0 }
Zaitsev 10:41552d038a69 57 };
Zaitsev 10:41552d038a69 58
Zaitsev 10:41552d038a69 59 const PinMap PinMap_I2C_SCL[] = {
Zaitsev 10:41552d038a69 60 { P0_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev 10:41552d038a69 61 { P0_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_H | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev 10:41552d038a69 62 { NC, NC, 0 }
Zaitsev 10:41552d038a69 63 };
Zaitsev 10:41552d038a69 64
Zaitsev 10:41552d038a69 65 /************UART***************/
Zaitsev 10:41552d038a69 66 const PinMap PinMap_UART_TX[] = {
Zaitsev 10:41552d038a69 67 { P1_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev 10:41552d038a69 68 { P1_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev 10:41552d038a69 69 { P2_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev 10:41552d038a69 70 { P2_5, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev 10:41552d038a69 71 { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev 10:41552d038a69 72 { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev 10:41552d038a69 73 { NC, NC, 0 }
Zaitsev 10:41552d038a69 74 };
Zaitsev 10:41552d038a69 75
Zaitsev 10:41552d038a69 76 const PinMap PinMap_UART_RX[] = {
Zaitsev 10:41552d038a69 77 { P1_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev 10:41552d038a69 78 { P1_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev 10:41552d038a69 79 { P2_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev 10:41552d038a69 80 { P2_4, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev 10:41552d038a69 81 { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev 10:41552d038a69 82 { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev 10:41552d038a69 83 { NC, NC, 0 }
Zaitsev 10:41552d038a69 84 };
Zaitsev 10:41552d038a69 85
Zaitsev 10:41552d038a69 86 const PinMap PinMap_UART_CTS[] = {
Zaitsev 10:41552d038a69 87 { P1_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
Zaitsev 10:41552d038a69 88 { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
Zaitsev 10:41552d038a69 89 { P2_4, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
Zaitsev 10:41552d038a69 90 { P2_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
Zaitsev 10:41552d038a69 91 { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
Zaitsev 10:41552d038a69 92 { NC, NC, 0 }
Zaitsev 10:41552d038a69 93 };
Zaitsev 10:41552d038a69 94
Zaitsev 10:41552d038a69 95 const PinMap PinMap_UART_RTS[] = {
Zaitsev 10:41552d038a69 96 { P1_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
Zaitsev 10:41552d038a69 97 { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
Zaitsev 10:41552d038a69 98 { P2_5, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
Zaitsev 10:41552d038a69 99 { P2_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
Zaitsev 10:41552d038a69 100 { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
Zaitsev 10:41552d038a69 101 { NC, NC, 0 }
Zaitsev 10:41552d038a69 102 };
Zaitsev 10:41552d038a69 103
Zaitsev 10:41552d038a69 104 /************SPI***************/
Zaitsev 10:41552d038a69 105 const PinMap PinMap_SPI_SCLK[] = {
Zaitsev 10:41552d038a69 106 { P0_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev 10:41552d038a69 107 { P2_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev 10:41552d038a69 108 { NC, NC, 0}
Zaitsev 10:41552d038a69 109 };
Zaitsev 10:41552d038a69 110
Zaitsev 10:41552d038a69 111 const PinMap PinMap_SPI_MOSI[] = {
Zaitsev 10:41552d038a69 112 { P0_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev 10:41552d038a69 113 { P2_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev 10:41552d038a69 114 { NC, NC, 0}
Zaitsev 10:41552d038a69 115 };
Zaitsev 10:41552d038a69 116
Zaitsev 10:41552d038a69 117 const PinMap PinMap_SPI_MISO[] = {
Zaitsev 10:41552d038a69 118 { P0_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev 10:41552d038a69 119 { P2_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev 10:41552d038a69 120 { NC, NC, 0}
Zaitsev 10:41552d038a69 121 };
Zaitsev 10:41552d038a69 122
Zaitsev 10:41552d038a69 123 const PinMap PinMap_SPI_SSEL[] = {
Zaitsev 10:41552d038a69 124 { P0_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
Zaitsev 10:41552d038a69 125 { P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO)}) },
Zaitsev 10:41552d038a69 126 { NC, NC, 0}
Zaitsev 10:41552d038a69 127 };
Zaitsev 10:41552d038a69 128
Zaitsev 10:41552d038a69 129 /************PWM***************/
Zaitsev 10:41552d038a69 130 const PinMap PinMap_PWM[] = {
Zaitsev 10:41552d038a69 131 {P0_0, PWM_0, 1}, {P0_0, PWM_0, 2}, {P0_0, PWM_4, 3},
Zaitsev 10:41552d038a69 132 {P0_1, PWM_1, 1}, {P0_1, PWM_4, 2}, {P0_1, PWM_0, 3},
Zaitsev 10:41552d038a69 133 {P0_2, PWM_2, 1}, {P0_2, PWM_1, 2}, {P0_2, PWM_5, 3},
Zaitsev 10:41552d038a69 134 {P0_3, PWM_3, 1}, {P0_3, PWM_5, 2}, {P0_3, PWM_1, 3},
Zaitsev 10:41552d038a69 135 {P0_4, PWM_4, 1}, {P0_4, PWM_2, 2}, {P0_4, PWM_6, 3},
Zaitsev 10:41552d038a69 136 {P0_5, PWM_5, 1}, {P0_5, PWM_6, 2}, {P0_5, PWM_2, 3},
Zaitsev 10:41552d038a69 137 {P0_6, PWM_6, 1}, {P0_6, PWM_3, 2}, {P0_6, PWM_7, 3},
Zaitsev 10:41552d038a69 138 {P0_7, PWM_7, 1}, {P0_7, PWM_7, 2}, {P0_7, PWM_3, 3},
Zaitsev 10:41552d038a69 139
Zaitsev 10:41552d038a69 140 {P1_0, PWM_0, 1}, {P1_0, PWM_0, 2}, {P1_0, PWM_4, 3},
Zaitsev 10:41552d038a69 141 {P1_1, PWM_1, 1}, {P1_1, PWM_4, 2}, {P1_1, PWM_0, 3},
Zaitsev 10:41552d038a69 142 {P1_2, PWM_2, 1}, {P1_2, PWM_1, 2}, {P1_2, PWM_5, 3},
Zaitsev 10:41552d038a69 143 {P1_3, PWM_3, 1}, {P1_3, PWM_5, 2}, {P1_3, PWM_1, 3},
Zaitsev 10:41552d038a69 144 {P1_4, PWM_4, 1}, {P1_4, PWM_2, 2}, {P1_4, PWM_6, 3},
Zaitsev 10:41552d038a69 145 {P1_5, PWM_5, 1}, {P1_5, PWM_6, 2}, {P1_5, PWM_2, 3},
Zaitsev 10:41552d038a69 146 {P1_6, PWM_6, 1}, {P1_6, PWM_3, 2}, {P1_6, PWM_7, 3},
Zaitsev 10:41552d038a69 147 {P1_7, PWM_7, 1}, {P1_7, PWM_7, 2}, {P1_7, PWM_3, 3},
Zaitsev 10:41552d038a69 148
Zaitsev 10:41552d038a69 149 {P2_0, PWM_0, 1}, {P2_0, PWM_0, 2}, {P2_0, PWM_4, 3},
Zaitsev 10:41552d038a69 150 {P2_1, PWM_1, 1}, {P2_1, PWM_4, 2}, {P2_1, PWM_0, 3},
Zaitsev 10:41552d038a69 151 {P2_2, PWM_2, 1}, {P2_2, PWM_1, 2}, {P2_2, PWM_5, 3},
Zaitsev 10:41552d038a69 152 {P2_3, PWM_3, 1}, {P2_3, PWM_5, 2}, {P2_3, PWM_1, 3},
Zaitsev 10:41552d038a69 153 {P2_4, PWM_4, 1}, {P2_4, PWM_2, 2}, {P2_4, PWM_6, 3},
Zaitsev 10:41552d038a69 154 {P2_5, PWM_5, 1}, {P2_5, PWM_6, 2}, {P2_5, PWM_2, 3},
Zaitsev 10:41552d038a69 155 {P2_6, PWM_6, 1}, {P2_6, PWM_3, 2}, {P2_6, PWM_7, 3},
Zaitsev 10:41552d038a69 156 {P2_7, PWM_7, 1}, {P2_7, PWM_7, 2}, {P2_7, PWM_3, 3},
Zaitsev 10:41552d038a69 157
Zaitsev 10:41552d038a69 158 {NC, NC, 0}
Zaitsev 10:41552d038a69 159 };
Zaitsev 10:41552d038a69 160
Zaitsev 10:41552d038a69 161 /************ADC***************/
Zaitsev 10:41552d038a69 162 const PinMap PinMap_ADC[] = {
Zaitsev 10:41552d038a69 163 {AIN_0P, ADC, 0},
Zaitsev 10:41552d038a69 164 {AIN_1P, ADC, 0},
Zaitsev 10:41552d038a69 165 {AIN_2P, ADC, 0},
Zaitsev 10:41552d038a69 166 {AIN_3P, ADC, 0},
Zaitsev 10:41552d038a69 167 {AIN_4P, ADC, 0},
Zaitsev 10:41552d038a69 168 {AIN_5P, ADC, 0},
Zaitsev 10:41552d038a69 169 {AIN_0N, ADC, 0},
Zaitsev 10:41552d038a69 170 {AIN_1N, ADC, 0},
Zaitsev 10:41552d038a69 171 {AIN_2N, ADC, 0},
Zaitsev 10:41552d038a69 172 {AIN_3N, ADC, 0},
Zaitsev 10:41552d038a69 173 {AIN_4N, ADC, 0},
Zaitsev 10:41552d038a69 174 {AIN_5N, ADC, 0},
Zaitsev 10:41552d038a69 175 {AIN_0D, ADC, 1},
Zaitsev 10:41552d038a69 176 {AIN_1D, ADC, 1},
Zaitsev 10:41552d038a69 177 {AIN_2D, ADC, 1},
Zaitsev 10:41552d038a69 178 {AIN_3D, ADC, 1},
Zaitsev 10:41552d038a69 179 {AIN_4D, ADC, 1},
Zaitsev 10:41552d038a69 180 {AIN_5D, ADC, 1},
Zaitsev 10:41552d038a69 181 {NC, NC, 0}
Zaitsev 10:41552d038a69 182 };
Zaitsev 10:41552d038a69 183
Zaitsev 10:41552d038a69 184 /************DAC***************/
Zaitsev 10:41552d038a69 185 const PinMap PinMap_DAC[] = {
Zaitsev 10:41552d038a69 186 {AOUT_AO, DAC0, 0},
Zaitsev 10:41552d038a69 187 {AOUT_BO, DAC1, 0},
Zaitsev 10:41552d038a69 188 {AOUT_CO, DAC2, 0},
Zaitsev 10:41552d038a69 189 {AOUT_DO, DAC3, 0},
Zaitsev 10:41552d038a69 190 {NC, NC, 0}
Zaitsev 10:41552d038a69 191 };