Daniel Sygut / Application

lol

Dependencies:   MMA8451Q

Fork of Application by Mateusz Kowalik

mbed-dev/targets/TARGET_Maxim/TARGET_MAX32610/sleep.c@12:3a30cdffa27c, 2018-01-21 (annotated)

Committer:
danix
Date:
Sun Jan 21 22:28:30 2018 +0000
Revision:
12:3a30cdffa27c
Parent:
10:41552d038a69 
Working acelerometer and mouse

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Zaitsev 10:41552d038a69 1 /*******************************************************************************
Zaitsev 10:41552d038a69 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
Zaitsev 10:41552d038a69 3 *
Zaitsev 10:41552d038a69 4 * Permission is hereby granted, free of charge, to any person obtaining a
Zaitsev 10:41552d038a69 5 * copy of this software and associated documentation files (the "Software"),
Zaitsev 10:41552d038a69 6 * to deal in the Software without restriction, including without limitation
Zaitsev 10:41552d038a69 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Zaitsev 10:41552d038a69 8 * and/or sell copies of the Software, and to permit persons to whom the
Zaitsev 10:41552d038a69 9 * Software is furnished to do so, subject to the following conditions:
Zaitsev 10:41552d038a69 10 *
Zaitsev 10:41552d038a69 11 * The above copyright notice and this permission notice shall be included
Zaitsev 10:41552d038a69 12 * in all copies or substantial portions of the Software.
Zaitsev 10:41552d038a69 13 *
Zaitsev 10:41552d038a69 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Zaitsev 10:41552d038a69 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Zaitsev 10:41552d038a69 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Zaitsev 10:41552d038a69 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Zaitsev 10:41552d038a69 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Zaitsev 10:41552d038a69 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Zaitsev 10:41552d038a69 20 * OTHER DEALINGS IN THE SOFTWARE.
Zaitsev 10:41552d038a69 21 *
Zaitsev 10:41552d038a69 22 * Except as contained in this notice, the name of Maxim Integrated
Zaitsev 10:41552d038a69 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Zaitsev 10:41552d038a69 24 * Products, Inc. Branding Policy.
Zaitsev 10:41552d038a69 25 *
Zaitsev 10:41552d038a69 26 * The mere transfer of this software does not imply any licenses
Zaitsev 10:41552d038a69 27 * of trade secrets, proprietary technology, copyrights, patents,
Zaitsev 10:41552d038a69 28 * trademarks, maskwork rights, or any other form of intellectual
Zaitsev 10:41552d038a69 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
Zaitsev 10:41552d038a69 30 * ownership rights.
Zaitsev 10:41552d038a69 31 *******************************************************************************
Zaitsev 10:41552d038a69 32 */
Zaitsev 10:41552d038a69 33
Zaitsev 10:41552d038a69 34 #include "sleep_api.h"
Zaitsev 10:41552d038a69 35 #include "cmsis.h"
Zaitsev 10:41552d038a69 36 #include "pwrman_regs.h"
Zaitsev 10:41552d038a69 37 #include "pwrseq_regs.h"
Zaitsev 10:41552d038a69 38 #include "ioman_regs.h"
Zaitsev 10:41552d038a69 39 #include "rtc_regs.h"
Zaitsev 10:41552d038a69 40
Zaitsev 10:41552d038a69 41 static mxc_uart_regs_t *stdio_uart = (mxc_uart_regs_t*)STDIO_UART;
Zaitsev 10:41552d038a69 42
Zaitsev 10:41552d038a69 43 // Normal wait mode
Zaitsev 10:41552d038a69 44 void sleep(void)
Zaitsev 10:41552d038a69 45 {
Zaitsev 10:41552d038a69 46 // Normal sleep mode for ARM core
Zaitsev 10:41552d038a69 47 SCB->SCR = 0;
Zaitsev 10:41552d038a69 48
Zaitsev 10:41552d038a69 49 __DSB();
Zaitsev 10:41552d038a69 50 __WFI();
Zaitsev 10:41552d038a69 51 }
Zaitsev 10:41552d038a69 52
Zaitsev 10:41552d038a69 53 // Work-around for issue of clearing power sequencer I/O flag
Zaitsev 10:41552d038a69 54 static void clearAllGPIOWUD(void)
Zaitsev 10:41552d038a69 55 {
Zaitsev 10:41552d038a69 56 uint32_t wud_req0 = MXC_IOMAN->wud_req0;
Zaitsev 10:41552d038a69 57 uint32_t wud_req1 = MXC_IOMAN->wud_req1;
Zaitsev 10:41552d038a69 58
Zaitsev 10:41552d038a69 59 // I/O must be a wakeup detect to clear
Zaitsev 10:41552d038a69 60 MXC_IOMAN->wud_req0 = 0xffffffff;
Zaitsev 10:41552d038a69 61 MXC_IOMAN->wud_req1 = 0xffffffff;
Zaitsev 10:41552d038a69 62
Zaitsev 10:41552d038a69 63 // Clear all WUDs
Zaitsev 10:41552d038a69 64 MXC_PWRMAN->wud_ctrl = (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS) | MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL;
Zaitsev 10:41552d038a69 65 MXC_PWRMAN->wud_pulse0 = 1;
Zaitsev 10:41552d038a69 66
Zaitsev 10:41552d038a69 67 // Restore WUD requests
Zaitsev 10:41552d038a69 68 MXC_IOMAN->wud_req0 = wud_req0;
Zaitsev 10:41552d038a69 69 MXC_IOMAN->wud_req1 = wud_req1;
Zaitsev 10:41552d038a69 70 }
Zaitsev 10:41552d038a69 71
Zaitsev 10:41552d038a69 72 // Low-power stop mode
Zaitsev 10:41552d038a69 73 void deepsleep(void)
Zaitsev 10:41552d038a69 74 {
Zaitsev 10:41552d038a69 75 __disable_irq();
Zaitsev 10:41552d038a69 76
Zaitsev 10:41552d038a69 77 // Wait for all STDIO characters to be sent. The UART clock will stop.
Zaitsev 10:41552d038a69 78 while (stdio_uart->status & MXC_F_UART_STATUS_TX_BUSY);
Zaitsev 10:41552d038a69 79
Zaitsev 10:41552d038a69 80 // Prepare for LP1
Zaitsev 10:41552d038a69 81 uint32_t reg0 = MXC_PWRSEQ->reg0;
Zaitsev 10:41552d038a69 82 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP; // disable VDD3 SVM during sleep mode
Zaitsev 10:41552d038a69 83 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP; // disable VREG18 SVM during sleep mode
Zaitsev 10:41552d038a69 84 if (reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN) { // if real-time clock enabled during run
Zaitsev 10:41552d038a69 85 reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // enable real-time clock during sleep mode
Zaitsev 10:41552d038a69 86 } else {
Zaitsev 10:41552d038a69 87 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // disable real-time clock during sleep mode
Zaitsev 10:41552d038a69 88 }
Zaitsev 10:41552d038a69 89 reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP; // enable CHZY regulator during sleep mode
Zaitsev 10:41552d038a69 90 reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1; // go into LP1
Zaitsev 10:41552d038a69 91 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT; // clear first boot flag
Zaitsev 10:41552d038a69 92 MXC_PWRSEQ->reg0 = reg0;
Zaitsev 10:41552d038a69 93
Zaitsev 10:41552d038a69 94 MXC_PWRSEQ->reg3 = (MXC_PWRSEQ->reg3 & ~MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK) | (3 << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS);
Zaitsev 10:41552d038a69 95
Zaitsev 10:41552d038a69 96 // Deep sleep for ARM core
Zaitsev 10:41552d038a69 97 SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
Zaitsev 10:41552d038a69 98
Zaitsev 10:41552d038a69 99 // clear latches for wakeup detect
Zaitsev 10:41552d038a69 100 MXC_PWRSEQ->flags = MXC_PWRSEQ->flags;
Zaitsev 10:41552d038a69 101 if (MXC_PWRSEQ->flags & MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP) {
Zaitsev 10:41552d038a69 102 // attempt work-around for I/O flag clearing issue
Zaitsev 10:41552d038a69 103 clearAllGPIOWUD();
Zaitsev 10:41552d038a69 104 MXC_PWRSEQ->flags = MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP;
Zaitsev 10:41552d038a69 105 }
Zaitsev 10:41552d038a69 106
Zaitsev 10:41552d038a69 107 // Wait for pending RTC transaction
Zaitsev 10:41552d038a69 108 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
Zaitsev 10:41552d038a69 109
Zaitsev 10:41552d038a69 110 // Ensure that the event register is clear
Zaitsev 10:41552d038a69 111 __SEV(); // set event
Zaitsev 10:41552d038a69 112 __WFE(); // clear event
Zaitsev 10:41552d038a69 113
Zaitsev 10:41552d038a69 114 // Enter LP1
Zaitsev 10:41552d038a69 115 __WFE();
Zaitsev 10:41552d038a69 116 // Woke up from LP1
Zaitsev 10:41552d038a69 117
Zaitsev 10:41552d038a69 118 // The RTC timer does not update until the next tick
Zaitsev 10:41552d038a69 119 uint32_t temp = MXC_RTCTMR->timer;
Zaitsev 10:41552d038a69 120 while (MXC_RTCTMR->timer == temp);
Zaitsev 10:41552d038a69 121
Zaitsev 10:41552d038a69 122 __enable_irq();
Zaitsev 10:41552d038a69 123 }