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Fork of Application by Mateusz Kowalik

mbed-dev/targets/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.c@12:3a30cdffa27c, 2018-01-21 (annotated)

Committer:: danix
Date:: Sun Jan 21 22:28:30 2018 +0000
Revision:: 12:3a30cdffa27c
Parent:: 10:41552d038a69

Working acelerometer and mouse

Who changed what in which revision?

User	Revision	Line number	New contents of line
Zaitsev	10:41552d038a69	1	/*******************************************************************************
Zaitsev	10:41552d038a69	2	* Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
Zaitsev	10:41552d038a69	3	*
Zaitsev	10:41552d038a69	4	* Permission is hereby granted, free of charge, to any person obtaining a
Zaitsev	10:41552d038a69	5	* copy of this software and associated documentation files (the "Software"),
Zaitsev	10:41552d038a69	6	* to deal in the Software without restriction, including without limitation
Zaitsev	10:41552d038a69	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
Zaitsev	10:41552d038a69	8	* and/or sell copies of the Software, and to permit persons to whom the
Zaitsev	10:41552d038a69	9	* Software is furnished to do so, subject to the following conditions:
Zaitsev	10:41552d038a69	10	*
Zaitsev	10:41552d038a69	11	* The above copyright notice and this permission notice shall be included
Zaitsev	10:41552d038a69	12	* in all copies or substantial portions of the Software.
Zaitsev	10:41552d038a69	13	*
Zaitsev	10:41552d038a69	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Zaitsev	10:41552d038a69	15	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Zaitsev	10:41552d038a69	16	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Zaitsev	10:41552d038a69	17	* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Zaitsev	10:41552d038a69	18	* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Zaitsev	10:41552d038a69	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Zaitsev	10:41552d038a69	20	* OTHER DEALINGS IN THE SOFTWARE.
Zaitsev	10:41552d038a69	21	*
Zaitsev	10:41552d038a69	22	* Except as contained in this notice, the name of Maxim Integrated
Zaitsev	10:41552d038a69	23	* Products, Inc. shall not be used except as stated in the Maxim Integrated
Zaitsev	10:41552d038a69	24	* Products, Inc. Branding Policy.
Zaitsev	10:41552d038a69	25	*
Zaitsev	10:41552d038a69	26	* The mere transfer of this software does not imply any licenses
Zaitsev	10:41552d038a69	27	* of trade secrets, proprietary technology, copyrights, patents,
Zaitsev	10:41552d038a69	28	* trademarks, maskwork rights, or any other form of intellectual
Zaitsev	10:41552d038a69	29	* property whatsoever. Maxim Integrated Products, Inc. retains all
Zaitsev	10:41552d038a69	30	* ownership rights.
Zaitsev	10:41552d038a69	31	*******************************************************************************
Zaitsev	10:41552d038a69	32	*/
Zaitsev	10:41552d038a69	33
Zaitsev	10:41552d038a69	34	#include "device.h"
Zaitsev	10:41552d038a69	35	#include "PeripheralPins.h"
Zaitsev	10:41552d038a69	36	#include "ioman_regs.h"
Zaitsev	10:41552d038a69	37
Zaitsev	10:41552d038a69	38	/*
Zaitsev	10:41552d038a69	39	* To select a peripheral function on Maxim microcontrollers, multiple
Zaitsev	10:41552d038a69	40	* configurations must be made. The mbed PinMap structure only includes one
Zaitsev	10:41552d038a69	41	* data member to hold this information. To extend the configuration storage,
Zaitsev	10:41552d038a69	42	* the "function" data member is used as a pointer to a pin_function_t
Zaitsev	10:41552d038a69	43	* structure. This structure is defined in objects.h. The definitions below
Zaitsev	10:41552d038a69	44	* include the creation of the pin_function_t structures and the assignment of
Zaitsev	10:41552d038a69	45	* the pointers to the "function" data members.
Zaitsev	10:41552d038a69	46	*/
Zaitsev	10:41552d038a69	47
Zaitsev	10:41552d038a69	48	#ifdef TOOLCHAIN_ARM_STD
Zaitsev	10:41552d038a69	49	#pragma diag_suppress 1296
Zaitsev	10:41552d038a69	50	#endif
Zaitsev	10:41552d038a69	51
Zaitsev	10:41552d038a69	52	/**********I2C*************/
Zaitsev	10:41552d038a69	53	const PinMap PinMap_I2C_SDA[] = {
Zaitsev	10:41552d038a69	54	{ P2_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING \| MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev	10:41552d038a69	55	{ P2_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING \| MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev	10:41552d038a69	56	{ P1_6, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING \| MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev	10:41552d038a69	57	{ P2_2, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING \| MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev	10:41552d038a69	58	{ P7_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING \| MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev	10:41552d038a69	59	{ P7_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING \| MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev	10:41552d038a69	60	{ P7_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING \| MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev	10:41552d038a69	61	{ P7_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING \| MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev	10:41552d038a69	62	{ P0_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D \| MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING \| MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev	10:41552d038a69	63	{ P0_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D \| MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING \| MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev	10:41552d038a69	64	{ NC, NC, 0 }
Zaitsev	10:41552d038a69	65	};
Zaitsev	10:41552d038a69	66
Zaitsev	10:41552d038a69	67	const PinMap PinMap_I2C_SCL[] = {
Zaitsev	10:41552d038a69	68	{ P2_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING \| MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev	10:41552d038a69	69	{ P2_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING \| MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev	10:41552d038a69	70	{ P1_7, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING \| MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev	10:41552d038a69	71	{ P2_3, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING \| MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev	10:41552d038a69	72	{ P7_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING \| MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev	10:41552d038a69	73	{ P7_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING \| MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev	10:41552d038a69	74	{ P7_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING \| MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev	10:41552d038a69	75	{ P7_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING \| MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev	10:41552d038a69	76	{ P0_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D \| MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING \| MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev	10:41552d038a69	77	{ P0_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D \| MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING \| MXC_F_IOMAN_I2CM_CORE_IO)}) },
Zaitsev	10:41552d038a69	78	{ NC, NC, 0 }
Zaitsev	10:41552d038a69	79	};
Zaitsev	10:41552d038a69	80
Zaitsev	10:41552d038a69	81	/**********UART*************/
Zaitsev	10:41552d038a69	82	const PinMap PinMap_UART_TX[] = {
Zaitsev	10:41552d038a69	83	{ P1_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev	10:41552d038a69	84	{ P1_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev	10:41552d038a69	85	{ P2_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev	10:41552d038a69	86	{ P2_5, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev	10:41552d038a69	87	{ P7_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev	10:41552d038a69	88	{ P7_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev	10:41552d038a69	89	{ P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D \| MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev	10:41552d038a69	90	{ P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D \| MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev	10:41552d038a69	91	{ NC, NC, 0 }
Zaitsev	10:41552d038a69	92	};
Zaitsev	10:41552d038a69	93
Zaitsev	10:41552d038a69	94	const PinMap PinMap_UART_RX[] = {
Zaitsev	10:41552d038a69	95	{ P1_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev	10:41552d038a69	96	{ P1_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev	10:41552d038a69	97	{ P2_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev	10:41552d038a69	98	{ P2_4, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev	10:41552d038a69	99	{ P7_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev	10:41552d038a69	100	{ P7_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev	10:41552d038a69	101	{ P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D \| MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev	10:41552d038a69	102	{ P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D \| MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CORE_IO)}) },
Zaitsev	10:41552d038a69	103	{ NC, NC, 0 }
Zaitsev	10:41552d038a69	104	};
Zaitsev	10:41552d038a69	105
Zaitsev	10:41552d038a69	106	const PinMap PinMap_UART_CTS[] = {
Zaitsev	10:41552d038a69	107	{ P1_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CTS_IO)}) },
Zaitsev	10:41552d038a69	108	{ P2_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CTS_IO)}) },
Zaitsev	10:41552d038a69	109	{ P1_4, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CTS_IO)}) },
Zaitsev	10:41552d038a69	110	{ P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CTS_IO)}) },
Zaitsev	10:41552d038a69	111	{ P7_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CTS_IO)}) },
Zaitsev	10:41552d038a69	112	{ P7_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CTS_IO)}) },
Zaitsev	10:41552d038a69	113	{ P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D \| MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_CTS_IO)}) },
Zaitsev	10:41552d038a69	114	{ NC, NC, 0 }
Zaitsev	10:41552d038a69	115	};
Zaitsev	10:41552d038a69	116
Zaitsev	10:41552d038a69	117	const PinMap PinMap_UART_RTS[] = {
Zaitsev	10:41552d038a69	118	{ P1_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_RTS_IO)}) },
Zaitsev	10:41552d038a69	119	{ P2_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_RTS_IO)}) },
Zaitsev	10:41552d038a69	120	{ P1_5, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_RTS_IO)}) },
Zaitsev	10:41552d038a69	121	{ P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_RTS_IO)}) },
Zaitsev	10:41552d038a69	122	{ P7_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_RTS_IO)}) },
Zaitsev	10:41552d038a69	123	{ P7_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_RTS_IO)}) },
Zaitsev	10:41552d038a69	124	{ P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D \| MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING \| MXC_F_IOMAN_UART_RTS_IO)}) },
Zaitsev	10:41552d038a69	125	{ NC, NC, 0 }
Zaitsev	10:41552d038a69	126	};
Zaitsev	10:41552d038a69	127
Zaitsev	10:41552d038a69	128	/**********SPI*************/
Zaitsev	10:41552d038a69	129	const PinMap PinMap_SPI_SCLK[] = {
Zaitsev	10:41552d038a69	130	{ P0_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	131	{ P0_4, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	132	{ P2_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	133	{ P1_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	134	{ P2_4, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	135	{ P2_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	136	{ P6_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	137	{ P6_4, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	138	{ NC, NC, 0}
Zaitsev	10:41552d038a69	139	};
Zaitsev	10:41552d038a69	140
Zaitsev	10:41552d038a69	141	const PinMap PinMap_SPI_MOSI[] = {
Zaitsev	10:41552d038a69	142	{ P0_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	143	{ P0_5, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	144	{ P2_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	145	{ P1_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	146	{ P2_5, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	147	{ P2_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	148	{ P6_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	149	{ P6_5, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	150	{ NC, NC, 0}
Zaitsev	10:41552d038a69	151	};
Zaitsev	10:41552d038a69	152
Zaitsev	10:41552d038a69	153	const PinMap PinMap_SPI_MISO[] = {
Zaitsev	10:41552d038a69	154	{ P0_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	155	{ P0_6, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	156	{ P2_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	157	{ P1_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	158	{ P2_6, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	159	{ P2_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	160	{ P6_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	161	{ P6_6, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_CORE_IO)}) },
Zaitsev	10:41552d038a69	162	{ NC, NC, 0}
Zaitsev	10:41552d038a69	163	};
Zaitsev	10:41552d038a69	164
Zaitsev	10:41552d038a69	165	const PinMap PinMap_SPI_SSEL[] = {
Zaitsev	10:41552d038a69	166	#if (defined(EM9301_CSN) && (EM9301_CSN == P0_3))
Zaitsev	10:41552d038a69	167	{ P0_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_SPI_SS0_IO \| MXC_F_IOMAN_SPI_SR0_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_SS0_IO \| MXC_F_IOMAN_SPI_SR0_IO)}) },
Zaitsev	10:41552d038a69	168	#else
Zaitsev	10:41552d038a69	169	{ P0_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_SS0_IO)}) },
Zaitsev	10:41552d038a69	170	#endif
Zaitsev	10:41552d038a69	171	{ P0_7, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_SS0_IO)}) },
Zaitsev	10:41552d038a69	172	{ P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_SS0_IO)}) },
Zaitsev	10:41552d038a69	173	{ P1_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_SS0_IO)}) },
Zaitsev	10:41552d038a69	174	{ P2_7, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_SS0_IO)}) },
Zaitsev	10:41552d038a69	175	#if (defined(EM9301_CSN) && (EM9301_CSN == P2_3))
Zaitsev	10:41552d038a69	176	{ P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A \| MXC_F_IOMAN_SPI_SS0_IO \| MXC_F_IOMAN_SPI_SR0_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_SS0_IO \| MXC_F_IOMAN_SPI_SR0_IO)}) },
Zaitsev	10:41552d038a69	177	#else
Zaitsev	10:41552d038a69	178	{ P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B \| MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_SS0_IO)}) },
Zaitsev	10:41552d038a69	179	#endif
Zaitsev	10:41552d038a69	180	{ P6_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_SS0_IO)}) },
Zaitsev	10:41552d038a69	181	{ P6_7, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C \| MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING \| MXC_F_IOMAN_SPI_SS0_IO)}) },
Zaitsev	10:41552d038a69	182	{ NC, NC, 0}
Zaitsev	10:41552d038a69	183	};
Zaitsev	10:41552d038a69	184
Zaitsev	10:41552d038a69	185	/**********PWM*************/
Zaitsev	10:41552d038a69	186	const PinMap PinMap_PWM[] = {
Zaitsev	10:41552d038a69	187	{P0_0, PWM_0, 1}, {P0_0, PWM_0, 2}, {P0_0, PWM_4, 3},
Zaitsev	10:41552d038a69	188	{P0_1, PWM_1, 1}, {P0_1, PWM_4, 2}, {P0_1, PWM_0, 3},
Zaitsev	10:41552d038a69	189	{P0_2, PWM_2, 1}, {P0_2, PWM_1, 2}, {P0_2, PWM_5, 3},
Zaitsev	10:41552d038a69	190	{P0_3, PWM_3, 1}, {P0_3, PWM_5, 2}, {P0_3, PWM_1, 3},
Zaitsev	10:41552d038a69	191	{P0_4, PWM_4, 1}, {P0_4, PWM_2, 2}, {P0_4, PWM_6, 3},
Zaitsev	10:41552d038a69	192	{P0_5, PWM_5, 1}, {P0_5, PWM_6, 2}, {P0_5, PWM_2, 3},
Zaitsev	10:41552d038a69	193	{P0_6, PWM_6, 1}, {P0_6, PWM_3, 2}, {P0_6, PWM_7, 3},
Zaitsev	10:41552d038a69	194	{P0_7, PWM_7, 1}, {P0_7, PWM_7, 2}, {P0_7, PWM_3, 3},
Zaitsev	10:41552d038a69	195
Zaitsev	10:41552d038a69	196	{P1_0, PWM_0, 1}, {P1_0, PWM_0, 2}, {P1_0, PWM_4, 3},
Zaitsev	10:41552d038a69	197	{P1_1, PWM_1, 1}, {P1_1, PWM_4, 2}, {P1_1, PWM_0, 3},
Zaitsev	10:41552d038a69	198	{P1_2, PWM_2, 1}, {P1_2, PWM_1, 2}, {P1_2, PWM_5, 3},
Zaitsev	10:41552d038a69	199	{P1_3, PWM_3, 1}, {P1_3, PWM_5, 2}, {P1_3, PWM_1, 3},
Zaitsev	10:41552d038a69	200	{P1_4, PWM_4, 1}, {P1_4, PWM_2, 2}, {P1_4, PWM_6, 3},
Zaitsev	10:41552d038a69	201	{P1_5, PWM_5, 1}, {P1_5, PWM_6, 2}, {P1_5, PWM_2, 3},
Zaitsev	10:41552d038a69	202	{P1_6, PWM_6, 1}, {P1_6, PWM_3, 2}, {P1_6, PWM_7, 3},
Zaitsev	10:41552d038a69	203	{P1_7, PWM_7, 1}, {P1_7, PWM_7, 2}, {P1_7, PWM_3, 3},
Zaitsev	10:41552d038a69	204
Zaitsev	10:41552d038a69	205	{P2_0, PWM_0, 1}, {P2_0, PWM_0, 2}, {P2_0, PWM_4, 3},
Zaitsev	10:41552d038a69	206	{P2_1, PWM_1, 1}, {P2_1, PWM_4, 2}, {P2_1, PWM_0, 3},
Zaitsev	10:41552d038a69	207	{P2_2, PWM_2, 1}, {P2_2, PWM_1, 2}, {P2_2, PWM_5, 3},
Zaitsev	10:41552d038a69	208	{P2_3, PWM_3, 1}, {P2_3, PWM_5, 2}, {P2_3, PWM_1, 3},
Zaitsev	10:41552d038a69	209	{P2_4, PWM_4, 1}, {P2_4, PWM_2, 2}, {P2_4, PWM_6, 3},
Zaitsev	10:41552d038a69	210	{P2_5, PWM_5, 1}, {P2_5, PWM_6, 2}, {P2_5, PWM_2, 3},
Zaitsev	10:41552d038a69	211	{P2_6, PWM_6, 1}, {P2_6, PWM_3, 2}, {P2_6, PWM_7, 3},
Zaitsev	10:41552d038a69	212	{P2_7, PWM_7, 1}, {P2_7, PWM_7, 2}, {P2_7, PWM_3, 3},
Zaitsev	10:41552d038a69	213
Zaitsev	10:41552d038a69	214	{P6_0, PWM_0, 1}, {P6_0, PWM_0, 2}, {P6_0, PWM_4, 3},
Zaitsev	10:41552d038a69	215	{P6_1, PWM_1, 1}, {P6_1, PWM_4, 2}, {P6_1, PWM_0, 3},
Zaitsev	10:41552d038a69	216	{P6_2, PWM_2, 1}, {P6_2, PWM_1, 2}, {P6_2, PWM_5, 3},
Zaitsev	10:41552d038a69	217	{P6_3, PWM_3, 1}, {P6_3, PWM_5, 2}, {P6_3, PWM_1, 3},
Zaitsev	10:41552d038a69	218	{P6_4, PWM_4, 1}, {P6_4, PWM_2, 2}, {P6_4, PWM_6, 3},
Zaitsev	10:41552d038a69	219	{P6_5, PWM_5, 1}, {P6_5, PWM_6, 2}, {P6_5, PWM_2, 3},
Zaitsev	10:41552d038a69	220	{P6_6, PWM_6, 1}, {P6_6, PWM_3, 2}, {P6_6, PWM_7, 3},
Zaitsev	10:41552d038a69	221	{P6_7, PWM_7, 1}, {P6_7, PWM_7, 2}, {P6_7, PWM_3, 3},
Zaitsev	10:41552d038a69	222
Zaitsev	10:41552d038a69	223	{P7_0, PWM_0, 1}, {P7_0, PWM_0, 2}, {P7_0, PWM_4, 3},
Zaitsev	10:41552d038a69	224	{P7_1, PWM_1, 1}, {P7_1, PWM_4, 2}, {P7_1, PWM_0, 3},
Zaitsev	10:41552d038a69	225	{P7_2, PWM_2, 1}, {P7_2, PWM_1, 2}, {P7_2, PWM_5, 3},
Zaitsev	10:41552d038a69	226	{P7_3, PWM_3, 1}, {P7_3, PWM_5, 2}, {P7_3, PWM_1, 3},
Zaitsev	10:41552d038a69	227	{P7_4, PWM_4, 1}, {P7_4, PWM_2, 2}, {P7_4, PWM_6, 3},
Zaitsev	10:41552d038a69	228	{P7_5, PWM_5, 1}, {P7_5, PWM_6, 2}, {P7_5, PWM_2, 3},
Zaitsev	10:41552d038a69	229	{P7_6, PWM_6, 1}, {P7_6, PWM_3, 2}, {P7_6, PWM_7, 3},
Zaitsev	10:41552d038a69	230	{P7_7, PWM_7, 1}, {P7_7, PWM_7, 2}, {P7_7, PWM_3, 3},
Zaitsev	10:41552d038a69	231
Zaitsev	10:41552d038a69	232	{NC, NC, 0}
Zaitsev	10:41552d038a69	233	};
Zaitsev	10:41552d038a69	234
Zaitsev	10:41552d038a69	235	/**********ADC*************/
Zaitsev	10:41552d038a69	236	const PinMap PinMap_ADC[] = {
Zaitsev	10:41552d038a69	237	{AIN_0P, ADC, 0},
Zaitsev	10:41552d038a69	238	{AIN_1P, ADC, 0},
Zaitsev	10:41552d038a69	239	{AIN_2P, ADC, 0},
Zaitsev	10:41552d038a69	240	{AIN_3P, ADC, 0},
Zaitsev	10:41552d038a69	241	{AIN_4P, ADC, 0},
Zaitsev	10:41552d038a69	242	{AIN_5P, ADC, 0},
Zaitsev	10:41552d038a69	243	{AIN_6P, ADC, 0},
Zaitsev	10:41552d038a69	244	{AIN_7P, ADC, 0},
Zaitsev	10:41552d038a69	245
Zaitsev	10:41552d038a69	246	{AIN_0N, ADC, 0},
Zaitsev	10:41552d038a69	247	{AIN_1N, ADC, 0},
Zaitsev	10:41552d038a69	248	{AIN_2N, ADC, 0},
Zaitsev	10:41552d038a69	249	{AIN_3N, ADC, 0},
Zaitsev	10:41552d038a69	250	{AIN_4N, ADC, 0},
Zaitsev	10:41552d038a69	251	{AIN_5N, ADC, 0},
Zaitsev	10:41552d038a69	252	{AIN_6N, ADC, 0},
Zaitsev	10:41552d038a69	253	{AIN_7N, ADC, 0},
Zaitsev	10:41552d038a69	254
Zaitsev	10:41552d038a69	255	{AIN_0D, ADC, 1},
Zaitsev	10:41552d038a69	256	{AIN_1D, ADC, 1},
Zaitsev	10:41552d038a69	257	{AIN_2D, ADC, 1},
Zaitsev	10:41552d038a69	258	{AIN_3D, ADC, 1},
Zaitsev	10:41552d038a69	259	{AIN_4D, ADC, 1},
Zaitsev	10:41552d038a69	260	{AIN_5D, ADC, 1},
Zaitsev	10:41552d038a69	261	{AIN_6D, ADC, 1},
Zaitsev	10:41552d038a69	262	{AIN_7D, ADC, 1},
Zaitsev	10:41552d038a69	263	{NC, NC, 0}
Zaitsev	10:41552d038a69	264	};
Zaitsev	10:41552d038a69	265
Zaitsev	10:41552d038a69	266	/**********DAC*************/
Zaitsev	10:41552d038a69	267	const PinMap PinMap_DAC[] = {
Zaitsev	10:41552d038a69	268	{AOUT_AO, DAC0, 0},
Zaitsev	10:41552d038a69	269	{AOUT_BO, DAC1, 0},
Zaitsev	10:41552d038a69	270	{AOUT_CO, DAC2, 0},
Zaitsev	10:41552d038a69	271	{AOUT_DO, DAC3, 0},
Zaitsev	10:41552d038a69	272	{NC, NC, 0}
Zaitsev	10:41552d038a69	273	};

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Type:	Program
Created:	21 Jan 2018
Imports:	2
Forks:	1
Commits:	13
Dependents:	0
Dependencies:	1
Followers:	1

The code in this repository is Apache licensed.

mbed-dev/targets/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.c@12:3a30cdffa27c, 2018-01-21 (annotated)

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