Daniel Sygut / Application

lol

Dependencies:   MMA8451Q

Fork of Application by Mateusz Kowalik

mbed-dev/targets/TARGET_Freescale/TARGET_K20XX/sleep.c@12:3a30cdffa27c, 2018-01-21 (annotated)

Committer:
danix
Date:
Sun Jan 21 22:28:30 2018 +0000
Revision:
12:3a30cdffa27c
Parent:
10:41552d038a69 
Working acelerometer and mouse

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Zaitsev 10:41552d038a69 1 /* mbed Microcontroller Library
Zaitsev 10:41552d038a69 2 * Copyright (c) 2006-2015 ARM Limited
Zaitsev 10:41552d038a69 3 *
Zaitsev 10:41552d038a69 4 * Licensed under the Apache License, Version 2.0 (the "License");
Zaitsev 10:41552d038a69 5 * you may not use this file except in compliance with the License.
Zaitsev 10:41552d038a69 6 * You may obtain a copy of the License at
Zaitsev 10:41552d038a69 7 *
Zaitsev 10:41552d038a69 8 * http://www.apache.org/licenses/LICENSE-2.0
Zaitsev 10:41552d038a69 9 *
Zaitsev 10:41552d038a69 10 * Unless required by applicable law or agreed to in writing, software
Zaitsev 10:41552d038a69 11 * distributed under the License is distributed on an "AS IS" BASIS,
Zaitsev 10:41552d038a69 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Zaitsev 10:41552d038a69 13 * See the License for the specific language governing permissions and
Zaitsev 10:41552d038a69 14 * limitations under the License.
Zaitsev 10:41552d038a69 15 */
Zaitsev 10:41552d038a69 16 #include "sleep_api.h"
Zaitsev 10:41552d038a69 17 #include "cmsis.h"
Zaitsev 10:41552d038a69 18
Zaitsev 10:41552d038a69 19 //Normal wait mode
Zaitsev 10:41552d038a69 20 void sleep(void)
Zaitsev 10:41552d038a69 21 {
Zaitsev 10:41552d038a69 22 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
Zaitsev 10:41552d038a69 23
Zaitsev 10:41552d038a69 24 //Normal sleep mode for ARM core:
Zaitsev 10:41552d038a69 25 SCB->SCR = 0;
Zaitsev 10:41552d038a69 26 __WFI();
Zaitsev 10:41552d038a69 27 }
Zaitsev 10:41552d038a69 28
Zaitsev 10:41552d038a69 29 //Very low-power stop mode
Zaitsev 10:41552d038a69 30 void deepsleep(void)
Zaitsev 10:41552d038a69 31 {
Zaitsev 10:41552d038a69 32 //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
Zaitsev 10:41552d038a69 33 uint8_t ADC_HSC = 0;
Zaitsev 10:41552d038a69 34 if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) {
Zaitsev 10:41552d038a69 35 if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) {
Zaitsev 10:41552d038a69 36 ADC_HSC = 1;
Zaitsev 10:41552d038a69 37 ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK);
Zaitsev 10:41552d038a69 38 }
Zaitsev 10:41552d038a69 39 }
Zaitsev 10:41552d038a69 40
Zaitsev 10:41552d038a69 41 //Check if PLL/FLL is enabled:
Zaitsev 10:41552d038a69 42 uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
Zaitsev 10:41552d038a69 43
Zaitsev 10:41552d038a69 44 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
Zaitsev 10:41552d038a69 45 SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
Zaitsev 10:41552d038a69 46
Zaitsev 10:41552d038a69 47 //Deep sleep for ARM core:
Zaitsev 10:41552d038a69 48 SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos;
Zaitsev 10:41552d038a69 49
Zaitsev 10:41552d038a69 50 __WFI();
Zaitsev 10:41552d038a69 51 //Switch back to PLL as clock source if needed
Zaitsev 10:41552d038a69 52 //The interrupt that woke up the device will run at reduced speed
Zaitsev 10:41552d038a69 53 if (PLL_FLL_en) {
Zaitsev 10:41552d038a69 54
Zaitsev 10:41552d038a69 55 #if defined (TARGET_K20D50M)
Zaitsev 10:41552d038a69 56 if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */
Zaitsev 10:41552d038a69 57 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */
Zaitsev 10:41552d038a69 58 MCG->C1 &= ~MCG_C1_CLKS_MASK;
Zaitsev 10:41552d038a69 59 #else
Zaitsev 10:41552d038a69 60 // MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0
Zaitsev 10:41552d038a69 61 MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
Zaitsev 10:41552d038a69 62 // MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0
Zaitsev 10:41552d038a69 63 MCG->C6 = MCG_C6_VDIV0(0);
Zaitsev 10:41552d038a69 64 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } // Check that the oscillator is running
Zaitsev 10:41552d038a69 65 while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
Zaitsev 10:41552d038a69 66 // MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3
Zaitsev 10:41552d038a69 67 MCG->C5 = MCG_C5_PRDIV0(5);
Zaitsev 10:41552d038a69 68 // MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3
Zaitsev 10:41552d038a69 69 MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3);
Zaitsev 10:41552d038a69 70 while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
Zaitsev 10:41552d038a69 71 while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } // Wait until the source of the PLLS clock has switched to the PLL
Zaitsev 10:41552d038a69 72 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
Zaitsev 10:41552d038a69 73 // MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0
Zaitsev 10:41552d038a69 74 MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;;
Zaitsev 10:41552d038a69 75 while((MCG->S & 0x0Cu) != 0x0Cu) { } // Wait until output of the PLL is selected
Zaitsev 10:41552d038a69 76 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
Zaitsev 10:41552d038a69 77 #endif
Zaitsev 10:41552d038a69 78 }
Zaitsev 10:41552d038a69 79
Zaitsev 10:41552d038a69 80 if (ADC_HSC) {
Zaitsev 10:41552d038a69 81 ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK);
Zaitsev 10:41552d038a69 82 }
Zaitsev 10:41552d038a69 83 }