joey shelton / LED_Demo2

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Dependencies:   MAX44000 PWM_Tone_Library nexpaq_mdk

Fork of LED_Demo by joey shelton

mbd_os/hal/common/SPI.cpp@9:6bb35cef007d, 2016-10-22 (annotated)

Committer:
cyberjoey
Date:
Sat Oct 22 01:31:58 2016 +0000
Revision:
9:6bb35cef007d
Parent:
1:55a6170b404f 
WORKING

Who changed what in which revision?

UserRevisionLine numberNew contents of line
nexpaq 1:55a6170b404f 1 /* mbed Microcontroller Library
nexpaq 1:55a6170b404f 2 * Copyright (c) 2006-2013 ARM Limited
nexpaq 1:55a6170b404f 3 *
nexpaq 1:55a6170b404f 4 * Licensed under the Apache License, Version 2.0 (the "License");
nexpaq 1:55a6170b404f 5 * you may not use this file except in compliance with the License.
nexpaq 1:55a6170b404f 6 * You may obtain a copy of the License at
nexpaq 1:55a6170b404f 7 *
nexpaq 1:55a6170b404f 8 * http://www.apache.org/licenses/LICENSE-2.0
nexpaq 1:55a6170b404f 9 *
nexpaq 1:55a6170b404f 10 * Unless required by applicable law or agreed to in writing, software
nexpaq 1:55a6170b404f 11 * distributed under the License is distributed on an "AS IS" BASIS,
nexpaq 1:55a6170b404f 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
nexpaq 1:55a6170b404f 13 * See the License for the specific language governing permissions and
nexpaq 1:55a6170b404f 14 * limitations under the License.
nexpaq 1:55a6170b404f 15 */
nexpaq 1:55a6170b404f 16 #include "SPI.h"
nexpaq 1:55a6170b404f 17 #include "critical.h"
nexpaq 1:55a6170b404f 18
nexpaq 1:55a6170b404f 19 #if DEVICE_SPI
nexpaq 1:55a6170b404f 20
nexpaq 1:55a6170b404f 21 namespace mbed {
nexpaq 1:55a6170b404f 22
nexpaq 1:55a6170b404f 23 #if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI
nexpaq 1:55a6170b404f 24 CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer;
nexpaq 1:55a6170b404f 25 #endif
nexpaq 1:55a6170b404f 26
nexpaq 1:55a6170b404f 27 SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
nexpaq 1:55a6170b404f 28 _spi(),
nexpaq 1:55a6170b404f 29 #if DEVICE_SPI_ASYNCH
nexpaq 1:55a6170b404f 30 _irq(this),
nexpaq 1:55a6170b404f 31 _usage(DMA_USAGE_NEVER),
nexpaq 1:55a6170b404f 32 #endif
nexpaq 1:55a6170b404f 33 _bits(8),
nexpaq 1:55a6170b404f 34 _mode(0),
nexpaq 1:55a6170b404f 35 _hz(1000000) {
nexpaq 1:55a6170b404f 36 // No lock needed in the constructor
nexpaq 1:55a6170b404f 37
nexpaq 1:55a6170b404f 38 spi_init(&_spi, mosi, miso, sclk, ssel);
nexpaq 1:55a6170b404f 39 aquire();
nexpaq 1:55a6170b404f 40 }
nexpaq 1:55a6170b404f 41
nexpaq 1:55a6170b404f 42 void SPI::format(int bits, int mode) {
nexpaq 1:55a6170b404f 43 lock();
nexpaq 1:55a6170b404f 44 _bits = bits;
nexpaq 1:55a6170b404f 45 _mode = mode;
nexpaq 1:55a6170b404f 46 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
nexpaq 1:55a6170b404f 47 aquire();
nexpaq 1:55a6170b404f 48 unlock();
nexpaq 1:55a6170b404f 49 }
nexpaq 1:55a6170b404f 50
nexpaq 1:55a6170b404f 51 void SPI::frequency(int hz) {
nexpaq 1:55a6170b404f 52 lock();
nexpaq 1:55a6170b404f 53 _hz = hz;
nexpaq 1:55a6170b404f 54 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
nexpaq 1:55a6170b404f 55 aquire();
nexpaq 1:55a6170b404f 56 unlock();
nexpaq 1:55a6170b404f 57 }
nexpaq 1:55a6170b404f 58
nexpaq 1:55a6170b404f 59 SPI* SPI::_owner = NULL;
nexpaq 1:55a6170b404f 60 SingletonPtr<PlatformMutex> SPI::_mutex;
nexpaq 1:55a6170b404f 61
nexpaq 1:55a6170b404f 62 // ignore the fact there are multiple physical spis, and always update if it wasnt us last
nexpaq 1:55a6170b404f 63 void SPI::aquire() {
nexpaq 1:55a6170b404f 64 lock();
nexpaq 1:55a6170b404f 65 if (_owner != this) {
nexpaq 1:55a6170b404f 66 spi_format(&_spi, _bits, _mode, 0);
nexpaq 1:55a6170b404f 67 spi_frequency(&_spi, _hz);
nexpaq 1:55a6170b404f 68 _owner = this;
nexpaq 1:55a6170b404f 69 }
nexpaq 1:55a6170b404f 70 unlock();
nexpaq 1:55a6170b404f 71 }
nexpaq 1:55a6170b404f 72
nexpaq 1:55a6170b404f 73 int SPI::write(int value) {
nexpaq 1:55a6170b404f 74 lock();
nexpaq 1:55a6170b404f 75 aquire();
nexpaq 1:55a6170b404f 76 int ret = spi_master_write(&_spi, value);
nexpaq 1:55a6170b404f 77 unlock();
nexpaq 1:55a6170b404f 78 return ret;
nexpaq 1:55a6170b404f 79 }
nexpaq 1:55a6170b404f 80
nexpaq 1:55a6170b404f 81 void SPI::lock() {
nexpaq 1:55a6170b404f 82 _mutex->lock();
nexpaq 1:55a6170b404f 83 }
nexpaq 1:55a6170b404f 84
nexpaq 1:55a6170b404f 85 void SPI::unlock() {
nexpaq 1:55a6170b404f 86 _mutex->unlock();
nexpaq 1:55a6170b404f 87 }
nexpaq 1:55a6170b404f 88
nexpaq 1:55a6170b404f 89 #if DEVICE_SPI_ASYNCH
nexpaq 1:55a6170b404f 90
nexpaq 1:55a6170b404f 91 int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
nexpaq 1:55a6170b404f 92 {
nexpaq 1:55a6170b404f 93 if (spi_active(&_spi)) {
nexpaq 1:55a6170b404f 94 return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
nexpaq 1:55a6170b404f 95 }
nexpaq 1:55a6170b404f 96 start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
nexpaq 1:55a6170b404f 97 return 0;
nexpaq 1:55a6170b404f 98 }
nexpaq 1:55a6170b404f 99
nexpaq 1:55a6170b404f 100 void SPI::abort_transfer()
nexpaq 1:55a6170b404f 101 {
nexpaq 1:55a6170b404f 102 spi_abort_asynch(&_spi);
nexpaq 1:55a6170b404f 103 #if TRANSACTION_QUEUE_SIZE_SPI
nexpaq 1:55a6170b404f 104 dequeue_transaction();
nexpaq 1:55a6170b404f 105 #endif
nexpaq 1:55a6170b404f 106 }
nexpaq 1:55a6170b404f 107
nexpaq 1:55a6170b404f 108
nexpaq 1:55a6170b404f 109 void SPI::clear_transfer_buffer()
nexpaq 1:55a6170b404f 110 {
nexpaq 1:55a6170b404f 111 #if TRANSACTION_QUEUE_SIZE_SPI
nexpaq 1:55a6170b404f 112 _transaction_buffer.reset();
nexpaq 1:55a6170b404f 113 #endif
nexpaq 1:55a6170b404f 114 }
nexpaq 1:55a6170b404f 115
nexpaq 1:55a6170b404f 116 void SPI::abort_all_transfers()
nexpaq 1:55a6170b404f 117 {
nexpaq 1:55a6170b404f 118 clear_transfer_buffer();
nexpaq 1:55a6170b404f 119 abort_transfer();
nexpaq 1:55a6170b404f 120 }
nexpaq 1:55a6170b404f 121
nexpaq 1:55a6170b404f 122 int SPI::set_dma_usage(DMAUsage usage)
nexpaq 1:55a6170b404f 123 {
nexpaq 1:55a6170b404f 124 if (spi_active(&_spi)) {
nexpaq 1:55a6170b404f 125 return -1;
nexpaq 1:55a6170b404f 126 }
nexpaq 1:55a6170b404f 127 _usage = usage;
nexpaq 1:55a6170b404f 128 return 0;
nexpaq 1:55a6170b404f 129 }
nexpaq 1:55a6170b404f 130
nexpaq 1:55a6170b404f 131 int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
nexpaq 1:55a6170b404f 132 {
nexpaq 1:55a6170b404f 133 #if TRANSACTION_QUEUE_SIZE_SPI
nexpaq 1:55a6170b404f 134 transaction_t t;
nexpaq 1:55a6170b404f 135
nexpaq 1:55a6170b404f 136 t.tx_buffer = const_cast<void *>(tx_buffer);
nexpaq 1:55a6170b404f 137 t.tx_length = tx_length;
nexpaq 1:55a6170b404f 138 t.rx_buffer = rx_buffer;
nexpaq 1:55a6170b404f 139 t.rx_length = rx_length;
nexpaq 1:55a6170b404f 140 t.event = event;
nexpaq 1:55a6170b404f 141 t.callback = callback;
nexpaq 1:55a6170b404f 142 t.width = bit_width;
nexpaq 1:55a6170b404f 143 Transaction<SPI> transaction(this, t);
nexpaq 1:55a6170b404f 144 if (_transaction_buffer.full()) {
nexpaq 1:55a6170b404f 145 return -1; // the buffer is full
nexpaq 1:55a6170b404f 146 } else {
nexpaq 1:55a6170b404f 147 core_util_critical_section_enter();
nexpaq 1:55a6170b404f 148 _transaction_buffer.push(transaction);
nexpaq 1:55a6170b404f 149 if (!spi_active(&_spi)) {
nexpaq 1:55a6170b404f 150 dequeue_transaction();
nexpaq 1:55a6170b404f 151 }
nexpaq 1:55a6170b404f 152 core_util_critical_section_exit();
nexpaq 1:55a6170b404f 153 return 0;
nexpaq 1:55a6170b404f 154 }
nexpaq 1:55a6170b404f 155 #else
nexpaq 1:55a6170b404f 156 return -1;
nexpaq 1:55a6170b404f 157 #endif
nexpaq 1:55a6170b404f 158 }
nexpaq 1:55a6170b404f 159
nexpaq 1:55a6170b404f 160 void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
nexpaq 1:55a6170b404f 161 {
nexpaq 1:55a6170b404f 162 aquire();
nexpaq 1:55a6170b404f 163 _callback = callback;
nexpaq 1:55a6170b404f 164 _irq.callback(&SPI::irq_handler_asynch);
nexpaq 1:55a6170b404f 165 spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage);
nexpaq 1:55a6170b404f 166 }
nexpaq 1:55a6170b404f 167
nexpaq 1:55a6170b404f 168 #if TRANSACTION_QUEUE_SIZE_SPI
nexpaq 1:55a6170b404f 169
nexpaq 1:55a6170b404f 170 void SPI::start_transaction(transaction_t *data)
nexpaq 1:55a6170b404f 171 {
nexpaq 1:55a6170b404f 172 start_transfer(data->tx_buffer, data->tx_length, data->rx_buffer, data->rx_length, data->width, data->callback, data->event);
nexpaq 1:55a6170b404f 173 }
nexpaq 1:55a6170b404f 174
nexpaq 1:55a6170b404f 175 void SPI::dequeue_transaction()
nexpaq 1:55a6170b404f 176 {
nexpaq 1:55a6170b404f 177 Transaction<SPI> t;
nexpaq 1:55a6170b404f 178 if (_transaction_buffer.pop(t)) {
nexpaq 1:55a6170b404f 179 SPI* obj = t.get_object();
nexpaq 1:55a6170b404f 180 transaction_t* data = t.get_transaction();
nexpaq 1:55a6170b404f 181 obj->start_transaction(data);
nexpaq 1:55a6170b404f 182 }
nexpaq 1:55a6170b404f 183 }
nexpaq 1:55a6170b404f 184
nexpaq 1:55a6170b404f 185 #endif
nexpaq 1:55a6170b404f 186
nexpaq 1:55a6170b404f 187 void SPI::irq_handler_asynch(void)
nexpaq 1:55a6170b404f 188 {
nexpaq 1:55a6170b404f 189 int event = spi_irq_handler_asynch(&_spi);
nexpaq 1:55a6170b404f 190 if (_callback && (event & SPI_EVENT_ALL)) {
nexpaq 1:55a6170b404f 191 _callback.call(event & SPI_EVENT_ALL);
nexpaq 1:55a6170b404f 192 }
nexpaq 1:55a6170b404f 193 #if TRANSACTION_QUEUE_SIZE_SPI
nexpaq 1:55a6170b404f 194 if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) {
nexpaq 1:55a6170b404f 195 // SPI peripheral is free (event happend), dequeue transaction
nexpaq 1:55a6170b404f 196 dequeue_transaction();
nexpaq 1:55a6170b404f 197 }
nexpaq 1:55a6170b404f 198 #endif
nexpaq 1:55a6170b404f 199 }
nexpaq 1:55a6170b404f 200
nexpaq 1:55a6170b404f 201 #endif
nexpaq 1:55a6170b404f 202
nexpaq 1:55a6170b404f 203 } // namespace mbed
nexpaq 1:55a6170b404f 204
nexpaq 1:55a6170b404f 205 #endif