Ljubivoj Cvitas / Mbed 2 deprecated ANDROIC

Završni rad Androić H most upravljan MBED-om

Dependencies:   mbed

main.cpp@1:a09621d44b14, 2015-05-12 (annotated)

Committer:
cvitas
Date:
Tue May 12 19:31:21 2015 +0000
Revision:
1:a09621d44b14
Parent:
0:ce1da5b1e608
Child:
2:9500cf2f8f8b
V2

Who changed what in which revision?

UserRevisionLine numberNew contents of line
cvitas 0:ce1da5b1e608 1 #include "mbed.h"
cvitas 0:ce1da5b1e608 2
cvitas 1:a09621d44b14 3 //DigitalOut OUT_A(p21);
cvitas 1:a09621d44b14 4 //DigitalOut OUT_B(p22);
cvitas 1:a09621d44b14 5 PwmOut OUT_A(p21);
cvitas 1:a09621d44b14 6 PwmOut OUT_B(p22);
cvitas 1:a09621d44b14 7
cvitas 0:ce1da5b1e608 8
cvitas 0:ce1da5b1e608 9 int main() {
cvitas 1:a09621d44b14 10
cvitas 1:a09621d44b14 11 OUT_A.period(0.010); // set PWM period to 10 ms
cvitas 1:a09621d44b14 12 while(1) {
cvitas 1:a09621d44b14 13
cvitas 1:a09621d44b14 14 OUT_A=0.0; // set duty cycle to 0%
cvitas 1:a09621d44b14 15 for(float p = 0.0f; p < 1.0f; p += 0.05f) {
cvitas 1:a09621d44b14 16 OUT_B= p;
cvitas 1:a09621d44b14 17 wait(0.1);
cvitas 1:a09621d44b14 18 }
cvitas 1:a09621d44b14 19 wait(2);
cvitas 1:a09621d44b14 20 OUT_B=0.0; // set duty cycle to 0%
cvitas 1:a09621d44b14 21 OUT_A=0.0; // set duty cycle to 0%
cvitas 1:a09621d44b14 22 wait(0.5);
cvitas 1:a09621d44b14 23 OUT_B=0.0; // set duty cycle to 0%
cvitas 1:a09621d44b14 24 for(float p = 0.0f; p < 1.0f; p += 0.05f) {
cvitas 1:a09621d44b14 25 OUT_A= p;
cvitas 1:a09621d44b14 26 wait(0.1);
cvitas 1:a09621d44b14 27 }
cvitas 1:a09621d44b14 28 wait(2);
cvitas 1:a09621d44b14 29 OUT_B=0.0; // set duty cycle to 0%
cvitas 1:a09621d44b14 30 OUT_A=0.0; // set duty cycle to 0%
cvitas 1:a09621d44b14 31 wait(0.5);
cvitas 1:a09621d44b14 32
cvitas 1:a09621d44b14 33 }
cvitas 1:a09621d44b14 34
cvitas 1:a09621d44b14 35 /*
cvitas 0:ce1da5b1e608 36 OUT_A = 1;
cvitas 0:ce1da5b1e608 37 OUT_B = 0;
cvitas 0:ce1da5b1e608 38 wait(2);
cvitas 0:ce1da5b1e608 39 OUT_A = 0;
cvitas 0:ce1da5b1e608 40 OUT_B = 0;
cvitas 0:ce1da5b1e608 41 wait(1);
cvitas 0:ce1da5b1e608 42 OUT_A = 0;
cvitas 0:ce1da5b1e608 43 OUT_B = 1;
cvitas 0:ce1da5b1e608 44 wait(2);
cvitas 0:ce1da5b1e608 45 OUT_A = 0;
cvitas 0:ce1da5b1e608 46 OUT_B = 0;
cvitas 1:a09621d44b14 47 wait(1);*/
cvitas 1:a09621d44b14 48
cvitas 1:a09621d44b14 49
cvitas 0:ce1da5b1e608 50 }