fixed drive strength
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platform/mbed_application.c@160:d5399cc887bb, 2017-03-14 (annotated)
- Committer:
- <>
- Date:
- Tue Mar 14 16:40:56 2017 +0000
- Revision:
- 160:d5399cc887bb
This updates the lib to the mbed lib v138
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 160:d5399cc887bb | 1 | /* mbed Microcontroller Library |
<> | 160:d5399cc887bb | 2 | * Copyright (c) 2017-2017 ARM Limited |
<> | 160:d5399cc887bb | 3 | * |
<> | 160:d5399cc887bb | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
<> | 160:d5399cc887bb | 5 | * you may not use this file except in compliance with the License. |
<> | 160:d5399cc887bb | 6 | * You may obtain a copy of the License at |
<> | 160:d5399cc887bb | 7 | * |
<> | 160:d5399cc887bb | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 160:d5399cc887bb | 9 | * |
<> | 160:d5399cc887bb | 10 | * Unless required by applicable law or agreed to in writing, software |
<> | 160:d5399cc887bb | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
<> | 160:d5399cc887bb | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 160:d5399cc887bb | 13 | * See the License for the specific language governing permissions and |
<> | 160:d5399cc887bb | 14 | * limitations under the License. |
<> | 160:d5399cc887bb | 15 | */ |
<> | 160:d5399cc887bb | 16 | |
<> | 160:d5399cc887bb | 17 | #include <stdlib.h> |
<> | 160:d5399cc887bb | 18 | #include <stdarg.h> |
<> | 160:d5399cc887bb | 19 | #include "device.h" |
<> | 160:d5399cc887bb | 20 | #include "platform/mbed_application.h" |
<> | 160:d5399cc887bb | 21 | |
<> | 160:d5399cc887bb | 22 | #if MBED_APPLICATION_SUPPORT |
<> | 160:d5399cc887bb | 23 | |
<> | 160:d5399cc887bb | 24 | static void powerdown_nvic(void); |
<> | 160:d5399cc887bb | 25 | static void powerdown_scb(uint32_t vtor); |
<> | 160:d5399cc887bb | 26 | static void start_new_application(void *sp, void *pc); |
<> | 160:d5399cc887bb | 27 | |
<> | 160:d5399cc887bb | 28 | void mbed_start_application(uintptr_t address) |
<> | 160:d5399cc887bb | 29 | { |
<> | 160:d5399cc887bb | 30 | void *sp; |
<> | 160:d5399cc887bb | 31 | void *pc; |
<> | 160:d5399cc887bb | 32 | |
<> | 160:d5399cc887bb | 33 | // Interrupts are re-enabled in start_new_application |
<> | 160:d5399cc887bb | 34 | __disable_irq(); |
<> | 160:d5399cc887bb | 35 | |
<> | 160:d5399cc887bb | 36 | SysTick->CTRL = 0x00000000; |
<> | 160:d5399cc887bb | 37 | powerdown_nvic(); |
<> | 160:d5399cc887bb | 38 | powerdown_scb(address); |
<> | 160:d5399cc887bb | 39 | |
<> | 160:d5399cc887bb | 40 | sp = *((void**)address + 0); |
<> | 160:d5399cc887bb | 41 | pc = *((void**)address + 1); |
<> | 160:d5399cc887bb | 42 | start_new_application(sp, pc); |
<> | 160:d5399cc887bb | 43 | } |
<> | 160:d5399cc887bb | 44 | |
<> | 160:d5399cc887bb | 45 | static void powerdown_nvic() |
<> | 160:d5399cc887bb | 46 | { |
<> | 160:d5399cc887bb | 47 | int isr_count; |
<> | 160:d5399cc887bb | 48 | int i; |
<> | 160:d5399cc887bb | 49 | int j; |
<> | 160:d5399cc887bb | 50 | |
<> | 160:d5399cc887bb | 51 | isr_count = (SCnSCB->ICTR & SCnSCB_ICTR_INTLINESNUM_Msk) >> SCnSCB_ICTR_INTLINESNUM_Pos; |
<> | 160:d5399cc887bb | 52 | for (i = 0; i < isr_count; i++) { |
<> | 160:d5399cc887bb | 53 | NVIC->ICER[i] = 0xFFFFFFFF; |
<> | 160:d5399cc887bb | 54 | NVIC->ICPR[i] = 0xFFFFFFFF; |
<> | 160:d5399cc887bb | 55 | for (j = 0; j < 8; j++) { |
<> | 160:d5399cc887bb | 56 | NVIC->IP[i * 8 + j] = 0x00000000; |
<> | 160:d5399cc887bb | 57 | } |
<> | 160:d5399cc887bb | 58 | } |
<> | 160:d5399cc887bb | 59 | } |
<> | 160:d5399cc887bb | 60 | |
<> | 160:d5399cc887bb | 61 | static void powerdown_scb(uint32_t vtor) |
<> | 160:d5399cc887bb | 62 | { |
<> | 160:d5399cc887bb | 63 | int i; |
<> | 160:d5399cc887bb | 64 | |
<> | 160:d5399cc887bb | 65 | // SCB->CPUID - Read only CPU ID register |
<> | 160:d5399cc887bb | 66 | SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk | SCB_ICSR_PENDSTCLR_Msk; |
<> | 160:d5399cc887bb | 67 | SCB->VTOR = vtor; |
<> | 160:d5399cc887bb | 68 | SCB->AIRCR = 0x05FA | 0x0000; |
<> | 160:d5399cc887bb | 69 | SCB->SCR = 0x00000000; |
<> | 160:d5399cc887bb | 70 | // SCB->CCR - Implementation defined value |
<> | 160:d5399cc887bb | 71 | for (i = 0; i < 12; i++) { |
<> | 160:d5399cc887bb | 72 | #if defined(__CORTEX_M7) |
<> | 160:d5399cc887bb | 73 | SCB->SHPR[i] = 0x00; |
<> | 160:d5399cc887bb | 74 | #else |
<> | 160:d5399cc887bb | 75 | SCB->SHP[i] = 0x00; |
<> | 160:d5399cc887bb | 76 | #endif |
<> | 160:d5399cc887bb | 77 | } |
<> | 160:d5399cc887bb | 78 | SCB->SHCSR = 0x00000000; |
<> | 160:d5399cc887bb | 79 | SCB->CFSR = 0xFFFFFFFF; |
<> | 160:d5399cc887bb | 80 | SCB->HFSR = SCB_HFSR_DEBUGEVT_Msk | SCB_HFSR_FORCED_Msk | SCB_HFSR_VECTTBL_Msk; |
<> | 160:d5399cc887bb | 81 | SCB->DFSR = SCB_DFSR_EXTERNAL_Msk | SCB_DFSR_VCATCH_Msk | |
<> | 160:d5399cc887bb | 82 | SCB_DFSR_DWTTRAP_Msk | SCB_DFSR_BKPT_Msk | SCB_DFSR_HALTED_Msk; |
<> | 160:d5399cc887bb | 83 | // SCB->MMFAR - Implementation defined value |
<> | 160:d5399cc887bb | 84 | // SCB->BFAR - Implementation defined value |
<> | 160:d5399cc887bb | 85 | // SCB->AFSR - Implementation defined value |
<> | 160:d5399cc887bb | 86 | // SCB->PFR - Read only processor feature register |
<> | 160:d5399cc887bb | 87 | // SCB->DFR - Read only debug feature registers |
<> | 160:d5399cc887bb | 88 | // SCB->ADR - Read only auxiliary feature registers |
<> | 160:d5399cc887bb | 89 | // SCB->MMFR - Read only memory model feature registers |
<> | 160:d5399cc887bb | 90 | // SCB->ISAR - Read only instruction set attribute registers |
<> | 160:d5399cc887bb | 91 | // SCB->CPACR - Implementation defined value |
<> | 160:d5399cc887bb | 92 | } |
<> | 160:d5399cc887bb | 93 | |
<> | 160:d5399cc887bb | 94 | #if defined (__CC_ARM) |
<> | 160:d5399cc887bb | 95 | |
<> | 160:d5399cc887bb | 96 | __asm static void start_new_application(void *sp, void *pc) |
<> | 160:d5399cc887bb | 97 | { |
<> | 160:d5399cc887bb | 98 | MOV R2, #0 |
<> | 160:d5399cc887bb | 99 | MSR CONTROL, R2 // Switch to main stack |
<> | 160:d5399cc887bb | 100 | MOV SP, R0 |
<> | 160:d5399cc887bb | 101 | MSR PRIMASK, R2 // Enable interrupts |
<> | 160:d5399cc887bb | 102 | BX R1 |
<> | 160:d5399cc887bb | 103 | } |
<> | 160:d5399cc887bb | 104 | |
<> | 160:d5399cc887bb | 105 | #elif defined (__GNUC__) || defined (__ICCARM__) |
<> | 160:d5399cc887bb | 106 | |
<> | 160:d5399cc887bb | 107 | void start_new_application(void *sp, void *pc) |
<> | 160:d5399cc887bb | 108 | { |
<> | 160:d5399cc887bb | 109 | __asm volatile ( |
<> | 160:d5399cc887bb | 110 | "mov r2, #0 \n" |
<> | 160:d5399cc887bb | 111 | "msr control, r2 \n" // Switch to main stack |
<> | 160:d5399cc887bb | 112 | "mov sp, %0 \n" |
<> | 160:d5399cc887bb | 113 | "msr primask, r2 \n" // Enable interrupts |
<> | 160:d5399cc887bb | 114 | "bx %1 \n" |
<> | 160:d5399cc887bb | 115 | : |
<> | 160:d5399cc887bb | 116 | : "l" (sp), "l" (pc) |
<> | 160:d5399cc887bb | 117 | : "r2", "cc", "memory" |
<> | 160:d5399cc887bb | 118 | ); |
<> | 160:d5399cc887bb | 119 | } |
<> | 160:d5399cc887bb | 120 | |
<> | 160:d5399cc887bb | 121 | #else |
<> | 160:d5399cc887bb | 122 | |
<> | 160:d5399cc887bb | 123 | #error "Unsupported toolchain" |
<> | 160:d5399cc887bb | 124 | |
<> | 160:d5399cc887bb | 125 | #endif |
<> | 160:d5399cc887bb | 126 | |
<> | 160:d5399cc887bb | 127 | #endif /* MBED_APPLICATION_SUPPORT */ |