Cortney Padua / mbed-dev

fixed drive strength

Dependents:   capstone_i2c

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32620/serial_api.c@163:1d4c9d0af1e9, 2017-04-11 (annotated)

Committer:
cpadua
Date:
Tue Apr 11 20:39:24 2017 +0000
Revision:
163:1d4c9d0af1e9
Parent:
153:fa9ff456f731 
fixed i2c-api.c

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /*******************************************************************************
<> 149:156823d33999 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 149:156823d33999 3 *
<> 149:156823d33999 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 149:156823d33999 5 * copy of this software and associated documentation files (the "Software"),
<> 149:156823d33999 6 * to deal in the Software without restriction, including without limitation
<> 149:156823d33999 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 149:156823d33999 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 149:156823d33999 9 * Software is furnished to do so, subject to the following conditions:
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * The above copyright notice and this permission notice shall be included
<> 149:156823d33999 12 * in all copies or substantial portions of the Software.
<> 149:156823d33999 13 *
<> 149:156823d33999 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 149:156823d33999 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 149:156823d33999 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 149:156823d33999 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 149:156823d33999 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 149:156823d33999 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 149:156823d33999 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 149:156823d33999 21 *
<> 149:156823d33999 22 * Except as contained in this notice, the name of Maxim Integrated
<> 149:156823d33999 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 149:156823d33999 24 * Products, Inc. Branding Policy.
<> 149:156823d33999 25 *
<> 149:156823d33999 26 * The mere transfer of this software does not imply any licenses
<> 149:156823d33999 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 149:156823d33999 28 * trademarks, maskwork rights, or any other form of intellectual
<> 149:156823d33999 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 149:156823d33999 30 * ownership rights.
<> 149:156823d33999 31 *******************************************************************************
<> 149:156823d33999 32 */
<> 149:156823d33999 33
<> 149:156823d33999 34 #include <string.h>
<> 149:156823d33999 35 #include "mbed_assert.h"
<> 149:156823d33999 36 #include "cmsis.h"
<> 149:156823d33999 37 #include "serial_api.h"
<> 149:156823d33999 38 #include "uart_regs.h"
<> 149:156823d33999 39 #include "ioman_regs.h"
<> 149:156823d33999 40 #include "gpio_api.h"
<> 149:156823d33999 41 #include "clkman_regs.h"
<> 149:156823d33999 42 #include "PeripheralPins.h"
<> 149:156823d33999 43
<> 149:156823d33999 44 #define DEFAULT_BAUD 9600
<> 149:156823d33999 45 #define DEFAULT_STOP 1
<> 149:156823d33999 46 #define DEFAULT_PARITY ParityNone
<> 149:156823d33999 47
<> 149:156823d33999 48 #define UART_ERRORS (MXC_F_UART_INTFL_RX_FRAMING_ERR | \
<> 149:156823d33999 49 MXC_F_UART_INTFL_RX_PARITY_ERR | \
<> 149:156823d33999 50 MXC_F_UART_INTFL_RX_FIFO_OVERFLOW)
<> 149:156823d33999 51
<> 149:156823d33999 52 // Variables for managing the stdio UART
<> 149:156823d33999 53 int stdio_uart_inited;
<> 149:156823d33999 54 serial_t stdio_uart;
<> 149:156823d33999 55
<> 149:156823d33999 56 // Variables for interrupt driven
<> 149:156823d33999 57 static uart_irq_handler irq_handler;
<> 149:156823d33999 58 static uint32_t serial_irq_ids[MXC_CFG_UART_INSTANCES];
<> 149:156823d33999 59
<> 149:156823d33999 60 //******************************************************************************
<> 149:156823d33999 61 void serial_init(serial_t *obj, PinName tx, PinName rx)
<> 149:156823d33999 62 {
<> 149:156823d33999 63 // Determine which uart is associated with each pin
<> 149:156823d33999 64 UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
<> 149:156823d33999 65 UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
<> 149:156823d33999 66 UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
<> 149:156823d33999 67
<> 149:156823d33999 68 // Make sure that both pins are pointing to the same uart
<> 149:156823d33999 69 MBED_ASSERT(uart != (UARTName)NC);
<> 149:156823d33999 70
<> 149:156823d33999 71 // Ensure that the UART clock is enabled
<> 149:156823d33999 72 switch (uart) {
<> 149:156823d33999 73 case UART_0:
<> 149:156823d33999 74 MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER;
<> 149:156823d33999 75 break;
<> 149:156823d33999 76 case UART_1:
<> 149:156823d33999 77 MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER;
<> 149:156823d33999 78 break;
<> 149:156823d33999 79 case UART_2:
<> 149:156823d33999 80 MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER;
<> 149:156823d33999 81 break;
<> 149:156823d33999 82 case UART_3:
<> 149:156823d33999 83 MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER;
<> 149:156823d33999 84 break;
<> 149:156823d33999 85 default:
<> 149:156823d33999 86 break;
<> 149:156823d33999 87 }
<> 149:156823d33999 88
<> 149:156823d33999 89 // Ensure that the UART clock is enabled
<> 149:156823d33999 90 // But don't override the scaler
<> 149:156823d33999 91 //
<> 149:156823d33999 92 // To support the most common baud rates, 9600 and 115200, we need to
<> 149:156823d33999 93 // scale down the uart input clock.
<> 149:156823d33999 94 if (!(MXC_CLKMAN->sys_clk_ctrl_8_uart & MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE)) {
<> 149:156823d33999 95
<> 149:156823d33999 96 switch (SystemCoreClock) {
<> 149:156823d33999 97 case RO_FREQ:
<> 149:156823d33999 98 MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_4;
<> 149:156823d33999 99 break;
<> 149:156823d33999 100 case (RO_FREQ / 2):
<> 149:156823d33999 101 MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_2;
<> 149:156823d33999 102 break;
<> 149:156823d33999 103 default:
<> 149:156823d33999 104 MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_4;
<> 149:156823d33999 105 break;
<> 149:156823d33999 106 }
<> 149:156823d33999 107 }
<> 149:156823d33999 108
<> 149:156823d33999 109 // Set the obj pointer to the proper uart
<> 149:156823d33999 110 obj->uart = (mxc_uart_regs_t*)uart;
<> 149:156823d33999 111
<> 149:156823d33999 112 // Set the uart index
<> 149:156823d33999 113 obj->index = MXC_UART_GET_IDX(obj->uart);
<> 149:156823d33999 114 obj->fifo = (mxc_uart_fifo_regs_t*)MXC_UART_GET_BASE_FIFO(obj->index);
<> 149:156823d33999 115
<> 149:156823d33999 116 // Configure the pins
<> 149:156823d33999 117 pinmap_pinout(tx, PinMap_UART_TX);
<> 149:156823d33999 118 pinmap_pinout(rx, PinMap_UART_RX);
<> 149:156823d33999 119
<> 149:156823d33999 120 // Flush the RX and TX FIFOs, clear the settings
<> 149:156823d33999 121 obj->uart->ctrl &= ~(MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
<> 149:156823d33999 122 obj->uart->ctrl |= (MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
<> 149:156823d33999 123
<> 149:156823d33999 124 // Disable interrupts
<> 149:156823d33999 125 obj->uart->inten = 0;
<> 149:156823d33999 126 obj->uart->intfl = obj->uart->intfl;
<> 149:156823d33999 127
<> 149:156823d33999 128 // Configure to default settings
<> 149:156823d33999 129 serial_baud(obj, DEFAULT_BAUD);
<> 149:156823d33999 130 serial_format(obj, 8, ParityNone, 1);
<> 149:156823d33999 131
<> 149:156823d33999 132 // Manage stdio UART
<> 149:156823d33999 133 if (uart == STDIO_UART) {
<> 149:156823d33999 134 stdio_uart_inited = 1;
<> 149:156823d33999 135 memcpy(&stdio_uart, obj, sizeof(serial_t));
<> 149:156823d33999 136 }
<> 149:156823d33999 137
<> 149:156823d33999 138 // Enable UART
<> 149:156823d33999 139 obj->uart->ctrl |= MXC_F_UART_CTRL_UART_EN;
<> 149:156823d33999 140 }
<> 149:156823d33999 141
<> 149:156823d33999 142 //******************************************************************************
<> 149:156823d33999 143 void serial_baud(serial_t *obj, int baudrate)
<> 149:156823d33999 144 {
<> 149:156823d33999 145 uint32_t baud_setting = 0;
<> 149:156823d33999 146
<> 149:156823d33999 147 MBED_ASSERT(MXC_CLKMAN->sys_clk_ctrl_8_uart > MXC_S_CLKMAN_CLK_SCALE_DISABLED);
<> 149:156823d33999 148
<> 149:156823d33999 149 // Calculate the integer and decimal portions
<> 149:156823d33999 150 baud_setting = SystemCoreClock / (1<<(MXC_CLKMAN->sys_clk_ctrl_8_uart-1));
<> 149:156823d33999 151 baud_setting = baud_setting / (baudrate * 16);
<> 149:156823d33999 152
<> 149:156823d33999 153 // If the result doesn't fit in the register
<> 149:156823d33999 154 MBED_ASSERT(baud_setting <= UINT8_MAX);
<> 149:156823d33999 155
<> 149:156823d33999 156 obj->uart->baud = baud_setting;
<> 149:156823d33999 157 }
<> 149:156823d33999 158
<> 149:156823d33999 159 //******************************************************************************
<> 149:156823d33999 160 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
<> 149:156823d33999 161 {
<> 149:156823d33999 162 // Check the validity of the inputs
<> 149:156823d33999 163 MBED_ASSERT((data_bits > 4) && (data_bits < 9));
<> 149:156823d33999 164 MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) ||
<> 149:156823d33999 165 (parity == ParityEven) || (parity == ParityForced1) ||
<> 149:156823d33999 166 (parity == ParityForced0));
<> 149:156823d33999 167 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
<> 149:156823d33999 168
<> 149:156823d33999 169 // Adjust the stop and data bits
<> 149:156823d33999 170 stop_bits -= 1;
<> 149:156823d33999 171 data_bits -= 5;
<> 149:156823d33999 172
<> 149:156823d33999 173 // Adjust the parity setting
<> 149:156823d33999 174 int mode = 0;
<> 149:156823d33999 175 switch (parity) {
<> 149:156823d33999 176 case ParityNone:
<> 149:156823d33999 177 mode = 0;
<> 149:156823d33999 178 break;
<> 149:156823d33999 179 case ParityOdd :
<> 149:156823d33999 180 mode = 1;
<> 149:156823d33999 181 break;
<> 149:156823d33999 182 case ParityEven:
<> 149:156823d33999 183 mode = 2;
<> 149:156823d33999 184 break;
<> 149:156823d33999 185 case ParityForced1:
<> 149:156823d33999 186 // Hardware does not support forced parity
<> 149:156823d33999 187 MBED_ASSERT(0);
<> 149:156823d33999 188 break;
<> 149:156823d33999 189 case ParityForced0:
<> 149:156823d33999 190 // Hardware does not support forced parity
<> 149:156823d33999 191 MBED_ASSERT(0);
<> 149:156823d33999 192 break;
<> 149:156823d33999 193 default:
<> 149:156823d33999 194 mode = 0;
<> 149:156823d33999 195 break;
<> 149:156823d33999 196 }
<> 149:156823d33999 197
<> 149:156823d33999 198 int temp = obj->uart->ctrl;
<> 149:156823d33999 199 temp &= ~(MXC_F_UART_CTRL_DATA_SIZE | MXC_F_UART_CTRL_EXTRA_STOP | MXC_F_UART_CTRL_PARITY);
<> 149:156823d33999 200 temp |= (data_bits << MXC_F_UART_CTRL_DATA_SIZE_POS);
<> 149:156823d33999 201 temp |= (stop_bits << MXC_F_UART_CTRL_EXTRA_STOP_POS);
<> 149:156823d33999 202 temp |= (mode << MXC_F_UART_CTRL_PARITY_POS);
<> 149:156823d33999 203 obj->uart->ctrl = temp;
<> 149:156823d33999 204 }
<> 149:156823d33999 205
<> 149:156823d33999 206 //******************************************************************************
<> 149:156823d33999 207 void uart_handler(mxc_uart_regs_t* uart, int id)
<> 149:156823d33999 208 {
<> 149:156823d33999 209 // Check for errors or RX Threshold
<> 149:156823d33999 210 if (uart->intfl & (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS)) {
<> 149:156823d33999 211 if (serial_irq_ids[id]) {
<> 149:156823d33999 212 irq_handler(serial_irq_ids[id], RxIrq);
<> 149:156823d33999 213 }
<> 149:156823d33999 214 uart->intfl = (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS);
<> 149:156823d33999 215 }
<> 149:156823d33999 216
<> 149:156823d33999 217 // Check for TX Threshold
<> 149:156823d33999 218 if (uart->intfl & MXC_F_UART_INTFL_TX_FIFO_AE) {
<> 149:156823d33999 219 if (serial_irq_ids[id]) {
<> 149:156823d33999 220 irq_handler(serial_irq_ids[id], TxIrq);
<> 149:156823d33999 221 }
<> 149:156823d33999 222 uart->intfl = MXC_F_UART_INTFL_TX_FIFO_AE;
<> 149:156823d33999 223 }
<> 149:156823d33999 224 }
<> 149:156823d33999 225
<> 149:156823d33999 226 void uart0_handler(void) { uart_handler(MXC_UART0, 0); }
<> 149:156823d33999 227 void uart1_handler(void) { uart_handler(MXC_UART1, 1); }
<> 149:156823d33999 228 void uart2_handler(void) { uart_handler(MXC_UART2, 2); }
<> 149:156823d33999 229 void uart3_handler(void) { uart_handler(MXC_UART3, 3); }
<> 149:156823d33999 230
<> 149:156823d33999 231 //******************************************************************************
<> 149:156823d33999 232 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
<> 149:156823d33999 233 {
<> 149:156823d33999 234 irq_handler = handler;
<> 149:156823d33999 235 serial_irq_ids[obj->index] = id;
<> 149:156823d33999 236 }
<> 149:156823d33999 237
<> 149:156823d33999 238 //******************************************************************************
<> 149:156823d33999 239 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
<> 149:156823d33999 240 {
<> 149:156823d33999 241 switch (obj->index) {
<> 149:156823d33999 242 case 0:
<> 149:156823d33999 243 NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler);
<> 149:156823d33999 244 NVIC_EnableIRQ(UART0_IRQn);
<> 149:156823d33999 245 break;
<> 149:156823d33999 246 case 1:
<> 149:156823d33999 247 NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler);
<> 149:156823d33999 248 NVIC_EnableIRQ(UART1_IRQn);
<> 149:156823d33999 249 break;
<> 149:156823d33999 250 case 2:
<> 149:156823d33999 251 NVIC_SetVector(UART2_IRQn, (uint32_t)uart2_handler);
<> 149:156823d33999 252 NVIC_EnableIRQ(UART2_IRQn);
<> 149:156823d33999 253 break;
<> 149:156823d33999 254 case 3:
<> 149:156823d33999 255 NVIC_SetVector(UART3_IRQn, (uint32_t)uart3_handler);
<> 149:156823d33999 256 NVIC_EnableIRQ(UART3_IRQn);
<> 149:156823d33999 257 break;
<> 149:156823d33999 258 default:
<> 149:156823d33999 259 MBED_ASSERT(0);
<> 149:156823d33999 260 }
<> 149:156823d33999 261
<> 149:156823d33999 262 if (irq == RxIrq) {
<> 149:156823d33999 263 // Enable RX FIFO Threshold Interrupt
<> 149:156823d33999 264 if (enable) {
<> 149:156823d33999 265 // Clear pending interrupts
<> 149:156823d33999 266 obj->uart->intfl = obj->uart->intfl;
<> 149:156823d33999 267 obj->uart->inten |= (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS);
<> 149:156823d33999 268 } else {
<> 149:156823d33999 269 // Clear pending interrupts
<> 149:156823d33999 270 obj->uart->intfl = obj->uart->intfl;
<> 149:156823d33999 271 obj->uart->inten &= ~(MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS);
<> 149:156823d33999 272 }
<> 149:156823d33999 273
<> 149:156823d33999 274 } else if (irq == TxIrq) {
<> 149:156823d33999 275 // Set TX Almost Empty level to interrupt when empty
<> 149:156823d33999 276 MXC_SET_FIELD(&obj->uart->tx_fifo_ctrl, MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL,
<> 149:156823d33999 277 (MXC_UART_FIFO_DEPTH - 1) << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS);
<> 149:156823d33999 278
<> 149:156823d33999 279 // Enable TX Almost Empty Interrupt
<> 149:156823d33999 280 if (enable) {
<> 149:156823d33999 281 // Clear pending interrupts
<> 149:156823d33999 282 obj->uart->intfl = obj->uart->intfl;
<> 149:156823d33999 283 obj->uart->inten |= MXC_F_UART_INTFL_TX_FIFO_AE;
<> 149:156823d33999 284 } else {
<> 149:156823d33999 285 // Clear pending interrupts
<> 149:156823d33999 286 obj->uart->intfl = obj->uart->intfl;
<> 149:156823d33999 287 obj->uart->inten &= ~MXC_F_UART_INTFL_TX_FIFO_AE;
<> 149:156823d33999 288 }
<> 149:156823d33999 289
<> 149:156823d33999 290 } else {
<> 149:156823d33999 291 MBED_ASSERT(0);
<> 149:156823d33999 292 }
<> 149:156823d33999 293 }
<> 149:156823d33999 294
<> 149:156823d33999 295
<> 149:156823d33999 296 //******************************************************************************
<> 149:156823d33999 297 int serial_getc(serial_t *obj)
<> 149:156823d33999 298 {
<> 149:156823d33999 299 int c;
<> 149:156823d33999 300
<> 149:156823d33999 301 // Wait for data to be available
<> 149:156823d33999 302 while ((obj->uart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY) == 0);
<> 149:156823d33999 303
<> 149:156823d33999 304 c = *obj->fifo->rx_8;
<> 149:156823d33999 305
<> 149:156823d33999 306 return c;
<> 149:156823d33999 307 }
<> 149:156823d33999 308
<> 149:156823d33999 309 //******************************************************************************
<> 149:156823d33999 310 void serial_putc(serial_t *obj, int c)
<> 149:156823d33999 311 {
<> 149:156823d33999 312 // Wait for TXFIFO to not be full
<> 149:156823d33999 313 while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
<> 149:156823d33999 314 >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)
<> 149:156823d33999 315 >= MXC_UART_FIFO_DEPTH );
<> 149:156823d33999 316
<> 149:156823d33999 317 // Must clear before every write to the buffer to know that the fifo
<> 149:156823d33999 318 // is empty when the TX DONE bit is set
<> 149:156823d33999 319 obj->uart->intfl = MXC_F_UART_INTFL_TX_DONE;
<> 149:156823d33999 320 *obj->fifo->tx_8 = (uint8_t)c;
<> 149:156823d33999 321 }
<> 149:156823d33999 322
<> 149:156823d33999 323 //******************************************************************************
<> 149:156823d33999 324 int serial_readable(serial_t *obj)
<> 149:156823d33999 325 {
<> 153:fa9ff456f731 326 return (obj->uart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY);
<> 149:156823d33999 327 }
<> 149:156823d33999 328
<> 149:156823d33999 329 //******************************************************************************
<> 149:156823d33999 330 int serial_writable(serial_t *obj)
<> 149:156823d33999 331 {
<> 149:156823d33999 332 return ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
<> 149:156823d33999 333 >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)
<> 149:156823d33999 334 < MXC_UART_FIFO_DEPTH );
<> 149:156823d33999 335 }
<> 149:156823d33999 336
<> 149:156823d33999 337 //******************************************************************************
<> 149:156823d33999 338 void serial_clear(serial_t *obj)
<> 149:156823d33999 339 {
<> 149:156823d33999 340 // Clear the rx and tx fifos
<> 149:156823d33999 341 obj->uart->ctrl &= ~(MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
<> 149:156823d33999 342 obj->uart->ctrl |= (MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
<> 149:156823d33999 343 }
<> 149:156823d33999 344
<> 149:156823d33999 345
<> 149:156823d33999 346 //******************************************************************************
<> 149:156823d33999 347 void serial_break_set(serial_t *obj)
<> 149:156823d33999 348 {
<> 149:156823d33999 349 // Make sure that nothing is being sent
<> 149:156823d33999 350 while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
<> 149:156823d33999 351 >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) > 0);
<> 149:156823d33999 352 while (!(obj->uart->intfl & MXC_F_UART_INTFL_TX_DONE));
<> 149:156823d33999 353
<> 149:156823d33999 354 // Configure the GPIO to output 0
<> 149:156823d33999 355 gpio_t tx_gpio;
<> 149:156823d33999 356 switch (((UARTName)(obj->uart))) {
<> 149:156823d33999 357 case UART_0:
<> 149:156823d33999 358 gpio_init_out(&tx_gpio, UART0_TX);
<> 149:156823d33999 359 break;
<> 149:156823d33999 360 case UART_1:
<> 149:156823d33999 361 gpio_init_out(&tx_gpio, UART1_TX);
<> 149:156823d33999 362 break;
<> 149:156823d33999 363 case UART_2:
<> 149:156823d33999 364 gpio_init_out(&tx_gpio, UART2_TX);
<> 149:156823d33999 365 break;
<> 149:156823d33999 366 case UART_3:
<> 149:156823d33999 367 gpio_init_out(&tx_gpio, UART3_TX);
<> 149:156823d33999 368 break;
<> 149:156823d33999 369 default:
<> 149:156823d33999 370 gpio_init_out(&tx_gpio, (PinName)NC);
<> 149:156823d33999 371 break;
<> 149:156823d33999 372 }
<> 149:156823d33999 373
<> 149:156823d33999 374 gpio_write(&tx_gpio, 0);
<> 149:156823d33999 375
<> 149:156823d33999 376 // GPIO is setup now, but we need to map GPIO to the pin
<> 149:156823d33999 377 switch (((UARTName)(obj->uart))) {
<> 149:156823d33999 378 case UART_0:
<> 149:156823d33999 379 MXC_IOMAN->uart0_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ;
<> 149:156823d33999 380 MBED_ASSERT((MXC_IOMAN->uart0_ack & (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)) == 0);
<> 149:156823d33999 381 break;
<> 149:156823d33999 382 case UART_1:
<> 149:156823d33999 383 MXC_IOMAN->uart1_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ;
<> 149:156823d33999 384 MBED_ASSERT((MXC_IOMAN->uart1_ack & (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)) == 0);
<> 149:156823d33999 385 break;
<> 149:156823d33999 386 case UART_2:
<> 149:156823d33999 387 MXC_IOMAN->uart2_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ;
<> 149:156823d33999 388 MBED_ASSERT((MXC_IOMAN->uart2_ack & (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)) == 0);
<> 149:156823d33999 389 break;
<> 149:156823d33999 390 case UART_3:
<> 149:156823d33999 391 MXC_IOMAN->uart3_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ;
<> 149:156823d33999 392 MBED_ASSERT((MXC_IOMAN->uart3_ack & (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)) == 0);
<> 149:156823d33999 393 break;
<> 149:156823d33999 394 default:
<> 149:156823d33999 395 break;
<> 149:156823d33999 396 }
<> 149:156823d33999 397 }
<> 149:156823d33999 398
<> 149:156823d33999 399 //******************************************************************************
<> 149:156823d33999 400 void serial_break_clear(serial_t *obj)
<> 149:156823d33999 401 {
<> 149:156823d33999 402 // Configure the GPIO to output 1
<> 149:156823d33999 403 gpio_t tx_gpio;
<> 149:156823d33999 404 switch (((UARTName)(obj->uart))) {
<> 149:156823d33999 405 case UART_0:
<> 149:156823d33999 406 gpio_init_out(&tx_gpio, UART0_TX);
<> 149:156823d33999 407 break;
<> 149:156823d33999 408 case UART_1:
<> 149:156823d33999 409 gpio_init_out(&tx_gpio, UART1_TX);
<> 149:156823d33999 410 break;
<> 149:156823d33999 411 case UART_2:
<> 149:156823d33999 412 gpio_init_out(&tx_gpio, UART2_TX);
<> 149:156823d33999 413 break;
<> 149:156823d33999 414 case UART_3:
<> 149:156823d33999 415 gpio_init_out(&tx_gpio, UART3_TX);
<> 149:156823d33999 416 break;
<> 149:156823d33999 417 default:
<> 149:156823d33999 418 gpio_init_out(&tx_gpio, (PinName)NC);
<> 149:156823d33999 419 break;
<> 149:156823d33999 420 }
<> 149:156823d33999 421
<> 149:156823d33999 422 gpio_write(&tx_gpio, 1);
<> 149:156823d33999 423
<> 149:156823d33999 424 // Renable UART
<> 149:156823d33999 425 switch (((UARTName)(obj->uart))) {
<> 149:156823d33999 426 case UART_0:
<> 149:156823d33999 427 serial_pinout_tx(UART0_TX);
<> 149:156823d33999 428 break;
<> 149:156823d33999 429 case UART_1:
<> 149:156823d33999 430 serial_pinout_tx(UART1_TX);
<> 149:156823d33999 431 break;
<> 149:156823d33999 432 case UART_2:
<> 149:156823d33999 433 serial_pinout_tx(UART2_TX);
<> 149:156823d33999 434 break;
<> 149:156823d33999 435 case UART_3:
<> 149:156823d33999 436 serial_pinout_tx(UART3_TX);
<> 149:156823d33999 437 break;
<> 149:156823d33999 438 default:
<> 149:156823d33999 439 serial_pinout_tx((PinName)NC);
<> 149:156823d33999 440 break;
<> 149:156823d33999 441 }
<> 149:156823d33999 442 }
<> 149:156823d33999 443
<> 149:156823d33999 444 //******************************************************************************
<> 149:156823d33999 445 void serial_pinout_tx(PinName tx)
<> 149:156823d33999 446 {
<> 149:156823d33999 447 pinmap_pinout(tx, PinMap_UART_TX);
<> 149:156823d33999 448 }
<> 149:156823d33999 449
<> 149:156823d33999 450 //******************************************************************************
<> 149:156823d33999 451 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
<> 149:156823d33999 452 {
<> 149:156823d33999 453 uint32_t ctrl = obj->uart->ctrl;
<> 149:156823d33999 454
<> 149:156823d33999 455 // Disable hardware flow control
<> 149:156823d33999 456 ctrl &= ~(MXC_F_UART_CTRL_RTS_EN | MXC_F_UART_CTRL_CTS_EN);
<> 149:156823d33999 457
<> 149:156823d33999 458 if (FlowControlNone != type) {
<> 149:156823d33999 459 // Check to see if we can use HW flow control
<> 149:156823d33999 460 UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
<> 149:156823d33999 461 UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
<> 149:156823d33999 462 UARTName uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
<> 149:156823d33999 463
<> 149:156823d33999 464 // Make sure that the pins are pointing to the same UART
<> 149:156823d33999 465 MBED_ASSERT(uart != (UARTName)NC);
<> 149:156823d33999 466
<> 149:156823d33999 467 if ((FlowControlCTS == type) || (FlowControlRTSCTS == type)) {
<> 149:156823d33999 468 // Make sure pin is in the PinMap
<> 149:156823d33999 469 MBED_ASSERT(uart_cts != (UARTName)NC);
<> 149:156823d33999 470
<> 149:156823d33999 471 // Enable the pin for CTS function
<> 149:156823d33999 472 pinmap_pinout(txflow, PinMap_UART_CTS);
<> 149:156823d33999 473
<> 149:156823d33999 474 // Enable active-low hardware flow control
<> 149:156823d33999 475 ctrl |= (MXC_F_UART_CTRL_CTS_EN | MXC_F_UART_CTRL_CTS_POLARITY);
<> 149:156823d33999 476 }
<> 149:156823d33999 477
<> 149:156823d33999 478 if ((FlowControlRTS == type) || (FlowControlRTSCTS == type)) {
<> 149:156823d33999 479 // Make sure pin is in the PinMap
<> 149:156823d33999 480 MBED_ASSERT(uart_rts != (UARTName)NC);
<> 149:156823d33999 481
<> 149:156823d33999 482 // Enable the pin for RTS function
<> 149:156823d33999 483 pinmap_pinout(rxflow, PinMap_UART_RTS);
<> 149:156823d33999 484
<> 149:156823d33999 485 // Enable active-low hardware flow control
<> 149:156823d33999 486 ctrl |= (MXC_F_UART_CTRL_RTS_EN | MXC_F_UART_CTRL_RTS_POLARITY);
<> 149:156823d33999 487 }
<> 149:156823d33999 488 }
<> 149:156823d33999 489
<> 149:156823d33999 490 obj->uart->ctrl = ctrl;
<> 149:156823d33999 491 }