Cortney Padua / mbed-dev

fixed drive strength

Dependents:   capstone_i2c

Fork of mbed-dev by mbed official

targets/TARGET_NXP/TARGET_LPC2460/pwmout_api.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/hal/TARGET_NXP/TARGET_LPC2460/pwmout_api.c@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2015 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 17 #include "pwmout_api.h"
<> 144:ef7eb2e8f9f7 18 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 19 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 #define TCR_CNT_EN 0x00000001
<> 144:ef7eb2e8f9f7 22 #define TCR_RESET 0x00000002
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 // PORT ID, PWM ID, Pin function
<> 144:ef7eb2e8f9f7 25 static const PinMap PinMap_PWM[] = {
<> 144:ef7eb2e8f9f7 26 {P1_18, PWM_1, 2},
<> 144:ef7eb2e8f9f7 27 {P1_20, PWM_2, 2},
<> 144:ef7eb2e8f9f7 28 {P1_21, PWM_3, 2},
<> 144:ef7eb2e8f9f7 29 {P1_23, PWM_4, 2},
<> 144:ef7eb2e8f9f7 30 {P1_24, PWM_5, 2},
<> 144:ef7eb2e8f9f7 31 {P1_26, PWM_6, 2},
<> 144:ef7eb2e8f9f7 32 {P2_0 , PWM_1, 1},
<> 144:ef7eb2e8f9f7 33 {P2_1 , PWM_2, 1},
<> 144:ef7eb2e8f9f7 34 {P2_2 , PWM_3, 1},
<> 144:ef7eb2e8f9f7 35 {P2_3 , PWM_4, 1},
<> 144:ef7eb2e8f9f7 36 {P2_4 , PWM_5, 1},
<> 144:ef7eb2e8f9f7 37 {P2_5 , PWM_6, 1},
<> 144:ef7eb2e8f9f7 38 {P3_24, PWM_1, 3},
<> 144:ef7eb2e8f9f7 39 {P3_25, PWM_2, 3},
<> 144:ef7eb2e8f9f7 40 {P3_26, PWM_3, 3},
<> 144:ef7eb2e8f9f7 41 {P3_27, PWM_4, 3},
<> 144:ef7eb2e8f9f7 42 {P3_28, PWM_5, 3},
<> 144:ef7eb2e8f9f7 43 {P3_29, PWM_6, 3},
<> 144:ef7eb2e8f9f7 44 {NC, NC, 0}
<> 144:ef7eb2e8f9f7 45 };
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 __IO uint32_t *PWM_MATCH[] = {
<> 144:ef7eb2e8f9f7 48 &(LPC_PWM1->MR0),
<> 144:ef7eb2e8f9f7 49 &(LPC_PWM1->MR1),
<> 144:ef7eb2e8f9f7 50 &(LPC_PWM1->MR2),
<> 144:ef7eb2e8f9f7 51 &(LPC_PWM1->MR3),
<> 144:ef7eb2e8f9f7 52 &(LPC_PWM1->MR4),
<> 144:ef7eb2e8f9f7 53 &(LPC_PWM1->MR5),
<> 144:ef7eb2e8f9f7 54 &(LPC_PWM1->MR6)
<> 144:ef7eb2e8f9f7 55 };
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 #define TCR_PWM_EN 0x00000008
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 static unsigned int pwm_clock_mhz;
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 void pwmout_init(pwmout_t* obj, PinName pin) {
<> 144:ef7eb2e8f9f7 62 // determine the channel
<> 144:ef7eb2e8f9f7 63 PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
<> 144:ef7eb2e8f9f7 64 MBED_ASSERT(pwm != (PWMName)NC);
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 obj->pwm = pwm;
<> 144:ef7eb2e8f9f7 67 obj->MR = PWM_MATCH[pwm];
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 // ensure the power is on
<> 144:ef7eb2e8f9f7 70 LPC_SC->PCONP |= 1 << 6;
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 // ensure clock to /4
<> 144:ef7eb2e8f9f7 73 LPC_SC->PCLKSEL0 &= ~(0x3 << 12); // pclk = /4
<> 144:ef7eb2e8f9f7 74 LPC_PWM1->PR = 0; // no pre-scale
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 // ensure single PWM mode
<> 144:ef7eb2e8f9f7 77 LPC_PWM1->MCR = 1 << 1; // reset TC on match 0
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 // enable the specific PWM output
<> 144:ef7eb2e8f9f7 80 LPC_PWM1->PCR |= 1 << (8 + pwm);
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 pwm_clock_mhz = SystemCoreClock / 4000000;
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 // default to 20ms: standard for servos, and fine for e.g. brightness control
<> 144:ef7eb2e8f9f7 85 pwmout_period_ms(obj, 20);
<> 144:ef7eb2e8f9f7 86 pwmout_write (obj, 0);
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 // Wire pinout
<> 144:ef7eb2e8f9f7 89 pinmap_pinout(pin, PinMap_PWM);
<> 144:ef7eb2e8f9f7 90 }
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 void pwmout_free(pwmout_t* obj) {
<> 144:ef7eb2e8f9f7 93 // [TODO]
<> 144:ef7eb2e8f9f7 94 }
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 void pwmout_write(pwmout_t* obj, float value) {
<> 144:ef7eb2e8f9f7 97 if (value < 0.0f) {
<> 144:ef7eb2e8f9f7 98 value = 0.0;
<> 144:ef7eb2e8f9f7 99 } else if (value > 1.0f) {
<> 144:ef7eb2e8f9f7 100 value = 1.0;
<> 144:ef7eb2e8f9f7 101 }
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 // set channel match to percentage
<> 144:ef7eb2e8f9f7 104 uint32_t v = (uint32_t)((float)(LPC_PWM1->MR0) * value);
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
<> 144:ef7eb2e8f9f7 107 if (v == LPC_PWM1->MR0) {
<> 144:ef7eb2e8f9f7 108 v++;
<> 144:ef7eb2e8f9f7 109 }
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 *obj->MR = v;
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 // accept on next period start
<> 144:ef7eb2e8f9f7 114 LPC_PWM1->LER |= 1 << obj->pwm;
<> 144:ef7eb2e8f9f7 115 }
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 float pwmout_read(pwmout_t* obj) {
<> 144:ef7eb2e8f9f7 118 float v = (float)(*obj->MR) / (float)(LPC_PWM1->MR0);
<> 144:ef7eb2e8f9f7 119 return (v > 1.0f) ? (1.0f) : (v);
<> 144:ef7eb2e8f9f7 120 }
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 void pwmout_period(pwmout_t* obj, float seconds) {
<> 144:ef7eb2e8f9f7 123 pwmout_period_us(obj, seconds * 1000000.0f);
<> 144:ef7eb2e8f9f7 124 }
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 void pwmout_period_ms(pwmout_t* obj, int ms) {
<> 144:ef7eb2e8f9f7 127 pwmout_period_us(obj, ms * 1000);
<> 144:ef7eb2e8f9f7 128 }
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 // Set the PWM period, keeping the duty cycle the same.
<> 144:ef7eb2e8f9f7 131 void pwmout_period_us(pwmout_t* obj, int us) {
<> 144:ef7eb2e8f9f7 132 // calculate number of ticks
<> 144:ef7eb2e8f9f7 133 uint32_t ticks = pwm_clock_mhz * us;
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 // set reset
<> 144:ef7eb2e8f9f7 136 LPC_PWM1->TCR = TCR_RESET;
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 // set the global match register
<> 144:ef7eb2e8f9f7 139 LPC_PWM1->MR0 = ticks;
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 // Scale the pulse width to preserve the duty ratio
<> 144:ef7eb2e8f9f7 142 if (LPC_PWM1->MR0 > 0) {
<> 144:ef7eb2e8f9f7 143 *obj->MR = (*obj->MR * ticks) / LPC_PWM1->MR0;
<> 144:ef7eb2e8f9f7 144 }
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 // set the channel latch to update value at next period start
<> 144:ef7eb2e8f9f7 147 LPC_PWM1->LER |= 1 << 0;
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 // enable counter and pwm, clear reset
<> 144:ef7eb2e8f9f7 150 LPC_PWM1->TCR = TCR_CNT_EN | TCR_PWM_EN;
<> 144:ef7eb2e8f9f7 151 }
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
<> 144:ef7eb2e8f9f7 154 pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
<> 144:ef7eb2e8f9f7 155 }
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
<> 144:ef7eb2e8f9f7 158 pwmout_pulsewidth_us(obj, ms * 1000);
<> 144:ef7eb2e8f9f7 159 }
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
<> 144:ef7eb2e8f9f7 162 // calculate number of ticks
<> 144:ef7eb2e8f9f7 163 uint32_t v = pwm_clock_mhz * us;
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
<> 144:ef7eb2e8f9f7 166 if (v == LPC_PWM1->MR0) {
<> 144:ef7eb2e8f9f7 167 v++;
<> 144:ef7eb2e8f9f7 168 }
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 // set the match register value
<> 144:ef7eb2e8f9f7 171 *obj->MR = v;
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 // set the channel latch to update value at next period start
<> 144:ef7eb2e8f9f7 174 LPC_PWM1->LER |= 1 << obj->pwm;
<> 144:ef7eb2e8f9f7 175 }