Cortney Padua / mbed-dev

fixed drive strength

Dependents:   capstone_i2c

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32600/i2c_api.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/hal/TARGET_Maxim/TARGET_MAX32610/i2c_api.c@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 35 #include "i2c_api.h"
<> 144:ef7eb2e8f9f7 36 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 37 #include "i2cm_regs.h"
<> 144:ef7eb2e8f9f7 38 #include "clkman_regs.h"
<> 144:ef7eb2e8f9f7 39 #include "ioman_regs.h"
<> 144:ef7eb2e8f9f7 40 #include "PeripheralPins.h"
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #define I2C_SLAVE_ADDR_READ_BIT 0x0001
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 #ifndef MXC_I2CM_TX_TIMEOUT
<> 144:ef7eb2e8f9f7 45 #define MXC_I2CM_TX_TIMEOUT 0x5000
<> 144:ef7eb2e8f9f7 46 #endif
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 #ifndef MXC_I2CM_RX_TIMEOUT
<> 144:ef7eb2e8f9f7 49 #define MXC_I2CM_RX_TIMEOUT 0x5000
<> 144:ef7eb2e8f9f7 50 #endif
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 typedef enum {
<> 144:ef7eb2e8f9f7 53 /** 100KHz */
<> 144:ef7eb2e8f9f7 54 MXC_E_I2CM_SPEED_100KHZ = 0,
<> 144:ef7eb2e8f9f7 55 /** 400KHz */
<> 144:ef7eb2e8f9f7 56 MXC_E_I2CM_SPEED_400KHZ,
<> 144:ef7eb2e8f9f7 57 /** 1MHz */
<> 144:ef7eb2e8f9f7 58 MXC_E_I2CM_SPEED_1MHZ
<> 144:ef7eb2e8f9f7 59 } i2cm_speed_t;
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /* Clock divider lookup table */
<> 144:ef7eb2e8f9f7 62 static const uint32_t clk_div_table[3][8] = {
<> 144:ef7eb2e8f9f7 63 /* MXC_E_I2CM_SPEED_100KHZ */
<> 144:ef7eb2e8f9f7 64 {
<> 144:ef7eb2e8f9f7 65 /* 0: */ 0, /* not supported */
<> 144:ef7eb2e8f9f7 66 /* 1: 6MHz */ (( 3 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | ( 7 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 36 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
<> 144:ef7eb2e8f9f7 67 /* 2: 8MHz */ (( 4 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (10 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 48 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
<> 144:ef7eb2e8f9f7 68 /* 3: 12MHz */ (( 6 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (17 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 72 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
<> 144:ef7eb2e8f9f7 69 /* 4: 16MHz */ (( 8 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (24 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 96 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
<> 144:ef7eb2e8f9f7 70 /* 5: */ 0, /* not supported */
<> 144:ef7eb2e8f9f7 71 /* 6: */ 0, /* not supported */
<> 144:ef7eb2e8f9f7 72 /* 7: 24MHz */ ((12 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (38 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (144 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
<> 144:ef7eb2e8f9f7 73 },
<> 144:ef7eb2e8f9f7 74 /* MXC_E_I2CM_SPEED_400KHZ */
<> 144:ef7eb2e8f9f7 75 {
<> 144:ef7eb2e8f9f7 76 /* 0: */ 0, /* not supported */
<> 144:ef7eb2e8f9f7 77 /* 1: */ 0, /* not supported */
<> 144:ef7eb2e8f9f7 78 /* 2: */ 0, /* not supported */
<> 144:ef7eb2e8f9f7 79 /* 3: 12MHz */ ((2 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (1 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (18 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
<> 144:ef7eb2e8f9f7 80 /* 4: 16MHz */ ((2 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (2 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (24 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
<> 144:ef7eb2e8f9f7 81 /* 5: */ 0, /* not supported */
<> 144:ef7eb2e8f9f7 82 /* 6: */ 0, /* not supported */
<> 144:ef7eb2e8f9f7 83 /* 7: 24MHz */ ((3 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (5 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (36 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
<> 144:ef7eb2e8f9f7 84 },
<> 144:ef7eb2e8f9f7 85 /* MXC_E_I2CM_SPEED_1MHZ */
<> 144:ef7eb2e8f9f7 86 {
<> 144:ef7eb2e8f9f7 87 /* 0: */ 0, /* not supported */
<> 144:ef7eb2e8f9f7 88 /* 1: */ 0, /* not supported */
<> 144:ef7eb2e8f9f7 89 /* 2: */ 0, /* not supported */
<> 144:ef7eb2e8f9f7 90 /* 3: */ 0, /* not supported */
<> 144:ef7eb2e8f9f7 91 /* 4: */ 0, /* not supported */
<> 144:ef7eb2e8f9f7 92 /* 5: */ 0, /* not supported */
<> 144:ef7eb2e8f9f7 93 /* 6: */ 0, /* not supported */
<> 144:ef7eb2e8f9f7 94 /* 7: 24MHz */ ((1 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (0 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (14 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
<> 144:ef7eb2e8f9f7 95 },
<> 144:ef7eb2e8f9f7 96 };
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
<> 144:ef7eb2e8f9f7 99 {
<> 144:ef7eb2e8f9f7 100 // determine the I2C to use
<> 144:ef7eb2e8f9f7 101 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
<> 144:ef7eb2e8f9f7 102 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
<> 144:ef7eb2e8f9f7 103 mxc_i2cm_regs_t *i2c = (mxc_i2cm_regs_t*)pinmap_merge(i2c_sda, i2c_scl);
<> 144:ef7eb2e8f9f7 104 MBED_ASSERT((int)i2c != NC);
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 obj->i2c = i2c;
<> 144:ef7eb2e8f9f7 107 obj->txfifo = (uint16_t*)MXC_I2CM_GET_BASE_TX_FIFO(MXC_I2CM_BASE_TO_INSTANCE(i2c));
<> 144:ef7eb2e8f9f7 108 obj->rxfifo = (uint16_t*)MXC_I2CM_GET_BASE_RX_FIFO(MXC_I2CM_BASE_TO_INSTANCE(i2c));
<> 144:ef7eb2e8f9f7 109 obj->start_pending = 0;
<> 144:ef7eb2e8f9f7 110 obj->stop_pending = 0;
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 // configure the pins
<> 144:ef7eb2e8f9f7 113 pinmap_pinout(sda, PinMap_I2C_SDA);
<> 144:ef7eb2e8f9f7 114 pinmap_pinout(scl, PinMap_I2C_SCL);
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 // enable the clock
<> 144:ef7eb2e8f9f7 117 MXC_CLKMAN->clk_ctrl_6_i2cm = MXC_E_CLKMAN_CLK_SCALE_ENABLED;
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 // reset module
<> 144:ef7eb2e8f9f7 120 i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
<> 144:ef7eb2e8f9f7 121 i2c->ctrl = 0;
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 // set default frequency at 100k
<> 144:ef7eb2e8f9f7 124 i2c_frequency(obj, 100000);
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 // set timeout to 255 ms and turn on the auto-stop option
<> 144:ef7eb2e8f9f7 127 i2c->timeout = (0xFF << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS) | MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN;
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 // enable tx_fifo and rx_fifo
<> 144:ef7eb2e8f9f7 130 i2c->ctrl |= (MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN);
<> 144:ef7eb2e8f9f7 131 }
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 void i2c_frequency(i2c_t *obj, int hz)
<> 144:ef7eb2e8f9f7 134 {
<> 144:ef7eb2e8f9f7 135 // compute clock array index
<> 144:ef7eb2e8f9f7 136 int clki = ((SystemCoreClock + 1500000) / 3000000) - 1;
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 // get clock divider settings from lookup table
<> 144:ef7eb2e8f9f7 139 if ((hz < 400000) && (clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki] > 0)) {
<> 144:ef7eb2e8f9f7 140 obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki];
<> 144:ef7eb2e8f9f7 141 } else if ((hz < 1000000) && (clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki] > 0)) {
<> 144:ef7eb2e8f9f7 142 obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki];
<> 144:ef7eb2e8f9f7 143 } else if ((hz >= 1000000) && (clk_div_table[MXC_E_I2CM_SPEED_1MHZ][clki] > 0)) {
<> 144:ef7eb2e8f9f7 144 obj->i2c->hs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_1MHZ][clki];
<> 144:ef7eb2e8f9f7 145 }
<> 144:ef7eb2e8f9f7 146 }
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 static int write_tx_fifo(i2c_t *obj, const uint16_t data)
<> 144:ef7eb2e8f9f7 149 {
<> 144:ef7eb2e8f9f7 150 int timeout = MXC_I2CM_TX_TIMEOUT;
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 while (*obj->txfifo) {
<> 144:ef7eb2e8f9f7 153 uint32_t intfl = obj->i2c->intfl;
<> 144:ef7eb2e8f9f7 154 if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
<> 144:ef7eb2e8f9f7 155 return I2C_ERROR_NO_SLAVE;
<> 144:ef7eb2e8f9f7 156 }
<> 144:ef7eb2e8f9f7 157 if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) {
<> 144:ef7eb2e8f9f7 158 return I2C_ERROR_BUS_BUSY;
<> 144:ef7eb2e8f9f7 159 }
<> 144:ef7eb2e8f9f7 160 timeout--;
<> 144:ef7eb2e8f9f7 161 }
<> 144:ef7eb2e8f9f7 162 *obj->txfifo = data;
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 return 0;
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 static int wait_tx_in_progress(i2c_t *obj)
<> 144:ef7eb2e8f9f7 168 {
<> 144:ef7eb2e8f9f7 169 int timeout = MXC_I2CM_TX_TIMEOUT;
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 while ((obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS) && --timeout);
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 uint32_t intfl = obj->i2c->intfl;
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
<> 144:ef7eb2e8f9f7 176 i2c_reset(obj);
<> 144:ef7eb2e8f9f7 177 return I2C_ERROR_NO_SLAVE;
<> 144:ef7eb2e8f9f7 178 }
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) {
<> 144:ef7eb2e8f9f7 181 i2c_reset(obj);
<> 144:ef7eb2e8f9f7 182 return I2C_ERROR_BUS_BUSY;
<> 144:ef7eb2e8f9f7 183 }
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 return 0;
<> 144:ef7eb2e8f9f7 186 }
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 int i2c_start(i2c_t *obj)
<> 144:ef7eb2e8f9f7 189 {
<> 144:ef7eb2e8f9f7 190 obj->start_pending = 1;
<> 144:ef7eb2e8f9f7 191 return 0;
<> 144:ef7eb2e8f9f7 192 }
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 int i2c_stop(i2c_t *obj)
<> 144:ef7eb2e8f9f7 195 {
<> 144:ef7eb2e8f9f7 196 obj->start_pending = 0;
<> 144:ef7eb2e8f9f7 197 write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP);
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 return wait_tx_in_progress(obj);
<> 144:ef7eb2e8f9f7 200 }
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 void i2c_reset(i2c_t *obj)
<> 144:ef7eb2e8f9f7 203 {
<> 144:ef7eb2e8f9f7 204 obj->i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
<> 144:ef7eb2e8f9f7 205 obj->i2c->intfl = 0x3FF; // clear all interrupts
<> 144:ef7eb2e8f9f7 206 obj->i2c->ctrl = MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN;
<> 144:ef7eb2e8f9f7 207 obj->start_pending = 0;
<> 144:ef7eb2e8f9f7 208 }
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 int i2c_byte_write(i2c_t *obj, int data)
<> 144:ef7eb2e8f9f7 211 {
<> 144:ef7eb2e8f9f7 212 int err;
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 // clear all interrupts
<> 144:ef7eb2e8f9f7 215 obj->i2c->intfl = 0x3FF;
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 if (obj->start_pending) {
<> 144:ef7eb2e8f9f7 218 obj->start_pending = 0;
<> 144:ef7eb2e8f9f7 219 data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_START;
<> 144:ef7eb2e8f9f7 220 } else {
<> 144:ef7eb2e8f9f7 221 data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_TXDATA_ACK;
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 if ((err = write_tx_fifo(obj, data)) != 0) {
<> 144:ef7eb2e8f9f7 225 return err;
<> 144:ef7eb2e8f9f7 226 }
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 // Wait for the FIFO to be empty
<> 144:ef7eb2e8f9f7 231 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY));
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 if (obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
<> 144:ef7eb2e8f9f7 234 i2c_reset(obj);
<> 144:ef7eb2e8f9f7 235 return 0;
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 if (obj->i2c->intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR)) {
<> 144:ef7eb2e8f9f7 239 i2c_reset(obj);
<> 144:ef7eb2e8f9f7 240 return 2;
<> 144:ef7eb2e8f9f7 241 }
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 return 1;
<> 144:ef7eb2e8f9f7 244 }
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 int i2c_byte_read(i2c_t *obj, int last)
<> 144:ef7eb2e8f9f7 247 {
<> 144:ef7eb2e8f9f7 248 uint16_t fifo_value;
<> 144:ef7eb2e8f9f7 249 int err;
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 // clear all interrupts
<> 144:ef7eb2e8f9f7 252 obj->i2c->intfl = 0x3FF;
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 if (last) {
<> 144:ef7eb2e8f9f7 255 fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_NACK;
<> 144:ef7eb2e8f9f7 256 } else {
<> 144:ef7eb2e8f9f7 257 fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT;
<> 144:ef7eb2e8f9f7 258 }
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 if ((err = write_tx_fifo(obj, fifo_value)) != 0) {
<> 144:ef7eb2e8f9f7 261 i2c_reset(obj);
<> 144:ef7eb2e8f9f7 262 return err;
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 int timeout = MXC_I2CM_RX_TIMEOUT;
<> 144:ef7eb2e8f9f7 268 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
<> 144:ef7eb2e8f9f7 269 (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) {
<> 144:ef7eb2e8f9f7 270 if ((--timeout < 0) || (obj->i2c->trans & (MXC_F_I2CM_TRANS_TX_TIMEOUT |
<> 144:ef7eb2e8f9f7 271 MXC_F_I2CM_TRANS_TX_LOST_ARBITR | MXC_F_I2CM_TRANS_TX_NACKED))) {
<> 144:ef7eb2e8f9f7 272 break;
<> 144:ef7eb2e8f9f7 273 }
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 if (obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) {
<> 144:ef7eb2e8f9f7 277 obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
<> 144:ef7eb2e8f9f7 278 return *obj->rxfifo;
<> 144:ef7eb2e8f9f7 279 }
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 i2c_reset(obj);
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 return -1;
<> 144:ef7eb2e8f9f7 284 }
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
<> 144:ef7eb2e8f9f7 287 {
<> 144:ef7eb2e8f9f7 288 int err, retval = 0;
<> 144:ef7eb2e8f9f7 289 int i;
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
<> 144:ef7eb2e8f9f7 292 return 0;
<> 144:ef7eb2e8f9f7 293 }
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 // clear all interrupts
<> 144:ef7eb2e8f9f7 296 obj->i2c->intfl = 0x3FF;
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 // write the address to the fifo
<> 144:ef7eb2e8f9f7 299 if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address))) != 0) { // start + addr (write)
<> 144:ef7eb2e8f9f7 300 i2c_reset(obj);
<> 144:ef7eb2e8f9f7 301 return err;
<> 144:ef7eb2e8f9f7 302 }
<> 144:ef7eb2e8f9f7 303 obj->start_pending = 0;
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 // start the transaction
<> 144:ef7eb2e8f9f7 306 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 // load as much of the cmd into the FIFO as possible
<> 144:ef7eb2e8f9f7 309 for (i = 0; i < length; i++) {
<> 144:ef7eb2e8f9f7 310 if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | data[i]))) != 0) { // cmd (expect ACK)
<> 144:ef7eb2e8f9f7 311 retval = (retval ? retval : err);
<> 144:ef7eb2e8f9f7 312 break;
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 if (stop) {
<> 144:ef7eb2e8f9f7 317 obj->stop_pending = 0;
<> 144:ef7eb2e8f9f7 318 if ((err = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
<> 144:ef7eb2e8f9f7 319 retval = (retval ? retval : err);
<> 144:ef7eb2e8f9f7 320 }
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 if ((err = wait_tx_in_progress(obj)) != 0) {
<> 144:ef7eb2e8f9f7 323 retval = (retval ? retval : err);
<> 144:ef7eb2e8f9f7 324 }
<> 144:ef7eb2e8f9f7 325 } else {
<> 144:ef7eb2e8f9f7 326 obj->stop_pending = 1;
<> 144:ef7eb2e8f9f7 327 int timeout = MXC_I2CM_TX_TIMEOUT;
<> 144:ef7eb2e8f9f7 328 // Wait for TX fifo to be empty
<> 144:ef7eb2e8f9f7 329 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY) && timeout--);
<> 144:ef7eb2e8f9f7 330 }
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 if (retval == 0) {
<> 144:ef7eb2e8f9f7 333 return length;
<> 144:ef7eb2e8f9f7 334 }
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 i2c_reset(obj);
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 return retval;
<> 144:ef7eb2e8f9f7 339 }
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
<> 144:ef7eb2e8f9f7 342 {
<> 144:ef7eb2e8f9f7 343 int err, retval = 0;
<> 144:ef7eb2e8f9f7 344 int i = length;
<> 144:ef7eb2e8f9f7 345 int timeout;
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
<> 144:ef7eb2e8f9f7 348 return 0;
<> 144:ef7eb2e8f9f7 349 }
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 // clear all interrupts
<> 144:ef7eb2e8f9f7 352 obj->i2c->intfl = 0x3FF;
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 // start + addr (read)
<> 144:ef7eb2e8f9f7 355 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address | I2C_SLAVE_ADDR_READ_BIT))) != 0) {
<> 144:ef7eb2e8f9f7 356 goto read_done;
<> 144:ef7eb2e8f9f7 357 }
<> 144:ef7eb2e8f9f7 358 obj->start_pending = 0;
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 while (i > 256) {
<> 144:ef7eb2e8f9f7 361 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | 255))) != 0) {
<> 144:ef7eb2e8f9f7 362 goto read_done;
<> 144:ef7eb2e8f9f7 363 }
<> 144:ef7eb2e8f9f7 364 i -= 256;
<> 144:ef7eb2e8f9f7 365 }
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 if (i > 1) {
<> 144:ef7eb2e8f9f7 368 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | (i - 2)))) != 0) {
<> 144:ef7eb2e8f9f7 369 goto read_done;
<> 144:ef7eb2e8f9f7 370 }
<> 144:ef7eb2e8f9f7 371 }
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 // start the transaction
<> 144:ef7eb2e8f9f7 374 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_RXDATA_NACK)) != 0) { // NACK last data byte
<> 144:ef7eb2e8f9f7 377 goto read_done;
<> 144:ef7eb2e8f9f7 378 }
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 if (stop) {
<> 144:ef7eb2e8f9f7 381 if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
<> 144:ef7eb2e8f9f7 382 goto read_done;
<> 144:ef7eb2e8f9f7 383 }
<> 144:ef7eb2e8f9f7 384 }
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 timeout = MXC_I2CM_RX_TIMEOUT;
<> 144:ef7eb2e8f9f7 387 i = 0;
<> 144:ef7eb2e8f9f7 388 while (i < length) {
<> 144:ef7eb2e8f9f7 389 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
<> 144:ef7eb2e8f9f7 390 (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) {
<> 144:ef7eb2e8f9f7 391 if ((--timeout < 0) || (obj->i2c->trans & (MXC_F_I2CM_TRANS_TX_TIMEOUT |
<> 144:ef7eb2e8f9f7 392 MXC_F_I2CM_TRANS_TX_LOST_ARBITR | MXC_F_I2CM_TRANS_TX_NACKED))) {
<> 144:ef7eb2e8f9f7 393 retval = -3;
<> 144:ef7eb2e8f9f7 394 goto read_done;
<> 144:ef7eb2e8f9f7 395 }
<> 144:ef7eb2e8f9f7 396 }
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 timeout = MXC_I2CM_RX_TIMEOUT;
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 uint16_t temp = *obj->rxfifo;
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 if (temp & MXC_S_I2CM_RSTLS_TAG_EMPTY) {
<> 144:ef7eb2e8f9f7 405 continue;
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407 data[i++] = (uint8_t) temp;
<> 144:ef7eb2e8f9f7 408 }
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 read_done:
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 if (stop) {
<> 144:ef7eb2e8f9f7 413 obj->stop_pending = 0;
<> 144:ef7eb2e8f9f7 414 if ((err = wait_tx_in_progress(obj)) != 0) {
<> 144:ef7eb2e8f9f7 415 retval = (retval ? retval : err);
<> 144:ef7eb2e8f9f7 416 }
<> 144:ef7eb2e8f9f7 417 } else {
<> 144:ef7eb2e8f9f7 418 obj->stop_pending = 1;
<> 144:ef7eb2e8f9f7 419 }
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 if (retval == 0) {
<> 144:ef7eb2e8f9f7 422 return length;
<> 144:ef7eb2e8f9f7 423 }
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 i2c_reset(obj);
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 return retval;
<> 144:ef7eb2e8f9f7 428 }