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cmsis/core_sc000.h@0:fb7af294d5d9, 2016-11-17 (annotated)

Committer:
Simon Cooksey
Date:
Thu Nov 17 16:43:53 2016 +0000
Revision:
0:fb7af294d5d9
Initial commit

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Simon Cooksey 0:fb7af294d5d9 1 /**************************************************************************//**
Simon Cooksey 0:fb7af294d5d9 2 * @file core_sc000.h
Simon Cooksey 0:fb7af294d5d9 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
Simon Cooksey 0:fb7af294d5d9 4 * @version V4.10
Simon Cooksey 0:fb7af294d5d9 5 * @date 18. March 2015
Simon Cooksey 0:fb7af294d5d9 6 *
Simon Cooksey 0:fb7af294d5d9 7 * @note
Simon Cooksey 0:fb7af294d5d9 8 *
Simon Cooksey 0:fb7af294d5d9 9 ******************************************************************************/
Simon Cooksey 0:fb7af294d5d9 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Simon Cooksey 0:fb7af294d5d9 11
Simon Cooksey 0:fb7af294d5d9 12 All rights reserved.
Simon Cooksey 0:fb7af294d5d9 13 Redistribution and use in source and binary forms, with or without
Simon Cooksey 0:fb7af294d5d9 14 modification, are permitted provided that the following conditions are met:
Simon Cooksey 0:fb7af294d5d9 15 - Redistributions of source code must retain the above copyright
Simon Cooksey 0:fb7af294d5d9 16 notice, this list of conditions and the following disclaimer.
Simon Cooksey 0:fb7af294d5d9 17 - Redistributions in binary form must reproduce the above copyright
Simon Cooksey 0:fb7af294d5d9 18 notice, this list of conditions and the following disclaimer in the
Simon Cooksey 0:fb7af294d5d9 19 documentation and/or other materials provided with the distribution.
Simon Cooksey 0:fb7af294d5d9 20 - Neither the name of ARM nor the names of its contributors may be used
Simon Cooksey 0:fb7af294d5d9 21 to endorse or promote products derived from this software without
Simon Cooksey 0:fb7af294d5d9 22 specific prior written permission.
Simon Cooksey 0:fb7af294d5d9 23 *
Simon Cooksey 0:fb7af294d5d9 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Simon Cooksey 0:fb7af294d5d9 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Simon Cooksey 0:fb7af294d5d9 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Simon Cooksey 0:fb7af294d5d9 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Simon Cooksey 0:fb7af294d5d9 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Simon Cooksey 0:fb7af294d5d9 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Simon Cooksey 0:fb7af294d5d9 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Simon Cooksey 0:fb7af294d5d9 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Simon Cooksey 0:fb7af294d5d9 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Simon Cooksey 0:fb7af294d5d9 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Simon Cooksey 0:fb7af294d5d9 34 POSSIBILITY OF SUCH DAMAGE.
Simon Cooksey 0:fb7af294d5d9 35 ---------------------------------------------------------------------------*/
Simon Cooksey 0:fb7af294d5d9 36
Simon Cooksey 0:fb7af294d5d9 37
Simon Cooksey 0:fb7af294d5d9 38 #if defined ( __ICCARM__ )
Simon Cooksey 0:fb7af294d5d9 39 #pragma system_include /* treat file as system include file for MISRA check */
Simon Cooksey 0:fb7af294d5d9 40 #endif
Simon Cooksey 0:fb7af294d5d9 41
Simon Cooksey 0:fb7af294d5d9 42 #ifndef __CORE_SC000_H_GENERIC
Simon Cooksey 0:fb7af294d5d9 43 #define __CORE_SC000_H_GENERIC
Simon Cooksey 0:fb7af294d5d9 44
Simon Cooksey 0:fb7af294d5d9 45 #ifdef __cplusplus
Simon Cooksey 0:fb7af294d5d9 46 extern "C" {
Simon Cooksey 0:fb7af294d5d9 47 #endif
Simon Cooksey 0:fb7af294d5d9 48
Simon Cooksey 0:fb7af294d5d9 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Simon Cooksey 0:fb7af294d5d9 50 CMSIS violates the following MISRA-C:2004 rules:
Simon Cooksey 0:fb7af294d5d9 51
Simon Cooksey 0:fb7af294d5d9 52 \li Required Rule 8.5, object/function definition in header file.<br>
Simon Cooksey 0:fb7af294d5d9 53 Function definitions in header files are used to allow 'inlining'.
Simon Cooksey 0:fb7af294d5d9 54
Simon Cooksey 0:fb7af294d5d9 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Simon Cooksey 0:fb7af294d5d9 56 Unions are used for effective representation of core registers.
Simon Cooksey 0:fb7af294d5d9 57
Simon Cooksey 0:fb7af294d5d9 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Simon Cooksey 0:fb7af294d5d9 59 Function-like macros are used to allow more efficient code.
Simon Cooksey 0:fb7af294d5d9 60 */
Simon Cooksey 0:fb7af294d5d9 61
Simon Cooksey 0:fb7af294d5d9 62
Simon Cooksey 0:fb7af294d5d9 63 /*******************************************************************************
Simon Cooksey 0:fb7af294d5d9 64 * CMSIS definitions
Simon Cooksey 0:fb7af294d5d9 65 ******************************************************************************/
Simon Cooksey 0:fb7af294d5d9 66 /** \ingroup SC000
Simon Cooksey 0:fb7af294d5d9 67 @{
Simon Cooksey 0:fb7af294d5d9 68 */
Simon Cooksey 0:fb7af294d5d9 69
Simon Cooksey 0:fb7af294d5d9 70 /* CMSIS SC000 definitions */
Simon Cooksey 0:fb7af294d5d9 71 #define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Simon Cooksey 0:fb7af294d5d9 72 #define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Simon Cooksey 0:fb7af294d5d9 73 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
Simon Cooksey 0:fb7af294d5d9 74 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Simon Cooksey 0:fb7af294d5d9 75
Simon Cooksey 0:fb7af294d5d9 76 #define __CORTEX_SC (000) /*!< Cortex secure core */
Simon Cooksey 0:fb7af294d5d9 77
Simon Cooksey 0:fb7af294d5d9 78
Simon Cooksey 0:fb7af294d5d9 79 #if defined ( __CC_ARM )
Simon Cooksey 0:fb7af294d5d9 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Simon Cooksey 0:fb7af294d5d9 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Simon Cooksey 0:fb7af294d5d9 82 #define __STATIC_INLINE static __inline
Simon Cooksey 0:fb7af294d5d9 83
Simon Cooksey 0:fb7af294d5d9 84 #elif defined ( __GNUC__ )
Simon Cooksey 0:fb7af294d5d9 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Simon Cooksey 0:fb7af294d5d9 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Simon Cooksey 0:fb7af294d5d9 87 #define __STATIC_INLINE static inline
Simon Cooksey 0:fb7af294d5d9 88
Simon Cooksey 0:fb7af294d5d9 89 #elif defined ( __ICCARM__ )
Simon Cooksey 0:fb7af294d5d9 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Simon Cooksey 0:fb7af294d5d9 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Simon Cooksey 0:fb7af294d5d9 92 #define __STATIC_INLINE static inline
Simon Cooksey 0:fb7af294d5d9 93
Simon Cooksey 0:fb7af294d5d9 94 #elif defined ( __TMS470__ )
Simon Cooksey 0:fb7af294d5d9 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Simon Cooksey 0:fb7af294d5d9 96 #define __STATIC_INLINE static inline
Simon Cooksey 0:fb7af294d5d9 97
Simon Cooksey 0:fb7af294d5d9 98 #elif defined ( __TASKING__ )
Simon Cooksey 0:fb7af294d5d9 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Simon Cooksey 0:fb7af294d5d9 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Simon Cooksey 0:fb7af294d5d9 101 #define __STATIC_INLINE static inline
Simon Cooksey 0:fb7af294d5d9 102
Simon Cooksey 0:fb7af294d5d9 103 #elif defined ( __CSMC__ )
Simon Cooksey 0:fb7af294d5d9 104 #define __packed
Simon Cooksey 0:fb7af294d5d9 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Simon Cooksey 0:fb7af294d5d9 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Simon Cooksey 0:fb7af294d5d9 107 #define __STATIC_INLINE static inline
Simon Cooksey 0:fb7af294d5d9 108
Simon Cooksey 0:fb7af294d5d9 109 #endif
Simon Cooksey 0:fb7af294d5d9 110
Simon Cooksey 0:fb7af294d5d9 111 /** __FPU_USED indicates whether an FPU is used or not.
Simon Cooksey 0:fb7af294d5d9 112 This core does not support an FPU at all
Simon Cooksey 0:fb7af294d5d9 113 */
Simon Cooksey 0:fb7af294d5d9 114 #define __FPU_USED 0
Simon Cooksey 0:fb7af294d5d9 115
Simon Cooksey 0:fb7af294d5d9 116 #if defined ( __CC_ARM )
Simon Cooksey 0:fb7af294d5d9 117 #if defined __TARGET_FPU_VFP
Simon Cooksey 0:fb7af294d5d9 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Simon Cooksey 0:fb7af294d5d9 119 #endif
Simon Cooksey 0:fb7af294d5d9 120
Simon Cooksey 0:fb7af294d5d9 121 #elif defined ( __GNUC__ )
Simon Cooksey 0:fb7af294d5d9 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Simon Cooksey 0:fb7af294d5d9 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Simon Cooksey 0:fb7af294d5d9 124 #endif
Simon Cooksey 0:fb7af294d5d9 125
Simon Cooksey 0:fb7af294d5d9 126 #elif defined ( __ICCARM__ )
Simon Cooksey 0:fb7af294d5d9 127 #if defined __ARMVFP__
Simon Cooksey 0:fb7af294d5d9 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Simon Cooksey 0:fb7af294d5d9 129 #endif
Simon Cooksey 0:fb7af294d5d9 130
Simon Cooksey 0:fb7af294d5d9 131 #elif defined ( __TMS470__ )
Simon Cooksey 0:fb7af294d5d9 132 #if defined __TI__VFP_SUPPORT____
Simon Cooksey 0:fb7af294d5d9 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Simon Cooksey 0:fb7af294d5d9 134 #endif
Simon Cooksey 0:fb7af294d5d9 135
Simon Cooksey 0:fb7af294d5d9 136 #elif defined ( __TASKING__ )
Simon Cooksey 0:fb7af294d5d9 137 #if defined __FPU_VFP__
Simon Cooksey 0:fb7af294d5d9 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Simon Cooksey 0:fb7af294d5d9 139 #endif
Simon Cooksey 0:fb7af294d5d9 140
Simon Cooksey 0:fb7af294d5d9 141 #elif defined ( __CSMC__ ) /* Cosmic */
Simon Cooksey 0:fb7af294d5d9 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Simon Cooksey 0:fb7af294d5d9 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Simon Cooksey 0:fb7af294d5d9 144 #endif
Simon Cooksey 0:fb7af294d5d9 145 #endif
Simon Cooksey 0:fb7af294d5d9 146
Simon Cooksey 0:fb7af294d5d9 147 #include <stdint.h> /* standard types definitions */
Simon Cooksey 0:fb7af294d5d9 148 #include <core_cmInstr.h> /* Core Instruction Access */
Simon Cooksey 0:fb7af294d5d9 149 #include <core_cmFunc.h> /* Core Function Access */
Simon Cooksey 0:fb7af294d5d9 150
Simon Cooksey 0:fb7af294d5d9 151 #ifdef __cplusplus
Simon Cooksey 0:fb7af294d5d9 152 }
Simon Cooksey 0:fb7af294d5d9 153 #endif
Simon Cooksey 0:fb7af294d5d9 154
Simon Cooksey 0:fb7af294d5d9 155 #endif /* __CORE_SC000_H_GENERIC */
Simon Cooksey 0:fb7af294d5d9 156
Simon Cooksey 0:fb7af294d5d9 157 #ifndef __CMSIS_GENERIC
Simon Cooksey 0:fb7af294d5d9 158
Simon Cooksey 0:fb7af294d5d9 159 #ifndef __CORE_SC000_H_DEPENDANT
Simon Cooksey 0:fb7af294d5d9 160 #define __CORE_SC000_H_DEPENDANT
Simon Cooksey 0:fb7af294d5d9 161
Simon Cooksey 0:fb7af294d5d9 162 #ifdef __cplusplus
Simon Cooksey 0:fb7af294d5d9 163 extern "C" {
Simon Cooksey 0:fb7af294d5d9 164 #endif
Simon Cooksey 0:fb7af294d5d9 165
Simon Cooksey 0:fb7af294d5d9 166 /* check device defines and use defaults */
Simon Cooksey 0:fb7af294d5d9 167 #if defined __CHECK_DEVICE_DEFINES
Simon Cooksey 0:fb7af294d5d9 168 #ifndef __SC000_REV
Simon Cooksey 0:fb7af294d5d9 169 #define __SC000_REV 0x0000
Simon Cooksey 0:fb7af294d5d9 170 #warning "__SC000_REV not defined in device header file; using default!"
Simon Cooksey 0:fb7af294d5d9 171 #endif
Simon Cooksey 0:fb7af294d5d9 172
Simon Cooksey 0:fb7af294d5d9 173 #ifndef __MPU_PRESENT
Simon Cooksey 0:fb7af294d5d9 174 #define __MPU_PRESENT 0
Simon Cooksey 0:fb7af294d5d9 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
Simon Cooksey 0:fb7af294d5d9 176 #endif
Simon Cooksey 0:fb7af294d5d9 177
Simon Cooksey 0:fb7af294d5d9 178 #ifndef __NVIC_PRIO_BITS
Simon Cooksey 0:fb7af294d5d9 179 #define __NVIC_PRIO_BITS 2
Simon Cooksey 0:fb7af294d5d9 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Simon Cooksey 0:fb7af294d5d9 181 #endif
Simon Cooksey 0:fb7af294d5d9 182
Simon Cooksey 0:fb7af294d5d9 183 #ifndef __Vendor_SysTickConfig
Simon Cooksey 0:fb7af294d5d9 184 #define __Vendor_SysTickConfig 0
Simon Cooksey 0:fb7af294d5d9 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Simon Cooksey 0:fb7af294d5d9 186 #endif
Simon Cooksey 0:fb7af294d5d9 187 #endif
Simon Cooksey 0:fb7af294d5d9 188
Simon Cooksey 0:fb7af294d5d9 189 /* IO definitions (access restrictions to peripheral registers) */
Simon Cooksey 0:fb7af294d5d9 190 /**
Simon Cooksey 0:fb7af294d5d9 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
Simon Cooksey 0:fb7af294d5d9 192
Simon Cooksey 0:fb7af294d5d9 193 <strong>IO Type Qualifiers</strong> are used
Simon Cooksey 0:fb7af294d5d9 194 \li to specify the access to peripheral variables.
Simon Cooksey 0:fb7af294d5d9 195 \li for automatic generation of peripheral register debug information.
Simon Cooksey 0:fb7af294d5d9 196 */
Simon Cooksey 0:fb7af294d5d9 197 #ifdef __cplusplus
Simon Cooksey 0:fb7af294d5d9 198 #define __I volatile /*!< Defines 'read only' permissions */
Simon Cooksey 0:fb7af294d5d9 199 #else
Simon Cooksey 0:fb7af294d5d9 200 #define __I volatile const /*!< Defines 'read only' permissions */
Simon Cooksey 0:fb7af294d5d9 201 #endif
Simon Cooksey 0:fb7af294d5d9 202 #define __O volatile /*!< Defines 'write only' permissions */
Simon Cooksey 0:fb7af294d5d9 203 #define __IO volatile /*!< Defines 'read / write' permissions */
Simon Cooksey 0:fb7af294d5d9 204
Simon Cooksey 0:fb7af294d5d9 205 /*@} end of group SC000 */
Simon Cooksey 0:fb7af294d5d9 206
Simon Cooksey 0:fb7af294d5d9 207
Simon Cooksey 0:fb7af294d5d9 208
Simon Cooksey 0:fb7af294d5d9 209 /*******************************************************************************
Simon Cooksey 0:fb7af294d5d9 210 * Register Abstraction
Simon Cooksey 0:fb7af294d5d9 211 Core Register contain:
Simon Cooksey 0:fb7af294d5d9 212 - Core Register
Simon Cooksey 0:fb7af294d5d9 213 - Core NVIC Register
Simon Cooksey 0:fb7af294d5d9 214 - Core SCB Register
Simon Cooksey 0:fb7af294d5d9 215 - Core SysTick Register
Simon Cooksey 0:fb7af294d5d9 216 - Core MPU Register
Simon Cooksey 0:fb7af294d5d9 217 ******************************************************************************/
Simon Cooksey 0:fb7af294d5d9 218 /** \defgroup CMSIS_core_register Defines and Type Definitions
Simon Cooksey 0:fb7af294d5d9 219 \brief Type definitions and defines for Cortex-M processor based devices.
Simon Cooksey 0:fb7af294d5d9 220 */
Simon Cooksey 0:fb7af294d5d9 221
Simon Cooksey 0:fb7af294d5d9 222 /** \ingroup CMSIS_core_register
Simon Cooksey 0:fb7af294d5d9 223 \defgroup CMSIS_CORE Status and Control Registers
Simon Cooksey 0:fb7af294d5d9 224 \brief Core Register type definitions.
Simon Cooksey 0:fb7af294d5d9 225 @{
Simon Cooksey 0:fb7af294d5d9 226 */
Simon Cooksey 0:fb7af294d5d9 227
Simon Cooksey 0:fb7af294d5d9 228 /** \brief Union type to access the Application Program Status Register (APSR).
Simon Cooksey 0:fb7af294d5d9 229 */
Simon Cooksey 0:fb7af294d5d9 230 typedef union
Simon Cooksey 0:fb7af294d5d9 231 {
Simon Cooksey 0:fb7af294d5d9 232 struct
Simon Cooksey 0:fb7af294d5d9 233 {
Simon Cooksey 0:fb7af294d5d9 234 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Simon Cooksey 0:fb7af294d5d9 235 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Simon Cooksey 0:fb7af294d5d9 236 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Simon Cooksey 0:fb7af294d5d9 237 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Simon Cooksey 0:fb7af294d5d9 238 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Simon Cooksey 0:fb7af294d5d9 239 } b; /*!< Structure used for bit access */
Simon Cooksey 0:fb7af294d5d9 240 uint32_t w; /*!< Type used for word access */
Simon Cooksey 0:fb7af294d5d9 241 } APSR_Type;
Simon Cooksey 0:fb7af294d5d9 242
Simon Cooksey 0:fb7af294d5d9 243 /* APSR Register Definitions */
Simon Cooksey 0:fb7af294d5d9 244 #define APSR_N_Pos 31 /*!< APSR: N Position */
Simon Cooksey 0:fb7af294d5d9 245 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Simon Cooksey 0:fb7af294d5d9 246
Simon Cooksey 0:fb7af294d5d9 247 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Simon Cooksey 0:fb7af294d5d9 248 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Simon Cooksey 0:fb7af294d5d9 249
Simon Cooksey 0:fb7af294d5d9 250 #define APSR_C_Pos 29 /*!< APSR: C Position */
Simon Cooksey 0:fb7af294d5d9 251 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Simon Cooksey 0:fb7af294d5d9 252
Simon Cooksey 0:fb7af294d5d9 253 #define APSR_V_Pos 28 /*!< APSR: V Position */
Simon Cooksey 0:fb7af294d5d9 254 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Simon Cooksey 0:fb7af294d5d9 255
Simon Cooksey 0:fb7af294d5d9 256
Simon Cooksey 0:fb7af294d5d9 257 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Simon Cooksey 0:fb7af294d5d9 258 */
Simon Cooksey 0:fb7af294d5d9 259 typedef union
Simon Cooksey 0:fb7af294d5d9 260 {
Simon Cooksey 0:fb7af294d5d9 261 struct
Simon Cooksey 0:fb7af294d5d9 262 {
Simon Cooksey 0:fb7af294d5d9 263 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Simon Cooksey 0:fb7af294d5d9 264 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Simon Cooksey 0:fb7af294d5d9 265 } b; /*!< Structure used for bit access */
Simon Cooksey 0:fb7af294d5d9 266 uint32_t w; /*!< Type used for word access */
Simon Cooksey 0:fb7af294d5d9 267 } IPSR_Type;
Simon Cooksey 0:fb7af294d5d9 268
Simon Cooksey 0:fb7af294d5d9 269 /* IPSR Register Definitions */
Simon Cooksey 0:fb7af294d5d9 270 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Simon Cooksey 0:fb7af294d5d9 271 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Simon Cooksey 0:fb7af294d5d9 272
Simon Cooksey 0:fb7af294d5d9 273
Simon Cooksey 0:fb7af294d5d9 274 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Simon Cooksey 0:fb7af294d5d9 275 */
Simon Cooksey 0:fb7af294d5d9 276 typedef union
Simon Cooksey 0:fb7af294d5d9 277 {
Simon Cooksey 0:fb7af294d5d9 278 struct
Simon Cooksey 0:fb7af294d5d9 279 {
Simon Cooksey 0:fb7af294d5d9 280 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Simon Cooksey 0:fb7af294d5d9 281 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Simon Cooksey 0:fb7af294d5d9 282 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Simon Cooksey 0:fb7af294d5d9 283 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Simon Cooksey 0:fb7af294d5d9 284 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Simon Cooksey 0:fb7af294d5d9 285 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Simon Cooksey 0:fb7af294d5d9 286 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Simon Cooksey 0:fb7af294d5d9 287 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Simon Cooksey 0:fb7af294d5d9 288 } b; /*!< Structure used for bit access */
Simon Cooksey 0:fb7af294d5d9 289 uint32_t w; /*!< Type used for word access */
Simon Cooksey 0:fb7af294d5d9 290 } xPSR_Type;
Simon Cooksey 0:fb7af294d5d9 291
Simon Cooksey 0:fb7af294d5d9 292 /* xPSR Register Definitions */
Simon Cooksey 0:fb7af294d5d9 293 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Simon Cooksey 0:fb7af294d5d9 294 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Simon Cooksey 0:fb7af294d5d9 295
Simon Cooksey 0:fb7af294d5d9 296 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Simon Cooksey 0:fb7af294d5d9 297 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Simon Cooksey 0:fb7af294d5d9 298
Simon Cooksey 0:fb7af294d5d9 299 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Simon Cooksey 0:fb7af294d5d9 300 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Simon Cooksey 0:fb7af294d5d9 301
Simon Cooksey 0:fb7af294d5d9 302 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Simon Cooksey 0:fb7af294d5d9 303 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Simon Cooksey 0:fb7af294d5d9 304
Simon Cooksey 0:fb7af294d5d9 305 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Simon Cooksey 0:fb7af294d5d9 306 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Simon Cooksey 0:fb7af294d5d9 307
Simon Cooksey 0:fb7af294d5d9 308 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Simon Cooksey 0:fb7af294d5d9 309 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Simon Cooksey 0:fb7af294d5d9 310
Simon Cooksey 0:fb7af294d5d9 311
Simon Cooksey 0:fb7af294d5d9 312 /** \brief Union type to access the Control Registers (CONTROL).
Simon Cooksey 0:fb7af294d5d9 313 */
Simon Cooksey 0:fb7af294d5d9 314 typedef union
Simon Cooksey 0:fb7af294d5d9 315 {
Simon Cooksey 0:fb7af294d5d9 316 struct
Simon Cooksey 0:fb7af294d5d9 317 {
Simon Cooksey 0:fb7af294d5d9 318 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
Simon Cooksey 0:fb7af294d5d9 319 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Simon Cooksey 0:fb7af294d5d9 320 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Simon Cooksey 0:fb7af294d5d9 321 } b; /*!< Structure used for bit access */
Simon Cooksey 0:fb7af294d5d9 322 uint32_t w; /*!< Type used for word access */
Simon Cooksey 0:fb7af294d5d9 323 } CONTROL_Type;
Simon Cooksey 0:fb7af294d5d9 324
Simon Cooksey 0:fb7af294d5d9 325 /* CONTROL Register Definitions */
Simon Cooksey 0:fb7af294d5d9 326 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Simon Cooksey 0:fb7af294d5d9 327 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Simon Cooksey 0:fb7af294d5d9 328
Simon Cooksey 0:fb7af294d5d9 329 /*@} end of group CMSIS_CORE */
Simon Cooksey 0:fb7af294d5d9 330
Simon Cooksey 0:fb7af294d5d9 331
Simon Cooksey 0:fb7af294d5d9 332 /** \ingroup CMSIS_core_register
Simon Cooksey 0:fb7af294d5d9 333 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Simon Cooksey 0:fb7af294d5d9 334 \brief Type definitions for the NVIC Registers
Simon Cooksey 0:fb7af294d5d9 335 @{
Simon Cooksey 0:fb7af294d5d9 336 */
Simon Cooksey 0:fb7af294d5d9 337
Simon Cooksey 0:fb7af294d5d9 338 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Simon Cooksey 0:fb7af294d5d9 339 */
Simon Cooksey 0:fb7af294d5d9 340 typedef struct
Simon Cooksey 0:fb7af294d5d9 341 {
Simon Cooksey 0:fb7af294d5d9 342 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Simon Cooksey 0:fb7af294d5d9 343 uint32_t RESERVED0[31];
Simon Cooksey 0:fb7af294d5d9 344 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Simon Cooksey 0:fb7af294d5d9 345 uint32_t RSERVED1[31];
Simon Cooksey 0:fb7af294d5d9 346 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Simon Cooksey 0:fb7af294d5d9 347 uint32_t RESERVED2[31];
Simon Cooksey 0:fb7af294d5d9 348 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Simon Cooksey 0:fb7af294d5d9 349 uint32_t RESERVED3[31];
Simon Cooksey 0:fb7af294d5d9 350 uint32_t RESERVED4[64];
Simon Cooksey 0:fb7af294d5d9 351 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Simon Cooksey 0:fb7af294d5d9 352 } NVIC_Type;
Simon Cooksey 0:fb7af294d5d9 353
Simon Cooksey 0:fb7af294d5d9 354 /*@} end of group CMSIS_NVIC */
Simon Cooksey 0:fb7af294d5d9 355
Simon Cooksey 0:fb7af294d5d9 356
Simon Cooksey 0:fb7af294d5d9 357 /** \ingroup CMSIS_core_register
Simon Cooksey 0:fb7af294d5d9 358 \defgroup CMSIS_SCB System Control Block (SCB)
Simon Cooksey 0:fb7af294d5d9 359 \brief Type definitions for the System Control Block Registers
Simon Cooksey 0:fb7af294d5d9 360 @{
Simon Cooksey 0:fb7af294d5d9 361 */
Simon Cooksey 0:fb7af294d5d9 362
Simon Cooksey 0:fb7af294d5d9 363 /** \brief Structure type to access the System Control Block (SCB).
Simon Cooksey 0:fb7af294d5d9 364 */
Simon Cooksey 0:fb7af294d5d9 365 typedef struct
Simon Cooksey 0:fb7af294d5d9 366 {
Simon Cooksey 0:fb7af294d5d9 367 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Simon Cooksey 0:fb7af294d5d9 368 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Simon Cooksey 0:fb7af294d5d9 369 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Simon Cooksey 0:fb7af294d5d9 370 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Simon Cooksey 0:fb7af294d5d9 371 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Simon Cooksey 0:fb7af294d5d9 372 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Simon Cooksey 0:fb7af294d5d9 373 uint32_t RESERVED0[1];
Simon Cooksey 0:fb7af294d5d9 374 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Simon Cooksey 0:fb7af294d5d9 375 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Simon Cooksey 0:fb7af294d5d9 376 uint32_t RESERVED1[154];
Simon Cooksey 0:fb7af294d5d9 377 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
Simon Cooksey 0:fb7af294d5d9 378 } SCB_Type;
Simon Cooksey 0:fb7af294d5d9 379
Simon Cooksey 0:fb7af294d5d9 380 /* SCB CPUID Register Definitions */
Simon Cooksey 0:fb7af294d5d9 381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Simon Cooksey 0:fb7af294d5d9 382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Simon Cooksey 0:fb7af294d5d9 383
Simon Cooksey 0:fb7af294d5d9 384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Simon Cooksey 0:fb7af294d5d9 385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Simon Cooksey 0:fb7af294d5d9 386
Simon Cooksey 0:fb7af294d5d9 387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Simon Cooksey 0:fb7af294d5d9 388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Simon Cooksey 0:fb7af294d5d9 389
Simon Cooksey 0:fb7af294d5d9 390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Simon Cooksey 0:fb7af294d5d9 391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Simon Cooksey 0:fb7af294d5d9 392
Simon Cooksey 0:fb7af294d5d9 393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Simon Cooksey 0:fb7af294d5d9 394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Simon Cooksey 0:fb7af294d5d9 395
Simon Cooksey 0:fb7af294d5d9 396 /* SCB Interrupt Control State Register Definitions */
Simon Cooksey 0:fb7af294d5d9 397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Simon Cooksey 0:fb7af294d5d9 398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Simon Cooksey 0:fb7af294d5d9 399
Simon Cooksey 0:fb7af294d5d9 400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Simon Cooksey 0:fb7af294d5d9 401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Simon Cooksey 0:fb7af294d5d9 402
Simon Cooksey 0:fb7af294d5d9 403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Simon Cooksey 0:fb7af294d5d9 404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Simon Cooksey 0:fb7af294d5d9 405
Simon Cooksey 0:fb7af294d5d9 406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Simon Cooksey 0:fb7af294d5d9 407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Simon Cooksey 0:fb7af294d5d9 408
Simon Cooksey 0:fb7af294d5d9 409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Simon Cooksey 0:fb7af294d5d9 410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Simon Cooksey 0:fb7af294d5d9 411
Simon Cooksey 0:fb7af294d5d9 412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Simon Cooksey 0:fb7af294d5d9 413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Simon Cooksey 0:fb7af294d5d9 414
Simon Cooksey 0:fb7af294d5d9 415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Simon Cooksey 0:fb7af294d5d9 416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Simon Cooksey 0:fb7af294d5d9 417
Simon Cooksey 0:fb7af294d5d9 418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Simon Cooksey 0:fb7af294d5d9 419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Simon Cooksey 0:fb7af294d5d9 420
Simon Cooksey 0:fb7af294d5d9 421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Simon Cooksey 0:fb7af294d5d9 422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Simon Cooksey 0:fb7af294d5d9 423
Simon Cooksey 0:fb7af294d5d9 424 /* SCB Interrupt Control State Register Definitions */
Simon Cooksey 0:fb7af294d5d9 425 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
Simon Cooksey 0:fb7af294d5d9 426 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Simon Cooksey 0:fb7af294d5d9 427
Simon Cooksey 0:fb7af294d5d9 428 /* SCB Application Interrupt and Reset Control Register Definitions */
Simon Cooksey 0:fb7af294d5d9 429 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Simon Cooksey 0:fb7af294d5d9 430 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Simon Cooksey 0:fb7af294d5d9 431
Simon Cooksey 0:fb7af294d5d9 432 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Simon Cooksey 0:fb7af294d5d9 433 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Simon Cooksey 0:fb7af294d5d9 434
Simon Cooksey 0:fb7af294d5d9 435 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Simon Cooksey 0:fb7af294d5d9 436 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Simon Cooksey 0:fb7af294d5d9 437
Simon Cooksey 0:fb7af294d5d9 438 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Simon Cooksey 0:fb7af294d5d9 439 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Simon Cooksey 0:fb7af294d5d9 440
Simon Cooksey 0:fb7af294d5d9 441 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Simon Cooksey 0:fb7af294d5d9 442 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Simon Cooksey 0:fb7af294d5d9 443
Simon Cooksey 0:fb7af294d5d9 444 /* SCB System Control Register Definitions */
Simon Cooksey 0:fb7af294d5d9 445 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Simon Cooksey 0:fb7af294d5d9 446 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Simon Cooksey 0:fb7af294d5d9 447
Simon Cooksey 0:fb7af294d5d9 448 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Simon Cooksey 0:fb7af294d5d9 449 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Simon Cooksey 0:fb7af294d5d9 450
Simon Cooksey 0:fb7af294d5d9 451 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Simon Cooksey 0:fb7af294d5d9 452 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Simon Cooksey 0:fb7af294d5d9 453
Simon Cooksey 0:fb7af294d5d9 454 /* SCB Configuration Control Register Definitions */
Simon Cooksey 0:fb7af294d5d9 455 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Simon Cooksey 0:fb7af294d5d9 456 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Simon Cooksey 0:fb7af294d5d9 457
Simon Cooksey 0:fb7af294d5d9 458 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Simon Cooksey 0:fb7af294d5d9 459 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Simon Cooksey 0:fb7af294d5d9 460
Simon Cooksey 0:fb7af294d5d9 461 /* SCB System Handler Control and State Register Definitions */
Simon Cooksey 0:fb7af294d5d9 462 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Simon Cooksey 0:fb7af294d5d9 463 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Simon Cooksey 0:fb7af294d5d9 464
Simon Cooksey 0:fb7af294d5d9 465 /*@} end of group CMSIS_SCB */
Simon Cooksey 0:fb7af294d5d9 466
Simon Cooksey 0:fb7af294d5d9 467
Simon Cooksey 0:fb7af294d5d9 468 /** \ingroup CMSIS_core_register
Simon Cooksey 0:fb7af294d5d9 469 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Simon Cooksey 0:fb7af294d5d9 470 \brief Type definitions for the System Control and ID Register not in the SCB
Simon Cooksey 0:fb7af294d5d9 471 @{
Simon Cooksey 0:fb7af294d5d9 472 */
Simon Cooksey 0:fb7af294d5d9 473
Simon Cooksey 0:fb7af294d5d9 474 /** \brief Structure type to access the System Control and ID Register not in the SCB.
Simon Cooksey 0:fb7af294d5d9 475 */
Simon Cooksey 0:fb7af294d5d9 476 typedef struct
Simon Cooksey 0:fb7af294d5d9 477 {
Simon Cooksey 0:fb7af294d5d9 478 uint32_t RESERVED0[2];
Simon Cooksey 0:fb7af294d5d9 479 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
Simon Cooksey 0:fb7af294d5d9 480 } SCnSCB_Type;
Simon Cooksey 0:fb7af294d5d9 481
Simon Cooksey 0:fb7af294d5d9 482 /* Auxiliary Control Register Definitions */
Simon Cooksey 0:fb7af294d5d9 483 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
Simon Cooksey 0:fb7af294d5d9 484 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
Simon Cooksey 0:fb7af294d5d9 485
Simon Cooksey 0:fb7af294d5d9 486 /*@} end of group CMSIS_SCnotSCB */
Simon Cooksey 0:fb7af294d5d9 487
Simon Cooksey 0:fb7af294d5d9 488
Simon Cooksey 0:fb7af294d5d9 489 /** \ingroup CMSIS_core_register
Simon Cooksey 0:fb7af294d5d9 490 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Simon Cooksey 0:fb7af294d5d9 491 \brief Type definitions for the System Timer Registers.
Simon Cooksey 0:fb7af294d5d9 492 @{
Simon Cooksey 0:fb7af294d5d9 493 */
Simon Cooksey 0:fb7af294d5d9 494
Simon Cooksey 0:fb7af294d5d9 495 /** \brief Structure type to access the System Timer (SysTick).
Simon Cooksey 0:fb7af294d5d9 496 */
Simon Cooksey 0:fb7af294d5d9 497 typedef struct
Simon Cooksey 0:fb7af294d5d9 498 {
Simon Cooksey 0:fb7af294d5d9 499 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Simon Cooksey 0:fb7af294d5d9 500 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Simon Cooksey 0:fb7af294d5d9 501 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Simon Cooksey 0:fb7af294d5d9 502 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Simon Cooksey 0:fb7af294d5d9 503 } SysTick_Type;
Simon Cooksey 0:fb7af294d5d9 504
Simon Cooksey 0:fb7af294d5d9 505 /* SysTick Control / Status Register Definitions */
Simon Cooksey 0:fb7af294d5d9 506 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Simon Cooksey 0:fb7af294d5d9 507 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Simon Cooksey 0:fb7af294d5d9 508
Simon Cooksey 0:fb7af294d5d9 509 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Simon Cooksey 0:fb7af294d5d9 510 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Simon Cooksey 0:fb7af294d5d9 511
Simon Cooksey 0:fb7af294d5d9 512 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Simon Cooksey 0:fb7af294d5d9 513 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Simon Cooksey 0:fb7af294d5d9 514
Simon Cooksey 0:fb7af294d5d9 515 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Simon Cooksey 0:fb7af294d5d9 516 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Simon Cooksey 0:fb7af294d5d9 517
Simon Cooksey 0:fb7af294d5d9 518 /* SysTick Reload Register Definitions */
Simon Cooksey 0:fb7af294d5d9 519 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Simon Cooksey 0:fb7af294d5d9 520 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Simon Cooksey 0:fb7af294d5d9 521
Simon Cooksey 0:fb7af294d5d9 522 /* SysTick Current Register Definitions */
Simon Cooksey 0:fb7af294d5d9 523 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Simon Cooksey 0:fb7af294d5d9 524 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Simon Cooksey 0:fb7af294d5d9 525
Simon Cooksey 0:fb7af294d5d9 526 /* SysTick Calibration Register Definitions */
Simon Cooksey 0:fb7af294d5d9 527 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Simon Cooksey 0:fb7af294d5d9 528 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Simon Cooksey 0:fb7af294d5d9 529
Simon Cooksey 0:fb7af294d5d9 530 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Simon Cooksey 0:fb7af294d5d9 531 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Simon Cooksey 0:fb7af294d5d9 532
Simon Cooksey 0:fb7af294d5d9 533 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Simon Cooksey 0:fb7af294d5d9 534 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Simon Cooksey 0:fb7af294d5d9 535
Simon Cooksey 0:fb7af294d5d9 536 /*@} end of group CMSIS_SysTick */
Simon Cooksey 0:fb7af294d5d9 537
Simon Cooksey 0:fb7af294d5d9 538 #if (__MPU_PRESENT == 1)
Simon Cooksey 0:fb7af294d5d9 539 /** \ingroup CMSIS_core_register
Simon Cooksey 0:fb7af294d5d9 540 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Simon Cooksey 0:fb7af294d5d9 541 \brief Type definitions for the Memory Protection Unit (MPU)
Simon Cooksey 0:fb7af294d5d9 542 @{
Simon Cooksey 0:fb7af294d5d9 543 */
Simon Cooksey 0:fb7af294d5d9 544
Simon Cooksey 0:fb7af294d5d9 545 /** \brief Structure type to access the Memory Protection Unit (MPU).
Simon Cooksey 0:fb7af294d5d9 546 */
Simon Cooksey 0:fb7af294d5d9 547 typedef struct
Simon Cooksey 0:fb7af294d5d9 548 {
Simon Cooksey 0:fb7af294d5d9 549 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Simon Cooksey 0:fb7af294d5d9 550 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Simon Cooksey 0:fb7af294d5d9 551 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Simon Cooksey 0:fb7af294d5d9 552 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Simon Cooksey 0:fb7af294d5d9 553 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Simon Cooksey 0:fb7af294d5d9 554 } MPU_Type;
Simon Cooksey 0:fb7af294d5d9 555
Simon Cooksey 0:fb7af294d5d9 556 /* MPU Type Register */
Simon Cooksey 0:fb7af294d5d9 557 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Simon Cooksey 0:fb7af294d5d9 558 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Simon Cooksey 0:fb7af294d5d9 559
Simon Cooksey 0:fb7af294d5d9 560 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Simon Cooksey 0:fb7af294d5d9 561 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Simon Cooksey 0:fb7af294d5d9 562
Simon Cooksey 0:fb7af294d5d9 563 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Simon Cooksey 0:fb7af294d5d9 564 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Simon Cooksey 0:fb7af294d5d9 565
Simon Cooksey 0:fb7af294d5d9 566 /* MPU Control Register */
Simon Cooksey 0:fb7af294d5d9 567 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Simon Cooksey 0:fb7af294d5d9 568 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Simon Cooksey 0:fb7af294d5d9 569
Simon Cooksey 0:fb7af294d5d9 570 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Simon Cooksey 0:fb7af294d5d9 571 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Simon Cooksey 0:fb7af294d5d9 572
Simon Cooksey 0:fb7af294d5d9 573 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Simon Cooksey 0:fb7af294d5d9 574 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Simon Cooksey 0:fb7af294d5d9 575
Simon Cooksey 0:fb7af294d5d9 576 /* MPU Region Number Register */
Simon Cooksey 0:fb7af294d5d9 577 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Simon Cooksey 0:fb7af294d5d9 578 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Simon Cooksey 0:fb7af294d5d9 579
Simon Cooksey 0:fb7af294d5d9 580 /* MPU Region Base Address Register */
Simon Cooksey 0:fb7af294d5d9 581 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Simon Cooksey 0:fb7af294d5d9 582 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Simon Cooksey 0:fb7af294d5d9 583
Simon Cooksey 0:fb7af294d5d9 584 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Simon Cooksey 0:fb7af294d5d9 585 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Simon Cooksey 0:fb7af294d5d9 586
Simon Cooksey 0:fb7af294d5d9 587 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Simon Cooksey 0:fb7af294d5d9 588 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Simon Cooksey 0:fb7af294d5d9 589
Simon Cooksey 0:fb7af294d5d9 590 /* MPU Region Attribute and Size Register */
Simon Cooksey 0:fb7af294d5d9 591 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Simon Cooksey 0:fb7af294d5d9 592 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Simon Cooksey 0:fb7af294d5d9 593
Simon Cooksey 0:fb7af294d5d9 594 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Simon Cooksey 0:fb7af294d5d9 595 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Simon Cooksey 0:fb7af294d5d9 596
Simon Cooksey 0:fb7af294d5d9 597 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Simon Cooksey 0:fb7af294d5d9 598 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Simon Cooksey 0:fb7af294d5d9 599
Simon Cooksey 0:fb7af294d5d9 600 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Simon Cooksey 0:fb7af294d5d9 601 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Simon Cooksey 0:fb7af294d5d9 602
Simon Cooksey 0:fb7af294d5d9 603 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Simon Cooksey 0:fb7af294d5d9 604 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Simon Cooksey 0:fb7af294d5d9 605
Simon Cooksey 0:fb7af294d5d9 606 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Simon Cooksey 0:fb7af294d5d9 607 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Simon Cooksey 0:fb7af294d5d9 608
Simon Cooksey 0:fb7af294d5d9 609 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Simon Cooksey 0:fb7af294d5d9 610 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Simon Cooksey 0:fb7af294d5d9 611
Simon Cooksey 0:fb7af294d5d9 612 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Simon Cooksey 0:fb7af294d5d9 613 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Simon Cooksey 0:fb7af294d5d9 614
Simon Cooksey 0:fb7af294d5d9 615 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Simon Cooksey 0:fb7af294d5d9 616 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Simon Cooksey 0:fb7af294d5d9 617
Simon Cooksey 0:fb7af294d5d9 618 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Simon Cooksey 0:fb7af294d5d9 619 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Simon Cooksey 0:fb7af294d5d9 620
Simon Cooksey 0:fb7af294d5d9 621 /*@} end of group CMSIS_MPU */
Simon Cooksey 0:fb7af294d5d9 622 #endif
Simon Cooksey 0:fb7af294d5d9 623
Simon Cooksey 0:fb7af294d5d9 624
Simon Cooksey 0:fb7af294d5d9 625 /** \ingroup CMSIS_core_register
Simon Cooksey 0:fb7af294d5d9 626 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Simon Cooksey 0:fb7af294d5d9 627 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
Simon Cooksey 0:fb7af294d5d9 628 are only accessible over DAP and not via processor. Therefore
Simon Cooksey 0:fb7af294d5d9 629 they are not covered by the Cortex-M0 header file.
Simon Cooksey 0:fb7af294d5d9 630 @{
Simon Cooksey 0:fb7af294d5d9 631 */
Simon Cooksey 0:fb7af294d5d9 632 /*@} end of group CMSIS_CoreDebug */
Simon Cooksey 0:fb7af294d5d9 633
Simon Cooksey 0:fb7af294d5d9 634
Simon Cooksey 0:fb7af294d5d9 635 /** \ingroup CMSIS_core_register
Simon Cooksey 0:fb7af294d5d9 636 \defgroup CMSIS_core_base Core Definitions
Simon Cooksey 0:fb7af294d5d9 637 \brief Definitions for base addresses, unions, and structures.
Simon Cooksey 0:fb7af294d5d9 638 @{
Simon Cooksey 0:fb7af294d5d9 639 */
Simon Cooksey 0:fb7af294d5d9 640
Simon Cooksey 0:fb7af294d5d9 641 /* Memory mapping of SC000 Hardware */
Simon Cooksey 0:fb7af294d5d9 642 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Simon Cooksey 0:fb7af294d5d9 643 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Simon Cooksey 0:fb7af294d5d9 644 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Simon Cooksey 0:fb7af294d5d9 645 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Simon Cooksey 0:fb7af294d5d9 646
Simon Cooksey 0:fb7af294d5d9 647 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
Simon Cooksey 0:fb7af294d5d9 648 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Simon Cooksey 0:fb7af294d5d9 649 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Simon Cooksey 0:fb7af294d5d9 650 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Simon Cooksey 0:fb7af294d5d9 651
Simon Cooksey 0:fb7af294d5d9 652 #if (__MPU_PRESENT == 1)
Simon Cooksey 0:fb7af294d5d9 653 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Simon Cooksey 0:fb7af294d5d9 654 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Simon Cooksey 0:fb7af294d5d9 655 #endif
Simon Cooksey 0:fb7af294d5d9 656
Simon Cooksey 0:fb7af294d5d9 657 /*@} */
Simon Cooksey 0:fb7af294d5d9 658
Simon Cooksey 0:fb7af294d5d9 659
Simon Cooksey 0:fb7af294d5d9 660
Simon Cooksey 0:fb7af294d5d9 661 /*******************************************************************************
Simon Cooksey 0:fb7af294d5d9 662 * Hardware Abstraction Layer
Simon Cooksey 0:fb7af294d5d9 663 Core Function Interface contains:
Simon Cooksey 0:fb7af294d5d9 664 - Core NVIC Functions
Simon Cooksey 0:fb7af294d5d9 665 - Core SysTick Functions
Simon Cooksey 0:fb7af294d5d9 666 - Core Register Access Functions
Simon Cooksey 0:fb7af294d5d9 667 ******************************************************************************/
Simon Cooksey 0:fb7af294d5d9 668 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Simon Cooksey 0:fb7af294d5d9 669 */
Simon Cooksey 0:fb7af294d5d9 670
Simon Cooksey 0:fb7af294d5d9 671
Simon Cooksey 0:fb7af294d5d9 672
Simon Cooksey 0:fb7af294d5d9 673 /* ########################## NVIC functions #################################### */
Simon Cooksey 0:fb7af294d5d9 674 /** \ingroup CMSIS_Core_FunctionInterface
Simon Cooksey 0:fb7af294d5d9 675 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Simon Cooksey 0:fb7af294d5d9 676 \brief Functions that manage interrupts and exceptions via the NVIC.
Simon Cooksey 0:fb7af294d5d9 677 @{
Simon Cooksey 0:fb7af294d5d9 678 */
Simon Cooksey 0:fb7af294d5d9 679
Simon Cooksey 0:fb7af294d5d9 680 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Simon Cooksey 0:fb7af294d5d9 681 /* The following MACROS handle generation of the register offset and byte masks */
Simon Cooksey 0:fb7af294d5d9 682 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Simon Cooksey 0:fb7af294d5d9 683 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Simon Cooksey 0:fb7af294d5d9 684 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Simon Cooksey 0:fb7af294d5d9 685
Simon Cooksey 0:fb7af294d5d9 686
Simon Cooksey 0:fb7af294d5d9 687 /** \brief Enable External Interrupt
Simon Cooksey 0:fb7af294d5d9 688
Simon Cooksey 0:fb7af294d5d9 689 The function enables a device-specific interrupt in the NVIC interrupt controller.
Simon Cooksey 0:fb7af294d5d9 690
Simon Cooksey 0:fb7af294d5d9 691 \param [in] IRQn External interrupt number. Value cannot be negative.
Simon Cooksey 0:fb7af294d5d9 692 */
Simon Cooksey 0:fb7af294d5d9 693 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Simon Cooksey 0:fb7af294d5d9 694 {
Simon Cooksey 0:fb7af294d5d9 695 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Simon Cooksey 0:fb7af294d5d9 696 }
Simon Cooksey 0:fb7af294d5d9 697
Simon Cooksey 0:fb7af294d5d9 698
Simon Cooksey 0:fb7af294d5d9 699 /** \brief Disable External Interrupt
Simon Cooksey 0:fb7af294d5d9 700
Simon Cooksey 0:fb7af294d5d9 701 The function disables a device-specific interrupt in the NVIC interrupt controller.
Simon Cooksey 0:fb7af294d5d9 702
Simon Cooksey 0:fb7af294d5d9 703 \param [in] IRQn External interrupt number. Value cannot be negative.
Simon Cooksey 0:fb7af294d5d9 704 */
Simon Cooksey 0:fb7af294d5d9 705 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Simon Cooksey 0:fb7af294d5d9 706 {
Simon Cooksey 0:fb7af294d5d9 707 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Simon Cooksey 0:fb7af294d5d9 708 }
Simon Cooksey 0:fb7af294d5d9 709
Simon Cooksey 0:fb7af294d5d9 710
Simon Cooksey 0:fb7af294d5d9 711 /** \brief Get Pending Interrupt
Simon Cooksey 0:fb7af294d5d9 712
Simon Cooksey 0:fb7af294d5d9 713 The function reads the pending register in the NVIC and returns the pending bit
Simon Cooksey 0:fb7af294d5d9 714 for the specified interrupt.
Simon Cooksey 0:fb7af294d5d9 715
Simon Cooksey 0:fb7af294d5d9 716 \param [in] IRQn Interrupt number.
Simon Cooksey 0:fb7af294d5d9 717
Simon Cooksey 0:fb7af294d5d9 718 \return 0 Interrupt status is not pending.
Simon Cooksey 0:fb7af294d5d9 719 \return 1 Interrupt status is pending.
Simon Cooksey 0:fb7af294d5d9 720 */
Simon Cooksey 0:fb7af294d5d9 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Simon Cooksey 0:fb7af294d5d9 722 {
Simon Cooksey 0:fb7af294d5d9 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Simon Cooksey 0:fb7af294d5d9 724 }
Simon Cooksey 0:fb7af294d5d9 725
Simon Cooksey 0:fb7af294d5d9 726
Simon Cooksey 0:fb7af294d5d9 727 /** \brief Set Pending Interrupt
Simon Cooksey 0:fb7af294d5d9 728
Simon Cooksey 0:fb7af294d5d9 729 The function sets the pending bit of an external interrupt.
Simon Cooksey 0:fb7af294d5d9 730
Simon Cooksey 0:fb7af294d5d9 731 \param [in] IRQn Interrupt number. Value cannot be negative.
Simon Cooksey 0:fb7af294d5d9 732 */
Simon Cooksey 0:fb7af294d5d9 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Simon Cooksey 0:fb7af294d5d9 734 {
Simon Cooksey 0:fb7af294d5d9 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Simon Cooksey 0:fb7af294d5d9 736 }
Simon Cooksey 0:fb7af294d5d9 737
Simon Cooksey 0:fb7af294d5d9 738
Simon Cooksey 0:fb7af294d5d9 739 /** \brief Clear Pending Interrupt
Simon Cooksey 0:fb7af294d5d9 740
Simon Cooksey 0:fb7af294d5d9 741 The function clears the pending bit of an external interrupt.
Simon Cooksey 0:fb7af294d5d9 742
Simon Cooksey 0:fb7af294d5d9 743 \param [in] IRQn External interrupt number. Value cannot be negative.
Simon Cooksey 0:fb7af294d5d9 744 */
Simon Cooksey 0:fb7af294d5d9 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Simon Cooksey 0:fb7af294d5d9 746 {
Simon Cooksey 0:fb7af294d5d9 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Simon Cooksey 0:fb7af294d5d9 748 }
Simon Cooksey 0:fb7af294d5d9 749
Simon Cooksey 0:fb7af294d5d9 750
Simon Cooksey 0:fb7af294d5d9 751 /** \brief Set Interrupt Priority
Simon Cooksey 0:fb7af294d5d9 752
Simon Cooksey 0:fb7af294d5d9 753 The function sets the priority of an interrupt.
Simon Cooksey 0:fb7af294d5d9 754
Simon Cooksey 0:fb7af294d5d9 755 \note The priority cannot be set for every core interrupt.
Simon Cooksey 0:fb7af294d5d9 756
Simon Cooksey 0:fb7af294d5d9 757 \param [in] IRQn Interrupt number.
Simon Cooksey 0:fb7af294d5d9 758 \param [in] priority Priority to set.
Simon Cooksey 0:fb7af294d5d9 759 */
Simon Cooksey 0:fb7af294d5d9 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Simon Cooksey 0:fb7af294d5d9 761 {
Simon Cooksey 0:fb7af294d5d9 762 if((int32_t)(IRQn) < 0) {
Simon Cooksey 0:fb7af294d5d9 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Simon Cooksey 0:fb7af294d5d9 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Simon Cooksey 0:fb7af294d5d9 765 }
Simon Cooksey 0:fb7af294d5d9 766 else {
Simon Cooksey 0:fb7af294d5d9 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Simon Cooksey 0:fb7af294d5d9 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Simon Cooksey 0:fb7af294d5d9 769 }
Simon Cooksey 0:fb7af294d5d9 770 }
Simon Cooksey 0:fb7af294d5d9 771
Simon Cooksey 0:fb7af294d5d9 772
Simon Cooksey 0:fb7af294d5d9 773 /** \brief Get Interrupt Priority
Simon Cooksey 0:fb7af294d5d9 774
Simon Cooksey 0:fb7af294d5d9 775 The function reads the priority of an interrupt. The interrupt
Simon Cooksey 0:fb7af294d5d9 776 number can be positive to specify an external (device specific)
Simon Cooksey 0:fb7af294d5d9 777 interrupt, or negative to specify an internal (core) interrupt.
Simon Cooksey 0:fb7af294d5d9 778
Simon Cooksey 0:fb7af294d5d9 779
Simon Cooksey 0:fb7af294d5d9 780 \param [in] IRQn Interrupt number.
Simon Cooksey 0:fb7af294d5d9 781 \return Interrupt Priority. Value is aligned automatically to the implemented
Simon Cooksey 0:fb7af294d5d9 782 priority bits of the microcontroller.
Simon Cooksey 0:fb7af294d5d9 783 */
Simon Cooksey 0:fb7af294d5d9 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Simon Cooksey 0:fb7af294d5d9 785 {
Simon Cooksey 0:fb7af294d5d9 786
Simon Cooksey 0:fb7af294d5d9 787 if((int32_t)(IRQn) < 0) {
Simon Cooksey 0:fb7af294d5d9 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Simon Cooksey 0:fb7af294d5d9 789 }
Simon Cooksey 0:fb7af294d5d9 790 else {
Simon Cooksey 0:fb7af294d5d9 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Simon Cooksey 0:fb7af294d5d9 792 }
Simon Cooksey 0:fb7af294d5d9 793 }
Simon Cooksey 0:fb7af294d5d9 794
Simon Cooksey 0:fb7af294d5d9 795
Simon Cooksey 0:fb7af294d5d9 796 /** \brief System Reset
Simon Cooksey 0:fb7af294d5d9 797
Simon Cooksey 0:fb7af294d5d9 798 The function initiates a system reset request to reset the MCU.
Simon Cooksey 0:fb7af294d5d9 799 */
Simon Cooksey 0:fb7af294d5d9 800 __STATIC_INLINE void NVIC_SystemReset(void)
Simon Cooksey 0:fb7af294d5d9 801 {
Simon Cooksey 0:fb7af294d5d9 802 __DSB(); /* Ensure all outstanding memory accesses included
Simon Cooksey 0:fb7af294d5d9 803 buffered write are completed before reset */
Simon Cooksey 0:fb7af294d5d9 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Simon Cooksey 0:fb7af294d5d9 805 SCB_AIRCR_SYSRESETREQ_Msk);
Simon Cooksey 0:fb7af294d5d9 806 __DSB(); /* Ensure completion of memory access */
Simon Cooksey 0:fb7af294d5d9 807 while(1) { __NOP(); } /* wait until reset */
Simon Cooksey 0:fb7af294d5d9 808 }
Simon Cooksey 0:fb7af294d5d9 809
Simon Cooksey 0:fb7af294d5d9 810 /*@} end of CMSIS_Core_NVICFunctions */
Simon Cooksey 0:fb7af294d5d9 811
Simon Cooksey 0:fb7af294d5d9 812
Simon Cooksey 0:fb7af294d5d9 813
Simon Cooksey 0:fb7af294d5d9 814 /* ################################## SysTick function ############################################ */
Simon Cooksey 0:fb7af294d5d9 815 /** \ingroup CMSIS_Core_FunctionInterface
Simon Cooksey 0:fb7af294d5d9 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Simon Cooksey 0:fb7af294d5d9 817 \brief Functions that configure the System.
Simon Cooksey 0:fb7af294d5d9 818 @{
Simon Cooksey 0:fb7af294d5d9 819 */
Simon Cooksey 0:fb7af294d5d9 820
Simon Cooksey 0:fb7af294d5d9 821 #if (__Vendor_SysTickConfig == 0)
Simon Cooksey 0:fb7af294d5d9 822
Simon Cooksey 0:fb7af294d5d9 823 /** \brief System Tick Configuration
Simon Cooksey 0:fb7af294d5d9 824
Simon Cooksey 0:fb7af294d5d9 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Simon Cooksey 0:fb7af294d5d9 826 Counter is in free running mode to generate periodic interrupts.
Simon Cooksey 0:fb7af294d5d9 827
Simon Cooksey 0:fb7af294d5d9 828 \param [in] ticks Number of ticks between two interrupts.
Simon Cooksey 0:fb7af294d5d9 829
Simon Cooksey 0:fb7af294d5d9 830 \return 0 Function succeeded.
Simon Cooksey 0:fb7af294d5d9 831 \return 1 Function failed.
Simon Cooksey 0:fb7af294d5d9 832
Simon Cooksey 0:fb7af294d5d9 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Simon Cooksey 0:fb7af294d5d9 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Simon Cooksey 0:fb7af294d5d9 835 must contain a vendor-specific implementation of this function.
Simon Cooksey 0:fb7af294d5d9 836
Simon Cooksey 0:fb7af294d5d9 837 */
Simon Cooksey 0:fb7af294d5d9 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Simon Cooksey 0:fb7af294d5d9 839 {
Simon Cooksey 0:fb7af294d5d9 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
Simon Cooksey 0:fb7af294d5d9 841
Simon Cooksey 0:fb7af294d5d9 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Simon Cooksey 0:fb7af294d5d9 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Simon Cooksey 0:fb7af294d5d9 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Simon Cooksey 0:fb7af294d5d9 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Simon Cooksey 0:fb7af294d5d9 846 SysTick_CTRL_TICKINT_Msk |
Simon Cooksey 0:fb7af294d5d9 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Simon Cooksey 0:fb7af294d5d9 848 return (0UL); /* Function successful */
Simon Cooksey 0:fb7af294d5d9 849 }
Simon Cooksey 0:fb7af294d5d9 850
Simon Cooksey 0:fb7af294d5d9 851 #endif
Simon Cooksey 0:fb7af294d5d9 852
Simon Cooksey 0:fb7af294d5d9 853 /*@} end of CMSIS_Core_SysTickFunctions */
Simon Cooksey 0:fb7af294d5d9 854
Simon Cooksey 0:fb7af294d5d9 855
Simon Cooksey 0:fb7af294d5d9 856
Simon Cooksey 0:fb7af294d5d9 857
Simon Cooksey 0:fb7af294d5d9 858 #ifdef __cplusplus
Simon Cooksey 0:fb7af294d5d9 859 }
Simon Cooksey 0:fb7af294d5d9 860 #endif
Simon Cooksey 0:fb7af294d5d9 861
Simon Cooksey 0:fb7af294d5d9 862 #endif /* __CORE_SC000_H_DEPENDANT */
Simon Cooksey 0:fb7af294d5d9 863
Simon Cooksey 0:fb7af294d5d9 864 #endif /* __CMSIS_GENERIC */