Simon Cooksey / mbed-os

Pinned to some recent date

cmsis/core_cmFunc.h@0:fb7af294d5d9, 2016-11-17 (annotated)

Committer:
Simon Cooksey
Date:
Thu Nov 17 16:43:53 2016 +0000
Revision:
0:fb7af294d5d9
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Simon Cooksey 0:fb7af294d5d9 1 /**************************************************************************//**
Simon Cooksey 0:fb7af294d5d9 2 * @file core_cmFunc.h
Simon Cooksey 0:fb7af294d5d9 3 * @brief CMSIS Cortex-M Core Function Access Header File
Simon Cooksey 0:fb7af294d5d9 4 * @version V4.10
Simon Cooksey 0:fb7af294d5d9 5 * @date 18. March 2015
Simon Cooksey 0:fb7af294d5d9 6 *
Simon Cooksey 0:fb7af294d5d9 7 * @note
Simon Cooksey 0:fb7af294d5d9 8 *
Simon Cooksey 0:fb7af294d5d9 9 ******************************************************************************/
Simon Cooksey 0:fb7af294d5d9 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Simon Cooksey 0:fb7af294d5d9 11
Simon Cooksey 0:fb7af294d5d9 12 All rights reserved.
Simon Cooksey 0:fb7af294d5d9 13 Redistribution and use in source and binary forms, with or without
Simon Cooksey 0:fb7af294d5d9 14 modification, are permitted provided that the following conditions are met:
Simon Cooksey 0:fb7af294d5d9 15 - Redistributions of source code must retain the above copyright
Simon Cooksey 0:fb7af294d5d9 16 notice, this list of conditions and the following disclaimer.
Simon Cooksey 0:fb7af294d5d9 17 - Redistributions in binary form must reproduce the above copyright
Simon Cooksey 0:fb7af294d5d9 18 notice, this list of conditions and the following disclaimer in the
Simon Cooksey 0:fb7af294d5d9 19 documentation and/or other materials provided with the distribution.
Simon Cooksey 0:fb7af294d5d9 20 - Neither the name of ARM nor the names of its contributors may be used
Simon Cooksey 0:fb7af294d5d9 21 to endorse or promote products derived from this software without
Simon Cooksey 0:fb7af294d5d9 22 specific prior written permission.
Simon Cooksey 0:fb7af294d5d9 23 *
Simon Cooksey 0:fb7af294d5d9 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Simon Cooksey 0:fb7af294d5d9 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Simon Cooksey 0:fb7af294d5d9 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Simon Cooksey 0:fb7af294d5d9 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Simon Cooksey 0:fb7af294d5d9 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Simon Cooksey 0:fb7af294d5d9 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Simon Cooksey 0:fb7af294d5d9 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Simon Cooksey 0:fb7af294d5d9 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Simon Cooksey 0:fb7af294d5d9 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Simon Cooksey 0:fb7af294d5d9 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Simon Cooksey 0:fb7af294d5d9 34 POSSIBILITY OF SUCH DAMAGE.
Simon Cooksey 0:fb7af294d5d9 35 ---------------------------------------------------------------------------*/
Simon Cooksey 0:fb7af294d5d9 36
Simon Cooksey 0:fb7af294d5d9 37
Simon Cooksey 0:fb7af294d5d9 38 #ifndef __CORE_CMFUNC_H
Simon Cooksey 0:fb7af294d5d9 39 #define __CORE_CMFUNC_H
Simon Cooksey 0:fb7af294d5d9 40
Simon Cooksey 0:fb7af294d5d9 41
Simon Cooksey 0:fb7af294d5d9 42 /* ########################### Core Function Access ########################### */
Simon Cooksey 0:fb7af294d5d9 43 /** \ingroup CMSIS_Core_FunctionInterface
Simon Cooksey 0:fb7af294d5d9 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Simon Cooksey 0:fb7af294d5d9 45 @{
Simon Cooksey 0:fb7af294d5d9 46 */
Simon Cooksey 0:fb7af294d5d9 47
Simon Cooksey 0:fb7af294d5d9 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Simon Cooksey 0:fb7af294d5d9 49 /* ARM armcc specific functions */
Simon Cooksey 0:fb7af294d5d9 50
Simon Cooksey 0:fb7af294d5d9 51 #if (__ARMCC_VERSION < 400677)
Simon Cooksey 0:fb7af294d5d9 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Simon Cooksey 0:fb7af294d5d9 53 #endif
Simon Cooksey 0:fb7af294d5d9 54
Simon Cooksey 0:fb7af294d5d9 55 /* intrinsic void __enable_irq(); */
Simon Cooksey 0:fb7af294d5d9 56 /* intrinsic void __disable_irq(); */
Simon Cooksey 0:fb7af294d5d9 57
Simon Cooksey 0:fb7af294d5d9 58 /** \brief Get Control Register
Simon Cooksey 0:fb7af294d5d9 59
Simon Cooksey 0:fb7af294d5d9 60 This function returns the content of the Control Register.
Simon Cooksey 0:fb7af294d5d9 61
Simon Cooksey 0:fb7af294d5d9 62 \return Control Register value
Simon Cooksey 0:fb7af294d5d9 63 */
Simon Cooksey 0:fb7af294d5d9 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
Simon Cooksey 0:fb7af294d5d9 65 {
Simon Cooksey 0:fb7af294d5d9 66 register uint32_t __regControl __ASM("control");
Simon Cooksey 0:fb7af294d5d9 67 return(__regControl);
Simon Cooksey 0:fb7af294d5d9 68 }
Simon Cooksey 0:fb7af294d5d9 69
Simon Cooksey 0:fb7af294d5d9 70
Simon Cooksey 0:fb7af294d5d9 71 /** \brief Set Control Register
Simon Cooksey 0:fb7af294d5d9 72
Simon Cooksey 0:fb7af294d5d9 73 This function writes the given value to the Control Register.
Simon Cooksey 0:fb7af294d5d9 74
Simon Cooksey 0:fb7af294d5d9 75 \param [in] control Control Register value to set
Simon Cooksey 0:fb7af294d5d9 76 */
Simon Cooksey 0:fb7af294d5d9 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
Simon Cooksey 0:fb7af294d5d9 78 {
Simon Cooksey 0:fb7af294d5d9 79 register uint32_t __regControl __ASM("control");
Simon Cooksey 0:fb7af294d5d9 80 __regControl = control;
Simon Cooksey 0:fb7af294d5d9 81 }
Simon Cooksey 0:fb7af294d5d9 82
Simon Cooksey 0:fb7af294d5d9 83
Simon Cooksey 0:fb7af294d5d9 84 /** \brief Get IPSR Register
Simon Cooksey 0:fb7af294d5d9 85
Simon Cooksey 0:fb7af294d5d9 86 This function returns the content of the IPSR Register.
Simon Cooksey 0:fb7af294d5d9 87
Simon Cooksey 0:fb7af294d5d9 88 \return IPSR Register value
Simon Cooksey 0:fb7af294d5d9 89 */
Simon Cooksey 0:fb7af294d5d9 90 __STATIC_INLINE uint32_t __get_IPSR(void)
Simon Cooksey 0:fb7af294d5d9 91 {
Simon Cooksey 0:fb7af294d5d9 92 register uint32_t __regIPSR __ASM("ipsr");
Simon Cooksey 0:fb7af294d5d9 93 return(__regIPSR);
Simon Cooksey 0:fb7af294d5d9 94 }
Simon Cooksey 0:fb7af294d5d9 95
Simon Cooksey 0:fb7af294d5d9 96
Simon Cooksey 0:fb7af294d5d9 97 /** \brief Get APSR Register
Simon Cooksey 0:fb7af294d5d9 98
Simon Cooksey 0:fb7af294d5d9 99 This function returns the content of the APSR Register.
Simon Cooksey 0:fb7af294d5d9 100
Simon Cooksey 0:fb7af294d5d9 101 \return APSR Register value
Simon Cooksey 0:fb7af294d5d9 102 */
Simon Cooksey 0:fb7af294d5d9 103 __STATIC_INLINE uint32_t __get_APSR(void)
Simon Cooksey 0:fb7af294d5d9 104 {
Simon Cooksey 0:fb7af294d5d9 105 register uint32_t __regAPSR __ASM("apsr");
Simon Cooksey 0:fb7af294d5d9 106 return(__regAPSR);
Simon Cooksey 0:fb7af294d5d9 107 }
Simon Cooksey 0:fb7af294d5d9 108
Simon Cooksey 0:fb7af294d5d9 109
Simon Cooksey 0:fb7af294d5d9 110 /** \brief Get xPSR Register
Simon Cooksey 0:fb7af294d5d9 111
Simon Cooksey 0:fb7af294d5d9 112 This function returns the content of the xPSR Register.
Simon Cooksey 0:fb7af294d5d9 113
Simon Cooksey 0:fb7af294d5d9 114 \return xPSR Register value
Simon Cooksey 0:fb7af294d5d9 115 */
Simon Cooksey 0:fb7af294d5d9 116 __STATIC_INLINE uint32_t __get_xPSR(void)
Simon Cooksey 0:fb7af294d5d9 117 {
Simon Cooksey 0:fb7af294d5d9 118 register uint32_t __regXPSR __ASM("xpsr");
Simon Cooksey 0:fb7af294d5d9 119 return(__regXPSR);
Simon Cooksey 0:fb7af294d5d9 120 }
Simon Cooksey 0:fb7af294d5d9 121
Simon Cooksey 0:fb7af294d5d9 122
Simon Cooksey 0:fb7af294d5d9 123 /** \brief Get Process Stack Pointer
Simon Cooksey 0:fb7af294d5d9 124
Simon Cooksey 0:fb7af294d5d9 125 This function returns the current value of the Process Stack Pointer (PSP).
Simon Cooksey 0:fb7af294d5d9 126
Simon Cooksey 0:fb7af294d5d9 127 \return PSP Register value
Simon Cooksey 0:fb7af294d5d9 128 */
Simon Cooksey 0:fb7af294d5d9 129 __STATIC_INLINE uint32_t __get_PSP(void)
Simon Cooksey 0:fb7af294d5d9 130 {
Simon Cooksey 0:fb7af294d5d9 131 register uint32_t __regProcessStackPointer __ASM("psp");
Simon Cooksey 0:fb7af294d5d9 132 return(__regProcessStackPointer);
Simon Cooksey 0:fb7af294d5d9 133 }
Simon Cooksey 0:fb7af294d5d9 134
Simon Cooksey 0:fb7af294d5d9 135
Simon Cooksey 0:fb7af294d5d9 136 /** \brief Set Process Stack Pointer
Simon Cooksey 0:fb7af294d5d9 137
Simon Cooksey 0:fb7af294d5d9 138 This function assigns the given value to the Process Stack Pointer (PSP).
Simon Cooksey 0:fb7af294d5d9 139
Simon Cooksey 0:fb7af294d5d9 140 \param [in] topOfProcStack Process Stack Pointer value to set
Simon Cooksey 0:fb7af294d5d9 141 */
Simon Cooksey 0:fb7af294d5d9 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Simon Cooksey 0:fb7af294d5d9 143 {
Simon Cooksey 0:fb7af294d5d9 144 register uint32_t __regProcessStackPointer __ASM("psp");
Simon Cooksey 0:fb7af294d5d9 145 __regProcessStackPointer = topOfProcStack;
Simon Cooksey 0:fb7af294d5d9 146 }
Simon Cooksey 0:fb7af294d5d9 147
Simon Cooksey 0:fb7af294d5d9 148
Simon Cooksey 0:fb7af294d5d9 149 /** \brief Get Main Stack Pointer
Simon Cooksey 0:fb7af294d5d9 150
Simon Cooksey 0:fb7af294d5d9 151 This function returns the current value of the Main Stack Pointer (MSP).
Simon Cooksey 0:fb7af294d5d9 152
Simon Cooksey 0:fb7af294d5d9 153 \return MSP Register value
Simon Cooksey 0:fb7af294d5d9 154 */
Simon Cooksey 0:fb7af294d5d9 155 __STATIC_INLINE uint32_t __get_MSP(void)
Simon Cooksey 0:fb7af294d5d9 156 {
Simon Cooksey 0:fb7af294d5d9 157 register uint32_t __regMainStackPointer __ASM("msp");
Simon Cooksey 0:fb7af294d5d9 158 return(__regMainStackPointer);
Simon Cooksey 0:fb7af294d5d9 159 }
Simon Cooksey 0:fb7af294d5d9 160
Simon Cooksey 0:fb7af294d5d9 161
Simon Cooksey 0:fb7af294d5d9 162 /** \brief Set Main Stack Pointer
Simon Cooksey 0:fb7af294d5d9 163
Simon Cooksey 0:fb7af294d5d9 164 This function assigns the given value to the Main Stack Pointer (MSP).
Simon Cooksey 0:fb7af294d5d9 165
Simon Cooksey 0:fb7af294d5d9 166 \param [in] topOfMainStack Main Stack Pointer value to set
Simon Cooksey 0:fb7af294d5d9 167 */
Simon Cooksey 0:fb7af294d5d9 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
Simon Cooksey 0:fb7af294d5d9 169 {
Simon Cooksey 0:fb7af294d5d9 170 register uint32_t __regMainStackPointer __ASM("msp");
Simon Cooksey 0:fb7af294d5d9 171 __regMainStackPointer = topOfMainStack;
Simon Cooksey 0:fb7af294d5d9 172 }
Simon Cooksey 0:fb7af294d5d9 173
Simon Cooksey 0:fb7af294d5d9 174
Simon Cooksey 0:fb7af294d5d9 175 /** \brief Get Priority Mask
Simon Cooksey 0:fb7af294d5d9 176
Simon Cooksey 0:fb7af294d5d9 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
Simon Cooksey 0:fb7af294d5d9 178
Simon Cooksey 0:fb7af294d5d9 179 \return Priority Mask value
Simon Cooksey 0:fb7af294d5d9 180 */
Simon Cooksey 0:fb7af294d5d9 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
Simon Cooksey 0:fb7af294d5d9 182 {
Simon Cooksey 0:fb7af294d5d9 183 register uint32_t __regPriMask __ASM("primask");
Simon Cooksey 0:fb7af294d5d9 184 return(__regPriMask);
Simon Cooksey 0:fb7af294d5d9 185 }
Simon Cooksey 0:fb7af294d5d9 186
Simon Cooksey 0:fb7af294d5d9 187
Simon Cooksey 0:fb7af294d5d9 188 /** \brief Set Priority Mask
Simon Cooksey 0:fb7af294d5d9 189
Simon Cooksey 0:fb7af294d5d9 190 This function assigns the given value to the Priority Mask Register.
Simon Cooksey 0:fb7af294d5d9 191
Simon Cooksey 0:fb7af294d5d9 192 \param [in] priMask Priority Mask
Simon Cooksey 0:fb7af294d5d9 193 */
Simon Cooksey 0:fb7af294d5d9 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
Simon Cooksey 0:fb7af294d5d9 195 {
Simon Cooksey 0:fb7af294d5d9 196 register uint32_t __regPriMask __ASM("primask");
Simon Cooksey 0:fb7af294d5d9 197 __regPriMask = (priMask);
Simon Cooksey 0:fb7af294d5d9 198 }
Simon Cooksey 0:fb7af294d5d9 199
Simon Cooksey 0:fb7af294d5d9 200
Simon Cooksey 0:fb7af294d5d9 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
Simon Cooksey 0:fb7af294d5d9 202
Simon Cooksey 0:fb7af294d5d9 203 /** \brief Enable FIQ
Simon Cooksey 0:fb7af294d5d9 204
Simon Cooksey 0:fb7af294d5d9 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Simon Cooksey 0:fb7af294d5d9 206 Can only be executed in Privileged modes.
Simon Cooksey 0:fb7af294d5d9 207 */
Simon Cooksey 0:fb7af294d5d9 208 #define __enable_fault_irq __enable_fiq
Simon Cooksey 0:fb7af294d5d9 209
Simon Cooksey 0:fb7af294d5d9 210
Simon Cooksey 0:fb7af294d5d9 211 /** \brief Disable FIQ
Simon Cooksey 0:fb7af294d5d9 212
Simon Cooksey 0:fb7af294d5d9 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Simon Cooksey 0:fb7af294d5d9 214 Can only be executed in Privileged modes.
Simon Cooksey 0:fb7af294d5d9 215 */
Simon Cooksey 0:fb7af294d5d9 216 #define __disable_fault_irq __disable_fiq
Simon Cooksey 0:fb7af294d5d9 217
Simon Cooksey 0:fb7af294d5d9 218
Simon Cooksey 0:fb7af294d5d9 219 /** \brief Get Base Priority
Simon Cooksey 0:fb7af294d5d9 220
Simon Cooksey 0:fb7af294d5d9 221 This function returns the current value of the Base Priority register.
Simon Cooksey 0:fb7af294d5d9 222
Simon Cooksey 0:fb7af294d5d9 223 \return Base Priority register value
Simon Cooksey 0:fb7af294d5d9 224 */
Simon Cooksey 0:fb7af294d5d9 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
Simon Cooksey 0:fb7af294d5d9 226 {
Simon Cooksey 0:fb7af294d5d9 227 register uint32_t __regBasePri __ASM("basepri");
Simon Cooksey 0:fb7af294d5d9 228 return(__regBasePri);
Simon Cooksey 0:fb7af294d5d9 229 }
Simon Cooksey 0:fb7af294d5d9 230
Simon Cooksey 0:fb7af294d5d9 231
Simon Cooksey 0:fb7af294d5d9 232 /** \brief Set Base Priority
Simon Cooksey 0:fb7af294d5d9 233
Simon Cooksey 0:fb7af294d5d9 234 This function assigns the given value to the Base Priority register.
Simon Cooksey 0:fb7af294d5d9 235
Simon Cooksey 0:fb7af294d5d9 236 \param [in] basePri Base Priority value to set
Simon Cooksey 0:fb7af294d5d9 237 */
Simon Cooksey 0:fb7af294d5d9 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
Simon Cooksey 0:fb7af294d5d9 239 {
Simon Cooksey 0:fb7af294d5d9 240 register uint32_t __regBasePri __ASM("basepri");
Simon Cooksey 0:fb7af294d5d9 241 __regBasePri = (basePri & 0xff);
Simon Cooksey 0:fb7af294d5d9 242 }
Simon Cooksey 0:fb7af294d5d9 243
Simon Cooksey 0:fb7af294d5d9 244
Simon Cooksey 0:fb7af294d5d9 245 /** \brief Set Base Priority with condition
Simon Cooksey 0:fb7af294d5d9 246
Simon Cooksey 0:fb7af294d5d9 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
Simon Cooksey 0:fb7af294d5d9 248 or the new value increases the BASEPRI priority level.
Simon Cooksey 0:fb7af294d5d9 249
Simon Cooksey 0:fb7af294d5d9 250 \param [in] basePri Base Priority value to set
Simon Cooksey 0:fb7af294d5d9 251 */
Simon Cooksey 0:fb7af294d5d9 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
Simon Cooksey 0:fb7af294d5d9 253 {
Simon Cooksey 0:fb7af294d5d9 254 register uint32_t __regBasePriMax __ASM("basepri_max");
Simon Cooksey 0:fb7af294d5d9 255 __regBasePriMax = (basePri & 0xff);
Simon Cooksey 0:fb7af294d5d9 256 }
Simon Cooksey 0:fb7af294d5d9 257
Simon Cooksey 0:fb7af294d5d9 258
Simon Cooksey 0:fb7af294d5d9 259 /** \brief Get Fault Mask
Simon Cooksey 0:fb7af294d5d9 260
Simon Cooksey 0:fb7af294d5d9 261 This function returns the current value of the Fault Mask register.
Simon Cooksey 0:fb7af294d5d9 262
Simon Cooksey 0:fb7af294d5d9 263 \return Fault Mask register value
Simon Cooksey 0:fb7af294d5d9 264 */
Simon Cooksey 0:fb7af294d5d9 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
Simon Cooksey 0:fb7af294d5d9 266 {
Simon Cooksey 0:fb7af294d5d9 267 register uint32_t __regFaultMask __ASM("faultmask");
Simon Cooksey 0:fb7af294d5d9 268 return(__regFaultMask);
Simon Cooksey 0:fb7af294d5d9 269 }
Simon Cooksey 0:fb7af294d5d9 270
Simon Cooksey 0:fb7af294d5d9 271
Simon Cooksey 0:fb7af294d5d9 272 /** \brief Set Fault Mask
Simon Cooksey 0:fb7af294d5d9 273
Simon Cooksey 0:fb7af294d5d9 274 This function assigns the given value to the Fault Mask register.
Simon Cooksey 0:fb7af294d5d9 275
Simon Cooksey 0:fb7af294d5d9 276 \param [in] faultMask Fault Mask value to set
Simon Cooksey 0:fb7af294d5d9 277 */
Simon Cooksey 0:fb7af294d5d9 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
Simon Cooksey 0:fb7af294d5d9 279 {
Simon Cooksey 0:fb7af294d5d9 280 register uint32_t __regFaultMask __ASM("faultmask");
Simon Cooksey 0:fb7af294d5d9 281 __regFaultMask = (faultMask & (uint32_t)1);
Simon Cooksey 0:fb7af294d5d9 282 }
Simon Cooksey 0:fb7af294d5d9 283
Simon Cooksey 0:fb7af294d5d9 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
Simon Cooksey 0:fb7af294d5d9 285
Simon Cooksey 0:fb7af294d5d9 286
Simon Cooksey 0:fb7af294d5d9 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
Simon Cooksey 0:fb7af294d5d9 288
Simon Cooksey 0:fb7af294d5d9 289 /** \brief Get FPSCR
Simon Cooksey 0:fb7af294d5d9 290
Simon Cooksey 0:fb7af294d5d9 291 This function returns the current value of the Floating Point Status/Control register.
Simon Cooksey 0:fb7af294d5d9 292
Simon Cooksey 0:fb7af294d5d9 293 \return Floating Point Status/Control register value
Simon Cooksey 0:fb7af294d5d9 294 */
Simon Cooksey 0:fb7af294d5d9 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
Simon Cooksey 0:fb7af294d5d9 296 {
Simon Cooksey 0:fb7af294d5d9 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Simon Cooksey 0:fb7af294d5d9 298 register uint32_t __regfpscr __ASM("fpscr");
Simon Cooksey 0:fb7af294d5d9 299 return(__regfpscr);
Simon Cooksey 0:fb7af294d5d9 300 #else
Simon Cooksey 0:fb7af294d5d9 301 return(0);
Simon Cooksey 0:fb7af294d5d9 302 #endif
Simon Cooksey 0:fb7af294d5d9 303 }
Simon Cooksey 0:fb7af294d5d9 304
Simon Cooksey 0:fb7af294d5d9 305
Simon Cooksey 0:fb7af294d5d9 306 /** \brief Set FPSCR
Simon Cooksey 0:fb7af294d5d9 307
Simon Cooksey 0:fb7af294d5d9 308 This function assigns the given value to the Floating Point Status/Control register.
Simon Cooksey 0:fb7af294d5d9 309
Simon Cooksey 0:fb7af294d5d9 310 \param [in] fpscr Floating Point Status/Control value to set
Simon Cooksey 0:fb7af294d5d9 311 */
Simon Cooksey 0:fb7af294d5d9 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Simon Cooksey 0:fb7af294d5d9 313 {
Simon Cooksey 0:fb7af294d5d9 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Simon Cooksey 0:fb7af294d5d9 315 register uint32_t __regfpscr __ASM("fpscr");
Simon Cooksey 0:fb7af294d5d9 316 __regfpscr = (fpscr);
Simon Cooksey 0:fb7af294d5d9 317 #endif
Simon Cooksey 0:fb7af294d5d9 318 }
Simon Cooksey 0:fb7af294d5d9 319
Simon Cooksey 0:fb7af294d5d9 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
Simon Cooksey 0:fb7af294d5d9 321
Simon Cooksey 0:fb7af294d5d9 322
Simon Cooksey 0:fb7af294d5d9 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
Simon Cooksey 0:fb7af294d5d9 324 /* GNU gcc specific functions */
Simon Cooksey 0:fb7af294d5d9 325
Simon Cooksey 0:fb7af294d5d9 326 /** \brief Enable IRQ Interrupts
Simon Cooksey 0:fb7af294d5d9 327
Simon Cooksey 0:fb7af294d5d9 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Simon Cooksey 0:fb7af294d5d9 329 Can only be executed in Privileged modes.
Simon Cooksey 0:fb7af294d5d9 330 */
Simon Cooksey 0:fb7af294d5d9 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Simon Cooksey 0:fb7af294d5d9 332 {
Simon Cooksey 0:fb7af294d5d9 333 __ASM volatile ("cpsie i" : : : "memory");
Simon Cooksey 0:fb7af294d5d9 334 }
Simon Cooksey 0:fb7af294d5d9 335
Simon Cooksey 0:fb7af294d5d9 336
Simon Cooksey 0:fb7af294d5d9 337 /** \brief Disable IRQ Interrupts
Simon Cooksey 0:fb7af294d5d9 338
Simon Cooksey 0:fb7af294d5d9 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Simon Cooksey 0:fb7af294d5d9 340 Can only be executed in Privileged modes.
Simon Cooksey 0:fb7af294d5d9 341 */
Simon Cooksey 0:fb7af294d5d9 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
Simon Cooksey 0:fb7af294d5d9 343 {
Simon Cooksey 0:fb7af294d5d9 344 __ASM volatile ("cpsid i" : : : "memory");
Simon Cooksey 0:fb7af294d5d9 345 }
Simon Cooksey 0:fb7af294d5d9 346
Simon Cooksey 0:fb7af294d5d9 347
Simon Cooksey 0:fb7af294d5d9 348 /** \brief Get Control Register
Simon Cooksey 0:fb7af294d5d9 349
Simon Cooksey 0:fb7af294d5d9 350 This function returns the content of the Control Register.
Simon Cooksey 0:fb7af294d5d9 351
Simon Cooksey 0:fb7af294d5d9 352 \return Control Register value
Simon Cooksey 0:fb7af294d5d9 353 */
Simon Cooksey 0:fb7af294d5d9 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
Simon Cooksey 0:fb7af294d5d9 355 {
Simon Cooksey 0:fb7af294d5d9 356 uint32_t result;
Simon Cooksey 0:fb7af294d5d9 357
Simon Cooksey 0:fb7af294d5d9 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
Simon Cooksey 0:fb7af294d5d9 359 return(result);
Simon Cooksey 0:fb7af294d5d9 360 }
Simon Cooksey 0:fb7af294d5d9 361
Simon Cooksey 0:fb7af294d5d9 362
Simon Cooksey 0:fb7af294d5d9 363 /** \brief Set Control Register
Simon Cooksey 0:fb7af294d5d9 364
Simon Cooksey 0:fb7af294d5d9 365 This function writes the given value to the Control Register.
Simon Cooksey 0:fb7af294d5d9 366
Simon Cooksey 0:fb7af294d5d9 367 \param [in] control Control Register value to set
Simon Cooksey 0:fb7af294d5d9 368 */
Simon Cooksey 0:fb7af294d5d9 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
Simon Cooksey 0:fb7af294d5d9 370 {
Simon Cooksey 0:fb7af294d5d9 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
Simon Cooksey 0:fb7af294d5d9 372 }
Simon Cooksey 0:fb7af294d5d9 373
Simon Cooksey 0:fb7af294d5d9 374
Simon Cooksey 0:fb7af294d5d9 375 /** \brief Get IPSR Register
Simon Cooksey 0:fb7af294d5d9 376
Simon Cooksey 0:fb7af294d5d9 377 This function returns the content of the IPSR Register.
Simon Cooksey 0:fb7af294d5d9 378
Simon Cooksey 0:fb7af294d5d9 379 \return IPSR Register value
Simon Cooksey 0:fb7af294d5d9 380 */
Simon Cooksey 0:fb7af294d5d9 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
Simon Cooksey 0:fb7af294d5d9 382 {
Simon Cooksey 0:fb7af294d5d9 383 uint32_t result;
Simon Cooksey 0:fb7af294d5d9 384
Simon Cooksey 0:fb7af294d5d9 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
Simon Cooksey 0:fb7af294d5d9 386 return(result);
Simon Cooksey 0:fb7af294d5d9 387 }
Simon Cooksey 0:fb7af294d5d9 388
Simon Cooksey 0:fb7af294d5d9 389
Simon Cooksey 0:fb7af294d5d9 390 /** \brief Get APSR Register
Simon Cooksey 0:fb7af294d5d9 391
Simon Cooksey 0:fb7af294d5d9 392 This function returns the content of the APSR Register.
Simon Cooksey 0:fb7af294d5d9 393
Simon Cooksey 0:fb7af294d5d9 394 \return APSR Register value
Simon Cooksey 0:fb7af294d5d9 395 */
Simon Cooksey 0:fb7af294d5d9 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Simon Cooksey 0:fb7af294d5d9 397 {
Simon Cooksey 0:fb7af294d5d9 398 uint32_t result;
Simon Cooksey 0:fb7af294d5d9 399
Simon Cooksey 0:fb7af294d5d9 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
Simon Cooksey 0:fb7af294d5d9 401 return(result);
Simon Cooksey 0:fb7af294d5d9 402 }
Simon Cooksey 0:fb7af294d5d9 403
Simon Cooksey 0:fb7af294d5d9 404
Simon Cooksey 0:fb7af294d5d9 405 /** \brief Get xPSR Register
Simon Cooksey 0:fb7af294d5d9 406
Simon Cooksey 0:fb7af294d5d9 407 This function returns the content of the xPSR Register.
Simon Cooksey 0:fb7af294d5d9 408
Simon Cooksey 0:fb7af294d5d9 409 \return xPSR Register value
Simon Cooksey 0:fb7af294d5d9 410 */
Simon Cooksey 0:fb7af294d5d9 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
Simon Cooksey 0:fb7af294d5d9 412 {
Simon Cooksey 0:fb7af294d5d9 413 uint32_t result;
Simon Cooksey 0:fb7af294d5d9 414
Simon Cooksey 0:fb7af294d5d9 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
Simon Cooksey 0:fb7af294d5d9 416 return(result);
Simon Cooksey 0:fb7af294d5d9 417 }
Simon Cooksey 0:fb7af294d5d9 418
Simon Cooksey 0:fb7af294d5d9 419
Simon Cooksey 0:fb7af294d5d9 420 /** \brief Get Process Stack Pointer
Simon Cooksey 0:fb7af294d5d9 421
Simon Cooksey 0:fb7af294d5d9 422 This function returns the current value of the Process Stack Pointer (PSP).
Simon Cooksey 0:fb7af294d5d9 423
Simon Cooksey 0:fb7af294d5d9 424 \return PSP Register value
Simon Cooksey 0:fb7af294d5d9 425 */
Simon Cooksey 0:fb7af294d5d9 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
Simon Cooksey 0:fb7af294d5d9 427 {
Simon Cooksey 0:fb7af294d5d9 428 register uint32_t result;
Simon Cooksey 0:fb7af294d5d9 429
Simon Cooksey 0:fb7af294d5d9 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
Simon Cooksey 0:fb7af294d5d9 431 return(result);
Simon Cooksey 0:fb7af294d5d9 432 }
Simon Cooksey 0:fb7af294d5d9 433
Simon Cooksey 0:fb7af294d5d9 434
Simon Cooksey 0:fb7af294d5d9 435 /** \brief Set Process Stack Pointer
Simon Cooksey 0:fb7af294d5d9 436
Simon Cooksey 0:fb7af294d5d9 437 This function assigns the given value to the Process Stack Pointer (PSP).
Simon Cooksey 0:fb7af294d5d9 438
Simon Cooksey 0:fb7af294d5d9 439 \param [in] topOfProcStack Process Stack Pointer value to set
Simon Cooksey 0:fb7af294d5d9 440 */
Simon Cooksey 0:fb7af294d5d9 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Simon Cooksey 0:fb7af294d5d9 442 {
Simon Cooksey 0:fb7af294d5d9 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
Simon Cooksey 0:fb7af294d5d9 444 }
Simon Cooksey 0:fb7af294d5d9 445
Simon Cooksey 0:fb7af294d5d9 446
Simon Cooksey 0:fb7af294d5d9 447 /** \brief Get Main Stack Pointer
Simon Cooksey 0:fb7af294d5d9 448
Simon Cooksey 0:fb7af294d5d9 449 This function returns the current value of the Main Stack Pointer (MSP).
Simon Cooksey 0:fb7af294d5d9 450
Simon Cooksey 0:fb7af294d5d9 451 \return MSP Register value
Simon Cooksey 0:fb7af294d5d9 452 */
Simon Cooksey 0:fb7af294d5d9 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
Simon Cooksey 0:fb7af294d5d9 454 {
Simon Cooksey 0:fb7af294d5d9 455 register uint32_t result;
Simon Cooksey 0:fb7af294d5d9 456
Simon Cooksey 0:fb7af294d5d9 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
Simon Cooksey 0:fb7af294d5d9 458 return(result);
Simon Cooksey 0:fb7af294d5d9 459 }
Simon Cooksey 0:fb7af294d5d9 460
Simon Cooksey 0:fb7af294d5d9 461
Simon Cooksey 0:fb7af294d5d9 462 /** \brief Set Main Stack Pointer
Simon Cooksey 0:fb7af294d5d9 463
Simon Cooksey 0:fb7af294d5d9 464 This function assigns the given value to the Main Stack Pointer (MSP).
Simon Cooksey 0:fb7af294d5d9 465
Simon Cooksey 0:fb7af294d5d9 466 \param [in] topOfMainStack Main Stack Pointer value to set
Simon Cooksey 0:fb7af294d5d9 467 */
Simon Cooksey 0:fb7af294d5d9 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
Simon Cooksey 0:fb7af294d5d9 469 {
Simon Cooksey 0:fb7af294d5d9 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
Simon Cooksey 0:fb7af294d5d9 471 }
Simon Cooksey 0:fb7af294d5d9 472
Simon Cooksey 0:fb7af294d5d9 473
Simon Cooksey 0:fb7af294d5d9 474 /** \brief Get Priority Mask
Simon Cooksey 0:fb7af294d5d9 475
Simon Cooksey 0:fb7af294d5d9 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
Simon Cooksey 0:fb7af294d5d9 477
Simon Cooksey 0:fb7af294d5d9 478 \return Priority Mask value
Simon Cooksey 0:fb7af294d5d9 479 */
Simon Cooksey 0:fb7af294d5d9 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
Simon Cooksey 0:fb7af294d5d9 481 {
Simon Cooksey 0:fb7af294d5d9 482 uint32_t result;
Simon Cooksey 0:fb7af294d5d9 483
Simon Cooksey 0:fb7af294d5d9 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
Simon Cooksey 0:fb7af294d5d9 485 return(result);
Simon Cooksey 0:fb7af294d5d9 486 }
Simon Cooksey 0:fb7af294d5d9 487
Simon Cooksey 0:fb7af294d5d9 488
Simon Cooksey 0:fb7af294d5d9 489 /** \brief Set Priority Mask
Simon Cooksey 0:fb7af294d5d9 490
Simon Cooksey 0:fb7af294d5d9 491 This function assigns the given value to the Priority Mask Register.
Simon Cooksey 0:fb7af294d5d9 492
Simon Cooksey 0:fb7af294d5d9 493 \param [in] priMask Priority Mask
Simon Cooksey 0:fb7af294d5d9 494 */
Simon Cooksey 0:fb7af294d5d9 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
Simon Cooksey 0:fb7af294d5d9 496 {
Simon Cooksey 0:fb7af294d5d9 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
Simon Cooksey 0:fb7af294d5d9 498 }
Simon Cooksey 0:fb7af294d5d9 499
Simon Cooksey 0:fb7af294d5d9 500
Simon Cooksey 0:fb7af294d5d9 501 #if (__CORTEX_M >= 0x03)
Simon Cooksey 0:fb7af294d5d9 502
Simon Cooksey 0:fb7af294d5d9 503 /** \brief Enable FIQ
Simon Cooksey 0:fb7af294d5d9 504
Simon Cooksey 0:fb7af294d5d9 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Simon Cooksey 0:fb7af294d5d9 506 Can only be executed in Privileged modes.
Simon Cooksey 0:fb7af294d5d9 507 */
Simon Cooksey 0:fb7af294d5d9 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
Simon Cooksey 0:fb7af294d5d9 509 {
Simon Cooksey 0:fb7af294d5d9 510 __ASM volatile ("cpsie f" : : : "memory");
Simon Cooksey 0:fb7af294d5d9 511 }
Simon Cooksey 0:fb7af294d5d9 512
Simon Cooksey 0:fb7af294d5d9 513
Simon Cooksey 0:fb7af294d5d9 514 /** \brief Disable FIQ
Simon Cooksey 0:fb7af294d5d9 515
Simon Cooksey 0:fb7af294d5d9 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Simon Cooksey 0:fb7af294d5d9 517 Can only be executed in Privileged modes.
Simon Cooksey 0:fb7af294d5d9 518 */
Simon Cooksey 0:fb7af294d5d9 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
Simon Cooksey 0:fb7af294d5d9 520 {
Simon Cooksey 0:fb7af294d5d9 521 __ASM volatile ("cpsid f" : : : "memory");
Simon Cooksey 0:fb7af294d5d9 522 }
Simon Cooksey 0:fb7af294d5d9 523
Simon Cooksey 0:fb7af294d5d9 524
Simon Cooksey 0:fb7af294d5d9 525 /** \brief Get Base Priority
Simon Cooksey 0:fb7af294d5d9 526
Simon Cooksey 0:fb7af294d5d9 527 This function returns the current value of the Base Priority register.
Simon Cooksey 0:fb7af294d5d9 528
Simon Cooksey 0:fb7af294d5d9 529 \return Base Priority register value
Simon Cooksey 0:fb7af294d5d9 530 */
Simon Cooksey 0:fb7af294d5d9 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
Simon Cooksey 0:fb7af294d5d9 532 {
Simon Cooksey 0:fb7af294d5d9 533 uint32_t result;
Simon Cooksey 0:fb7af294d5d9 534
Simon Cooksey 0:fb7af294d5d9 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
Simon Cooksey 0:fb7af294d5d9 536 return(result);
Simon Cooksey 0:fb7af294d5d9 537 }
Simon Cooksey 0:fb7af294d5d9 538
Simon Cooksey 0:fb7af294d5d9 539
Simon Cooksey 0:fb7af294d5d9 540 /** \brief Set Base Priority
Simon Cooksey 0:fb7af294d5d9 541
Simon Cooksey 0:fb7af294d5d9 542 This function assigns the given value to the Base Priority register.
Simon Cooksey 0:fb7af294d5d9 543
Simon Cooksey 0:fb7af294d5d9 544 \param [in] basePri Base Priority value to set
Simon Cooksey 0:fb7af294d5d9 545 */
Simon Cooksey 0:fb7af294d5d9 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
Simon Cooksey 0:fb7af294d5d9 547 {
Simon Cooksey 0:fb7af294d5d9 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
Simon Cooksey 0:fb7af294d5d9 549 }
Simon Cooksey 0:fb7af294d5d9 550
Simon Cooksey 0:fb7af294d5d9 551
Simon Cooksey 0:fb7af294d5d9 552 /** \brief Set Base Priority with condition
Simon Cooksey 0:fb7af294d5d9 553
Simon Cooksey 0:fb7af294d5d9 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
Simon Cooksey 0:fb7af294d5d9 555 or the new value increases the BASEPRI priority level.
Simon Cooksey 0:fb7af294d5d9 556
Simon Cooksey 0:fb7af294d5d9 557 \param [in] basePri Base Priority value to set
Simon Cooksey 0:fb7af294d5d9 558 */
Simon Cooksey 0:fb7af294d5d9 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
Simon Cooksey 0:fb7af294d5d9 560 {
Simon Cooksey 0:fb7af294d5d9 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
Simon Cooksey 0:fb7af294d5d9 562 }
Simon Cooksey 0:fb7af294d5d9 563
Simon Cooksey 0:fb7af294d5d9 564
Simon Cooksey 0:fb7af294d5d9 565 /** \brief Get Fault Mask
Simon Cooksey 0:fb7af294d5d9 566
Simon Cooksey 0:fb7af294d5d9 567 This function returns the current value of the Fault Mask register.
Simon Cooksey 0:fb7af294d5d9 568
Simon Cooksey 0:fb7af294d5d9 569 \return Fault Mask register value
Simon Cooksey 0:fb7af294d5d9 570 */
Simon Cooksey 0:fb7af294d5d9 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
Simon Cooksey 0:fb7af294d5d9 572 {
Simon Cooksey 0:fb7af294d5d9 573 uint32_t result;
Simon Cooksey 0:fb7af294d5d9 574
Simon Cooksey 0:fb7af294d5d9 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
Simon Cooksey 0:fb7af294d5d9 576 return(result);
Simon Cooksey 0:fb7af294d5d9 577 }
Simon Cooksey 0:fb7af294d5d9 578
Simon Cooksey 0:fb7af294d5d9 579
Simon Cooksey 0:fb7af294d5d9 580 /** \brief Set Fault Mask
Simon Cooksey 0:fb7af294d5d9 581
Simon Cooksey 0:fb7af294d5d9 582 This function assigns the given value to the Fault Mask register.
Simon Cooksey 0:fb7af294d5d9 583
Simon Cooksey 0:fb7af294d5d9 584 \param [in] faultMask Fault Mask value to set
Simon Cooksey 0:fb7af294d5d9 585 */
Simon Cooksey 0:fb7af294d5d9 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
Simon Cooksey 0:fb7af294d5d9 587 {
Simon Cooksey 0:fb7af294d5d9 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
Simon Cooksey 0:fb7af294d5d9 589 }
Simon Cooksey 0:fb7af294d5d9 590
Simon Cooksey 0:fb7af294d5d9 591 #endif /* (__CORTEX_M >= 0x03) */
Simon Cooksey 0:fb7af294d5d9 592
Simon Cooksey 0:fb7af294d5d9 593
Simon Cooksey 0:fb7af294d5d9 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
Simon Cooksey 0:fb7af294d5d9 595
Simon Cooksey 0:fb7af294d5d9 596 /** \brief Get FPSCR
Simon Cooksey 0:fb7af294d5d9 597
Simon Cooksey 0:fb7af294d5d9 598 This function returns the current value of the Floating Point Status/Control register.
Simon Cooksey 0:fb7af294d5d9 599
Simon Cooksey 0:fb7af294d5d9 600 \return Floating Point Status/Control register value
Simon Cooksey 0:fb7af294d5d9 601 */
Simon Cooksey 0:fb7af294d5d9 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Simon Cooksey 0:fb7af294d5d9 603 {
Simon Cooksey 0:fb7af294d5d9 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Simon Cooksey 0:fb7af294d5d9 605 uint32_t result;
Simon Cooksey 0:fb7af294d5d9 606
Simon Cooksey 0:fb7af294d5d9 607 /* Empty asm statement works as a scheduling barrier */
Simon Cooksey 0:fb7af294d5d9 608 __ASM volatile ("");
Simon Cooksey 0:fb7af294d5d9 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
Simon Cooksey 0:fb7af294d5d9 610 __ASM volatile ("");
Simon Cooksey 0:fb7af294d5d9 611 return(result);
Simon Cooksey 0:fb7af294d5d9 612 #else
Simon Cooksey 0:fb7af294d5d9 613 return(0);
Simon Cooksey 0:fb7af294d5d9 614 #endif
Simon Cooksey 0:fb7af294d5d9 615 }
Simon Cooksey 0:fb7af294d5d9 616
Simon Cooksey 0:fb7af294d5d9 617
Simon Cooksey 0:fb7af294d5d9 618 /** \brief Set FPSCR
Simon Cooksey 0:fb7af294d5d9 619
Simon Cooksey 0:fb7af294d5d9 620 This function assigns the given value to the Floating Point Status/Control register.
Simon Cooksey 0:fb7af294d5d9 621
Simon Cooksey 0:fb7af294d5d9 622 \param [in] fpscr Floating Point Status/Control value to set
Simon Cooksey 0:fb7af294d5d9 623 */
Simon Cooksey 0:fb7af294d5d9 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Simon Cooksey 0:fb7af294d5d9 625 {
Simon Cooksey 0:fb7af294d5d9 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Simon Cooksey 0:fb7af294d5d9 627 /* Empty asm statement works as a scheduling barrier */
Simon Cooksey 0:fb7af294d5d9 628 __ASM volatile ("");
Simon Cooksey 0:fb7af294d5d9 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
Simon Cooksey 0:fb7af294d5d9 630 __ASM volatile ("");
Simon Cooksey 0:fb7af294d5d9 631 #endif
Simon Cooksey 0:fb7af294d5d9 632 }
Simon Cooksey 0:fb7af294d5d9 633
Simon Cooksey 0:fb7af294d5d9 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
Simon Cooksey 0:fb7af294d5d9 635
Simon Cooksey 0:fb7af294d5d9 636
Simon Cooksey 0:fb7af294d5d9 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
Simon Cooksey 0:fb7af294d5d9 638 /* IAR iccarm specific functions */
Simon Cooksey 0:fb7af294d5d9 639 #include <cmsis_iar.h>
Simon Cooksey 0:fb7af294d5d9 640
Simon Cooksey 0:fb7af294d5d9 641
Simon Cooksey 0:fb7af294d5d9 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
Simon Cooksey 0:fb7af294d5d9 643 /* TI CCS specific functions */
Simon Cooksey 0:fb7af294d5d9 644 #include <cmsis_ccs.h>
Simon Cooksey 0:fb7af294d5d9 645
Simon Cooksey 0:fb7af294d5d9 646
Simon Cooksey 0:fb7af294d5d9 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
Simon Cooksey 0:fb7af294d5d9 648 /* TASKING carm specific functions */
Simon Cooksey 0:fb7af294d5d9 649 /*
Simon Cooksey 0:fb7af294d5d9 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
Simon Cooksey 0:fb7af294d5d9 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
Simon Cooksey 0:fb7af294d5d9 652 * Including the CMSIS ones.
Simon Cooksey 0:fb7af294d5d9 653 */
Simon Cooksey 0:fb7af294d5d9 654
Simon Cooksey 0:fb7af294d5d9 655
Simon Cooksey 0:fb7af294d5d9 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
Simon Cooksey 0:fb7af294d5d9 657 /* Cosmic specific functions */
Simon Cooksey 0:fb7af294d5d9 658 #include <cmsis_csm.h>
Simon Cooksey 0:fb7af294d5d9 659
Simon Cooksey 0:fb7af294d5d9 660 #endif
Simon Cooksey 0:fb7af294d5d9 661
Simon Cooksey 0:fb7af294d5d9 662 /*@} end of CMSIS_Core_RegAccFunctions */
Simon Cooksey 0:fb7af294d5d9 663
Simon Cooksey 0:fb7af294d5d9 664 #endif /* __CORE_CMFUNC_H */