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cmsis/core_cm7.h@0:fb7af294d5d9, 2016-11-17 (annotated)

Committer:: Simon Cooksey
Date:: Thu Nov 17 16:43:53 2016 +0000
Revision:: 0:fb7af294d5d9

Initial commit

Who changed what in which revision?

User	Revision	Line number	New contents of line
Simon Cooksey	0:fb7af294d5d9	1	/************************************************************************//
Simon Cooksey	0:fb7af294d5d9	2	* @file core_cm7.h
Simon Cooksey	0:fb7af294d5d9	3	* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
Simon Cooksey	0:fb7af294d5d9	4	* @version V4.10
Simon Cooksey	0:fb7af294d5d9	5	* @date 18. March 2015
Simon Cooksey	0:fb7af294d5d9	6	*
Simon Cooksey	0:fb7af294d5d9	7	* @note
Simon Cooksey	0:fb7af294d5d9	8	*
Simon Cooksey	0:fb7af294d5d9	9	******************************************************************************/
Simon Cooksey	0:fb7af294d5d9	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
Simon Cooksey	0:fb7af294d5d9	11
Simon Cooksey	0:fb7af294d5d9	12	All rights reserved.
Simon Cooksey	0:fb7af294d5d9	13	Redistribution and use in source and binary forms, with or without
Simon Cooksey	0:fb7af294d5d9	14	modification, are permitted provided that the following conditions are met:
Simon Cooksey	0:fb7af294d5d9	15	- Redistributions of source code must retain the above copyright
Simon Cooksey	0:fb7af294d5d9	16	notice, this list of conditions and the following disclaimer.
Simon Cooksey	0:fb7af294d5d9	17	- Redistributions in binary form must reproduce the above copyright
Simon Cooksey	0:fb7af294d5d9	18	notice, this list of conditions and the following disclaimer in the
Simon Cooksey	0:fb7af294d5d9	19	documentation and/or other materials provided with the distribution.
Simon Cooksey	0:fb7af294d5d9	20	- Neither the name of ARM nor the names of its contributors may be used
Simon Cooksey	0:fb7af294d5d9	21	to endorse or promote products derived from this software without
Simon Cooksey	0:fb7af294d5d9	22	specific prior written permission.
Simon Cooksey	0:fb7af294d5d9	23	*
Simon Cooksey	0:fb7af294d5d9	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Simon Cooksey	0:fb7af294d5d9	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Simon Cooksey	0:fb7af294d5d9	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Simon Cooksey	0:fb7af294d5d9	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Simon Cooksey	0:fb7af294d5d9	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Simon Cooksey	0:fb7af294d5d9	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Simon Cooksey	0:fb7af294d5d9	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Simon Cooksey	0:fb7af294d5d9	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Simon Cooksey	0:fb7af294d5d9	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Simon Cooksey	0:fb7af294d5d9	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Simon Cooksey	0:fb7af294d5d9	34	POSSIBILITY OF SUCH DAMAGE.
Simon Cooksey	0:fb7af294d5d9	35	---------------------------------------------------------------------------*/
Simon Cooksey	0:fb7af294d5d9	36
Simon Cooksey	0:fb7af294d5d9	37
Simon Cooksey	0:fb7af294d5d9	38	#if defined ( __ICCARM__ )
Simon Cooksey	0:fb7af294d5d9	39	#pragma system_include /* treat file as system include file for MISRA check */
Simon Cooksey	0:fb7af294d5d9	40	#endif
Simon Cooksey	0:fb7af294d5d9	41
Simon Cooksey	0:fb7af294d5d9	42	#ifndef __CORE_CM7_H_GENERIC
Simon Cooksey	0:fb7af294d5d9	43	#define __CORE_CM7_H_GENERIC
Simon Cooksey	0:fb7af294d5d9	44
Simon Cooksey	0:fb7af294d5d9	45	#ifdef __cplusplus
Simon Cooksey	0:fb7af294d5d9	46	extern "C" {
Simon Cooksey	0:fb7af294d5d9	47	#endif
Simon Cooksey	0:fb7af294d5d9	48
Simon Cooksey	0:fb7af294d5d9	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Simon Cooksey	0:fb7af294d5d9	50	CMSIS violates the following MISRA-C:2004 rules:
Simon Cooksey	0:fb7af294d5d9	51
Simon Cooksey	0:fb7af294d5d9	52	\li Required Rule 8.5, object/function definition in header file.<br>
Simon Cooksey	0:fb7af294d5d9	53	Function definitions in header files are used to allow 'inlining'.
Simon Cooksey	0:fb7af294d5d9	54
Simon Cooksey	0:fb7af294d5d9	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Simon Cooksey	0:fb7af294d5d9	56	Unions are used for effective representation of core registers.
Simon Cooksey	0:fb7af294d5d9	57
Simon Cooksey	0:fb7af294d5d9	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
Simon Cooksey	0:fb7af294d5d9	59	Function-like macros are used to allow more efficient code.
Simon Cooksey	0:fb7af294d5d9	60	*/
Simon Cooksey	0:fb7af294d5d9	61
Simon Cooksey	0:fb7af294d5d9	62
Simon Cooksey	0:fb7af294d5d9	63	/*******************************************************************************
Simon Cooksey	0:fb7af294d5d9	64	* CMSIS definitions
Simon Cooksey	0:fb7af294d5d9	65	******************************************************************************/
Simon Cooksey	0:fb7af294d5d9	66	/** \ingroup Cortex_M7
Simon Cooksey	0:fb7af294d5d9	67	@{
Simon Cooksey	0:fb7af294d5d9	68	*/
Simon Cooksey	0:fb7af294d5d9	69
Simon Cooksey	0:fb7af294d5d9	70	/* CMSIS CM7 definitions */
Simon Cooksey	0:fb7af294d5d9	71	#define __CM7_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
Simon Cooksey	0:fb7af294d5d9	72	#define __CM7_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
Simon Cooksey	0:fb7af294d5d9	73	#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) \| \
Simon Cooksey	0:fb7af294d5d9	74	__CM7_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
Simon Cooksey	0:fb7af294d5d9	75
Simon Cooksey	0:fb7af294d5d9	76	#define __CORTEX_M (0x07) /!< Cortex-M Core /
Simon Cooksey	0:fb7af294d5d9	77
Simon Cooksey	0:fb7af294d5d9	78
Simon Cooksey	0:fb7af294d5d9	79	#if defined ( __CC_ARM )
Simon Cooksey	0:fb7af294d5d9	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
Simon Cooksey	0:fb7af294d5d9	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
Simon Cooksey	0:fb7af294d5d9	82	#define __STATIC_INLINE static __inline
Simon Cooksey	0:fb7af294d5d9	83
Simon Cooksey	0:fb7af294d5d9	84	#elif defined ( __GNUC__ )
Simon Cooksey	0:fb7af294d5d9	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
Simon Cooksey	0:fb7af294d5d9	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
Simon Cooksey	0:fb7af294d5d9	87	#define __STATIC_INLINE static inline
Simon Cooksey	0:fb7af294d5d9	88
Simon Cooksey	0:fb7af294d5d9	89	#elif defined ( __ICCARM__ )
Simon Cooksey	0:fb7af294d5d9	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
Simon Cooksey	0:fb7af294d5d9	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
Simon Cooksey	0:fb7af294d5d9	92	#define __STATIC_INLINE static inline
Simon Cooksey	0:fb7af294d5d9	93
Simon Cooksey	0:fb7af294d5d9	94	#elif defined ( __TMS470__ )
Simon Cooksey	0:fb7af294d5d9	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
Simon Cooksey	0:fb7af294d5d9	96	#define __STATIC_INLINE static inline
Simon Cooksey	0:fb7af294d5d9	97
Simon Cooksey	0:fb7af294d5d9	98	#elif defined ( __TASKING__ )
Simon Cooksey	0:fb7af294d5d9	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
Simon Cooksey	0:fb7af294d5d9	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
Simon Cooksey	0:fb7af294d5d9	101	#define __STATIC_INLINE static inline
Simon Cooksey	0:fb7af294d5d9	102
Simon Cooksey	0:fb7af294d5d9	103	#elif defined ( __CSMC__ )
Simon Cooksey	0:fb7af294d5d9	104	#define __packed
Simon Cooksey	0:fb7af294d5d9	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
Simon Cooksey	0:fb7af294d5d9	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
Simon Cooksey	0:fb7af294d5d9	107	#define __STATIC_INLINE static inline
Simon Cooksey	0:fb7af294d5d9	108
Simon Cooksey	0:fb7af294d5d9	109	#endif
Simon Cooksey	0:fb7af294d5d9	110
Simon Cooksey	0:fb7af294d5d9	111	/** __FPU_USED indicates whether an FPU is used or not.
Simon Cooksey	0:fb7af294d5d9	112	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
Simon Cooksey	0:fb7af294d5d9	113	*/
Simon Cooksey	0:fb7af294d5d9	114	#if defined ( __CC_ARM )
Simon Cooksey	0:fb7af294d5d9	115	#if defined __TARGET_FPU_VFP
Simon Cooksey	0:fb7af294d5d9	116	#if (__FPU_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	117	#define __FPU_USED 1
Simon Cooksey	0:fb7af294d5d9	118	#else
Simon Cooksey	0:fb7af294d5d9	119	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Simon Cooksey	0:fb7af294d5d9	120	#define __FPU_USED 0
Simon Cooksey	0:fb7af294d5d9	121	#endif
Simon Cooksey	0:fb7af294d5d9	122	#else
Simon Cooksey	0:fb7af294d5d9	123	#define __FPU_USED 0
Simon Cooksey	0:fb7af294d5d9	124	#endif
Simon Cooksey	0:fb7af294d5d9	125
Simon Cooksey	0:fb7af294d5d9	126	#elif defined ( __GNUC__ )
Simon Cooksey	0:fb7af294d5d9	127	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
Simon Cooksey	0:fb7af294d5d9	128	#if (__FPU_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	129	#define __FPU_USED 1
Simon Cooksey	0:fb7af294d5d9	130	#else
Simon Cooksey	0:fb7af294d5d9	131	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Simon Cooksey	0:fb7af294d5d9	132	#define __FPU_USED 0
Simon Cooksey	0:fb7af294d5d9	133	#endif
Simon Cooksey	0:fb7af294d5d9	134	#else
Simon Cooksey	0:fb7af294d5d9	135	#define __FPU_USED 0
Simon Cooksey	0:fb7af294d5d9	136	#endif
Simon Cooksey	0:fb7af294d5d9	137
Simon Cooksey	0:fb7af294d5d9	138	#elif defined ( __ICCARM__ )
Simon Cooksey	0:fb7af294d5d9	139	#if defined __ARMVFP__
Simon Cooksey	0:fb7af294d5d9	140	#if (__FPU_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	141	#define __FPU_USED 1
Simon Cooksey	0:fb7af294d5d9	142	#else
Simon Cooksey	0:fb7af294d5d9	143	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Simon Cooksey	0:fb7af294d5d9	144	#define __FPU_USED 0
Simon Cooksey	0:fb7af294d5d9	145	#endif
Simon Cooksey	0:fb7af294d5d9	146	#else
Simon Cooksey	0:fb7af294d5d9	147	#define __FPU_USED 0
Simon Cooksey	0:fb7af294d5d9	148	#endif
Simon Cooksey	0:fb7af294d5d9	149
Simon Cooksey	0:fb7af294d5d9	150	#elif defined ( __TMS470__ )
Simon Cooksey	0:fb7af294d5d9	151	#if defined __TI_VFP_SUPPORT__
Simon Cooksey	0:fb7af294d5d9	152	#if (__FPU_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	153	#define __FPU_USED 1
Simon Cooksey	0:fb7af294d5d9	154	#else
Simon Cooksey	0:fb7af294d5d9	155	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Simon Cooksey	0:fb7af294d5d9	156	#define __FPU_USED 0
Simon Cooksey	0:fb7af294d5d9	157	#endif
Simon Cooksey	0:fb7af294d5d9	158	#else
Simon Cooksey	0:fb7af294d5d9	159	#define __FPU_USED 0
Simon Cooksey	0:fb7af294d5d9	160	#endif
Simon Cooksey	0:fb7af294d5d9	161
Simon Cooksey	0:fb7af294d5d9	162	#elif defined ( __TASKING__ )
Simon Cooksey	0:fb7af294d5d9	163	#if defined __FPU_VFP__
Simon Cooksey	0:fb7af294d5d9	164	#if (__FPU_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	165	#define __FPU_USED 1
Simon Cooksey	0:fb7af294d5d9	166	#else
Simon Cooksey	0:fb7af294d5d9	167	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Simon Cooksey	0:fb7af294d5d9	168	#define __FPU_USED 0
Simon Cooksey	0:fb7af294d5d9	169	#endif
Simon Cooksey	0:fb7af294d5d9	170	#else
Simon Cooksey	0:fb7af294d5d9	171	#define __FPU_USED 0
Simon Cooksey	0:fb7af294d5d9	172	#endif
Simon Cooksey	0:fb7af294d5d9	173
Simon Cooksey	0:fb7af294d5d9	174	#elif defined ( __CSMC__ ) /* Cosmic */
Simon Cooksey	0:fb7af294d5d9	175	#if ( __CSMC__ & 0x400) // FPU present for parser
Simon Cooksey	0:fb7af294d5d9	176	#if (__FPU_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	177	#define __FPU_USED 1
Simon Cooksey	0:fb7af294d5d9	178	#else
Simon Cooksey	0:fb7af294d5d9	179	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Simon Cooksey	0:fb7af294d5d9	180	#define __FPU_USED 0
Simon Cooksey	0:fb7af294d5d9	181	#endif
Simon Cooksey	0:fb7af294d5d9	182	#else
Simon Cooksey	0:fb7af294d5d9	183	#define __FPU_USED 0
Simon Cooksey	0:fb7af294d5d9	184	#endif
Simon Cooksey	0:fb7af294d5d9	185	#endif
Simon Cooksey	0:fb7af294d5d9	186
Simon Cooksey	0:fb7af294d5d9	187	#include <stdint.h> /* standard types definitions */
Simon Cooksey	0:fb7af294d5d9	188	#include <core_cmInstr.h> /* Core Instruction Access */
Simon Cooksey	0:fb7af294d5d9	189	#include <core_cmFunc.h> /* Core Function Access */
Simon Cooksey	0:fb7af294d5d9	190	#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
Simon Cooksey	0:fb7af294d5d9	191
Simon Cooksey	0:fb7af294d5d9	192	#ifdef __cplusplus
Simon Cooksey	0:fb7af294d5d9	193	}
Simon Cooksey	0:fb7af294d5d9	194	#endif
Simon Cooksey	0:fb7af294d5d9	195
Simon Cooksey	0:fb7af294d5d9	196	#endif /* __CORE_CM7_H_GENERIC */
Simon Cooksey	0:fb7af294d5d9	197
Simon Cooksey	0:fb7af294d5d9	198	#ifndef __CMSIS_GENERIC
Simon Cooksey	0:fb7af294d5d9	199
Simon Cooksey	0:fb7af294d5d9	200	#ifndef __CORE_CM7_H_DEPENDANT
Simon Cooksey	0:fb7af294d5d9	201	#define __CORE_CM7_H_DEPENDANT
Simon Cooksey	0:fb7af294d5d9	202
Simon Cooksey	0:fb7af294d5d9	203	#ifdef __cplusplus
Simon Cooksey	0:fb7af294d5d9	204	extern "C" {
Simon Cooksey	0:fb7af294d5d9	205	#endif
Simon Cooksey	0:fb7af294d5d9	206
Simon Cooksey	0:fb7af294d5d9	207	/* check device defines and use defaults */
Simon Cooksey	0:fb7af294d5d9	208	#if defined __CHECK_DEVICE_DEFINES
Simon Cooksey	0:fb7af294d5d9	209	#ifndef __CM7_REV
Simon Cooksey	0:fb7af294d5d9	210	#define __CM7_REV 0x0000
Simon Cooksey	0:fb7af294d5d9	211	#warning "__CM7_REV not defined in device header file; using default!"
Simon Cooksey	0:fb7af294d5d9	212	#endif
Simon Cooksey	0:fb7af294d5d9	213
Simon Cooksey	0:fb7af294d5d9	214	#ifndef __FPU_PRESENT
Simon Cooksey	0:fb7af294d5d9	215	#define __FPU_PRESENT 0
Simon Cooksey	0:fb7af294d5d9	216	#warning "__FPU_PRESENT not defined in device header file; using default!"
Simon Cooksey	0:fb7af294d5d9	217	#endif
Simon Cooksey	0:fb7af294d5d9	218
Simon Cooksey	0:fb7af294d5d9	219	#ifndef __MPU_PRESENT
Simon Cooksey	0:fb7af294d5d9	220	#define __MPU_PRESENT 0
Simon Cooksey	0:fb7af294d5d9	221	#warning "__MPU_PRESENT not defined in device header file; using default!"
Simon Cooksey	0:fb7af294d5d9	222	#endif
Simon Cooksey	0:fb7af294d5d9	223
Simon Cooksey	0:fb7af294d5d9	224	#ifndef __ICACHE_PRESENT
Simon Cooksey	0:fb7af294d5d9	225	#define __ICACHE_PRESENT 0
Simon Cooksey	0:fb7af294d5d9	226	#warning "__ICACHE_PRESENT not defined in device header file; using default!"
Simon Cooksey	0:fb7af294d5d9	227	#endif
Simon Cooksey	0:fb7af294d5d9	228
Simon Cooksey	0:fb7af294d5d9	229	#ifndef __DCACHE_PRESENT
Simon Cooksey	0:fb7af294d5d9	230	#define __DCACHE_PRESENT 0
Simon Cooksey	0:fb7af294d5d9	231	#warning "__DCACHE_PRESENT not defined in device header file; using default!"
Simon Cooksey	0:fb7af294d5d9	232	#endif
Simon Cooksey	0:fb7af294d5d9	233
Simon Cooksey	0:fb7af294d5d9	234	#ifndef __DTCM_PRESENT
Simon Cooksey	0:fb7af294d5d9	235	#define __DTCM_PRESENT 0
Simon Cooksey	0:fb7af294d5d9	236	#warning "__DTCM_PRESENT not defined in device header file; using default!"
Simon Cooksey	0:fb7af294d5d9	237	#endif
Simon Cooksey	0:fb7af294d5d9	238
Simon Cooksey	0:fb7af294d5d9	239	#ifndef __NVIC_PRIO_BITS
Simon Cooksey	0:fb7af294d5d9	240	#define __NVIC_PRIO_BITS 3
Simon Cooksey	0:fb7af294d5d9	241	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Simon Cooksey	0:fb7af294d5d9	242	#endif
Simon Cooksey	0:fb7af294d5d9	243
Simon Cooksey	0:fb7af294d5d9	244	#ifndef __Vendor_SysTickConfig
Simon Cooksey	0:fb7af294d5d9	245	#define __Vendor_SysTickConfig 0
Simon Cooksey	0:fb7af294d5d9	246	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Simon Cooksey	0:fb7af294d5d9	247	#endif
Simon Cooksey	0:fb7af294d5d9	248	#endif
Simon Cooksey	0:fb7af294d5d9	249
Simon Cooksey	0:fb7af294d5d9	250	/* IO definitions (access restrictions to peripheral registers) */
Simon Cooksey	0:fb7af294d5d9	251	/**
Simon Cooksey	0:fb7af294d5d9	252	\defgroup CMSIS_glob_defs CMSIS Global Defines
Simon Cooksey	0:fb7af294d5d9	253
Simon Cooksey	0:fb7af294d5d9	254	<strong>IO Type Qualifiers</strong> are used
Simon Cooksey	0:fb7af294d5d9	255	\li to specify the access to peripheral variables.
Simon Cooksey	0:fb7af294d5d9	256	\li for automatic generation of peripheral register debug information.
Simon Cooksey	0:fb7af294d5d9	257	*/
Simon Cooksey	0:fb7af294d5d9	258	#ifdef __cplusplus
Simon Cooksey	0:fb7af294d5d9	259	#define __I volatile /!< Defines 'read only' permissions /
Simon Cooksey	0:fb7af294d5d9	260	#else
Simon Cooksey	0:fb7af294d5d9	261	#define __I volatile const /!< Defines 'read only' permissions /
Simon Cooksey	0:fb7af294d5d9	262	#endif
Simon Cooksey	0:fb7af294d5d9	263	#define __O volatile /!< Defines 'write only' permissions /
Simon Cooksey	0:fb7af294d5d9	264	#define __IO volatile /!< Defines 'read / write' permissions /
Simon Cooksey	0:fb7af294d5d9	265
Simon Cooksey	0:fb7af294d5d9	266	#ifdef __cplusplus
Simon Cooksey	0:fb7af294d5d9	267	#define __IM volatile /!< Defines 'read only' permissions /
Simon Cooksey	0:fb7af294d5d9	268	#else
Simon Cooksey	0:fb7af294d5d9	269	#define __IM volatile const /!< Defines 'read only' permissions /
Simon Cooksey	0:fb7af294d5d9	270	#endif
Simon Cooksey	0:fb7af294d5d9	271	#define __OM volatile /!< Defines 'write only' permissions /
Simon Cooksey	0:fb7af294d5d9	272	#define __IOM volatile /!< Defines 'read / write' permissions /
Simon Cooksey	0:fb7af294d5d9	273
Simon Cooksey	0:fb7af294d5d9	274	/@} end of group Cortex_M7 /
Simon Cooksey	0:fb7af294d5d9	275
Simon Cooksey	0:fb7af294d5d9	276
Simon Cooksey	0:fb7af294d5d9	277
Simon Cooksey	0:fb7af294d5d9	278	/*******************************************************************************
Simon Cooksey	0:fb7af294d5d9	279	* Register Abstraction
Simon Cooksey	0:fb7af294d5d9	280	Core Register contain:
Simon Cooksey	0:fb7af294d5d9	281	- Core Register
Simon Cooksey	0:fb7af294d5d9	282	- Core NVIC Register
Simon Cooksey	0:fb7af294d5d9	283	- Core SCB Register
Simon Cooksey	0:fb7af294d5d9	284	- Core SysTick Register
Simon Cooksey	0:fb7af294d5d9	285	- Core Debug Register
Simon Cooksey	0:fb7af294d5d9	286	- Core MPU Register
Simon Cooksey	0:fb7af294d5d9	287	- Core FPU Register
Simon Cooksey	0:fb7af294d5d9	288	******************************************************************************/
Simon Cooksey	0:fb7af294d5d9	289	/** \defgroup CMSIS_core_register Defines and Type Definitions
Simon Cooksey	0:fb7af294d5d9	290	\brief Type definitions and defines for Cortex-M processor based devices.
Simon Cooksey	0:fb7af294d5d9	291	*/
Simon Cooksey	0:fb7af294d5d9	292
Simon Cooksey	0:fb7af294d5d9	293	/** \ingroup CMSIS_core_register
Simon Cooksey	0:fb7af294d5d9	294	\defgroup CMSIS_CORE Status and Control Registers
Simon Cooksey	0:fb7af294d5d9	295	\brief Core Register type definitions.
Simon Cooksey	0:fb7af294d5d9	296	@{
Simon Cooksey	0:fb7af294d5d9	297	*/
Simon Cooksey	0:fb7af294d5d9	298
Simon Cooksey	0:fb7af294d5d9	299	/** \brief Union type to access the Application Program Status Register (APSR).
Simon Cooksey	0:fb7af294d5d9	300	*/
Simon Cooksey	0:fb7af294d5d9	301	typedef union
Simon Cooksey	0:fb7af294d5d9	302	{
Simon Cooksey	0:fb7af294d5d9	303	struct
Simon Cooksey	0:fb7af294d5d9	304	{
Simon Cooksey	0:fb7af294d5d9	305	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
Simon Cooksey	0:fb7af294d5d9	306	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Simon Cooksey	0:fb7af294d5d9	307	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
Simon Cooksey	0:fb7af294d5d9	308	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Simon Cooksey	0:fb7af294d5d9	309	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Simon Cooksey	0:fb7af294d5d9	310	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Simon Cooksey	0:fb7af294d5d9	311	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Simon Cooksey	0:fb7af294d5d9	312	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Simon Cooksey	0:fb7af294d5d9	313	} b; /!< Structure used for bit access /
Simon Cooksey	0:fb7af294d5d9	314	uint32_t w; /!< Type used for word access /
Simon Cooksey	0:fb7af294d5d9	315	} APSR_Type;
Simon Cooksey	0:fb7af294d5d9	316
Simon Cooksey	0:fb7af294d5d9	317	/* APSR Register Definitions */
Simon Cooksey	0:fb7af294d5d9	318	#define APSR_N_Pos 31 /!< APSR: N Position /
Simon Cooksey	0:fb7af294d5d9	319	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
Simon Cooksey	0:fb7af294d5d9	320
Simon Cooksey	0:fb7af294d5d9	321	#define APSR_Z_Pos 30 /!< APSR: Z Position /
Simon Cooksey	0:fb7af294d5d9	322	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
Simon Cooksey	0:fb7af294d5d9	323
Simon Cooksey	0:fb7af294d5d9	324	#define APSR_C_Pos 29 /!< APSR: C Position /
Simon Cooksey	0:fb7af294d5d9	325	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
Simon Cooksey	0:fb7af294d5d9	326
Simon Cooksey	0:fb7af294d5d9	327	#define APSR_V_Pos 28 /!< APSR: V Position /
Simon Cooksey	0:fb7af294d5d9	328	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
Simon Cooksey	0:fb7af294d5d9	329
Simon Cooksey	0:fb7af294d5d9	330	#define APSR_Q_Pos 27 /!< APSR: Q Position /
Simon Cooksey	0:fb7af294d5d9	331	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
Simon Cooksey	0:fb7af294d5d9	332
Simon Cooksey	0:fb7af294d5d9	333	#define APSR_GE_Pos 16 /!< APSR: GE Position /
Simon Cooksey	0:fb7af294d5d9	334	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
Simon Cooksey	0:fb7af294d5d9	335
Simon Cooksey	0:fb7af294d5d9	336
Simon Cooksey	0:fb7af294d5d9	337	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
Simon Cooksey	0:fb7af294d5d9	338	*/
Simon Cooksey	0:fb7af294d5d9	339	typedef union
Simon Cooksey	0:fb7af294d5d9	340	{
Simon Cooksey	0:fb7af294d5d9	341	struct
Simon Cooksey	0:fb7af294d5d9	342	{
Simon Cooksey	0:fb7af294d5d9	343	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Simon Cooksey	0:fb7af294d5d9	344	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
Simon Cooksey	0:fb7af294d5d9	345	} b; /!< Structure used for bit access /
Simon Cooksey	0:fb7af294d5d9	346	uint32_t w; /!< Type used for word access /
Simon Cooksey	0:fb7af294d5d9	347	} IPSR_Type;
Simon Cooksey	0:fb7af294d5d9	348
Simon Cooksey	0:fb7af294d5d9	349	/* IPSR Register Definitions */
Simon Cooksey	0:fb7af294d5d9	350	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
Simon Cooksey	0:fb7af294d5d9	351	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
Simon Cooksey	0:fb7af294d5d9	352
Simon Cooksey	0:fb7af294d5d9	353
Simon Cooksey	0:fb7af294d5d9	354	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Simon Cooksey	0:fb7af294d5d9	355	*/
Simon Cooksey	0:fb7af294d5d9	356	typedef union
Simon Cooksey	0:fb7af294d5d9	357	{
Simon Cooksey	0:fb7af294d5d9	358	struct
Simon Cooksey	0:fb7af294d5d9	359	{
Simon Cooksey	0:fb7af294d5d9	360	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Simon Cooksey	0:fb7af294d5d9	361	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
Simon Cooksey	0:fb7af294d5d9	362	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Simon Cooksey	0:fb7af294d5d9	363	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
Simon Cooksey	0:fb7af294d5d9	364	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
Simon Cooksey	0:fb7af294d5d9	365	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
Simon Cooksey	0:fb7af294d5d9	366	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Simon Cooksey	0:fb7af294d5d9	367	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Simon Cooksey	0:fb7af294d5d9	368	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Simon Cooksey	0:fb7af294d5d9	369	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Simon Cooksey	0:fb7af294d5d9	370	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Simon Cooksey	0:fb7af294d5d9	371	} b; /!< Structure used for bit access /
Simon Cooksey	0:fb7af294d5d9	372	uint32_t w; /!< Type used for word access /
Simon Cooksey	0:fb7af294d5d9	373	} xPSR_Type;
Simon Cooksey	0:fb7af294d5d9	374
Simon Cooksey	0:fb7af294d5d9	375	/* xPSR Register Definitions */
Simon Cooksey	0:fb7af294d5d9	376	#define xPSR_N_Pos 31 /!< xPSR: N Position /
Simon Cooksey	0:fb7af294d5d9	377	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
Simon Cooksey	0:fb7af294d5d9	378
Simon Cooksey	0:fb7af294d5d9	379	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
Simon Cooksey	0:fb7af294d5d9	380	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
Simon Cooksey	0:fb7af294d5d9	381
Simon Cooksey	0:fb7af294d5d9	382	#define xPSR_C_Pos 29 /!< xPSR: C Position /
Simon Cooksey	0:fb7af294d5d9	383	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
Simon Cooksey	0:fb7af294d5d9	384
Simon Cooksey	0:fb7af294d5d9	385	#define xPSR_V_Pos 28 /!< xPSR: V Position /
Simon Cooksey	0:fb7af294d5d9	386	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
Simon Cooksey	0:fb7af294d5d9	387
Simon Cooksey	0:fb7af294d5d9	388	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
Simon Cooksey	0:fb7af294d5d9	389	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
Simon Cooksey	0:fb7af294d5d9	390
Simon Cooksey	0:fb7af294d5d9	391	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
Simon Cooksey	0:fb7af294d5d9	392	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
Simon Cooksey	0:fb7af294d5d9	393
Simon Cooksey	0:fb7af294d5d9	394	#define xPSR_T_Pos 24 /!< xPSR: T Position /
Simon Cooksey	0:fb7af294d5d9	395	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
Simon Cooksey	0:fb7af294d5d9	396
Simon Cooksey	0:fb7af294d5d9	397	#define xPSR_GE_Pos 16 /!< xPSR: GE Position /
Simon Cooksey	0:fb7af294d5d9	398	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
Simon Cooksey	0:fb7af294d5d9	399
Simon Cooksey	0:fb7af294d5d9	400	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
Simon Cooksey	0:fb7af294d5d9	401	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
Simon Cooksey	0:fb7af294d5d9	402
Simon Cooksey	0:fb7af294d5d9	403
Simon Cooksey	0:fb7af294d5d9	404	/** \brief Union type to access the Control Registers (CONTROL).
Simon Cooksey	0:fb7af294d5d9	405	*/
Simon Cooksey	0:fb7af294d5d9	406	typedef union
Simon Cooksey	0:fb7af294d5d9	407	{
Simon Cooksey	0:fb7af294d5d9	408	struct
Simon Cooksey	0:fb7af294d5d9	409	{
Simon Cooksey	0:fb7af294d5d9	410	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
Simon Cooksey	0:fb7af294d5d9	411	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
Simon Cooksey	0:fb7af294d5d9	412	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
Simon Cooksey	0:fb7af294d5d9	413	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
Simon Cooksey	0:fb7af294d5d9	414	} b; /!< Structure used for bit access /
Simon Cooksey	0:fb7af294d5d9	415	uint32_t w; /!< Type used for word access /
Simon Cooksey	0:fb7af294d5d9	416	} CONTROL_Type;
Simon Cooksey	0:fb7af294d5d9	417
Simon Cooksey	0:fb7af294d5d9	418	/* CONTROL Register Definitions */
Simon Cooksey	0:fb7af294d5d9	419	#define CONTROL_FPCA_Pos 2 /!< CONTROL: FPCA Position /
Simon Cooksey	0:fb7af294d5d9	420	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
Simon Cooksey	0:fb7af294d5d9	421
Simon Cooksey	0:fb7af294d5d9	422	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
Simon Cooksey	0:fb7af294d5d9	423	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
Simon Cooksey	0:fb7af294d5d9	424
Simon Cooksey	0:fb7af294d5d9	425	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
Simon Cooksey	0:fb7af294d5d9	426	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
Simon Cooksey	0:fb7af294d5d9	427
Simon Cooksey	0:fb7af294d5d9	428	/@} end of group CMSIS_CORE /
Simon Cooksey	0:fb7af294d5d9	429
Simon Cooksey	0:fb7af294d5d9	430
Simon Cooksey	0:fb7af294d5d9	431	/** \ingroup CMSIS_core_register
Simon Cooksey	0:fb7af294d5d9	432	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Simon Cooksey	0:fb7af294d5d9	433	\brief Type definitions for the NVIC Registers
Simon Cooksey	0:fb7af294d5d9	434	@{
Simon Cooksey	0:fb7af294d5d9	435	*/
Simon Cooksey	0:fb7af294d5d9	436
Simon Cooksey	0:fb7af294d5d9	437	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Simon Cooksey	0:fb7af294d5d9	438	*/
Simon Cooksey	0:fb7af294d5d9	439	typedef struct
Simon Cooksey	0:fb7af294d5d9	440	{
Simon Cooksey	0:fb7af294d5d9	441	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
Simon Cooksey	0:fb7af294d5d9	442	uint32_t RESERVED0[24];
Simon Cooksey	0:fb7af294d5d9	443	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
Simon Cooksey	0:fb7af294d5d9	444	uint32_t RSERVED1[24];
Simon Cooksey	0:fb7af294d5d9	445	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
Simon Cooksey	0:fb7af294d5d9	446	uint32_t RESERVED2[24];
Simon Cooksey	0:fb7af294d5d9	447	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
Simon Cooksey	0:fb7af294d5d9	448	uint32_t RESERVED3[24];
Simon Cooksey	0:fb7af294d5d9	449	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
Simon Cooksey	0:fb7af294d5d9	450	uint32_t RESERVED4[56];
Simon Cooksey	0:fb7af294d5d9	451	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
Simon Cooksey	0:fb7af294d5d9	452	uint32_t RESERVED5[644];
Simon Cooksey	0:fb7af294d5d9	453	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
Simon Cooksey	0:fb7af294d5d9	454	} NVIC_Type;
Simon Cooksey	0:fb7af294d5d9	455
Simon Cooksey	0:fb7af294d5d9	456	/* Software Triggered Interrupt Register Definitions */
Simon Cooksey	0:fb7af294d5d9	457	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
Simon Cooksey	0:fb7af294d5d9	458	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
Simon Cooksey	0:fb7af294d5d9	459
Simon Cooksey	0:fb7af294d5d9	460	/@} end of group CMSIS_NVIC /
Simon Cooksey	0:fb7af294d5d9	461
Simon Cooksey	0:fb7af294d5d9	462
Simon Cooksey	0:fb7af294d5d9	463	/** \ingroup CMSIS_core_register
Simon Cooksey	0:fb7af294d5d9	464	\defgroup CMSIS_SCB System Control Block (SCB)
Simon Cooksey	0:fb7af294d5d9	465	\brief Type definitions for the System Control Block Registers
Simon Cooksey	0:fb7af294d5d9	466	@{
Simon Cooksey	0:fb7af294d5d9	467	*/
Simon Cooksey	0:fb7af294d5d9	468
Simon Cooksey	0:fb7af294d5d9	469	/** \brief Structure type to access the System Control Block (SCB).
Simon Cooksey	0:fb7af294d5d9	470	*/
Simon Cooksey	0:fb7af294d5d9	471	typedef struct
Simon Cooksey	0:fb7af294d5d9	472	{
Simon Cooksey	0:fb7af294d5d9	473	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
Simon Cooksey	0:fb7af294d5d9	474	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
Simon Cooksey	0:fb7af294d5d9	475	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
Simon Cooksey	0:fb7af294d5d9	476	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
Simon Cooksey	0:fb7af294d5d9	477	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
Simon Cooksey	0:fb7af294d5d9	478	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
Simon Cooksey	0:fb7af294d5d9	479	__IO uint8_t SHPR[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
Simon Cooksey	0:fb7af294d5d9	480	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
Simon Cooksey	0:fb7af294d5d9	481	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
Simon Cooksey	0:fb7af294d5d9	482	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
Simon Cooksey	0:fb7af294d5d9	483	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
Simon Cooksey	0:fb7af294d5d9	484	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
Simon Cooksey	0:fb7af294d5d9	485	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
Simon Cooksey	0:fb7af294d5d9	486	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
Simon Cooksey	0:fb7af294d5d9	487	__I uint32_t ID_PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
Simon Cooksey	0:fb7af294d5d9	488	__I uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
Simon Cooksey	0:fb7af294d5d9	489	__I uint32_t ID_AFR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
Simon Cooksey	0:fb7af294d5d9	490	__I uint32_t ID_MFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
Simon Cooksey	0:fb7af294d5d9	491	__I uint32_t ID_ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
Simon Cooksey	0:fb7af294d5d9	492	uint32_t RESERVED0[1];
Simon Cooksey	0:fb7af294d5d9	493	__I uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
Simon Cooksey	0:fb7af294d5d9	494	__I uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
Simon Cooksey	0:fb7af294d5d9	495	__I uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
Simon Cooksey	0:fb7af294d5d9	496	__IO uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
Simon Cooksey	0:fb7af294d5d9	497	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
Simon Cooksey	0:fb7af294d5d9	498	uint32_t RESERVED3[93];
Simon Cooksey	0:fb7af294d5d9	499	__O uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
Simon Cooksey	0:fb7af294d5d9	500	uint32_t RESERVED4[15];
Simon Cooksey	0:fb7af294d5d9	501	__I uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
Simon Cooksey	0:fb7af294d5d9	502	__I uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
Simon Cooksey	0:fb7af294d5d9	503	__I uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 /
Simon Cooksey	0:fb7af294d5d9	504	uint32_t RESERVED5[1];
Simon Cooksey	0:fb7af294d5d9	505	__O uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
Simon Cooksey	0:fb7af294d5d9	506	uint32_t RESERVED6[1];
Simon Cooksey	0:fb7af294d5d9	507	__O uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
Simon Cooksey	0:fb7af294d5d9	508	__O uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
Simon Cooksey	0:fb7af294d5d9	509	__O uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
Simon Cooksey	0:fb7af294d5d9	510	__O uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
Simon Cooksey	0:fb7af294d5d9	511	__O uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
Simon Cooksey	0:fb7af294d5d9	512	__O uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
Simon Cooksey	0:fb7af294d5d9	513	__O uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
Simon Cooksey	0:fb7af294d5d9	514	__O uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
Simon Cooksey	0:fb7af294d5d9	515	uint32_t RESERVED7[6];
Simon Cooksey	0:fb7af294d5d9	516	__IO uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
Simon Cooksey	0:fb7af294d5d9	517	__IO uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
Simon Cooksey	0:fb7af294d5d9	518	__IO uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
Simon Cooksey	0:fb7af294d5d9	519	__IO uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
Simon Cooksey	0:fb7af294d5d9	520	__IO uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
Simon Cooksey	0:fb7af294d5d9	521	uint32_t RESERVED8[1];
Simon Cooksey	0:fb7af294d5d9	522	__IO uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
Simon Cooksey	0:fb7af294d5d9	523	} SCB_Type;
Simon Cooksey	0:fb7af294d5d9	524
Simon Cooksey	0:fb7af294d5d9	525	/* SCB CPUID Register Definitions */
Simon Cooksey	0:fb7af294d5d9	526	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
Simon Cooksey	0:fb7af294d5d9	527	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
Simon Cooksey	0:fb7af294d5d9	528
Simon Cooksey	0:fb7af294d5d9	529	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
Simon Cooksey	0:fb7af294d5d9	530	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
Simon Cooksey	0:fb7af294d5d9	531
Simon Cooksey	0:fb7af294d5d9	532	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
Simon Cooksey	0:fb7af294d5d9	533	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
Simon Cooksey	0:fb7af294d5d9	534
Simon Cooksey	0:fb7af294d5d9	535	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
Simon Cooksey	0:fb7af294d5d9	536	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
Simon Cooksey	0:fb7af294d5d9	537
Simon Cooksey	0:fb7af294d5d9	538	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
Simon Cooksey	0:fb7af294d5d9	539	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
Simon Cooksey	0:fb7af294d5d9	540
Simon Cooksey	0:fb7af294d5d9	541	/* SCB Interrupt Control State Register Definitions */
Simon Cooksey	0:fb7af294d5d9	542	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
Simon Cooksey	0:fb7af294d5d9	543	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
Simon Cooksey	0:fb7af294d5d9	544
Simon Cooksey	0:fb7af294d5d9	545	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
Simon Cooksey	0:fb7af294d5d9	546	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
Simon Cooksey	0:fb7af294d5d9	547
Simon Cooksey	0:fb7af294d5d9	548	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
Simon Cooksey	0:fb7af294d5d9	549	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
Simon Cooksey	0:fb7af294d5d9	550
Simon Cooksey	0:fb7af294d5d9	551	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
Simon Cooksey	0:fb7af294d5d9	552	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
Simon Cooksey	0:fb7af294d5d9	553
Simon Cooksey	0:fb7af294d5d9	554	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
Simon Cooksey	0:fb7af294d5d9	555	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
Simon Cooksey	0:fb7af294d5d9	556
Simon Cooksey	0:fb7af294d5d9	557	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
Simon Cooksey	0:fb7af294d5d9	558	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
Simon Cooksey	0:fb7af294d5d9	559
Simon Cooksey	0:fb7af294d5d9	560	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
Simon Cooksey	0:fb7af294d5d9	561	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
Simon Cooksey	0:fb7af294d5d9	562
Simon Cooksey	0:fb7af294d5d9	563	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
Simon Cooksey	0:fb7af294d5d9	564	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
Simon Cooksey	0:fb7af294d5d9	565
Simon Cooksey	0:fb7af294d5d9	566	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
Simon Cooksey	0:fb7af294d5d9	567	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
Simon Cooksey	0:fb7af294d5d9	568
Simon Cooksey	0:fb7af294d5d9	569	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
Simon Cooksey	0:fb7af294d5d9	570	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
Simon Cooksey	0:fb7af294d5d9	571
Simon Cooksey	0:fb7af294d5d9	572	/* SCB Vector Table Offset Register Definitions */
Simon Cooksey	0:fb7af294d5d9	573	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
Simon Cooksey	0:fb7af294d5d9	574	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Simon Cooksey	0:fb7af294d5d9	575
Simon Cooksey	0:fb7af294d5d9	576	/* SCB Application Interrupt and Reset Control Register Definitions */
Simon Cooksey	0:fb7af294d5d9	577	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
Simon Cooksey	0:fb7af294d5d9	578	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
Simon Cooksey	0:fb7af294d5d9	579
Simon Cooksey	0:fb7af294d5d9	580	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
Simon Cooksey	0:fb7af294d5d9	581	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
Simon Cooksey	0:fb7af294d5d9	582
Simon Cooksey	0:fb7af294d5d9	583	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
Simon Cooksey	0:fb7af294d5d9	584	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
Simon Cooksey	0:fb7af294d5d9	585
Simon Cooksey	0:fb7af294d5d9	586	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
Simon Cooksey	0:fb7af294d5d9	587	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
Simon Cooksey	0:fb7af294d5d9	588
Simon Cooksey	0:fb7af294d5d9	589	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
Simon Cooksey	0:fb7af294d5d9	590	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
Simon Cooksey	0:fb7af294d5d9	591
Simon Cooksey	0:fb7af294d5d9	592	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
Simon Cooksey	0:fb7af294d5d9	593	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
Simon Cooksey	0:fb7af294d5d9	594
Simon Cooksey	0:fb7af294d5d9	595	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
Simon Cooksey	0:fb7af294d5d9	596	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
Simon Cooksey	0:fb7af294d5d9	597
Simon Cooksey	0:fb7af294d5d9	598	/* SCB System Control Register Definitions */
Simon Cooksey	0:fb7af294d5d9	599	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
Simon Cooksey	0:fb7af294d5d9	600	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
Simon Cooksey	0:fb7af294d5d9	601
Simon Cooksey	0:fb7af294d5d9	602	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
Simon Cooksey	0:fb7af294d5d9	603	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
Simon Cooksey	0:fb7af294d5d9	604
Simon Cooksey	0:fb7af294d5d9	605	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
Simon Cooksey	0:fb7af294d5d9	606	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
Simon Cooksey	0:fb7af294d5d9	607
Simon Cooksey	0:fb7af294d5d9	608	/* SCB Configuration Control Register Definitions */
Simon Cooksey	0:fb7af294d5d9	609	#define SCB_CCR_BP_Pos 18 /!< SCB CCR: Branch prediction enable bit Position /
Simon Cooksey	0:fb7af294d5d9	610	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: Branch prediction enable bit Mask /
Simon Cooksey	0:fb7af294d5d9	611
Simon Cooksey	0:fb7af294d5d9	612	#define SCB_CCR_IC_Pos 17 /!< SCB CCR: Instruction cache enable bit Position /
Simon Cooksey	0:fb7af294d5d9	613	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: Instruction cache enable bit Mask /
Simon Cooksey	0:fb7af294d5d9	614
Simon Cooksey	0:fb7af294d5d9	615	#define SCB_CCR_DC_Pos 16 /!< SCB CCR: Cache enable bit Position /
Simon Cooksey	0:fb7af294d5d9	616	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: Cache enable bit Mask /
Simon Cooksey	0:fb7af294d5d9	617
Simon Cooksey	0:fb7af294d5d9	618	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
Simon Cooksey	0:fb7af294d5d9	619	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
Simon Cooksey	0:fb7af294d5d9	620
Simon Cooksey	0:fb7af294d5d9	621	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
Simon Cooksey	0:fb7af294d5d9	622	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
Simon Cooksey	0:fb7af294d5d9	623
Simon Cooksey	0:fb7af294d5d9	624	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
Simon Cooksey	0:fb7af294d5d9	625	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
Simon Cooksey	0:fb7af294d5d9	626
Simon Cooksey	0:fb7af294d5d9	627	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
Simon Cooksey	0:fb7af294d5d9	628	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
Simon Cooksey	0:fb7af294d5d9	629
Simon Cooksey	0:fb7af294d5d9	630	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
Simon Cooksey	0:fb7af294d5d9	631	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
Simon Cooksey	0:fb7af294d5d9	632
Simon Cooksey	0:fb7af294d5d9	633	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
Simon Cooksey	0:fb7af294d5d9	634	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
Simon Cooksey	0:fb7af294d5d9	635
Simon Cooksey	0:fb7af294d5d9	636	/* SCB System Handler Control and State Register Definitions */
Simon Cooksey	0:fb7af294d5d9	637	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
Simon Cooksey	0:fb7af294d5d9	638	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
Simon Cooksey	0:fb7af294d5d9	639
Simon Cooksey	0:fb7af294d5d9	640	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
Simon Cooksey	0:fb7af294d5d9	641	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
Simon Cooksey	0:fb7af294d5d9	642
Simon Cooksey	0:fb7af294d5d9	643	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
Simon Cooksey	0:fb7af294d5d9	644	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
Simon Cooksey	0:fb7af294d5d9	645
Simon Cooksey	0:fb7af294d5d9	646	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
Simon Cooksey	0:fb7af294d5d9	647	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
Simon Cooksey	0:fb7af294d5d9	648
Simon Cooksey	0:fb7af294d5d9	649	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
Simon Cooksey	0:fb7af294d5d9	650	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
Simon Cooksey	0:fb7af294d5d9	651
Simon Cooksey	0:fb7af294d5d9	652	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
Simon Cooksey	0:fb7af294d5d9	653	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
Simon Cooksey	0:fb7af294d5d9	654
Simon Cooksey	0:fb7af294d5d9	655	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
Simon Cooksey	0:fb7af294d5d9	656	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
Simon Cooksey	0:fb7af294d5d9	657
Simon Cooksey	0:fb7af294d5d9	658	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
Simon Cooksey	0:fb7af294d5d9	659	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
Simon Cooksey	0:fb7af294d5d9	660
Simon Cooksey	0:fb7af294d5d9	661	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
Simon Cooksey	0:fb7af294d5d9	662	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
Simon Cooksey	0:fb7af294d5d9	663
Simon Cooksey	0:fb7af294d5d9	664	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
Simon Cooksey	0:fb7af294d5d9	665	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
Simon Cooksey	0:fb7af294d5d9	666
Simon Cooksey	0:fb7af294d5d9	667	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
Simon Cooksey	0:fb7af294d5d9	668	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
Simon Cooksey	0:fb7af294d5d9	669
Simon Cooksey	0:fb7af294d5d9	670	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
Simon Cooksey	0:fb7af294d5d9	671	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
Simon Cooksey	0:fb7af294d5d9	672
Simon Cooksey	0:fb7af294d5d9	673	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
Simon Cooksey	0:fb7af294d5d9	674	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
Simon Cooksey	0:fb7af294d5d9	675
Simon Cooksey	0:fb7af294d5d9	676	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
Simon Cooksey	0:fb7af294d5d9	677	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
Simon Cooksey	0:fb7af294d5d9	678
Simon Cooksey	0:fb7af294d5d9	679	/* SCB Configurable Fault Status Registers Definitions */
Simon Cooksey	0:fb7af294d5d9	680	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
Simon Cooksey	0:fb7af294d5d9	681	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
Simon Cooksey	0:fb7af294d5d9	682
Simon Cooksey	0:fb7af294d5d9	683	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
Simon Cooksey	0:fb7af294d5d9	684	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
Simon Cooksey	0:fb7af294d5d9	685
Simon Cooksey	0:fb7af294d5d9	686	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
Simon Cooksey	0:fb7af294d5d9	687	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
Simon Cooksey	0:fb7af294d5d9	688
Simon Cooksey	0:fb7af294d5d9	689	/* SCB Hard Fault Status Registers Definitions */
Simon Cooksey	0:fb7af294d5d9	690	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
Simon Cooksey	0:fb7af294d5d9	691	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
Simon Cooksey	0:fb7af294d5d9	692
Simon Cooksey	0:fb7af294d5d9	693	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
Simon Cooksey	0:fb7af294d5d9	694	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
Simon Cooksey	0:fb7af294d5d9	695
Simon Cooksey	0:fb7af294d5d9	696	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
Simon Cooksey	0:fb7af294d5d9	697	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
Simon Cooksey	0:fb7af294d5d9	698
Simon Cooksey	0:fb7af294d5d9	699	/* SCB Debug Fault Status Register Definitions */
Simon Cooksey	0:fb7af294d5d9	700	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
Simon Cooksey	0:fb7af294d5d9	701	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
Simon Cooksey	0:fb7af294d5d9	702
Simon Cooksey	0:fb7af294d5d9	703	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
Simon Cooksey	0:fb7af294d5d9	704	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
Simon Cooksey	0:fb7af294d5d9	705
Simon Cooksey	0:fb7af294d5d9	706	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
Simon Cooksey	0:fb7af294d5d9	707	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
Simon Cooksey	0:fb7af294d5d9	708
Simon Cooksey	0:fb7af294d5d9	709	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
Simon Cooksey	0:fb7af294d5d9	710	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
Simon Cooksey	0:fb7af294d5d9	711
Simon Cooksey	0:fb7af294d5d9	712	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
Simon Cooksey	0:fb7af294d5d9	713	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
Simon Cooksey	0:fb7af294d5d9	714
Simon Cooksey	0:fb7af294d5d9	715	/* Cache Level ID register */
Simon Cooksey	0:fb7af294d5d9	716	#define SCB_CLIDR_LOUU_Pos 27 /!< SCB CLIDR: LoUU Position /
Simon Cooksey	0:fb7af294d5d9	717	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
Simon Cooksey	0:fb7af294d5d9	718
Simon Cooksey	0:fb7af294d5d9	719	#define SCB_CLIDR_LOC_Pos 24 /!< SCB CLIDR: LoC Position /
Simon Cooksey	0:fb7af294d5d9	720	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /!< SCB CLIDR: LoC Mask /
Simon Cooksey	0:fb7af294d5d9	721
Simon Cooksey	0:fb7af294d5d9	722	/* Cache Type register */
Simon Cooksey	0:fb7af294d5d9	723	#define SCB_CTR_FORMAT_Pos 29 /!< SCB CTR: Format Position /
Simon Cooksey	0:fb7af294d5d9	724	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
Simon Cooksey	0:fb7af294d5d9	725
Simon Cooksey	0:fb7af294d5d9	726	#define SCB_CTR_CWG_Pos 24 /!< SCB CTR: CWG Position /
Simon Cooksey	0:fb7af294d5d9	727	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
Simon Cooksey	0:fb7af294d5d9	728
Simon Cooksey	0:fb7af294d5d9	729	#define SCB_CTR_ERG_Pos 20 /!< SCB CTR: ERG Position /
Simon Cooksey	0:fb7af294d5d9	730	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
Simon Cooksey	0:fb7af294d5d9	731
Simon Cooksey	0:fb7af294d5d9	732	#define SCB_CTR_DMINLINE_Pos 16 /!< SCB CTR: DminLine Position /
Simon Cooksey	0:fb7af294d5d9	733	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
Simon Cooksey	0:fb7af294d5d9	734
Simon Cooksey	0:fb7af294d5d9	735	#define SCB_CTR_IMINLINE_Pos 0 /!< SCB CTR: ImInLine Position /
Simon Cooksey	0:fb7af294d5d9	736	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
Simon Cooksey	0:fb7af294d5d9	737
Simon Cooksey	0:fb7af294d5d9	738	/* Cache Size ID Register */
Simon Cooksey	0:fb7af294d5d9	739	#define SCB_CCSIDR_WT_Pos 31 /!< SCB CCSIDR: WT Position /
Simon Cooksey	0:fb7af294d5d9	740	#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
Simon Cooksey	0:fb7af294d5d9	741
Simon Cooksey	0:fb7af294d5d9	742	#define SCB_CCSIDR_WB_Pos 30 /!< SCB CCSIDR: WB Position /
Simon Cooksey	0:fb7af294d5d9	743	#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
Simon Cooksey	0:fb7af294d5d9	744
Simon Cooksey	0:fb7af294d5d9	745	#define SCB_CCSIDR_RA_Pos 29 /!< SCB CCSIDR: RA Position /
Simon Cooksey	0:fb7af294d5d9	746	#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
Simon Cooksey	0:fb7af294d5d9	747
Simon Cooksey	0:fb7af294d5d9	748	#define SCB_CCSIDR_WA_Pos 28 /!< SCB CCSIDR: WA Position /
Simon Cooksey	0:fb7af294d5d9	749	#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
Simon Cooksey	0:fb7af294d5d9	750
Simon Cooksey	0:fb7af294d5d9	751	#define SCB_CCSIDR_NUMSETS_Pos 13 /!< SCB CCSIDR: NumSets Position /
Simon Cooksey	0:fb7af294d5d9	752	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
Simon Cooksey	0:fb7af294d5d9	753
Simon Cooksey	0:fb7af294d5d9	754	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /!< SCB CCSIDR: Associativity Position /
Simon Cooksey	0:fb7af294d5d9	755	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
Simon Cooksey	0:fb7af294d5d9	756
Simon Cooksey	0:fb7af294d5d9	757	#define SCB_CCSIDR_LINESIZE_Pos 0 /!< SCB CCSIDR: LineSize Position /
Simon Cooksey	0:fb7af294d5d9	758	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
Simon Cooksey	0:fb7af294d5d9	759
Simon Cooksey	0:fb7af294d5d9	760	/* Cache Size Selection Register */
Simon Cooksey	0:fb7af294d5d9	761	#define SCB_CSSELR_LEVEL_Pos 1 /!< SCB CSSELR: Level Position /
Simon Cooksey	0:fb7af294d5d9	762	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
Simon Cooksey	0:fb7af294d5d9	763
Simon Cooksey	0:fb7af294d5d9	764	#define SCB_CSSELR_IND_Pos 0 /!< SCB CSSELR: InD Position /
Simon Cooksey	0:fb7af294d5d9	765	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
Simon Cooksey	0:fb7af294d5d9	766
Simon Cooksey	0:fb7af294d5d9	767	/* SCB Software Triggered Interrupt Register */
Simon Cooksey	0:fb7af294d5d9	768	#define SCB_STIR_INTID_Pos 0 /!< SCB STIR: INTID Position /
Simon Cooksey	0:fb7af294d5d9	769	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
Simon Cooksey	0:fb7af294d5d9	770
Simon Cooksey	0:fb7af294d5d9	771	/* Instruction Tightly-Coupled Memory Control Register*/
Simon Cooksey	0:fb7af294d5d9	772	#define SCB_ITCMCR_SZ_Pos 3 /!< SCB ITCMCR: SZ Position /
Simon Cooksey	0:fb7af294d5d9	773	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
Simon Cooksey	0:fb7af294d5d9	774
Simon Cooksey	0:fb7af294d5d9	775	#define SCB_ITCMCR_RETEN_Pos 2 /!< SCB ITCMCR: RETEN Position /
Simon Cooksey	0:fb7af294d5d9	776	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
Simon Cooksey	0:fb7af294d5d9	777
Simon Cooksey	0:fb7af294d5d9	778	#define SCB_ITCMCR_RMW_Pos 1 /!< SCB ITCMCR: RMW Position /
Simon Cooksey	0:fb7af294d5d9	779	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
Simon Cooksey	0:fb7af294d5d9	780
Simon Cooksey	0:fb7af294d5d9	781	#define SCB_ITCMCR_EN_Pos 0 /!< SCB ITCMCR: EN Position /
Simon Cooksey	0:fb7af294d5d9	782	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
Simon Cooksey	0:fb7af294d5d9	783
Simon Cooksey	0:fb7af294d5d9	784	/* Data Tightly-Coupled Memory Control Registers */
Simon Cooksey	0:fb7af294d5d9	785	#define SCB_DTCMCR_SZ_Pos 3 /!< SCB DTCMCR: SZ Position /
Simon Cooksey	0:fb7af294d5d9	786	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
Simon Cooksey	0:fb7af294d5d9	787
Simon Cooksey	0:fb7af294d5d9	788	#define SCB_DTCMCR_RETEN_Pos 2 /!< SCB DTCMCR: RETEN Position /
Simon Cooksey	0:fb7af294d5d9	789	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
Simon Cooksey	0:fb7af294d5d9	790
Simon Cooksey	0:fb7af294d5d9	791	#define SCB_DTCMCR_RMW_Pos 1 /!< SCB DTCMCR: RMW Position /
Simon Cooksey	0:fb7af294d5d9	792	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
Simon Cooksey	0:fb7af294d5d9	793
Simon Cooksey	0:fb7af294d5d9	794	#define SCB_DTCMCR_EN_Pos 0 /!< SCB DTCMCR: EN Position /
Simon Cooksey	0:fb7af294d5d9	795	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
Simon Cooksey	0:fb7af294d5d9	796
Simon Cooksey	0:fb7af294d5d9	797	/* AHBP Control Register */
Simon Cooksey	0:fb7af294d5d9	798	#define SCB_AHBPCR_SZ_Pos 1 /!< SCB AHBPCR: SZ Position /
Simon Cooksey	0:fb7af294d5d9	799	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
Simon Cooksey	0:fb7af294d5d9	800
Simon Cooksey	0:fb7af294d5d9	801	#define SCB_AHBPCR_EN_Pos 0 /!< SCB AHBPCR: EN Position /
Simon Cooksey	0:fb7af294d5d9	802	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
Simon Cooksey	0:fb7af294d5d9	803
Simon Cooksey	0:fb7af294d5d9	804	/* L1 Cache Control Register */
Simon Cooksey	0:fb7af294d5d9	805	#define SCB_CACR_FORCEWT_Pos 2 /!< SCB CACR: FORCEWT Position /
Simon Cooksey	0:fb7af294d5d9	806	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
Simon Cooksey	0:fb7af294d5d9	807
Simon Cooksey	0:fb7af294d5d9	808	#define SCB_CACR_ECCEN_Pos 1 /!< SCB CACR: ECCEN Position /
Simon Cooksey	0:fb7af294d5d9	809	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
Simon Cooksey	0:fb7af294d5d9	810
Simon Cooksey	0:fb7af294d5d9	811	#define SCB_CACR_SIWT_Pos 0 /!< SCB CACR: SIWT Position /
Simon Cooksey	0:fb7af294d5d9	812	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
Simon Cooksey	0:fb7af294d5d9	813
Simon Cooksey	0:fb7af294d5d9	814	/* AHBS control register */
Simon Cooksey	0:fb7af294d5d9	815	#define SCB_AHBSCR_INITCOUNT_Pos 11 /!< SCB AHBSCR: INITCOUNT Position /
Simon Cooksey	0:fb7af294d5d9	816	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
Simon Cooksey	0:fb7af294d5d9	817
Simon Cooksey	0:fb7af294d5d9	818	#define SCB_AHBSCR_TPRI_Pos 2 /!< SCB AHBSCR: TPRI Position /
Simon Cooksey	0:fb7af294d5d9	819	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
Simon Cooksey	0:fb7af294d5d9	820
Simon Cooksey	0:fb7af294d5d9	821	#define SCB_AHBSCR_CTL_Pos 0 /!< SCB AHBSCR: CTL Position/
Simon Cooksey	0:fb7af294d5d9	822	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
Simon Cooksey	0:fb7af294d5d9	823
Simon Cooksey	0:fb7af294d5d9	824	/* Auxiliary Bus Fault Status Register */
Simon Cooksey	0:fb7af294d5d9	825	#define SCB_ABFSR_AXIMTYPE_Pos 8 /!< SCB ABFSR: AXIMTYPE Position/
Simon Cooksey	0:fb7af294d5d9	826	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
Simon Cooksey	0:fb7af294d5d9	827
Simon Cooksey	0:fb7af294d5d9	828	#define SCB_ABFSR_EPPB_Pos 4 /!< SCB ABFSR: EPPB Position/
Simon Cooksey	0:fb7af294d5d9	829	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
Simon Cooksey	0:fb7af294d5d9	830
Simon Cooksey	0:fb7af294d5d9	831	#define SCB_ABFSR_AXIM_Pos 3 /!< SCB ABFSR: AXIM Position/
Simon Cooksey	0:fb7af294d5d9	832	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
Simon Cooksey	0:fb7af294d5d9	833
Simon Cooksey	0:fb7af294d5d9	834	#define SCB_ABFSR_AHBP_Pos 2 /!< SCB ABFSR: AHBP Position/
Simon Cooksey	0:fb7af294d5d9	835	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
Simon Cooksey	0:fb7af294d5d9	836
Simon Cooksey	0:fb7af294d5d9	837	#define SCB_ABFSR_DTCM_Pos 1 /!< SCB ABFSR: DTCM Position/
Simon Cooksey	0:fb7af294d5d9	838	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
Simon Cooksey	0:fb7af294d5d9	839
Simon Cooksey	0:fb7af294d5d9	840	#define SCB_ABFSR_ITCM_Pos 0 /!< SCB ABFSR: ITCM Position/
Simon Cooksey	0:fb7af294d5d9	841	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
Simon Cooksey	0:fb7af294d5d9	842
Simon Cooksey	0:fb7af294d5d9	843	/@} end of group CMSIS_SCB /
Simon Cooksey	0:fb7af294d5d9	844
Simon Cooksey	0:fb7af294d5d9	845
Simon Cooksey	0:fb7af294d5d9	846	/** \ingroup CMSIS_core_register
Simon Cooksey	0:fb7af294d5d9	847	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Simon Cooksey	0:fb7af294d5d9	848	\brief Type definitions for the System Control and ID Register not in the SCB
Simon Cooksey	0:fb7af294d5d9	849	@{
Simon Cooksey	0:fb7af294d5d9	850	*/
Simon Cooksey	0:fb7af294d5d9	851
Simon Cooksey	0:fb7af294d5d9	852	/** \brief Structure type to access the System Control and ID Register not in the SCB.
Simon Cooksey	0:fb7af294d5d9	853	*/
Simon Cooksey	0:fb7af294d5d9	854	typedef struct
Simon Cooksey	0:fb7af294d5d9	855	{
Simon Cooksey	0:fb7af294d5d9	856	uint32_t RESERVED0[1];
Simon Cooksey	0:fb7af294d5d9	857	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
Simon Cooksey	0:fb7af294d5d9	858	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
Simon Cooksey	0:fb7af294d5d9	859	} SCnSCB_Type;
Simon Cooksey	0:fb7af294d5d9	860
Simon Cooksey	0:fb7af294d5d9	861	/* Interrupt Controller Type Register Definitions */
Simon Cooksey	0:fb7af294d5d9	862	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
Simon Cooksey	0:fb7af294d5d9	863	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
Simon Cooksey	0:fb7af294d5d9	864
Simon Cooksey	0:fb7af294d5d9	865	/* Auxiliary Control Register Definitions */
Simon Cooksey	0:fb7af294d5d9	866	#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /!< ACTLR: DISITMATBFLUSH Position /
Simon Cooksey	0:fb7af294d5d9	867	#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /!< ACTLR: DISITMATBFLUSH Mask /
Simon Cooksey	0:fb7af294d5d9	868
Simon Cooksey	0:fb7af294d5d9	869	#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /!< ACTLR: DISRAMODE Position /
Simon Cooksey	0:fb7af294d5d9	870	#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /!< ACTLR: DISRAMODE Mask /
Simon Cooksey	0:fb7af294d5d9	871
Simon Cooksey	0:fb7af294d5d9	872	#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /!< ACTLR: FPEXCODIS Position /
Simon Cooksey	0:fb7af294d5d9	873	#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /!< ACTLR: FPEXCODIS Mask /
Simon Cooksey	0:fb7af294d5d9	874
Simon Cooksey	0:fb7af294d5d9	875	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
Simon Cooksey	0:fb7af294d5d9	876	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
Simon Cooksey	0:fb7af294d5d9	877
Simon Cooksey	0:fb7af294d5d9	878	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
Simon Cooksey	0:fb7af294d5d9	879	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
Simon Cooksey	0:fb7af294d5d9	880
Simon Cooksey	0:fb7af294d5d9	881	/@} end of group CMSIS_SCnotSCB /
Simon Cooksey	0:fb7af294d5d9	882
Simon Cooksey	0:fb7af294d5d9	883
Simon Cooksey	0:fb7af294d5d9	884	/** \ingroup CMSIS_core_register
Simon Cooksey	0:fb7af294d5d9	885	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
Simon Cooksey	0:fb7af294d5d9	886	\brief Type definitions for the System Timer Registers.
Simon Cooksey	0:fb7af294d5d9	887	@{
Simon Cooksey	0:fb7af294d5d9	888	*/
Simon Cooksey	0:fb7af294d5d9	889
Simon Cooksey	0:fb7af294d5d9	890	/** \brief Structure type to access the System Timer (SysTick).
Simon Cooksey	0:fb7af294d5d9	891	*/
Simon Cooksey	0:fb7af294d5d9	892	typedef struct
Simon Cooksey	0:fb7af294d5d9	893	{
Simon Cooksey	0:fb7af294d5d9	894	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
Simon Cooksey	0:fb7af294d5d9	895	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
Simon Cooksey	0:fb7af294d5d9	896	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
Simon Cooksey	0:fb7af294d5d9	897	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
Simon Cooksey	0:fb7af294d5d9	898	} SysTick_Type;
Simon Cooksey	0:fb7af294d5d9	899
Simon Cooksey	0:fb7af294d5d9	900	/* SysTick Control / Status Register Definitions */
Simon Cooksey	0:fb7af294d5d9	901	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
Simon Cooksey	0:fb7af294d5d9	902	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
Simon Cooksey	0:fb7af294d5d9	903
Simon Cooksey	0:fb7af294d5d9	904	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
Simon Cooksey	0:fb7af294d5d9	905	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
Simon Cooksey	0:fb7af294d5d9	906
Simon Cooksey	0:fb7af294d5d9	907	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
Simon Cooksey	0:fb7af294d5d9	908	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
Simon Cooksey	0:fb7af294d5d9	909
Simon Cooksey	0:fb7af294d5d9	910	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
Simon Cooksey	0:fb7af294d5d9	911	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
Simon Cooksey	0:fb7af294d5d9	912
Simon Cooksey	0:fb7af294d5d9	913	/* SysTick Reload Register Definitions */
Simon Cooksey	0:fb7af294d5d9	914	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
Simon Cooksey	0:fb7af294d5d9	915	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
Simon Cooksey	0:fb7af294d5d9	916
Simon Cooksey	0:fb7af294d5d9	917	/* SysTick Current Register Definitions */
Simon Cooksey	0:fb7af294d5d9	918	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
Simon Cooksey	0:fb7af294d5d9	919	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
Simon Cooksey	0:fb7af294d5d9	920
Simon Cooksey	0:fb7af294d5d9	921	/* SysTick Calibration Register Definitions */
Simon Cooksey	0:fb7af294d5d9	922	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
Simon Cooksey	0:fb7af294d5d9	923	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
Simon Cooksey	0:fb7af294d5d9	924
Simon Cooksey	0:fb7af294d5d9	925	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
Simon Cooksey	0:fb7af294d5d9	926	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
Simon Cooksey	0:fb7af294d5d9	927
Simon Cooksey	0:fb7af294d5d9	928	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
Simon Cooksey	0:fb7af294d5d9	929	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
Simon Cooksey	0:fb7af294d5d9	930
Simon Cooksey	0:fb7af294d5d9	931	/@} end of group CMSIS_SysTick /
Simon Cooksey	0:fb7af294d5d9	932
Simon Cooksey	0:fb7af294d5d9	933
Simon Cooksey	0:fb7af294d5d9	934	/** \ingroup CMSIS_core_register
Simon Cooksey	0:fb7af294d5d9	935	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Simon Cooksey	0:fb7af294d5d9	936	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Simon Cooksey	0:fb7af294d5d9	937	@{
Simon Cooksey	0:fb7af294d5d9	938	*/
Simon Cooksey	0:fb7af294d5d9	939
Simon Cooksey	0:fb7af294d5d9	940	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Simon Cooksey	0:fb7af294d5d9	941	*/
Simon Cooksey	0:fb7af294d5d9	942	typedef struct
Simon Cooksey	0:fb7af294d5d9	943	{
Simon Cooksey	0:fb7af294d5d9	944	__O union
Simon Cooksey	0:fb7af294d5d9	945	{
Simon Cooksey	0:fb7af294d5d9	946	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
Simon Cooksey	0:fb7af294d5d9	947	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
Simon Cooksey	0:fb7af294d5d9	948	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
Simon Cooksey	0:fb7af294d5d9	949	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
Simon Cooksey	0:fb7af294d5d9	950	uint32_t RESERVED0[864];
Simon Cooksey	0:fb7af294d5d9	951	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
Simon Cooksey	0:fb7af294d5d9	952	uint32_t RESERVED1[15];
Simon Cooksey	0:fb7af294d5d9	953	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
Simon Cooksey	0:fb7af294d5d9	954	uint32_t RESERVED2[15];
Simon Cooksey	0:fb7af294d5d9	955	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
Simon Cooksey	0:fb7af294d5d9	956	uint32_t RESERVED3[29];
Simon Cooksey	0:fb7af294d5d9	957	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
Simon Cooksey	0:fb7af294d5d9	958	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
Simon Cooksey	0:fb7af294d5d9	959	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
Simon Cooksey	0:fb7af294d5d9	960	uint32_t RESERVED4[43];
Simon Cooksey	0:fb7af294d5d9	961	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
Simon Cooksey	0:fb7af294d5d9	962	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
Simon Cooksey	0:fb7af294d5d9	963	uint32_t RESERVED5[6];
Simon Cooksey	0:fb7af294d5d9	964	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
Simon Cooksey	0:fb7af294d5d9	965	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
Simon Cooksey	0:fb7af294d5d9	966	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
Simon Cooksey	0:fb7af294d5d9	967	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
Simon Cooksey	0:fb7af294d5d9	968	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
Simon Cooksey	0:fb7af294d5d9	969	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
Simon Cooksey	0:fb7af294d5d9	970	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
Simon Cooksey	0:fb7af294d5d9	971	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
Simon Cooksey	0:fb7af294d5d9	972	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
Simon Cooksey	0:fb7af294d5d9	973	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
Simon Cooksey	0:fb7af294d5d9	974	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
Simon Cooksey	0:fb7af294d5d9	975	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
Simon Cooksey	0:fb7af294d5d9	976	} ITM_Type;
Simon Cooksey	0:fb7af294d5d9	977
Simon Cooksey	0:fb7af294d5d9	978	/* ITM Trace Privilege Register Definitions */
Simon Cooksey	0:fb7af294d5d9	979	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
Simon Cooksey	0:fb7af294d5d9	980	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
Simon Cooksey	0:fb7af294d5d9	981
Simon Cooksey	0:fb7af294d5d9	982	/* ITM Trace Control Register Definitions */
Simon Cooksey	0:fb7af294d5d9	983	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
Simon Cooksey	0:fb7af294d5d9	984	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
Simon Cooksey	0:fb7af294d5d9	985
Simon Cooksey	0:fb7af294d5d9	986	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
Simon Cooksey	0:fb7af294d5d9	987	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
Simon Cooksey	0:fb7af294d5d9	988
Simon Cooksey	0:fb7af294d5d9	989	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
Simon Cooksey	0:fb7af294d5d9	990	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
Simon Cooksey	0:fb7af294d5d9	991
Simon Cooksey	0:fb7af294d5d9	992	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
Simon Cooksey	0:fb7af294d5d9	993	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
Simon Cooksey	0:fb7af294d5d9	994
Simon Cooksey	0:fb7af294d5d9	995	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
Simon Cooksey	0:fb7af294d5d9	996	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
Simon Cooksey	0:fb7af294d5d9	997
Simon Cooksey	0:fb7af294d5d9	998	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
Simon Cooksey	0:fb7af294d5d9	999	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
Simon Cooksey	0:fb7af294d5d9	1000
Simon Cooksey	0:fb7af294d5d9	1001	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
Simon Cooksey	0:fb7af294d5d9	1002	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
Simon Cooksey	0:fb7af294d5d9	1003
Simon Cooksey	0:fb7af294d5d9	1004	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
Simon Cooksey	0:fb7af294d5d9	1005	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
Simon Cooksey	0:fb7af294d5d9	1006
Simon Cooksey	0:fb7af294d5d9	1007	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
Simon Cooksey	0:fb7af294d5d9	1008	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
Simon Cooksey	0:fb7af294d5d9	1009
Simon Cooksey	0:fb7af294d5d9	1010	/* ITM Integration Write Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1011	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
Simon Cooksey	0:fb7af294d5d9	1012	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
Simon Cooksey	0:fb7af294d5d9	1013
Simon Cooksey	0:fb7af294d5d9	1014	/* ITM Integration Read Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1015	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
Simon Cooksey	0:fb7af294d5d9	1016	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
Simon Cooksey	0:fb7af294d5d9	1017
Simon Cooksey	0:fb7af294d5d9	1018	/* ITM Integration Mode Control Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1019	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
Simon Cooksey	0:fb7af294d5d9	1020	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
Simon Cooksey	0:fb7af294d5d9	1021
Simon Cooksey	0:fb7af294d5d9	1022	/* ITM Lock Status Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1023	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
Simon Cooksey	0:fb7af294d5d9	1024	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
Simon Cooksey	0:fb7af294d5d9	1025
Simon Cooksey	0:fb7af294d5d9	1026	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
Simon Cooksey	0:fb7af294d5d9	1027	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
Simon Cooksey	0:fb7af294d5d9	1028
Simon Cooksey	0:fb7af294d5d9	1029	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
Simon Cooksey	0:fb7af294d5d9	1030	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
Simon Cooksey	0:fb7af294d5d9	1031
Simon Cooksey	0:fb7af294d5d9	1032	/@}/ /* end of group CMSIS_ITM */
Simon Cooksey	0:fb7af294d5d9	1033
Simon Cooksey	0:fb7af294d5d9	1034
Simon Cooksey	0:fb7af294d5d9	1035	/** \ingroup CMSIS_core_register
Simon Cooksey	0:fb7af294d5d9	1036	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Simon Cooksey	0:fb7af294d5d9	1037	\brief Type definitions for the Data Watchpoint and Trace (DWT)
Simon Cooksey	0:fb7af294d5d9	1038	@{
Simon Cooksey	0:fb7af294d5d9	1039	*/
Simon Cooksey	0:fb7af294d5d9	1040
Simon Cooksey	0:fb7af294d5d9	1041	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Simon Cooksey	0:fb7af294d5d9	1042	*/
Simon Cooksey	0:fb7af294d5d9	1043	typedef struct
Simon Cooksey	0:fb7af294d5d9	1044	{
Simon Cooksey	0:fb7af294d5d9	1045	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
Simon Cooksey	0:fb7af294d5d9	1046	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
Simon Cooksey	0:fb7af294d5d9	1047	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
Simon Cooksey	0:fb7af294d5d9	1048	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
Simon Cooksey	0:fb7af294d5d9	1049	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
Simon Cooksey	0:fb7af294d5d9	1050	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
Simon Cooksey	0:fb7af294d5d9	1051	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
Simon Cooksey	0:fb7af294d5d9	1052	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
Simon Cooksey	0:fb7af294d5d9	1053	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
Simon Cooksey	0:fb7af294d5d9	1054	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
Simon Cooksey	0:fb7af294d5d9	1055	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
Simon Cooksey	0:fb7af294d5d9	1056	uint32_t RESERVED0[1];
Simon Cooksey	0:fb7af294d5d9	1057	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
Simon Cooksey	0:fb7af294d5d9	1058	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
Simon Cooksey	0:fb7af294d5d9	1059	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
Simon Cooksey	0:fb7af294d5d9	1060	uint32_t RESERVED1[1];
Simon Cooksey	0:fb7af294d5d9	1061	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
Simon Cooksey	0:fb7af294d5d9	1062	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
Simon Cooksey	0:fb7af294d5d9	1063	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
Simon Cooksey	0:fb7af294d5d9	1064	uint32_t RESERVED2[1];
Simon Cooksey	0:fb7af294d5d9	1065	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
Simon Cooksey	0:fb7af294d5d9	1066	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
Simon Cooksey	0:fb7af294d5d9	1067	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
Simon Cooksey	0:fb7af294d5d9	1068	uint32_t RESERVED3[981];
Simon Cooksey	0:fb7af294d5d9	1069	__O uint32_t LAR; /!< Offset: 0xFB0 ( W) Lock Access Register /
Simon Cooksey	0:fb7af294d5d9	1070	__I uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
Simon Cooksey	0:fb7af294d5d9	1071	} DWT_Type;
Simon Cooksey	0:fb7af294d5d9	1072
Simon Cooksey	0:fb7af294d5d9	1073	/* DWT Control Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1074	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
Simon Cooksey	0:fb7af294d5d9	1075	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
Simon Cooksey	0:fb7af294d5d9	1076
Simon Cooksey	0:fb7af294d5d9	1077	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
Simon Cooksey	0:fb7af294d5d9	1078	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
Simon Cooksey	0:fb7af294d5d9	1079
Simon Cooksey	0:fb7af294d5d9	1080	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
Simon Cooksey	0:fb7af294d5d9	1081	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
Simon Cooksey	0:fb7af294d5d9	1082
Simon Cooksey	0:fb7af294d5d9	1083	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
Simon Cooksey	0:fb7af294d5d9	1084	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
Simon Cooksey	0:fb7af294d5d9	1085
Simon Cooksey	0:fb7af294d5d9	1086	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
Simon Cooksey	0:fb7af294d5d9	1087	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
Simon Cooksey	0:fb7af294d5d9	1088
Simon Cooksey	0:fb7af294d5d9	1089	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
Simon Cooksey	0:fb7af294d5d9	1090	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
Simon Cooksey	0:fb7af294d5d9	1091
Simon Cooksey	0:fb7af294d5d9	1092	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
Simon Cooksey	0:fb7af294d5d9	1093	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
Simon Cooksey	0:fb7af294d5d9	1094
Simon Cooksey	0:fb7af294d5d9	1095	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
Simon Cooksey	0:fb7af294d5d9	1096	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
Simon Cooksey	0:fb7af294d5d9	1097
Simon Cooksey	0:fb7af294d5d9	1098	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
Simon Cooksey	0:fb7af294d5d9	1099	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
Simon Cooksey	0:fb7af294d5d9	1100
Simon Cooksey	0:fb7af294d5d9	1101	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
Simon Cooksey	0:fb7af294d5d9	1102	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
Simon Cooksey	0:fb7af294d5d9	1103
Simon Cooksey	0:fb7af294d5d9	1104	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
Simon Cooksey	0:fb7af294d5d9	1105	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
Simon Cooksey	0:fb7af294d5d9	1106
Simon Cooksey	0:fb7af294d5d9	1107	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
Simon Cooksey	0:fb7af294d5d9	1108	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
Simon Cooksey	0:fb7af294d5d9	1109
Simon Cooksey	0:fb7af294d5d9	1110	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
Simon Cooksey	0:fb7af294d5d9	1111	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
Simon Cooksey	0:fb7af294d5d9	1112
Simon Cooksey	0:fb7af294d5d9	1113	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
Simon Cooksey	0:fb7af294d5d9	1114	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
Simon Cooksey	0:fb7af294d5d9	1115
Simon Cooksey	0:fb7af294d5d9	1116	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
Simon Cooksey	0:fb7af294d5d9	1117	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
Simon Cooksey	0:fb7af294d5d9	1118
Simon Cooksey	0:fb7af294d5d9	1119	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
Simon Cooksey	0:fb7af294d5d9	1120	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
Simon Cooksey	0:fb7af294d5d9	1121
Simon Cooksey	0:fb7af294d5d9	1122	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
Simon Cooksey	0:fb7af294d5d9	1123	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
Simon Cooksey	0:fb7af294d5d9	1124
Simon Cooksey	0:fb7af294d5d9	1125	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
Simon Cooksey	0:fb7af294d5d9	1126	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
Simon Cooksey	0:fb7af294d5d9	1127
Simon Cooksey	0:fb7af294d5d9	1128	/* DWT CPI Count Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1129	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
Simon Cooksey	0:fb7af294d5d9	1130	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
Simon Cooksey	0:fb7af294d5d9	1131
Simon Cooksey	0:fb7af294d5d9	1132	/* DWT Exception Overhead Count Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1133	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
Simon Cooksey	0:fb7af294d5d9	1134	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
Simon Cooksey	0:fb7af294d5d9	1135
Simon Cooksey	0:fb7af294d5d9	1136	/* DWT Sleep Count Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1137	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
Simon Cooksey	0:fb7af294d5d9	1138	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
Simon Cooksey	0:fb7af294d5d9	1139
Simon Cooksey	0:fb7af294d5d9	1140	/* DWT LSU Count Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1141	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
Simon Cooksey	0:fb7af294d5d9	1142	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
Simon Cooksey	0:fb7af294d5d9	1143
Simon Cooksey	0:fb7af294d5d9	1144	/* DWT Folded-instruction Count Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1145	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
Simon Cooksey	0:fb7af294d5d9	1146	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
Simon Cooksey	0:fb7af294d5d9	1147
Simon Cooksey	0:fb7af294d5d9	1148	/* DWT Comparator Mask Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1149	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
Simon Cooksey	0:fb7af294d5d9	1150	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
Simon Cooksey	0:fb7af294d5d9	1151
Simon Cooksey	0:fb7af294d5d9	1152	/* DWT Comparator Function Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1153	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
Simon Cooksey	0:fb7af294d5d9	1154	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
Simon Cooksey	0:fb7af294d5d9	1155
Simon Cooksey	0:fb7af294d5d9	1156	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
Simon Cooksey	0:fb7af294d5d9	1157	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
Simon Cooksey	0:fb7af294d5d9	1158
Simon Cooksey	0:fb7af294d5d9	1159	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
Simon Cooksey	0:fb7af294d5d9	1160	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
Simon Cooksey	0:fb7af294d5d9	1161
Simon Cooksey	0:fb7af294d5d9	1162	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
Simon Cooksey	0:fb7af294d5d9	1163	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
Simon Cooksey	0:fb7af294d5d9	1164
Simon Cooksey	0:fb7af294d5d9	1165	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
Simon Cooksey	0:fb7af294d5d9	1166	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
Simon Cooksey	0:fb7af294d5d9	1167
Simon Cooksey	0:fb7af294d5d9	1168	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
Simon Cooksey	0:fb7af294d5d9	1169	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
Simon Cooksey	0:fb7af294d5d9	1170
Simon Cooksey	0:fb7af294d5d9	1171	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
Simon Cooksey	0:fb7af294d5d9	1172	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
Simon Cooksey	0:fb7af294d5d9	1173
Simon Cooksey	0:fb7af294d5d9	1174	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
Simon Cooksey	0:fb7af294d5d9	1175	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
Simon Cooksey	0:fb7af294d5d9	1176
Simon Cooksey	0:fb7af294d5d9	1177	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
Simon Cooksey	0:fb7af294d5d9	1178	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
Simon Cooksey	0:fb7af294d5d9	1179
Simon Cooksey	0:fb7af294d5d9	1180	/@}/ /* end of group CMSIS_DWT */
Simon Cooksey	0:fb7af294d5d9	1181
Simon Cooksey	0:fb7af294d5d9	1182
Simon Cooksey	0:fb7af294d5d9	1183	/** \ingroup CMSIS_core_register
Simon Cooksey	0:fb7af294d5d9	1184	\defgroup CMSIS_TPI Trace Port Interface (TPI)
Simon Cooksey	0:fb7af294d5d9	1185	\brief Type definitions for the Trace Port Interface (TPI)
Simon Cooksey	0:fb7af294d5d9	1186	@{
Simon Cooksey	0:fb7af294d5d9	1187	*/
Simon Cooksey	0:fb7af294d5d9	1188
Simon Cooksey	0:fb7af294d5d9	1189	/** \brief Structure type to access the Trace Port Interface Register (TPI).
Simon Cooksey	0:fb7af294d5d9	1190	*/
Simon Cooksey	0:fb7af294d5d9	1191	typedef struct
Simon Cooksey	0:fb7af294d5d9	1192	{
Simon Cooksey	0:fb7af294d5d9	1193	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
Simon Cooksey	0:fb7af294d5d9	1194	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
Simon Cooksey	0:fb7af294d5d9	1195	uint32_t RESERVED0[2];
Simon Cooksey	0:fb7af294d5d9	1196	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
Simon Cooksey	0:fb7af294d5d9	1197	uint32_t RESERVED1[55];
Simon Cooksey	0:fb7af294d5d9	1198	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
Simon Cooksey	0:fb7af294d5d9	1199	uint32_t RESERVED2[131];
Simon Cooksey	0:fb7af294d5d9	1200	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
Simon Cooksey	0:fb7af294d5d9	1201	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
Simon Cooksey	0:fb7af294d5d9	1202	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
Simon Cooksey	0:fb7af294d5d9	1203	uint32_t RESERVED3[759];
Simon Cooksey	0:fb7af294d5d9	1204	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
Simon Cooksey	0:fb7af294d5d9	1205	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
Simon Cooksey	0:fb7af294d5d9	1206	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
Simon Cooksey	0:fb7af294d5d9	1207	uint32_t RESERVED4[1];
Simon Cooksey	0:fb7af294d5d9	1208	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
Simon Cooksey	0:fb7af294d5d9	1209	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
Simon Cooksey	0:fb7af294d5d9	1210	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
Simon Cooksey	0:fb7af294d5d9	1211	uint32_t RESERVED5[39];
Simon Cooksey	0:fb7af294d5d9	1212	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
Simon Cooksey	0:fb7af294d5d9	1213	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
Simon Cooksey	0:fb7af294d5d9	1214	uint32_t RESERVED7[8];
Simon Cooksey	0:fb7af294d5d9	1215	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
Simon Cooksey	0:fb7af294d5d9	1216	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
Simon Cooksey	0:fb7af294d5d9	1217	} TPI_Type;
Simon Cooksey	0:fb7af294d5d9	1218
Simon Cooksey	0:fb7af294d5d9	1219	/* TPI Asynchronous Clock Prescaler Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1220	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
Simon Cooksey	0:fb7af294d5d9	1221	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
Simon Cooksey	0:fb7af294d5d9	1222
Simon Cooksey	0:fb7af294d5d9	1223	/* TPI Selected Pin Protocol Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1224	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
Simon Cooksey	0:fb7af294d5d9	1225	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
Simon Cooksey	0:fb7af294d5d9	1226
Simon Cooksey	0:fb7af294d5d9	1227	/* TPI Formatter and Flush Status Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1228	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
Simon Cooksey	0:fb7af294d5d9	1229	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
Simon Cooksey	0:fb7af294d5d9	1230
Simon Cooksey	0:fb7af294d5d9	1231	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
Simon Cooksey	0:fb7af294d5d9	1232	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
Simon Cooksey	0:fb7af294d5d9	1233
Simon Cooksey	0:fb7af294d5d9	1234	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
Simon Cooksey	0:fb7af294d5d9	1235	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
Simon Cooksey	0:fb7af294d5d9	1236
Simon Cooksey	0:fb7af294d5d9	1237	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
Simon Cooksey	0:fb7af294d5d9	1238	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
Simon Cooksey	0:fb7af294d5d9	1239
Simon Cooksey	0:fb7af294d5d9	1240	/* TPI Formatter and Flush Control Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1241	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
Simon Cooksey	0:fb7af294d5d9	1242	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
Simon Cooksey	0:fb7af294d5d9	1243
Simon Cooksey	0:fb7af294d5d9	1244	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
Simon Cooksey	0:fb7af294d5d9	1245	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
Simon Cooksey	0:fb7af294d5d9	1246
Simon Cooksey	0:fb7af294d5d9	1247	/* TPI TRIGGER Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1248	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
Simon Cooksey	0:fb7af294d5d9	1249	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
Simon Cooksey	0:fb7af294d5d9	1250
Simon Cooksey	0:fb7af294d5d9	1251	/* TPI Integration ETM Data Register Definitions (FIFO0) */
Simon Cooksey	0:fb7af294d5d9	1252	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
Simon Cooksey	0:fb7af294d5d9	1253	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
Simon Cooksey	0:fb7af294d5d9	1254
Simon Cooksey	0:fb7af294d5d9	1255	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
Simon Cooksey	0:fb7af294d5d9	1256	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
Simon Cooksey	0:fb7af294d5d9	1257
Simon Cooksey	0:fb7af294d5d9	1258	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
Simon Cooksey	0:fb7af294d5d9	1259	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
Simon Cooksey	0:fb7af294d5d9	1260
Simon Cooksey	0:fb7af294d5d9	1261	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
Simon Cooksey	0:fb7af294d5d9	1262	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
Simon Cooksey	0:fb7af294d5d9	1263
Simon Cooksey	0:fb7af294d5d9	1264	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
Simon Cooksey	0:fb7af294d5d9	1265	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
Simon Cooksey	0:fb7af294d5d9	1266
Simon Cooksey	0:fb7af294d5d9	1267	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
Simon Cooksey	0:fb7af294d5d9	1268	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
Simon Cooksey	0:fb7af294d5d9	1269
Simon Cooksey	0:fb7af294d5d9	1270	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
Simon Cooksey	0:fb7af294d5d9	1271	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
Simon Cooksey	0:fb7af294d5d9	1272
Simon Cooksey	0:fb7af294d5d9	1273	/* TPI ITATBCTR2 Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1274	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
Simon Cooksey	0:fb7af294d5d9	1275	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
Simon Cooksey	0:fb7af294d5d9	1276
Simon Cooksey	0:fb7af294d5d9	1277	/* TPI Integration ITM Data Register Definitions (FIFO1) */
Simon Cooksey	0:fb7af294d5d9	1278	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
Simon Cooksey	0:fb7af294d5d9	1279	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
Simon Cooksey	0:fb7af294d5d9	1280
Simon Cooksey	0:fb7af294d5d9	1281	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
Simon Cooksey	0:fb7af294d5d9	1282	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
Simon Cooksey	0:fb7af294d5d9	1283
Simon Cooksey	0:fb7af294d5d9	1284	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
Simon Cooksey	0:fb7af294d5d9	1285	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
Simon Cooksey	0:fb7af294d5d9	1286
Simon Cooksey	0:fb7af294d5d9	1287	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
Simon Cooksey	0:fb7af294d5d9	1288	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
Simon Cooksey	0:fb7af294d5d9	1289
Simon Cooksey	0:fb7af294d5d9	1290	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
Simon Cooksey	0:fb7af294d5d9	1291	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
Simon Cooksey	0:fb7af294d5d9	1292
Simon Cooksey	0:fb7af294d5d9	1293	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
Simon Cooksey	0:fb7af294d5d9	1294	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
Simon Cooksey	0:fb7af294d5d9	1295
Simon Cooksey	0:fb7af294d5d9	1296	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
Simon Cooksey	0:fb7af294d5d9	1297	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
Simon Cooksey	0:fb7af294d5d9	1298
Simon Cooksey	0:fb7af294d5d9	1299	/* TPI ITATBCTR0 Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1300	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
Simon Cooksey	0:fb7af294d5d9	1301	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
Simon Cooksey	0:fb7af294d5d9	1302
Simon Cooksey	0:fb7af294d5d9	1303	/* TPI Integration Mode Control Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1304	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
Simon Cooksey	0:fb7af294d5d9	1305	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
Simon Cooksey	0:fb7af294d5d9	1306
Simon Cooksey	0:fb7af294d5d9	1307	/* TPI DEVID Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1308	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
Simon Cooksey	0:fb7af294d5d9	1309	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
Simon Cooksey	0:fb7af294d5d9	1310
Simon Cooksey	0:fb7af294d5d9	1311	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
Simon Cooksey	0:fb7af294d5d9	1312	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
Simon Cooksey	0:fb7af294d5d9	1313
Simon Cooksey	0:fb7af294d5d9	1314	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
Simon Cooksey	0:fb7af294d5d9	1315	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
Simon Cooksey	0:fb7af294d5d9	1316
Simon Cooksey	0:fb7af294d5d9	1317	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
Simon Cooksey	0:fb7af294d5d9	1318	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
Simon Cooksey	0:fb7af294d5d9	1319
Simon Cooksey	0:fb7af294d5d9	1320	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
Simon Cooksey	0:fb7af294d5d9	1321	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
Simon Cooksey	0:fb7af294d5d9	1322
Simon Cooksey	0:fb7af294d5d9	1323	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
Simon Cooksey	0:fb7af294d5d9	1324	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
Simon Cooksey	0:fb7af294d5d9	1325
Simon Cooksey	0:fb7af294d5d9	1326	/* TPI DEVTYPE Register Definitions */
Simon Cooksey	0:fb7af294d5d9	1327	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
Simon Cooksey	0:fb7af294d5d9	1328	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
Simon Cooksey	0:fb7af294d5d9	1329
Simon Cooksey	0:fb7af294d5d9	1330	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
Simon Cooksey	0:fb7af294d5d9	1331	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
Simon Cooksey	0:fb7af294d5d9	1332
Simon Cooksey	0:fb7af294d5d9	1333	/@}/ /* end of group CMSIS_TPI */
Simon Cooksey	0:fb7af294d5d9	1334
Simon Cooksey	0:fb7af294d5d9	1335
Simon Cooksey	0:fb7af294d5d9	1336	#if (__MPU_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	1337	/** \ingroup CMSIS_core_register
Simon Cooksey	0:fb7af294d5d9	1338	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
Simon Cooksey	0:fb7af294d5d9	1339	\brief Type definitions for the Memory Protection Unit (MPU)
Simon Cooksey	0:fb7af294d5d9	1340	@{
Simon Cooksey	0:fb7af294d5d9	1341	*/
Simon Cooksey	0:fb7af294d5d9	1342
Simon Cooksey	0:fb7af294d5d9	1343	/** \brief Structure type to access the Memory Protection Unit (MPU).
Simon Cooksey	0:fb7af294d5d9	1344	*/
Simon Cooksey	0:fb7af294d5d9	1345	typedef struct
Simon Cooksey	0:fb7af294d5d9	1346	{
Simon Cooksey	0:fb7af294d5d9	1347	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
Simon Cooksey	0:fb7af294d5d9	1348	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
Simon Cooksey	0:fb7af294d5d9	1349	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
Simon Cooksey	0:fb7af294d5d9	1350	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
Simon Cooksey	0:fb7af294d5d9	1351	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
Simon Cooksey	0:fb7af294d5d9	1352	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
Simon Cooksey	0:fb7af294d5d9	1353	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
Simon Cooksey	0:fb7af294d5d9	1354	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
Simon Cooksey	0:fb7af294d5d9	1355	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
Simon Cooksey	0:fb7af294d5d9	1356	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
Simon Cooksey	0:fb7af294d5d9	1357	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
Simon Cooksey	0:fb7af294d5d9	1358	} MPU_Type;
Simon Cooksey	0:fb7af294d5d9	1359
Simon Cooksey	0:fb7af294d5d9	1360	/* MPU Type Register */
Simon Cooksey	0:fb7af294d5d9	1361	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
Simon Cooksey	0:fb7af294d5d9	1362	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
Simon Cooksey	0:fb7af294d5d9	1363
Simon Cooksey	0:fb7af294d5d9	1364	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
Simon Cooksey	0:fb7af294d5d9	1365	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
Simon Cooksey	0:fb7af294d5d9	1366
Simon Cooksey	0:fb7af294d5d9	1367	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
Simon Cooksey	0:fb7af294d5d9	1368	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
Simon Cooksey	0:fb7af294d5d9	1369
Simon Cooksey	0:fb7af294d5d9	1370	/* MPU Control Register */
Simon Cooksey	0:fb7af294d5d9	1371	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
Simon Cooksey	0:fb7af294d5d9	1372	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
Simon Cooksey	0:fb7af294d5d9	1373
Simon Cooksey	0:fb7af294d5d9	1374	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
Simon Cooksey	0:fb7af294d5d9	1375	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
Simon Cooksey	0:fb7af294d5d9	1376
Simon Cooksey	0:fb7af294d5d9	1377	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
Simon Cooksey	0:fb7af294d5d9	1378	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
Simon Cooksey	0:fb7af294d5d9	1379
Simon Cooksey	0:fb7af294d5d9	1380	/* MPU Region Number Register */
Simon Cooksey	0:fb7af294d5d9	1381	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
Simon Cooksey	0:fb7af294d5d9	1382	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
Simon Cooksey	0:fb7af294d5d9	1383
Simon Cooksey	0:fb7af294d5d9	1384	/* MPU Region Base Address Register */
Simon Cooksey	0:fb7af294d5d9	1385	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
Simon Cooksey	0:fb7af294d5d9	1386	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
Simon Cooksey	0:fb7af294d5d9	1387
Simon Cooksey	0:fb7af294d5d9	1388	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
Simon Cooksey	0:fb7af294d5d9	1389	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
Simon Cooksey	0:fb7af294d5d9	1390
Simon Cooksey	0:fb7af294d5d9	1391	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
Simon Cooksey	0:fb7af294d5d9	1392	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
Simon Cooksey	0:fb7af294d5d9	1393
Simon Cooksey	0:fb7af294d5d9	1394	/* MPU Region Attribute and Size Register */
Simon Cooksey	0:fb7af294d5d9	1395	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
Simon Cooksey	0:fb7af294d5d9	1396	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
Simon Cooksey	0:fb7af294d5d9	1397
Simon Cooksey	0:fb7af294d5d9	1398	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
Simon Cooksey	0:fb7af294d5d9	1399	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
Simon Cooksey	0:fb7af294d5d9	1400
Simon Cooksey	0:fb7af294d5d9	1401	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
Simon Cooksey	0:fb7af294d5d9	1402	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
Simon Cooksey	0:fb7af294d5d9	1403
Simon Cooksey	0:fb7af294d5d9	1404	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
Simon Cooksey	0:fb7af294d5d9	1405	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
Simon Cooksey	0:fb7af294d5d9	1406
Simon Cooksey	0:fb7af294d5d9	1407	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
Simon Cooksey	0:fb7af294d5d9	1408	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
Simon Cooksey	0:fb7af294d5d9	1409
Simon Cooksey	0:fb7af294d5d9	1410	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
Simon Cooksey	0:fb7af294d5d9	1411	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
Simon Cooksey	0:fb7af294d5d9	1412
Simon Cooksey	0:fb7af294d5d9	1413	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
Simon Cooksey	0:fb7af294d5d9	1414	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
Simon Cooksey	0:fb7af294d5d9	1415
Simon Cooksey	0:fb7af294d5d9	1416	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
Simon Cooksey	0:fb7af294d5d9	1417	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
Simon Cooksey	0:fb7af294d5d9	1418
Simon Cooksey	0:fb7af294d5d9	1419	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
Simon Cooksey	0:fb7af294d5d9	1420	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
Simon Cooksey	0:fb7af294d5d9	1421
Simon Cooksey	0:fb7af294d5d9	1422	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
Simon Cooksey	0:fb7af294d5d9	1423	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
Simon Cooksey	0:fb7af294d5d9	1424
Simon Cooksey	0:fb7af294d5d9	1425	/@} end of group CMSIS_MPU /
Simon Cooksey	0:fb7af294d5d9	1426	#endif
Simon Cooksey	0:fb7af294d5d9	1427
Simon Cooksey	0:fb7af294d5d9	1428
Simon Cooksey	0:fb7af294d5d9	1429	#if (__FPU_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	1430	/** \ingroup CMSIS_core_register
Simon Cooksey	0:fb7af294d5d9	1431	\defgroup CMSIS_FPU Floating Point Unit (FPU)
Simon Cooksey	0:fb7af294d5d9	1432	\brief Type definitions for the Floating Point Unit (FPU)
Simon Cooksey	0:fb7af294d5d9	1433	@{
Simon Cooksey	0:fb7af294d5d9	1434	*/
Simon Cooksey	0:fb7af294d5d9	1435
Simon Cooksey	0:fb7af294d5d9	1436	/** \brief Structure type to access the Floating Point Unit (FPU).
Simon Cooksey	0:fb7af294d5d9	1437	*/
Simon Cooksey	0:fb7af294d5d9	1438	typedef struct
Simon Cooksey	0:fb7af294d5d9	1439	{
Simon Cooksey	0:fb7af294d5d9	1440	uint32_t RESERVED0[1];
Simon Cooksey	0:fb7af294d5d9	1441	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
Simon Cooksey	0:fb7af294d5d9	1442	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
Simon Cooksey	0:fb7af294d5d9	1443	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
Simon Cooksey	0:fb7af294d5d9	1444	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
Simon Cooksey	0:fb7af294d5d9	1445	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
Simon Cooksey	0:fb7af294d5d9	1446	__I uint32_t MVFR2; /!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 /
Simon Cooksey	0:fb7af294d5d9	1447	} FPU_Type;
Simon Cooksey	0:fb7af294d5d9	1448
Simon Cooksey	0:fb7af294d5d9	1449	/* Floating-Point Context Control Register */
Simon Cooksey	0:fb7af294d5d9	1450	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
Simon Cooksey	0:fb7af294d5d9	1451	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
Simon Cooksey	0:fb7af294d5d9	1452
Simon Cooksey	0:fb7af294d5d9	1453	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
Simon Cooksey	0:fb7af294d5d9	1454	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
Simon Cooksey	0:fb7af294d5d9	1455
Simon Cooksey	0:fb7af294d5d9	1456	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
Simon Cooksey	0:fb7af294d5d9	1457	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
Simon Cooksey	0:fb7af294d5d9	1458
Simon Cooksey	0:fb7af294d5d9	1459	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
Simon Cooksey	0:fb7af294d5d9	1460	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
Simon Cooksey	0:fb7af294d5d9	1461
Simon Cooksey	0:fb7af294d5d9	1462	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
Simon Cooksey	0:fb7af294d5d9	1463	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
Simon Cooksey	0:fb7af294d5d9	1464
Simon Cooksey	0:fb7af294d5d9	1465	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
Simon Cooksey	0:fb7af294d5d9	1466	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
Simon Cooksey	0:fb7af294d5d9	1467
Simon Cooksey	0:fb7af294d5d9	1468	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
Simon Cooksey	0:fb7af294d5d9	1469	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
Simon Cooksey	0:fb7af294d5d9	1470
Simon Cooksey	0:fb7af294d5d9	1471	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
Simon Cooksey	0:fb7af294d5d9	1472	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
Simon Cooksey	0:fb7af294d5d9	1473
Simon Cooksey	0:fb7af294d5d9	1474	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
Simon Cooksey	0:fb7af294d5d9	1475	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
Simon Cooksey	0:fb7af294d5d9	1476
Simon Cooksey	0:fb7af294d5d9	1477	/* Floating-Point Context Address Register */
Simon Cooksey	0:fb7af294d5d9	1478	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
Simon Cooksey	0:fb7af294d5d9	1479	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
Simon Cooksey	0:fb7af294d5d9	1480
Simon Cooksey	0:fb7af294d5d9	1481	/* Floating-Point Default Status Control Register */
Simon Cooksey	0:fb7af294d5d9	1482	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
Simon Cooksey	0:fb7af294d5d9	1483	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
Simon Cooksey	0:fb7af294d5d9	1484
Simon Cooksey	0:fb7af294d5d9	1485	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
Simon Cooksey	0:fb7af294d5d9	1486	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
Simon Cooksey	0:fb7af294d5d9	1487
Simon Cooksey	0:fb7af294d5d9	1488	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
Simon Cooksey	0:fb7af294d5d9	1489	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
Simon Cooksey	0:fb7af294d5d9	1490
Simon Cooksey	0:fb7af294d5d9	1491	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
Simon Cooksey	0:fb7af294d5d9	1492	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
Simon Cooksey	0:fb7af294d5d9	1493
Simon Cooksey	0:fb7af294d5d9	1494	/* Media and FP Feature Register 0 */
Simon Cooksey	0:fb7af294d5d9	1495	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
Simon Cooksey	0:fb7af294d5d9	1496	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
Simon Cooksey	0:fb7af294d5d9	1497
Simon Cooksey	0:fb7af294d5d9	1498	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
Simon Cooksey	0:fb7af294d5d9	1499	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
Simon Cooksey	0:fb7af294d5d9	1500
Simon Cooksey	0:fb7af294d5d9	1501	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
Simon Cooksey	0:fb7af294d5d9	1502	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
Simon Cooksey	0:fb7af294d5d9	1503
Simon Cooksey	0:fb7af294d5d9	1504	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
Simon Cooksey	0:fb7af294d5d9	1505	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
Simon Cooksey	0:fb7af294d5d9	1506
Simon Cooksey	0:fb7af294d5d9	1507	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
Simon Cooksey	0:fb7af294d5d9	1508	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
Simon Cooksey	0:fb7af294d5d9	1509
Simon Cooksey	0:fb7af294d5d9	1510	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
Simon Cooksey	0:fb7af294d5d9	1511	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
Simon Cooksey	0:fb7af294d5d9	1512
Simon Cooksey	0:fb7af294d5d9	1513	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
Simon Cooksey	0:fb7af294d5d9	1514	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
Simon Cooksey	0:fb7af294d5d9	1515
Simon Cooksey	0:fb7af294d5d9	1516	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
Simon Cooksey	0:fb7af294d5d9	1517	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
Simon Cooksey	0:fb7af294d5d9	1518
Simon Cooksey	0:fb7af294d5d9	1519	/* Media and FP Feature Register 1 */
Simon Cooksey	0:fb7af294d5d9	1520	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
Simon Cooksey	0:fb7af294d5d9	1521	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
Simon Cooksey	0:fb7af294d5d9	1522
Simon Cooksey	0:fb7af294d5d9	1523	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
Simon Cooksey	0:fb7af294d5d9	1524	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
Simon Cooksey	0:fb7af294d5d9	1525
Simon Cooksey	0:fb7af294d5d9	1526	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
Simon Cooksey	0:fb7af294d5d9	1527	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
Simon Cooksey	0:fb7af294d5d9	1528
Simon Cooksey	0:fb7af294d5d9	1529	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
Simon Cooksey	0:fb7af294d5d9	1530	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
Simon Cooksey	0:fb7af294d5d9	1531
Simon Cooksey	0:fb7af294d5d9	1532	/* Media and FP Feature Register 2 */
Simon Cooksey	0:fb7af294d5d9	1533
Simon Cooksey	0:fb7af294d5d9	1534	/@} end of group CMSIS_FPU /
Simon Cooksey	0:fb7af294d5d9	1535	#endif
Simon Cooksey	0:fb7af294d5d9	1536
Simon Cooksey	0:fb7af294d5d9	1537
Simon Cooksey	0:fb7af294d5d9	1538	/** \ingroup CMSIS_core_register
Simon Cooksey	0:fb7af294d5d9	1539	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Simon Cooksey	0:fb7af294d5d9	1540	\brief Type definitions for the Core Debug Registers
Simon Cooksey	0:fb7af294d5d9	1541	@{
Simon Cooksey	0:fb7af294d5d9	1542	*/
Simon Cooksey	0:fb7af294d5d9	1543
Simon Cooksey	0:fb7af294d5d9	1544	/** \brief Structure type to access the Core Debug Register (CoreDebug).
Simon Cooksey	0:fb7af294d5d9	1545	*/
Simon Cooksey	0:fb7af294d5d9	1546	typedef struct
Simon Cooksey	0:fb7af294d5d9	1547	{
Simon Cooksey	0:fb7af294d5d9	1548	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
Simon Cooksey	0:fb7af294d5d9	1549	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
Simon Cooksey	0:fb7af294d5d9	1550	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
Simon Cooksey	0:fb7af294d5d9	1551	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
Simon Cooksey	0:fb7af294d5d9	1552	} CoreDebug_Type;
Simon Cooksey	0:fb7af294d5d9	1553
Simon Cooksey	0:fb7af294d5d9	1554	/* Debug Halting Control and Status Register */
Simon Cooksey	0:fb7af294d5d9	1555	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
Simon Cooksey	0:fb7af294d5d9	1556	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
Simon Cooksey	0:fb7af294d5d9	1557
Simon Cooksey	0:fb7af294d5d9	1558	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
Simon Cooksey	0:fb7af294d5d9	1559	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
Simon Cooksey	0:fb7af294d5d9	1560
Simon Cooksey	0:fb7af294d5d9	1561	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
Simon Cooksey	0:fb7af294d5d9	1562	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
Simon Cooksey	0:fb7af294d5d9	1563
Simon Cooksey	0:fb7af294d5d9	1564	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
Simon Cooksey	0:fb7af294d5d9	1565	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
Simon Cooksey	0:fb7af294d5d9	1566
Simon Cooksey	0:fb7af294d5d9	1567	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
Simon Cooksey	0:fb7af294d5d9	1568	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
Simon Cooksey	0:fb7af294d5d9	1569
Simon Cooksey	0:fb7af294d5d9	1570	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
Simon Cooksey	0:fb7af294d5d9	1571	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
Simon Cooksey	0:fb7af294d5d9	1572
Simon Cooksey	0:fb7af294d5d9	1573	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
Simon Cooksey	0:fb7af294d5d9	1574	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
Simon Cooksey	0:fb7af294d5d9	1575
Simon Cooksey	0:fb7af294d5d9	1576	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
Simon Cooksey	0:fb7af294d5d9	1577	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
Simon Cooksey	0:fb7af294d5d9	1578
Simon Cooksey	0:fb7af294d5d9	1579	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
Simon Cooksey	0:fb7af294d5d9	1580	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
Simon Cooksey	0:fb7af294d5d9	1581
Simon Cooksey	0:fb7af294d5d9	1582	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
Simon Cooksey	0:fb7af294d5d9	1583	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
Simon Cooksey	0:fb7af294d5d9	1584
Simon Cooksey	0:fb7af294d5d9	1585	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
Simon Cooksey	0:fb7af294d5d9	1586	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
Simon Cooksey	0:fb7af294d5d9	1587
Simon Cooksey	0:fb7af294d5d9	1588	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
Simon Cooksey	0:fb7af294d5d9	1589	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
Simon Cooksey	0:fb7af294d5d9	1590
Simon Cooksey	0:fb7af294d5d9	1591	/* Debug Core Register Selector Register */
Simon Cooksey	0:fb7af294d5d9	1592	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
Simon Cooksey	0:fb7af294d5d9	1593	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
Simon Cooksey	0:fb7af294d5d9	1594
Simon Cooksey	0:fb7af294d5d9	1595	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
Simon Cooksey	0:fb7af294d5d9	1596	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
Simon Cooksey	0:fb7af294d5d9	1597
Simon Cooksey	0:fb7af294d5d9	1598	/* Debug Exception and Monitor Control Register */
Simon Cooksey	0:fb7af294d5d9	1599	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
Simon Cooksey	0:fb7af294d5d9	1600	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
Simon Cooksey	0:fb7af294d5d9	1601
Simon Cooksey	0:fb7af294d5d9	1602	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
Simon Cooksey	0:fb7af294d5d9	1603	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
Simon Cooksey	0:fb7af294d5d9	1604
Simon Cooksey	0:fb7af294d5d9	1605	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
Simon Cooksey	0:fb7af294d5d9	1606	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
Simon Cooksey	0:fb7af294d5d9	1607
Simon Cooksey	0:fb7af294d5d9	1608	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
Simon Cooksey	0:fb7af294d5d9	1609	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
Simon Cooksey	0:fb7af294d5d9	1610
Simon Cooksey	0:fb7af294d5d9	1611	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
Simon Cooksey	0:fb7af294d5d9	1612	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
Simon Cooksey	0:fb7af294d5d9	1613
Simon Cooksey	0:fb7af294d5d9	1614	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
Simon Cooksey	0:fb7af294d5d9	1615	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
Simon Cooksey	0:fb7af294d5d9	1616
Simon Cooksey	0:fb7af294d5d9	1617	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
Simon Cooksey	0:fb7af294d5d9	1618	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
Simon Cooksey	0:fb7af294d5d9	1619
Simon Cooksey	0:fb7af294d5d9	1620	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
Simon Cooksey	0:fb7af294d5d9	1621	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
Simon Cooksey	0:fb7af294d5d9	1622
Simon Cooksey	0:fb7af294d5d9	1623	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
Simon Cooksey	0:fb7af294d5d9	1624	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
Simon Cooksey	0:fb7af294d5d9	1625
Simon Cooksey	0:fb7af294d5d9	1626	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
Simon Cooksey	0:fb7af294d5d9	1627	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
Simon Cooksey	0:fb7af294d5d9	1628
Simon Cooksey	0:fb7af294d5d9	1629	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
Simon Cooksey	0:fb7af294d5d9	1630	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
Simon Cooksey	0:fb7af294d5d9	1631
Simon Cooksey	0:fb7af294d5d9	1632	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
Simon Cooksey	0:fb7af294d5d9	1633	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
Simon Cooksey	0:fb7af294d5d9	1634
Simon Cooksey	0:fb7af294d5d9	1635	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
Simon Cooksey	0:fb7af294d5d9	1636	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
Simon Cooksey	0:fb7af294d5d9	1637
Simon Cooksey	0:fb7af294d5d9	1638	/@} end of group CMSIS_CoreDebug /
Simon Cooksey	0:fb7af294d5d9	1639
Simon Cooksey	0:fb7af294d5d9	1640
Simon Cooksey	0:fb7af294d5d9	1641	/** \ingroup CMSIS_core_register
Simon Cooksey	0:fb7af294d5d9	1642	\defgroup CMSIS_core_base Core Definitions
Simon Cooksey	0:fb7af294d5d9	1643	\brief Definitions for base addresses, unions, and structures.
Simon Cooksey	0:fb7af294d5d9	1644	@{
Simon Cooksey	0:fb7af294d5d9	1645	*/
Simon Cooksey	0:fb7af294d5d9	1646
Simon Cooksey	0:fb7af294d5d9	1647	/* Memory mapping of Cortex-M4 Hardware */
Simon Cooksey	0:fb7af294d5d9	1648	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
Simon Cooksey	0:fb7af294d5d9	1649	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
Simon Cooksey	0:fb7af294d5d9	1650	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
Simon Cooksey	0:fb7af294d5d9	1651	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
Simon Cooksey	0:fb7af294d5d9	1652	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
Simon Cooksey	0:fb7af294d5d9	1653	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
Simon Cooksey	0:fb7af294d5d9	1654	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
Simon Cooksey	0:fb7af294d5d9	1655	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
Simon Cooksey	0:fb7af294d5d9	1656
Simon Cooksey	0:fb7af294d5d9	1657	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
Simon Cooksey	0:fb7af294d5d9	1658	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
Simon Cooksey	0:fb7af294d5d9	1659	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
Simon Cooksey	0:fb7af294d5d9	1660	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
Simon Cooksey	0:fb7af294d5d9	1661	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
Simon Cooksey	0:fb7af294d5d9	1662	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
Simon Cooksey	0:fb7af294d5d9	1663	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
Simon Cooksey	0:fb7af294d5d9	1664	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
Simon Cooksey	0:fb7af294d5d9	1665
Simon Cooksey	0:fb7af294d5d9	1666	#if (__MPU_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	1667	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
Simon Cooksey	0:fb7af294d5d9	1668	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
Simon Cooksey	0:fb7af294d5d9	1669	#endif
Simon Cooksey	0:fb7af294d5d9	1670
Simon Cooksey	0:fb7af294d5d9	1671	#if (__FPU_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	1672	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
Simon Cooksey	0:fb7af294d5d9	1673	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
Simon Cooksey	0:fb7af294d5d9	1674	#endif
Simon Cooksey	0:fb7af294d5d9	1675
Simon Cooksey	0:fb7af294d5d9	1676	/@} /
Simon Cooksey	0:fb7af294d5d9	1677
Simon Cooksey	0:fb7af294d5d9	1678
Simon Cooksey	0:fb7af294d5d9	1679
Simon Cooksey	0:fb7af294d5d9	1680	/*******************************************************************************
Simon Cooksey	0:fb7af294d5d9	1681	* Hardware Abstraction Layer
Simon Cooksey	0:fb7af294d5d9	1682	Core Function Interface contains:
Simon Cooksey	0:fb7af294d5d9	1683	- Core NVIC Functions
Simon Cooksey	0:fb7af294d5d9	1684	- Core SysTick Functions
Simon Cooksey	0:fb7af294d5d9	1685	- Core Debug Functions
Simon Cooksey	0:fb7af294d5d9	1686	- Core Register Access Functions
Simon Cooksey	0:fb7af294d5d9	1687	******************************************************************************/
Simon Cooksey	0:fb7af294d5d9	1688	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Simon Cooksey	0:fb7af294d5d9	1689	*/
Simon Cooksey	0:fb7af294d5d9	1690
Simon Cooksey	0:fb7af294d5d9	1691
Simon Cooksey	0:fb7af294d5d9	1692
Simon Cooksey	0:fb7af294d5d9	1693	/* ########################## NVIC functions #################################### */
Simon Cooksey	0:fb7af294d5d9	1694	/** \ingroup CMSIS_Core_FunctionInterface
Simon Cooksey	0:fb7af294d5d9	1695	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
Simon Cooksey	0:fb7af294d5d9	1696	\brief Functions that manage interrupts and exceptions via the NVIC.
Simon Cooksey	0:fb7af294d5d9	1697	@{
Simon Cooksey	0:fb7af294d5d9	1698	*/
Simon Cooksey	0:fb7af294d5d9	1699
Simon Cooksey	0:fb7af294d5d9	1700	/** \brief Set Priority Grouping
Simon Cooksey	0:fb7af294d5d9	1701
Simon Cooksey	0:fb7af294d5d9	1702	The function sets the priority grouping field using the required unlock sequence.
Simon Cooksey	0:fb7af294d5d9	1703	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Simon Cooksey	0:fb7af294d5d9	1704	Only values from 0..7 are used.
Simon Cooksey	0:fb7af294d5d9	1705	In case of a conflict between priority grouping and available
Simon Cooksey	0:fb7af294d5d9	1706	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Simon Cooksey	0:fb7af294d5d9	1707
Simon Cooksey	0:fb7af294d5d9	1708	\param [in] PriorityGroup Priority grouping field.
Simon Cooksey	0:fb7af294d5d9	1709	*/
Simon Cooksey	0:fb7af294d5d9	1710	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Simon Cooksey	0:fb7af294d5d9	1711	{
Simon Cooksey	0:fb7af294d5d9	1712	uint32_t reg_value;
Simon Cooksey	0:fb7af294d5d9	1713	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Simon Cooksey	0:fb7af294d5d9	1714
Simon Cooksey	0:fb7af294d5d9	1715	reg_value = SCB->AIRCR; /* read old register configuration */
Simon Cooksey	0:fb7af294d5d9	1716	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Simon Cooksey	0:fb7af294d5d9	1717	reg_value = (reg_value \|
Simon Cooksey	0:fb7af294d5d9	1718	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Simon Cooksey	0:fb7af294d5d9	1719	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
Simon Cooksey	0:fb7af294d5d9	1720	SCB->AIRCR = reg_value;
Simon Cooksey	0:fb7af294d5d9	1721	}
Simon Cooksey	0:fb7af294d5d9	1722
Simon Cooksey	0:fb7af294d5d9	1723
Simon Cooksey	0:fb7af294d5d9	1724	/** \brief Get Priority Grouping
Simon Cooksey	0:fb7af294d5d9	1725
Simon Cooksey	0:fb7af294d5d9	1726	The function reads the priority grouping field from the NVIC Interrupt Controller.
Simon Cooksey	0:fb7af294d5d9	1727
Simon Cooksey	0:fb7af294d5d9	1728	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Simon Cooksey	0:fb7af294d5d9	1729	*/
Simon Cooksey	0:fb7af294d5d9	1730	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Simon Cooksey	0:fb7af294d5d9	1731	{
Simon Cooksey	0:fb7af294d5d9	1732	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Simon Cooksey	0:fb7af294d5d9	1733	}
Simon Cooksey	0:fb7af294d5d9	1734
Simon Cooksey	0:fb7af294d5d9	1735
Simon Cooksey	0:fb7af294d5d9	1736	/** \brief Enable External Interrupt
Simon Cooksey	0:fb7af294d5d9	1737
Simon Cooksey	0:fb7af294d5d9	1738	The function enables a device-specific interrupt in the NVIC interrupt controller.
Simon Cooksey	0:fb7af294d5d9	1739
Simon Cooksey	0:fb7af294d5d9	1740	\param [in] IRQn External interrupt number. Value cannot be negative.
Simon Cooksey	0:fb7af294d5d9	1741	*/
Simon Cooksey	0:fb7af294d5d9	1742	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Simon Cooksey	0:fb7af294d5d9	1743	{
Simon Cooksey	0:fb7af294d5d9	1744	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Simon Cooksey	0:fb7af294d5d9	1745	}
Simon Cooksey	0:fb7af294d5d9	1746
Simon Cooksey	0:fb7af294d5d9	1747
Simon Cooksey	0:fb7af294d5d9	1748	/** \brief Disable External Interrupt
Simon Cooksey	0:fb7af294d5d9	1749
Simon Cooksey	0:fb7af294d5d9	1750	The function disables a device-specific interrupt in the NVIC interrupt controller.
Simon Cooksey	0:fb7af294d5d9	1751
Simon Cooksey	0:fb7af294d5d9	1752	\param [in] IRQn External interrupt number. Value cannot be negative.
Simon Cooksey	0:fb7af294d5d9	1753	*/
Simon Cooksey	0:fb7af294d5d9	1754	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Simon Cooksey	0:fb7af294d5d9	1755	{
Simon Cooksey	0:fb7af294d5d9	1756	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Simon Cooksey	0:fb7af294d5d9	1757	}
Simon Cooksey	0:fb7af294d5d9	1758
Simon Cooksey	0:fb7af294d5d9	1759
Simon Cooksey	0:fb7af294d5d9	1760	/** \brief Get Pending Interrupt
Simon Cooksey	0:fb7af294d5d9	1761
Simon Cooksey	0:fb7af294d5d9	1762	The function reads the pending register in the NVIC and returns the pending bit
Simon Cooksey	0:fb7af294d5d9	1763	for the specified interrupt.
Simon Cooksey	0:fb7af294d5d9	1764
Simon Cooksey	0:fb7af294d5d9	1765	\param [in] IRQn Interrupt number.
Simon Cooksey	0:fb7af294d5d9	1766
Simon Cooksey	0:fb7af294d5d9	1767	\return 0 Interrupt status is not pending.
Simon Cooksey	0:fb7af294d5d9	1768	\return 1 Interrupt status is pending.
Simon Cooksey	0:fb7af294d5d9	1769	*/
Simon Cooksey	0:fb7af294d5d9	1770	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Simon Cooksey	0:fb7af294d5d9	1771	{
Simon Cooksey	0:fb7af294d5d9	1772	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Simon Cooksey	0:fb7af294d5d9	1773	}
Simon Cooksey	0:fb7af294d5d9	1774
Simon Cooksey	0:fb7af294d5d9	1775
Simon Cooksey	0:fb7af294d5d9	1776	/** \brief Set Pending Interrupt
Simon Cooksey	0:fb7af294d5d9	1777
Simon Cooksey	0:fb7af294d5d9	1778	The function sets the pending bit of an external interrupt.
Simon Cooksey	0:fb7af294d5d9	1779
Simon Cooksey	0:fb7af294d5d9	1780	\param [in] IRQn Interrupt number. Value cannot be negative.
Simon Cooksey	0:fb7af294d5d9	1781	*/
Simon Cooksey	0:fb7af294d5d9	1782	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Simon Cooksey	0:fb7af294d5d9	1783	{
Simon Cooksey	0:fb7af294d5d9	1784	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Simon Cooksey	0:fb7af294d5d9	1785	}
Simon Cooksey	0:fb7af294d5d9	1786
Simon Cooksey	0:fb7af294d5d9	1787
Simon Cooksey	0:fb7af294d5d9	1788	/** \brief Clear Pending Interrupt
Simon Cooksey	0:fb7af294d5d9	1789
Simon Cooksey	0:fb7af294d5d9	1790	The function clears the pending bit of an external interrupt.
Simon Cooksey	0:fb7af294d5d9	1791
Simon Cooksey	0:fb7af294d5d9	1792	\param [in] IRQn External interrupt number. Value cannot be negative.
Simon Cooksey	0:fb7af294d5d9	1793	*/
Simon Cooksey	0:fb7af294d5d9	1794	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Simon Cooksey	0:fb7af294d5d9	1795	{
Simon Cooksey	0:fb7af294d5d9	1796	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Simon Cooksey	0:fb7af294d5d9	1797	}
Simon Cooksey	0:fb7af294d5d9	1798
Simon Cooksey	0:fb7af294d5d9	1799
Simon Cooksey	0:fb7af294d5d9	1800	/** \brief Get Active Interrupt
Simon Cooksey	0:fb7af294d5d9	1801
Simon Cooksey	0:fb7af294d5d9	1802	The function reads the active register in NVIC and returns the active bit.
Simon Cooksey	0:fb7af294d5d9	1803
Simon Cooksey	0:fb7af294d5d9	1804	\param [in] IRQn Interrupt number.
Simon Cooksey	0:fb7af294d5d9	1805
Simon Cooksey	0:fb7af294d5d9	1806	\return 0 Interrupt status is not active.
Simon Cooksey	0:fb7af294d5d9	1807	\return 1 Interrupt status is active.
Simon Cooksey	0:fb7af294d5d9	1808	*/
Simon Cooksey	0:fb7af294d5d9	1809	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Simon Cooksey	0:fb7af294d5d9	1810	{
Simon Cooksey	0:fb7af294d5d9	1811	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Simon Cooksey	0:fb7af294d5d9	1812	}
Simon Cooksey	0:fb7af294d5d9	1813
Simon Cooksey	0:fb7af294d5d9	1814
Simon Cooksey	0:fb7af294d5d9	1815	/** \brief Set Interrupt Priority
Simon Cooksey	0:fb7af294d5d9	1816
Simon Cooksey	0:fb7af294d5d9	1817	The function sets the priority of an interrupt.
Simon Cooksey	0:fb7af294d5d9	1818
Simon Cooksey	0:fb7af294d5d9	1819	\note The priority cannot be set for every core interrupt.
Simon Cooksey	0:fb7af294d5d9	1820
Simon Cooksey	0:fb7af294d5d9	1821	\param [in] IRQn Interrupt number.
Simon Cooksey	0:fb7af294d5d9	1822	\param [in] priority Priority to set.
Simon Cooksey	0:fb7af294d5d9	1823	*/
Simon Cooksey	0:fb7af294d5d9	1824	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Simon Cooksey	0:fb7af294d5d9	1825	{
Simon Cooksey	0:fb7af294d5d9	1826	if((int32_t)IRQn < 0) {
Simon Cooksey	0:fb7af294d5d9	1827	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Simon Cooksey	0:fb7af294d5d9	1828	}
Simon Cooksey	0:fb7af294d5d9	1829	else {
Simon Cooksey	0:fb7af294d5d9	1830	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Simon Cooksey	0:fb7af294d5d9	1831	}
Simon Cooksey	0:fb7af294d5d9	1832	}
Simon Cooksey	0:fb7af294d5d9	1833
Simon Cooksey	0:fb7af294d5d9	1834
Simon Cooksey	0:fb7af294d5d9	1835	/** \brief Get Interrupt Priority
Simon Cooksey	0:fb7af294d5d9	1836
Simon Cooksey	0:fb7af294d5d9	1837	The function reads the priority of an interrupt. The interrupt
Simon Cooksey	0:fb7af294d5d9	1838	number can be positive to specify an external (device specific)
Simon Cooksey	0:fb7af294d5d9	1839	interrupt, or negative to specify an internal (core) interrupt.
Simon Cooksey	0:fb7af294d5d9	1840
Simon Cooksey	0:fb7af294d5d9	1841
Simon Cooksey	0:fb7af294d5d9	1842	\param [in] IRQn Interrupt number.
Simon Cooksey	0:fb7af294d5d9	1843	\return Interrupt Priority. Value is aligned automatically to the implemented
Simon Cooksey	0:fb7af294d5d9	1844	priority bits of the microcontroller.
Simon Cooksey	0:fb7af294d5d9	1845	*/
Simon Cooksey	0:fb7af294d5d9	1846	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Simon Cooksey	0:fb7af294d5d9	1847	{
Simon Cooksey	0:fb7af294d5d9	1848
Simon Cooksey	0:fb7af294d5d9	1849	if((int32_t)IRQn < 0) {
Simon Cooksey	0:fb7af294d5d9	1850	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Simon Cooksey	0:fb7af294d5d9	1851	}
Simon Cooksey	0:fb7af294d5d9	1852	else {
Simon Cooksey	0:fb7af294d5d9	1853	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Simon Cooksey	0:fb7af294d5d9	1854	}
Simon Cooksey	0:fb7af294d5d9	1855	}
Simon Cooksey	0:fb7af294d5d9	1856
Simon Cooksey	0:fb7af294d5d9	1857
Simon Cooksey	0:fb7af294d5d9	1858	/** \brief Encode Priority
Simon Cooksey	0:fb7af294d5d9	1859
Simon Cooksey	0:fb7af294d5d9	1860	The function encodes the priority for an interrupt with the given priority group,
Simon Cooksey	0:fb7af294d5d9	1861	preemptive priority value, and subpriority value.
Simon Cooksey	0:fb7af294d5d9	1862	In case of a conflict between priority grouping and available
Simon Cooksey	0:fb7af294d5d9	1863	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Simon Cooksey	0:fb7af294d5d9	1864
Simon Cooksey	0:fb7af294d5d9	1865	\param [in] PriorityGroup Used priority group.
Simon Cooksey	0:fb7af294d5d9	1866	\param [in] PreemptPriority Preemptive priority value (starting from 0).
Simon Cooksey	0:fb7af294d5d9	1867	\param [in] SubPriority Subpriority value (starting from 0).
Simon Cooksey	0:fb7af294d5d9	1868	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Simon Cooksey	0:fb7af294d5d9	1869	*/
Simon Cooksey	0:fb7af294d5d9	1870	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Simon Cooksey	0:fb7af294d5d9	1871	{
Simon Cooksey	0:fb7af294d5d9	1872	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Simon Cooksey	0:fb7af294d5d9	1873	uint32_t PreemptPriorityBits;
Simon Cooksey	0:fb7af294d5d9	1874	uint32_t SubPriorityBits;
Simon Cooksey	0:fb7af294d5d9	1875
Simon Cooksey	0:fb7af294d5d9	1876	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Simon Cooksey	0:fb7af294d5d9	1877	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Simon Cooksey	0:fb7af294d5d9	1878
Simon Cooksey	0:fb7af294d5d9	1879	return (
Simon Cooksey	0:fb7af294d5d9	1880	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
Simon Cooksey	0:fb7af294d5d9	1881	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Simon Cooksey	0:fb7af294d5d9	1882	);
Simon Cooksey	0:fb7af294d5d9	1883	}
Simon Cooksey	0:fb7af294d5d9	1884
Simon Cooksey	0:fb7af294d5d9	1885
Simon Cooksey	0:fb7af294d5d9	1886	/** \brief Decode Priority
Simon Cooksey	0:fb7af294d5d9	1887
Simon Cooksey	0:fb7af294d5d9	1888	The function decodes an interrupt priority value with a given priority group to
Simon Cooksey	0:fb7af294d5d9	1889	preemptive priority value and subpriority value.
Simon Cooksey	0:fb7af294d5d9	1890	In case of a conflict between priority grouping and available
Simon Cooksey	0:fb7af294d5d9	1891	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Simon Cooksey	0:fb7af294d5d9	1892
Simon Cooksey	0:fb7af294d5d9	1893	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Simon Cooksey	0:fb7af294d5d9	1894	\param [in] PriorityGroup Used priority group.
Simon Cooksey	0:fb7af294d5d9	1895	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
Simon Cooksey	0:fb7af294d5d9	1896	\param [out] pSubPriority Subpriority value (starting from 0).
Simon Cooksey	0:fb7af294d5d9	1897	*/
Simon Cooksey	0:fb7af294d5d9	1898	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Simon Cooksey	0:fb7af294d5d9	1899	{
Simon Cooksey	0:fb7af294d5d9	1900	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Simon Cooksey	0:fb7af294d5d9	1901	uint32_t PreemptPriorityBits;
Simon Cooksey	0:fb7af294d5d9	1902	uint32_t SubPriorityBits;
Simon Cooksey	0:fb7af294d5d9	1903
Simon Cooksey	0:fb7af294d5d9	1904	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Simon Cooksey	0:fb7af294d5d9	1905	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Simon Cooksey	0:fb7af294d5d9	1906
Simon Cooksey	0:fb7af294d5d9	1907	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Simon Cooksey	0:fb7af294d5d9	1908	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Simon Cooksey	0:fb7af294d5d9	1909	}
Simon Cooksey	0:fb7af294d5d9	1910
Simon Cooksey	0:fb7af294d5d9	1911
Simon Cooksey	0:fb7af294d5d9	1912	/** \brief System Reset
Simon Cooksey	0:fb7af294d5d9	1913
Simon Cooksey	0:fb7af294d5d9	1914	The function initiates a system reset request to reset the MCU.
Simon Cooksey	0:fb7af294d5d9	1915	*/
Simon Cooksey	0:fb7af294d5d9	1916	__STATIC_INLINE void NVIC_SystemReset(void)
Simon Cooksey	0:fb7af294d5d9	1917	{
Simon Cooksey	0:fb7af294d5d9	1918	__DSB(); /* Ensure all outstanding memory accesses included
Simon Cooksey	0:fb7af294d5d9	1919	buffered write are completed before reset */
Simon Cooksey	0:fb7af294d5d9	1920	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Simon Cooksey	0:fb7af294d5d9	1921	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
Simon Cooksey	0:fb7af294d5d9	1922	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Simon Cooksey	0:fb7af294d5d9	1923	__DSB(); /* Ensure completion of memory access */
Simon Cooksey	0:fb7af294d5d9	1924	while(1) { __NOP(); } /* wait until reset */
Simon Cooksey	0:fb7af294d5d9	1925	}
Simon Cooksey	0:fb7af294d5d9	1926
Simon Cooksey	0:fb7af294d5d9	1927	/@} end of CMSIS_Core_NVICFunctions /
Simon Cooksey	0:fb7af294d5d9	1928
Simon Cooksey	0:fb7af294d5d9	1929
Simon Cooksey	0:fb7af294d5d9	1930	/* ########################## FPU functions #################################### */
Simon Cooksey	0:fb7af294d5d9	1931	/** \ingroup CMSIS_Core_FunctionInterface
Simon Cooksey	0:fb7af294d5d9	1932	\defgroup CMSIS_Core_FpuFunctions FPU Functions
Simon Cooksey	0:fb7af294d5d9	1933	\brief Function that provides FPU type.
Simon Cooksey	0:fb7af294d5d9	1934	@{
Simon Cooksey	0:fb7af294d5d9	1935	*/
Simon Cooksey	0:fb7af294d5d9	1936
Simon Cooksey	0:fb7af294d5d9	1937	/**
Simon Cooksey	0:fb7af294d5d9	1938	\fn uint32_t SCB_GetFPUType(void)
Simon Cooksey	0:fb7af294d5d9	1939	\brief get FPU type
Simon Cooksey	0:fb7af294d5d9	1940	\returns
Simon Cooksey	0:fb7af294d5d9	1941	- \b 0: No FPU
Simon Cooksey	0:fb7af294d5d9	1942	- \b 1: Single precision FPU
Simon Cooksey	0:fb7af294d5d9	1943	- \b 2: Double + Single precision FPU
Simon Cooksey	0:fb7af294d5d9	1944	*/
Simon Cooksey	0:fb7af294d5d9	1945	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
Simon Cooksey	0:fb7af294d5d9	1946	{
Simon Cooksey	0:fb7af294d5d9	1947	uint32_t mvfr0;
Simon Cooksey	0:fb7af294d5d9	1948
Simon Cooksey	0:fb7af294d5d9	1949	mvfr0 = SCB->MVFR0;
Simon Cooksey	0:fb7af294d5d9	1950	if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
Simon Cooksey	0:fb7af294d5d9	1951	return 2UL; // Double + Single precision FPU
Simon Cooksey	0:fb7af294d5d9	1952	} else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
Simon Cooksey	0:fb7af294d5d9	1953	return 1UL; // Single precision FPU
Simon Cooksey	0:fb7af294d5d9	1954	} else {
Simon Cooksey	0:fb7af294d5d9	1955	return 0UL; // No FPU
Simon Cooksey	0:fb7af294d5d9	1956	}
Simon Cooksey	0:fb7af294d5d9	1957	}
Simon Cooksey	0:fb7af294d5d9	1958
Simon Cooksey	0:fb7af294d5d9	1959
Simon Cooksey	0:fb7af294d5d9	1960	/@} end of CMSIS_Core_FpuFunctions /
Simon Cooksey	0:fb7af294d5d9	1961
Simon Cooksey	0:fb7af294d5d9	1962
Simon Cooksey	0:fb7af294d5d9	1963
Simon Cooksey	0:fb7af294d5d9	1964	/* ########################## Cache functions #################################### */
Simon Cooksey	0:fb7af294d5d9	1965	/** \ingroup CMSIS_Core_FunctionInterface
Simon Cooksey	0:fb7af294d5d9	1966	\defgroup CMSIS_Core_CacheFunctions Cache Functions
Simon Cooksey	0:fb7af294d5d9	1967	\brief Functions that configure Instruction and Data cache.
Simon Cooksey	0:fb7af294d5d9	1968	@{
Simon Cooksey	0:fb7af294d5d9	1969	*/
Simon Cooksey	0:fb7af294d5d9	1970
Simon Cooksey	0:fb7af294d5d9	1971	/* Cache Size ID Register Macros */
Simon Cooksey	0:fb7af294d5d9	1972	#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
Simon Cooksey	0:fb7af294d5d9	1973	#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
Simon Cooksey	0:fb7af294d5d9	1974	#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) />> SCB_CCSIDR_LINESIZE_Pos/ )
Simon Cooksey	0:fb7af294d5d9	1975
Simon Cooksey	0:fb7af294d5d9	1976
Simon Cooksey	0:fb7af294d5d9	1977	/** \brief Enable I-Cache
Simon Cooksey	0:fb7af294d5d9	1978
Simon Cooksey	0:fb7af294d5d9	1979	The function turns on I-Cache
Simon Cooksey	0:fb7af294d5d9	1980	*/
Simon Cooksey	0:fb7af294d5d9	1981	__STATIC_INLINE void SCB_EnableICache (void)
Simon Cooksey	0:fb7af294d5d9	1982	{
Simon Cooksey	0:fb7af294d5d9	1983	#if (__ICACHE_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	1984	__DSB();
Simon Cooksey	0:fb7af294d5d9	1985	__ISB();
Simon Cooksey	0:fb7af294d5d9	1986	SCB->ICIALLU = 0UL; // invalidate I-Cache
Simon Cooksey	0:fb7af294d5d9	1987	SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
Simon Cooksey	0:fb7af294d5d9	1988	__DSB();
Simon Cooksey	0:fb7af294d5d9	1989	__ISB();
Simon Cooksey	0:fb7af294d5d9	1990	#endif
Simon Cooksey	0:fb7af294d5d9	1991	}
Simon Cooksey	0:fb7af294d5d9	1992
Simon Cooksey	0:fb7af294d5d9	1993
Simon Cooksey	0:fb7af294d5d9	1994	/** \brief Disable I-Cache
Simon Cooksey	0:fb7af294d5d9	1995
Simon Cooksey	0:fb7af294d5d9	1996	The function turns off I-Cache
Simon Cooksey	0:fb7af294d5d9	1997	*/
Simon Cooksey	0:fb7af294d5d9	1998	__STATIC_INLINE void SCB_DisableICache (void)
Simon Cooksey	0:fb7af294d5d9	1999	{
Simon Cooksey	0:fb7af294d5d9	2000	#if (__ICACHE_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	2001	__DSB();
Simon Cooksey	0:fb7af294d5d9	2002	__ISB();
Simon Cooksey	0:fb7af294d5d9	2003	SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
Simon Cooksey	0:fb7af294d5d9	2004	SCB->ICIALLU = 0UL; // invalidate I-Cache
Simon Cooksey	0:fb7af294d5d9	2005	__DSB();
Simon Cooksey	0:fb7af294d5d9	2006	__ISB();
Simon Cooksey	0:fb7af294d5d9	2007	#endif
Simon Cooksey	0:fb7af294d5d9	2008	}
Simon Cooksey	0:fb7af294d5d9	2009
Simon Cooksey	0:fb7af294d5d9	2010
Simon Cooksey	0:fb7af294d5d9	2011	/** \brief Invalidate I-Cache
Simon Cooksey	0:fb7af294d5d9	2012
Simon Cooksey	0:fb7af294d5d9	2013	The function invalidates I-Cache
Simon Cooksey	0:fb7af294d5d9	2014	*/
Simon Cooksey	0:fb7af294d5d9	2015	__STATIC_INLINE void SCB_InvalidateICache (void)
Simon Cooksey	0:fb7af294d5d9	2016	{
Simon Cooksey	0:fb7af294d5d9	2017	#if (__ICACHE_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	2018	__DSB();
Simon Cooksey	0:fb7af294d5d9	2019	__ISB();
Simon Cooksey	0:fb7af294d5d9	2020	SCB->ICIALLU = 0UL;
Simon Cooksey	0:fb7af294d5d9	2021	__DSB();
Simon Cooksey	0:fb7af294d5d9	2022	__ISB();
Simon Cooksey	0:fb7af294d5d9	2023	#endif
Simon Cooksey	0:fb7af294d5d9	2024	}
Simon Cooksey	0:fb7af294d5d9	2025
Simon Cooksey	0:fb7af294d5d9	2026
Simon Cooksey	0:fb7af294d5d9	2027	/** \brief Enable D-Cache
Simon Cooksey	0:fb7af294d5d9	2028
Simon Cooksey	0:fb7af294d5d9	2029	The function turns on D-Cache
Simon Cooksey	0:fb7af294d5d9	2030	*/
Simon Cooksey	0:fb7af294d5d9	2031	__STATIC_INLINE void SCB_EnableDCache (void)
Simon Cooksey	0:fb7af294d5d9	2032	{
Simon Cooksey	0:fb7af294d5d9	2033	#if (__DCACHE_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	2034	uint32_t ccsidr, sshift, wshift, sw;
Simon Cooksey	0:fb7af294d5d9	2035	uint32_t sets, ways;
Simon Cooksey	0:fb7af294d5d9	2036
Simon Cooksey	0:fb7af294d5d9	2037	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
Simon Cooksey	0:fb7af294d5d9	2038	ccsidr = SCB->CCSIDR;
Simon Cooksey	0:fb7af294d5d9	2039	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Simon Cooksey	0:fb7af294d5d9	2040	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Simon Cooksey	0:fb7af294d5d9	2041	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Simon Cooksey	0:fb7af294d5d9	2042	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Simon Cooksey	0:fb7af294d5d9	2043
Simon Cooksey	0:fb7af294d5d9	2044	__DSB();
Simon Cooksey	0:fb7af294d5d9	2045
Simon Cooksey	0:fb7af294d5d9	2046	do { // invalidate D-Cache
Simon Cooksey	0:fb7af294d5d9	2047	uint32_t tmpways = ways;
Simon Cooksey	0:fb7af294d5d9	2048	do {
Simon Cooksey	0:fb7af294d5d9	2049	sw = ((tmpways << wshift) \| (sets << sshift));
Simon Cooksey	0:fb7af294d5d9	2050	SCB->DCISW = sw;
Simon Cooksey	0:fb7af294d5d9	2051	} while(tmpways--);
Simon Cooksey	0:fb7af294d5d9	2052	} while(sets--);
Simon Cooksey	0:fb7af294d5d9	2053	__DSB();
Simon Cooksey	0:fb7af294d5d9	2054
Simon Cooksey	0:fb7af294d5d9	2055	SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
Simon Cooksey	0:fb7af294d5d9	2056
Simon Cooksey	0:fb7af294d5d9	2057	__DSB();
Simon Cooksey	0:fb7af294d5d9	2058	__ISB();
Simon Cooksey	0:fb7af294d5d9	2059	#endif
Simon Cooksey	0:fb7af294d5d9	2060	}
Simon Cooksey	0:fb7af294d5d9	2061
Simon Cooksey	0:fb7af294d5d9	2062
Simon Cooksey	0:fb7af294d5d9	2063	/** \brief Disable D-Cache
Simon Cooksey	0:fb7af294d5d9	2064
Simon Cooksey	0:fb7af294d5d9	2065	The function turns off D-Cache
Simon Cooksey	0:fb7af294d5d9	2066	*/
Simon Cooksey	0:fb7af294d5d9	2067	__STATIC_INLINE void SCB_DisableDCache (void)
Simon Cooksey	0:fb7af294d5d9	2068	{
Simon Cooksey	0:fb7af294d5d9	2069	#if (__DCACHE_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	2070	uint32_t ccsidr, sshift, wshift, sw;
Simon Cooksey	0:fb7af294d5d9	2071	uint32_t sets, ways;
Simon Cooksey	0:fb7af294d5d9	2072
Simon Cooksey	0:fb7af294d5d9	2073	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
Simon Cooksey	0:fb7af294d5d9	2074	ccsidr = SCB->CCSIDR;
Simon Cooksey	0:fb7af294d5d9	2075	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Simon Cooksey	0:fb7af294d5d9	2076	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Simon Cooksey	0:fb7af294d5d9	2077	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Simon Cooksey	0:fb7af294d5d9	2078	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Simon Cooksey	0:fb7af294d5d9	2079
Simon Cooksey	0:fb7af294d5d9	2080	__DSB();
Simon Cooksey	0:fb7af294d5d9	2081
Simon Cooksey	0:fb7af294d5d9	2082	SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
Simon Cooksey	0:fb7af294d5d9	2083
Simon Cooksey	0:fb7af294d5d9	2084	do { // clean & invalidate D-Cache
Simon Cooksey	0:fb7af294d5d9	2085	uint32_t tmpways = ways;
Simon Cooksey	0:fb7af294d5d9	2086	do {
Simon Cooksey	0:fb7af294d5d9	2087	sw = ((tmpways << wshift) \| (sets << sshift));
Simon Cooksey	0:fb7af294d5d9	2088	SCB->DCCISW = sw;
Simon Cooksey	0:fb7af294d5d9	2089	} while(tmpways--);
Simon Cooksey	0:fb7af294d5d9	2090	} while(sets--);
Simon Cooksey	0:fb7af294d5d9	2091
Simon Cooksey	0:fb7af294d5d9	2092
Simon Cooksey	0:fb7af294d5d9	2093	__DSB();
Simon Cooksey	0:fb7af294d5d9	2094	__ISB();
Simon Cooksey	0:fb7af294d5d9	2095	#endif
Simon Cooksey	0:fb7af294d5d9	2096	}
Simon Cooksey	0:fb7af294d5d9	2097
Simon Cooksey	0:fb7af294d5d9	2098
Simon Cooksey	0:fb7af294d5d9	2099	/** \brief Invalidate D-Cache
Simon Cooksey	0:fb7af294d5d9	2100
Simon Cooksey	0:fb7af294d5d9	2101	The function invalidates D-Cache
Simon Cooksey	0:fb7af294d5d9	2102	*/
Simon Cooksey	0:fb7af294d5d9	2103	__STATIC_INLINE void SCB_InvalidateDCache (void)
Simon Cooksey	0:fb7af294d5d9	2104	{
Simon Cooksey	0:fb7af294d5d9	2105	#if (__DCACHE_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	2106	uint32_t ccsidr, sshift, wshift, sw;
Simon Cooksey	0:fb7af294d5d9	2107	uint32_t sets, ways;
Simon Cooksey	0:fb7af294d5d9	2108
Simon Cooksey	0:fb7af294d5d9	2109	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
Simon Cooksey	0:fb7af294d5d9	2110	ccsidr = SCB->CCSIDR;
Simon Cooksey	0:fb7af294d5d9	2111	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Simon Cooksey	0:fb7af294d5d9	2112	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Simon Cooksey	0:fb7af294d5d9	2113	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Simon Cooksey	0:fb7af294d5d9	2114	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Simon Cooksey	0:fb7af294d5d9	2115
Simon Cooksey	0:fb7af294d5d9	2116	__DSB();
Simon Cooksey	0:fb7af294d5d9	2117
Simon Cooksey	0:fb7af294d5d9	2118	do { // invalidate D-Cache
Simon Cooksey	0:fb7af294d5d9	2119	uint32_t tmpways = ways;
Simon Cooksey	0:fb7af294d5d9	2120	do {
Simon Cooksey	0:fb7af294d5d9	2121	sw = ((tmpways << wshift) \| (sets << sshift));
Simon Cooksey	0:fb7af294d5d9	2122	SCB->DCISW = sw;
Simon Cooksey	0:fb7af294d5d9	2123	} while(tmpways--);
Simon Cooksey	0:fb7af294d5d9	2124	} while(sets--);
Simon Cooksey	0:fb7af294d5d9	2125
Simon Cooksey	0:fb7af294d5d9	2126	__DSB();
Simon Cooksey	0:fb7af294d5d9	2127	__ISB();
Simon Cooksey	0:fb7af294d5d9	2128	#endif
Simon Cooksey	0:fb7af294d5d9	2129	}
Simon Cooksey	0:fb7af294d5d9	2130
Simon Cooksey	0:fb7af294d5d9	2131
Simon Cooksey	0:fb7af294d5d9	2132	/** \brief Clean D-Cache
Simon Cooksey	0:fb7af294d5d9	2133
Simon Cooksey	0:fb7af294d5d9	2134	The function cleans D-Cache
Simon Cooksey	0:fb7af294d5d9	2135	*/
Simon Cooksey	0:fb7af294d5d9	2136	__STATIC_INLINE void SCB_CleanDCache (void)
Simon Cooksey	0:fb7af294d5d9	2137	{
Simon Cooksey	0:fb7af294d5d9	2138	#if (__DCACHE_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	2139	uint32_t ccsidr, sshift, wshift, sw;
Simon Cooksey	0:fb7af294d5d9	2140	uint32_t sets, ways;
Simon Cooksey	0:fb7af294d5d9	2141
Simon Cooksey	0:fb7af294d5d9	2142	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
Simon Cooksey	0:fb7af294d5d9	2143	ccsidr = SCB->CCSIDR;
Simon Cooksey	0:fb7af294d5d9	2144	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Simon Cooksey	0:fb7af294d5d9	2145	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Simon Cooksey	0:fb7af294d5d9	2146	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Simon Cooksey	0:fb7af294d5d9	2147	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Simon Cooksey	0:fb7af294d5d9	2148
Simon Cooksey	0:fb7af294d5d9	2149	__DSB();
Simon Cooksey	0:fb7af294d5d9	2150
Simon Cooksey	0:fb7af294d5d9	2151	do { // clean D-Cache
Simon Cooksey	0:fb7af294d5d9	2152	uint32_t tmpways = ways;
Simon Cooksey	0:fb7af294d5d9	2153	do {
Simon Cooksey	0:fb7af294d5d9	2154	sw = ((tmpways << wshift) \| (sets << sshift));
Simon Cooksey	0:fb7af294d5d9	2155	SCB->DCCSW = sw;
Simon Cooksey	0:fb7af294d5d9	2156	} while(tmpways--);
Simon Cooksey	0:fb7af294d5d9	2157	} while(sets--);
Simon Cooksey	0:fb7af294d5d9	2158
Simon Cooksey	0:fb7af294d5d9	2159	__DSB();
Simon Cooksey	0:fb7af294d5d9	2160	__ISB();
Simon Cooksey	0:fb7af294d5d9	2161	#endif
Simon Cooksey	0:fb7af294d5d9	2162	}
Simon Cooksey	0:fb7af294d5d9	2163
Simon Cooksey	0:fb7af294d5d9	2164
Simon Cooksey	0:fb7af294d5d9	2165	/** \brief Clean & Invalidate D-Cache
Simon Cooksey	0:fb7af294d5d9	2166
Simon Cooksey	0:fb7af294d5d9	2167	The function cleans and Invalidates D-Cache
Simon Cooksey	0:fb7af294d5d9	2168	*/
Simon Cooksey	0:fb7af294d5d9	2169	__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
Simon Cooksey	0:fb7af294d5d9	2170	{
Simon Cooksey	0:fb7af294d5d9	2171	#if (__DCACHE_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	2172	uint32_t ccsidr, sshift, wshift, sw;
Simon Cooksey	0:fb7af294d5d9	2173	uint32_t sets, ways;
Simon Cooksey	0:fb7af294d5d9	2174
Simon Cooksey	0:fb7af294d5d9	2175	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
Simon Cooksey	0:fb7af294d5d9	2176	ccsidr = SCB->CCSIDR;
Simon Cooksey	0:fb7af294d5d9	2177	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Simon Cooksey	0:fb7af294d5d9	2178	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Simon Cooksey	0:fb7af294d5d9	2179	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Simon Cooksey	0:fb7af294d5d9	2180	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Simon Cooksey	0:fb7af294d5d9	2181
Simon Cooksey	0:fb7af294d5d9	2182	__DSB();
Simon Cooksey	0:fb7af294d5d9	2183
Simon Cooksey	0:fb7af294d5d9	2184	do { // clean & invalidate D-Cache
Simon Cooksey	0:fb7af294d5d9	2185	uint32_t tmpways = ways;
Simon Cooksey	0:fb7af294d5d9	2186	do {
Simon Cooksey	0:fb7af294d5d9	2187	sw = ((tmpways << wshift) \| (sets << sshift));
Simon Cooksey	0:fb7af294d5d9	2188	SCB->DCCISW = sw;
Simon Cooksey	0:fb7af294d5d9	2189	} while(tmpways--);
Simon Cooksey	0:fb7af294d5d9	2190	} while(sets--);
Simon Cooksey	0:fb7af294d5d9	2191
Simon Cooksey	0:fb7af294d5d9	2192	__DSB();
Simon Cooksey	0:fb7af294d5d9	2193	__ISB();
Simon Cooksey	0:fb7af294d5d9	2194	#endif
Simon Cooksey	0:fb7af294d5d9	2195	}
Simon Cooksey	0:fb7af294d5d9	2196
Simon Cooksey	0:fb7af294d5d9	2197
Simon Cooksey	0:fb7af294d5d9	2198	/**
Simon Cooksey	0:fb7af294d5d9	2199	\fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Simon Cooksey	0:fb7af294d5d9	2200	\brief D-Cache Invalidate by address
Simon Cooksey	0:fb7af294d5d9	2201	\param[in] addr address (aligned to 32-byte boundary)
Simon Cooksey	0:fb7af294d5d9	2202	\param[in] dsize size of memory block (in number of bytes)
Simon Cooksey	0:fb7af294d5d9	2203	*/
Simon Cooksey	0:fb7af294d5d9	2204	__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
Simon Cooksey	0:fb7af294d5d9	2205	{
Simon Cooksey	0:fb7af294d5d9	2206	#if (__DCACHE_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	2207	int32_t op_size = dsize;
Simon Cooksey	0:fb7af294d5d9	2208	uint32_t op_addr = (uint32_t)addr;
Simon Cooksey	0:fb7af294d5d9	2209	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Simon Cooksey	0:fb7af294d5d9	2210
Simon Cooksey	0:fb7af294d5d9	2211	__DSB();
Simon Cooksey	0:fb7af294d5d9	2212
Simon Cooksey	0:fb7af294d5d9	2213	while (op_size > 0) {
Simon Cooksey	0:fb7af294d5d9	2214	SCB->DCIMVAC = op_addr;
Simon Cooksey	0:fb7af294d5d9	2215	op_addr += linesize;
Simon Cooksey	0:fb7af294d5d9	2216	op_size -= (int32_t)linesize;
Simon Cooksey	0:fb7af294d5d9	2217	}
Simon Cooksey	0:fb7af294d5d9	2218
Simon Cooksey	0:fb7af294d5d9	2219	__DSB();
Simon Cooksey	0:fb7af294d5d9	2220	__ISB();
Simon Cooksey	0:fb7af294d5d9	2221	#endif
Simon Cooksey	0:fb7af294d5d9	2222	}
Simon Cooksey	0:fb7af294d5d9	2223
Simon Cooksey	0:fb7af294d5d9	2224
Simon Cooksey	0:fb7af294d5d9	2225	/**
Simon Cooksey	0:fb7af294d5d9	2226	\fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Simon Cooksey	0:fb7af294d5d9	2227	\brief D-Cache Clean by address
Simon Cooksey	0:fb7af294d5d9	2228	\param[in] addr address (aligned to 32-byte boundary)
Simon Cooksey	0:fb7af294d5d9	2229	\param[in] dsize size of memory block (in number of bytes)
Simon Cooksey	0:fb7af294d5d9	2230	*/
Simon Cooksey	0:fb7af294d5d9	2231	__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
Simon Cooksey	0:fb7af294d5d9	2232	{
Simon Cooksey	0:fb7af294d5d9	2233	#if (__DCACHE_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	2234	int32_t op_size = dsize;
Simon Cooksey	0:fb7af294d5d9	2235	uint32_t op_addr = (uint32_t) addr;
Simon Cooksey	0:fb7af294d5d9	2236	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Simon Cooksey	0:fb7af294d5d9	2237
Simon Cooksey	0:fb7af294d5d9	2238	__DSB();
Simon Cooksey	0:fb7af294d5d9	2239
Simon Cooksey	0:fb7af294d5d9	2240	while (op_size > 0) {
Simon Cooksey	0:fb7af294d5d9	2241	SCB->DCCMVAC = op_addr;
Simon Cooksey	0:fb7af294d5d9	2242	op_addr += linesize;
Simon Cooksey	0:fb7af294d5d9	2243	op_size -= (int32_t)linesize;
Simon Cooksey	0:fb7af294d5d9	2244	}
Simon Cooksey	0:fb7af294d5d9	2245
Simon Cooksey	0:fb7af294d5d9	2246	__DSB();
Simon Cooksey	0:fb7af294d5d9	2247	__ISB();
Simon Cooksey	0:fb7af294d5d9	2248	#endif
Simon Cooksey	0:fb7af294d5d9	2249	}
Simon Cooksey	0:fb7af294d5d9	2250
Simon Cooksey	0:fb7af294d5d9	2251
Simon Cooksey	0:fb7af294d5d9	2252	/**
Simon Cooksey	0:fb7af294d5d9	2253	\fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Simon Cooksey	0:fb7af294d5d9	2254	\brief D-Cache Clean and Invalidate by address
Simon Cooksey	0:fb7af294d5d9	2255	\param[in] addr address (aligned to 32-byte boundary)
Simon Cooksey	0:fb7af294d5d9	2256	\param[in] dsize size of memory block (in number of bytes)
Simon Cooksey	0:fb7af294d5d9	2257	*/
Simon Cooksey	0:fb7af294d5d9	2258	__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
Simon Cooksey	0:fb7af294d5d9	2259	{
Simon Cooksey	0:fb7af294d5d9	2260	#if (__DCACHE_PRESENT == 1)
Simon Cooksey	0:fb7af294d5d9	2261	int32_t op_size = dsize;
Simon Cooksey	0:fb7af294d5d9	2262	uint32_t op_addr = (uint32_t) addr;
Simon Cooksey	0:fb7af294d5d9	2263	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Simon Cooksey	0:fb7af294d5d9	2264
Simon Cooksey	0:fb7af294d5d9	2265	__DSB();
Simon Cooksey	0:fb7af294d5d9	2266
Simon Cooksey	0:fb7af294d5d9	2267	while (op_size > 0) {
Simon Cooksey	0:fb7af294d5d9	2268	SCB->DCCIMVAC = op_addr;
Simon Cooksey	0:fb7af294d5d9	2269	op_addr += linesize;
Simon Cooksey	0:fb7af294d5d9	2270	op_size -= (int32_t)linesize;
Simon Cooksey	0:fb7af294d5d9	2271	}
Simon Cooksey	0:fb7af294d5d9	2272
Simon Cooksey	0:fb7af294d5d9	2273	__DSB();
Simon Cooksey	0:fb7af294d5d9	2274	__ISB();
Simon Cooksey	0:fb7af294d5d9	2275	#endif
Simon Cooksey	0:fb7af294d5d9	2276	}
Simon Cooksey	0:fb7af294d5d9	2277
Simon Cooksey	0:fb7af294d5d9	2278
Simon Cooksey	0:fb7af294d5d9	2279	/@} end of CMSIS_Core_CacheFunctions /
Simon Cooksey	0:fb7af294d5d9	2280
Simon Cooksey	0:fb7af294d5d9	2281
Simon Cooksey	0:fb7af294d5d9	2282
Simon Cooksey	0:fb7af294d5d9	2283	/* ################################## SysTick function ############################################ */
Simon Cooksey	0:fb7af294d5d9	2284	/** \ingroup CMSIS_Core_FunctionInterface
Simon Cooksey	0:fb7af294d5d9	2285	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Simon Cooksey	0:fb7af294d5d9	2286	\brief Functions that configure the System.
Simon Cooksey	0:fb7af294d5d9	2287	@{
Simon Cooksey	0:fb7af294d5d9	2288	*/
Simon Cooksey	0:fb7af294d5d9	2289
Simon Cooksey	0:fb7af294d5d9	2290	#if (__Vendor_SysTickConfig == 0)
Simon Cooksey	0:fb7af294d5d9	2291
Simon Cooksey	0:fb7af294d5d9	2292	/** \brief System Tick Configuration
Simon Cooksey	0:fb7af294d5d9	2293
Simon Cooksey	0:fb7af294d5d9	2294	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Simon Cooksey	0:fb7af294d5d9	2295	Counter is in free running mode to generate periodic interrupts.
Simon Cooksey	0:fb7af294d5d9	2296
Simon Cooksey	0:fb7af294d5d9	2297	\param [in] ticks Number of ticks between two interrupts.
Simon Cooksey	0:fb7af294d5d9	2298
Simon Cooksey	0:fb7af294d5d9	2299	\return 0 Function succeeded.
Simon Cooksey	0:fb7af294d5d9	2300	\return 1 Function failed.
Simon Cooksey	0:fb7af294d5d9	2301
Simon Cooksey	0:fb7af294d5d9	2302	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Simon Cooksey	0:fb7af294d5d9	2303	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Simon Cooksey	0:fb7af294d5d9	2304	must contain a vendor-specific implementation of this function.
Simon Cooksey	0:fb7af294d5d9	2305
Simon Cooksey	0:fb7af294d5d9	2306	*/
Simon Cooksey	0:fb7af294d5d9	2307	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Simon Cooksey	0:fb7af294d5d9	2308	{
Simon Cooksey	0:fb7af294d5d9	2309	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Simon Cooksey	0:fb7af294d5d9	2310
Simon Cooksey	0:fb7af294d5d9	2311	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Simon Cooksey	0:fb7af294d5d9	2312	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Simon Cooksey	0:fb7af294d5d9	2313	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Simon Cooksey	0:fb7af294d5d9	2314	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Simon Cooksey	0:fb7af294d5d9	2315	SysTick_CTRL_TICKINT_Msk \|
Simon Cooksey	0:fb7af294d5d9	2316	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Simon Cooksey	0:fb7af294d5d9	2317	return (0UL); /* Function successful */
Simon Cooksey	0:fb7af294d5d9	2318	}
Simon Cooksey	0:fb7af294d5d9	2319
Simon Cooksey	0:fb7af294d5d9	2320	#endif
Simon Cooksey	0:fb7af294d5d9	2321
Simon Cooksey	0:fb7af294d5d9	2322	/@} end of CMSIS_Core_SysTickFunctions /
Simon Cooksey	0:fb7af294d5d9	2323
Simon Cooksey	0:fb7af294d5d9	2324
Simon Cooksey	0:fb7af294d5d9	2325
Simon Cooksey	0:fb7af294d5d9	2326	/* ##################################### Debug In/Output function ########################################### */
Simon Cooksey	0:fb7af294d5d9	2327	/** \ingroup CMSIS_Core_FunctionInterface
Simon Cooksey	0:fb7af294d5d9	2328	\defgroup CMSIS_core_DebugFunctions ITM Functions
Simon Cooksey	0:fb7af294d5d9	2329	\brief Functions that access the ITM debug interface.
Simon Cooksey	0:fb7af294d5d9	2330	@{
Simon Cooksey	0:fb7af294d5d9	2331	*/
Simon Cooksey	0:fb7af294d5d9	2332
Simon Cooksey	0:fb7af294d5d9	2333	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
Simon Cooksey	0:fb7af294d5d9	2334	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
Simon Cooksey	0:fb7af294d5d9	2335
Simon Cooksey	0:fb7af294d5d9	2336
Simon Cooksey	0:fb7af294d5d9	2337	/** \brief ITM Send Character
Simon Cooksey	0:fb7af294d5d9	2338
Simon Cooksey	0:fb7af294d5d9	2339	The function transmits a character via the ITM channel 0, and
Simon Cooksey	0:fb7af294d5d9	2340	\li Just returns when no debugger is connected that has booked the output.
Simon Cooksey	0:fb7af294d5d9	2341	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Simon Cooksey	0:fb7af294d5d9	2342
Simon Cooksey	0:fb7af294d5d9	2343	\param [in] ch Character to transmit.
Simon Cooksey	0:fb7af294d5d9	2344
Simon Cooksey	0:fb7af294d5d9	2345	\returns Character to transmit.
Simon Cooksey	0:fb7af294d5d9	2346	*/
Simon Cooksey	0:fb7af294d5d9	2347	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Simon Cooksey	0:fb7af294d5d9	2348	{
Simon Cooksey	0:fb7af294d5d9	2349	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Simon Cooksey	0:fb7af294d5d9	2350	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Simon Cooksey	0:fb7af294d5d9	2351	{
Simon Cooksey	0:fb7af294d5d9	2352	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Simon Cooksey	0:fb7af294d5d9	2353	ITM->PORT[0].u8 = (uint8_t)ch;
Simon Cooksey	0:fb7af294d5d9	2354	}
Simon Cooksey	0:fb7af294d5d9	2355	return (ch);
Simon Cooksey	0:fb7af294d5d9	2356	}
Simon Cooksey	0:fb7af294d5d9	2357
Simon Cooksey	0:fb7af294d5d9	2358
Simon Cooksey	0:fb7af294d5d9	2359	/** \brief ITM Receive Character
Simon Cooksey	0:fb7af294d5d9	2360
Simon Cooksey	0:fb7af294d5d9	2361	The function inputs a character via the external variable \ref ITM_RxBuffer.
Simon Cooksey	0:fb7af294d5d9	2362
Simon Cooksey	0:fb7af294d5d9	2363	\return Received character.
Simon Cooksey	0:fb7af294d5d9	2364	\return -1 No character pending.
Simon Cooksey	0:fb7af294d5d9	2365	*/
Simon Cooksey	0:fb7af294d5d9	2366	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Simon Cooksey	0:fb7af294d5d9	2367	int32_t ch = -1; /* no character available */
Simon Cooksey	0:fb7af294d5d9	2368
Simon Cooksey	0:fb7af294d5d9	2369	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Simon Cooksey	0:fb7af294d5d9	2370	ch = ITM_RxBuffer;
Simon Cooksey	0:fb7af294d5d9	2371	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Simon Cooksey	0:fb7af294d5d9	2372	}
Simon Cooksey	0:fb7af294d5d9	2373
Simon Cooksey	0:fb7af294d5d9	2374	return (ch);
Simon Cooksey	0:fb7af294d5d9	2375	}
Simon Cooksey	0:fb7af294d5d9	2376
Simon Cooksey	0:fb7af294d5d9	2377
Simon Cooksey	0:fb7af294d5d9	2378	/** \brief ITM Check Character
Simon Cooksey	0:fb7af294d5d9	2379
Simon Cooksey	0:fb7af294d5d9	2380	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Simon Cooksey	0:fb7af294d5d9	2381
Simon Cooksey	0:fb7af294d5d9	2382	\return 0 No character available.
Simon Cooksey	0:fb7af294d5d9	2383	\return 1 Character available.
Simon Cooksey	0:fb7af294d5d9	2384	*/
Simon Cooksey	0:fb7af294d5d9	2385	__STATIC_INLINE int32_t ITM_CheckChar (void) {
Simon Cooksey	0:fb7af294d5d9	2386
Simon Cooksey	0:fb7af294d5d9	2387	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Simon Cooksey	0:fb7af294d5d9	2388	return (0); /* no character available */
Simon Cooksey	0:fb7af294d5d9	2389	} else {
Simon Cooksey	0:fb7af294d5d9	2390	return (1); /* character available */
Simon Cooksey	0:fb7af294d5d9	2391	}
Simon Cooksey	0:fb7af294d5d9	2392	}
Simon Cooksey	0:fb7af294d5d9	2393
Simon Cooksey	0:fb7af294d5d9	2394	/@} end of CMSIS_core_DebugFunctions /
Simon Cooksey	0:fb7af294d5d9	2395
Simon Cooksey	0:fb7af294d5d9	2396
Simon Cooksey	0:fb7af294d5d9	2397
Simon Cooksey	0:fb7af294d5d9	2398
Simon Cooksey	0:fb7af294d5d9	2399	#ifdef __cplusplus
Simon Cooksey	0:fb7af294d5d9	2400	}
Simon Cooksey	0:fb7af294d5d9	2401	#endif
Simon Cooksey	0:fb7af294d5d9	2402
Simon Cooksey	0:fb7af294d5d9	2403	#endif /* __CORE_CM7_H_DEPENDANT */
Simon Cooksey	0:fb7af294d5d9	2404
Simon Cooksey	0:fb7af294d5d9	2405	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	17 Nov 2016
Imports:	992
Forks:	0
Commits:	1
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cmsis/core_cm7.h@0:fb7af294d5d9, 2016-11-17 (annotated)

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