Simon Cooksey / mbed-os

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cmsis/core_cm4.h@0:fb7af294d5d9, 2016-11-17 (annotated)

Committer:
Simon Cooksey
Date:
Thu Nov 17 16:43:53 2016 +0000
Revision:
0:fb7af294d5d9
Initial commit

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Simon Cooksey 0:fb7af294d5d9 1 /**************************************************************************//**
Simon Cooksey 0:fb7af294d5d9 2 * @file core_cm4.h
Simon Cooksey 0:fb7af294d5d9 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
Simon Cooksey 0:fb7af294d5d9 4 * @version V4.10
Simon Cooksey 0:fb7af294d5d9 5 * @date 18. March 2015
Simon Cooksey 0:fb7af294d5d9 6 *
Simon Cooksey 0:fb7af294d5d9 7 * @note
Simon Cooksey 0:fb7af294d5d9 8 *
Simon Cooksey 0:fb7af294d5d9 9 ******************************************************************************/
Simon Cooksey 0:fb7af294d5d9 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Simon Cooksey 0:fb7af294d5d9 11
Simon Cooksey 0:fb7af294d5d9 12 All rights reserved.
Simon Cooksey 0:fb7af294d5d9 13 Redistribution and use in source and binary forms, with or without
Simon Cooksey 0:fb7af294d5d9 14 modification, are permitted provided that the following conditions are met:
Simon Cooksey 0:fb7af294d5d9 15 - Redistributions of source code must retain the above copyright
Simon Cooksey 0:fb7af294d5d9 16 notice, this list of conditions and the following disclaimer.
Simon Cooksey 0:fb7af294d5d9 17 - Redistributions in binary form must reproduce the above copyright
Simon Cooksey 0:fb7af294d5d9 18 notice, this list of conditions and the following disclaimer in the
Simon Cooksey 0:fb7af294d5d9 19 documentation and/or other materials provided with the distribution.
Simon Cooksey 0:fb7af294d5d9 20 - Neither the name of ARM nor the names of its contributors may be used
Simon Cooksey 0:fb7af294d5d9 21 to endorse or promote products derived from this software without
Simon Cooksey 0:fb7af294d5d9 22 specific prior written permission.
Simon Cooksey 0:fb7af294d5d9 23 *
Simon Cooksey 0:fb7af294d5d9 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Simon Cooksey 0:fb7af294d5d9 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Simon Cooksey 0:fb7af294d5d9 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Simon Cooksey 0:fb7af294d5d9 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Simon Cooksey 0:fb7af294d5d9 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Simon Cooksey 0:fb7af294d5d9 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Simon Cooksey 0:fb7af294d5d9 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Simon Cooksey 0:fb7af294d5d9 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Simon Cooksey 0:fb7af294d5d9 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Simon Cooksey 0:fb7af294d5d9 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Simon Cooksey 0:fb7af294d5d9 34 POSSIBILITY OF SUCH DAMAGE.
Simon Cooksey 0:fb7af294d5d9 35 ---------------------------------------------------------------------------*/
Simon Cooksey 0:fb7af294d5d9 36
Simon Cooksey 0:fb7af294d5d9 37
Simon Cooksey 0:fb7af294d5d9 38 #if defined ( __ICCARM__ )
Simon Cooksey 0:fb7af294d5d9 39 #pragma system_include /* treat file as system include file for MISRA check */
Simon Cooksey 0:fb7af294d5d9 40 #endif
Simon Cooksey 0:fb7af294d5d9 41
Simon Cooksey 0:fb7af294d5d9 42 #ifndef __CORE_CM4_H_GENERIC
Simon Cooksey 0:fb7af294d5d9 43 #define __CORE_CM4_H_GENERIC
Simon Cooksey 0:fb7af294d5d9 44
Simon Cooksey 0:fb7af294d5d9 45 #ifdef __cplusplus
Simon Cooksey 0:fb7af294d5d9 46 extern "C" {
Simon Cooksey 0:fb7af294d5d9 47 #endif
Simon Cooksey 0:fb7af294d5d9 48
Simon Cooksey 0:fb7af294d5d9 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Simon Cooksey 0:fb7af294d5d9 50 CMSIS violates the following MISRA-C:2004 rules:
Simon Cooksey 0:fb7af294d5d9 51
Simon Cooksey 0:fb7af294d5d9 52 \li Required Rule 8.5, object/function definition in header file.<br>
Simon Cooksey 0:fb7af294d5d9 53 Function definitions in header files are used to allow 'inlining'.
Simon Cooksey 0:fb7af294d5d9 54
Simon Cooksey 0:fb7af294d5d9 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Simon Cooksey 0:fb7af294d5d9 56 Unions are used for effective representation of core registers.
Simon Cooksey 0:fb7af294d5d9 57
Simon Cooksey 0:fb7af294d5d9 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Simon Cooksey 0:fb7af294d5d9 59 Function-like macros are used to allow more efficient code.
Simon Cooksey 0:fb7af294d5d9 60 */
Simon Cooksey 0:fb7af294d5d9 61
Simon Cooksey 0:fb7af294d5d9 62
Simon Cooksey 0:fb7af294d5d9 63 /*******************************************************************************
Simon Cooksey 0:fb7af294d5d9 64 * CMSIS definitions
Simon Cooksey 0:fb7af294d5d9 65 ******************************************************************************/
Simon Cooksey 0:fb7af294d5d9 66 /** \ingroup Cortex_M4
Simon Cooksey 0:fb7af294d5d9 67 @{
Simon Cooksey 0:fb7af294d5d9 68 */
Simon Cooksey 0:fb7af294d5d9 69
Simon Cooksey 0:fb7af294d5d9 70 /* CMSIS CM4 definitions */
Simon Cooksey 0:fb7af294d5d9 71 #define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Simon Cooksey 0:fb7af294d5d9 72 #define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Simon Cooksey 0:fb7af294d5d9 73 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
Simon Cooksey 0:fb7af294d5d9 74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Simon Cooksey 0:fb7af294d5d9 75
Simon Cooksey 0:fb7af294d5d9 76 #define __CORTEX_M (0x04) /*!< Cortex-M Core */
Simon Cooksey 0:fb7af294d5d9 77
Simon Cooksey 0:fb7af294d5d9 78
Simon Cooksey 0:fb7af294d5d9 79 #if defined ( __CC_ARM )
Simon Cooksey 0:fb7af294d5d9 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Simon Cooksey 0:fb7af294d5d9 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Simon Cooksey 0:fb7af294d5d9 82 #define __STATIC_INLINE static __inline
Simon Cooksey 0:fb7af294d5d9 83
Simon Cooksey 0:fb7af294d5d9 84 #elif defined ( __GNUC__ )
Simon Cooksey 0:fb7af294d5d9 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Simon Cooksey 0:fb7af294d5d9 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Simon Cooksey 0:fb7af294d5d9 87 #define __STATIC_INLINE static inline
Simon Cooksey 0:fb7af294d5d9 88
Simon Cooksey 0:fb7af294d5d9 89 #elif defined ( __ICCARM__ )
Simon Cooksey 0:fb7af294d5d9 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Simon Cooksey 0:fb7af294d5d9 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Simon Cooksey 0:fb7af294d5d9 92 #define __STATIC_INLINE static inline
Simon Cooksey 0:fb7af294d5d9 93
Simon Cooksey 0:fb7af294d5d9 94 #elif defined ( __TMS470__ )
Simon Cooksey 0:fb7af294d5d9 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Simon Cooksey 0:fb7af294d5d9 96 #define __STATIC_INLINE static inline
Simon Cooksey 0:fb7af294d5d9 97
Simon Cooksey 0:fb7af294d5d9 98 #elif defined ( __TASKING__ )
Simon Cooksey 0:fb7af294d5d9 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Simon Cooksey 0:fb7af294d5d9 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Simon Cooksey 0:fb7af294d5d9 101 #define __STATIC_INLINE static inline
Simon Cooksey 0:fb7af294d5d9 102
Simon Cooksey 0:fb7af294d5d9 103 #elif defined ( __CSMC__ )
Simon Cooksey 0:fb7af294d5d9 104 #define __packed
Simon Cooksey 0:fb7af294d5d9 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Simon Cooksey 0:fb7af294d5d9 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Simon Cooksey 0:fb7af294d5d9 107 #define __STATIC_INLINE static inline
Simon Cooksey 0:fb7af294d5d9 108
Simon Cooksey 0:fb7af294d5d9 109 #endif
Simon Cooksey 0:fb7af294d5d9 110
Simon Cooksey 0:fb7af294d5d9 111 /** __FPU_USED indicates whether an FPU is used or not.
Simon Cooksey 0:fb7af294d5d9 112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
Simon Cooksey 0:fb7af294d5d9 113 */
Simon Cooksey 0:fb7af294d5d9 114 #if defined ( __CC_ARM )
Simon Cooksey 0:fb7af294d5d9 115 #if defined __TARGET_FPU_VFP
Simon Cooksey 0:fb7af294d5d9 116 #if (__FPU_PRESENT == 1)
Simon Cooksey 0:fb7af294d5d9 117 #define __FPU_USED 1
Simon Cooksey 0:fb7af294d5d9 118 #else
Simon Cooksey 0:fb7af294d5d9 119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Simon Cooksey 0:fb7af294d5d9 120 #define __FPU_USED 0
Simon Cooksey 0:fb7af294d5d9 121 #endif
Simon Cooksey 0:fb7af294d5d9 122 #else
Simon Cooksey 0:fb7af294d5d9 123 #define __FPU_USED 0
Simon Cooksey 0:fb7af294d5d9 124 #endif
Simon Cooksey 0:fb7af294d5d9 125
Simon Cooksey 0:fb7af294d5d9 126 #elif defined ( __GNUC__ )
Simon Cooksey 0:fb7af294d5d9 127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Simon Cooksey 0:fb7af294d5d9 128 #if (__FPU_PRESENT == 1)
Simon Cooksey 0:fb7af294d5d9 129 #define __FPU_USED 1
Simon Cooksey 0:fb7af294d5d9 130 #else
Simon Cooksey 0:fb7af294d5d9 131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Simon Cooksey 0:fb7af294d5d9 132 #define __FPU_USED 0
Simon Cooksey 0:fb7af294d5d9 133 #endif
Simon Cooksey 0:fb7af294d5d9 134 #else
Simon Cooksey 0:fb7af294d5d9 135 #define __FPU_USED 0
Simon Cooksey 0:fb7af294d5d9 136 #endif
Simon Cooksey 0:fb7af294d5d9 137
Simon Cooksey 0:fb7af294d5d9 138 #elif defined ( __ICCARM__ )
Simon Cooksey 0:fb7af294d5d9 139 #if defined __ARMVFP__
Simon Cooksey 0:fb7af294d5d9 140 #if (__FPU_PRESENT == 1)
Simon Cooksey 0:fb7af294d5d9 141 #define __FPU_USED 1
Simon Cooksey 0:fb7af294d5d9 142 #else
Simon Cooksey 0:fb7af294d5d9 143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Simon Cooksey 0:fb7af294d5d9 144 #define __FPU_USED 0
Simon Cooksey 0:fb7af294d5d9 145 #endif
Simon Cooksey 0:fb7af294d5d9 146 #else
Simon Cooksey 0:fb7af294d5d9 147 #define __FPU_USED 0
Simon Cooksey 0:fb7af294d5d9 148 #endif
Simon Cooksey 0:fb7af294d5d9 149
Simon Cooksey 0:fb7af294d5d9 150 #elif defined ( __TMS470__ )
Simon Cooksey 0:fb7af294d5d9 151 #if defined __TI_VFP_SUPPORT__
Simon Cooksey 0:fb7af294d5d9 152 #if (__FPU_PRESENT == 1)
Simon Cooksey 0:fb7af294d5d9 153 #define __FPU_USED 1
Simon Cooksey 0:fb7af294d5d9 154 #else
Simon Cooksey 0:fb7af294d5d9 155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Simon Cooksey 0:fb7af294d5d9 156 #define __FPU_USED 0
Simon Cooksey 0:fb7af294d5d9 157 #endif
Simon Cooksey 0:fb7af294d5d9 158 #else
Simon Cooksey 0:fb7af294d5d9 159 #define __FPU_USED 0
Simon Cooksey 0:fb7af294d5d9 160 #endif
Simon Cooksey 0:fb7af294d5d9 161
Simon Cooksey 0:fb7af294d5d9 162 #elif defined ( __TASKING__ )
Simon Cooksey 0:fb7af294d5d9 163 #if defined __FPU_VFP__
Simon Cooksey 0:fb7af294d5d9 164 #if (__FPU_PRESENT == 1)
Simon Cooksey 0:fb7af294d5d9 165 #define __FPU_USED 1
Simon Cooksey 0:fb7af294d5d9 166 #else
Simon Cooksey 0:fb7af294d5d9 167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Simon Cooksey 0:fb7af294d5d9 168 #define __FPU_USED 0
Simon Cooksey 0:fb7af294d5d9 169 #endif
Simon Cooksey 0:fb7af294d5d9 170 #else
Simon Cooksey 0:fb7af294d5d9 171 #define __FPU_USED 0
Simon Cooksey 0:fb7af294d5d9 172 #endif
Simon Cooksey 0:fb7af294d5d9 173
Simon Cooksey 0:fb7af294d5d9 174 #elif defined ( __CSMC__ ) /* Cosmic */
Simon Cooksey 0:fb7af294d5d9 175 #if ( __CSMC__ & 0x400) // FPU present for parser
Simon Cooksey 0:fb7af294d5d9 176 #if (__FPU_PRESENT == 1)
Simon Cooksey 0:fb7af294d5d9 177 #define __FPU_USED 1
Simon Cooksey 0:fb7af294d5d9 178 #else
Simon Cooksey 0:fb7af294d5d9 179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Simon Cooksey 0:fb7af294d5d9 180 #define __FPU_USED 0
Simon Cooksey 0:fb7af294d5d9 181 #endif
Simon Cooksey 0:fb7af294d5d9 182 #else
Simon Cooksey 0:fb7af294d5d9 183 #define __FPU_USED 0
Simon Cooksey 0:fb7af294d5d9 184 #endif
Simon Cooksey 0:fb7af294d5d9 185 #endif
Simon Cooksey 0:fb7af294d5d9 186
Simon Cooksey 0:fb7af294d5d9 187 #include <stdint.h> /* standard types definitions */
Simon Cooksey 0:fb7af294d5d9 188 #include <core_cmInstr.h> /* Core Instruction Access */
Simon Cooksey 0:fb7af294d5d9 189 #include <core_cmFunc.h> /* Core Function Access */
Simon Cooksey 0:fb7af294d5d9 190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
Simon Cooksey 0:fb7af294d5d9 191
Simon Cooksey 0:fb7af294d5d9 192 #ifdef __cplusplus
Simon Cooksey 0:fb7af294d5d9 193 }
Simon Cooksey 0:fb7af294d5d9 194 #endif
Simon Cooksey 0:fb7af294d5d9 195
Simon Cooksey 0:fb7af294d5d9 196 #endif /* __CORE_CM4_H_GENERIC */
Simon Cooksey 0:fb7af294d5d9 197
Simon Cooksey 0:fb7af294d5d9 198 #ifndef __CMSIS_GENERIC
Simon Cooksey 0:fb7af294d5d9 199
Simon Cooksey 0:fb7af294d5d9 200 #ifndef __CORE_CM4_H_DEPENDANT
Simon Cooksey 0:fb7af294d5d9 201 #define __CORE_CM4_H_DEPENDANT
Simon Cooksey 0:fb7af294d5d9 202
Simon Cooksey 0:fb7af294d5d9 203 #ifdef __cplusplus
Simon Cooksey 0:fb7af294d5d9 204 extern "C" {
Simon Cooksey 0:fb7af294d5d9 205 #endif
Simon Cooksey 0:fb7af294d5d9 206
Simon Cooksey 0:fb7af294d5d9 207 /* check device defines and use defaults */
Simon Cooksey 0:fb7af294d5d9 208 #if defined __CHECK_DEVICE_DEFINES
Simon Cooksey 0:fb7af294d5d9 209 #ifndef __CM4_REV
Simon Cooksey 0:fb7af294d5d9 210 #define __CM4_REV 0x0000
Simon Cooksey 0:fb7af294d5d9 211 #warning "__CM4_REV not defined in device header file; using default!"
Simon Cooksey 0:fb7af294d5d9 212 #endif
Simon Cooksey 0:fb7af294d5d9 213
Simon Cooksey 0:fb7af294d5d9 214 #ifndef __FPU_PRESENT
Simon Cooksey 0:fb7af294d5d9 215 #define __FPU_PRESENT 0
Simon Cooksey 0:fb7af294d5d9 216 #warning "__FPU_PRESENT not defined in device header file; using default!"
Simon Cooksey 0:fb7af294d5d9 217 #endif
Simon Cooksey 0:fb7af294d5d9 218
Simon Cooksey 0:fb7af294d5d9 219 #ifndef __MPU_PRESENT
Simon Cooksey 0:fb7af294d5d9 220 #define __MPU_PRESENT 0
Simon Cooksey 0:fb7af294d5d9 221 #warning "__MPU_PRESENT not defined in device header file; using default!"
Simon Cooksey 0:fb7af294d5d9 222 #endif
Simon Cooksey 0:fb7af294d5d9 223
Simon Cooksey 0:fb7af294d5d9 224 #ifndef __NVIC_PRIO_BITS
Simon Cooksey 0:fb7af294d5d9 225 #define __NVIC_PRIO_BITS 4
Simon Cooksey 0:fb7af294d5d9 226 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Simon Cooksey 0:fb7af294d5d9 227 #endif
Simon Cooksey 0:fb7af294d5d9 228
Simon Cooksey 0:fb7af294d5d9 229 #ifndef __Vendor_SysTickConfig
Simon Cooksey 0:fb7af294d5d9 230 #define __Vendor_SysTickConfig 0
Simon Cooksey 0:fb7af294d5d9 231 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Simon Cooksey 0:fb7af294d5d9 232 #endif
Simon Cooksey 0:fb7af294d5d9 233 #endif
Simon Cooksey 0:fb7af294d5d9 234
Simon Cooksey 0:fb7af294d5d9 235 /* IO definitions (access restrictions to peripheral registers) */
Simon Cooksey 0:fb7af294d5d9 236 /**
Simon Cooksey 0:fb7af294d5d9 237 \defgroup CMSIS_glob_defs CMSIS Global Defines
Simon Cooksey 0:fb7af294d5d9 238
Simon Cooksey 0:fb7af294d5d9 239 <strong>IO Type Qualifiers</strong> are used
Simon Cooksey 0:fb7af294d5d9 240 \li to specify the access to peripheral variables.
Simon Cooksey 0:fb7af294d5d9 241 \li for automatic generation of peripheral register debug information.
Simon Cooksey 0:fb7af294d5d9 242 */
Simon Cooksey 0:fb7af294d5d9 243 #ifdef __cplusplus
Simon Cooksey 0:fb7af294d5d9 244 #define __I volatile /*!< Defines 'read only' permissions */
Simon Cooksey 0:fb7af294d5d9 245 #else
Simon Cooksey 0:fb7af294d5d9 246 #define __I volatile const /*!< Defines 'read only' permissions */
Simon Cooksey 0:fb7af294d5d9 247 #endif
Simon Cooksey 0:fb7af294d5d9 248 #define __O volatile /*!< Defines 'write only' permissions */
Simon Cooksey 0:fb7af294d5d9 249 #define __IO volatile /*!< Defines 'read / write' permissions */
Simon Cooksey 0:fb7af294d5d9 250
Simon Cooksey 0:fb7af294d5d9 251 #ifdef __cplusplus
Simon Cooksey 0:fb7af294d5d9 252 #define __IM volatile /*!< Defines 'read only' permissions */
Simon Cooksey 0:fb7af294d5d9 253 #else
Simon Cooksey 0:fb7af294d5d9 254 #define __IM volatile const /*!< Defines 'read only' permissions */
Simon Cooksey 0:fb7af294d5d9 255 #endif
Simon Cooksey 0:fb7af294d5d9 256 #define __OM volatile /*!< Defines 'write only' permissions */
Simon Cooksey 0:fb7af294d5d9 257 #define __IOM volatile /*!< Defines 'read / write' permissions */
Simon Cooksey 0:fb7af294d5d9 258
Simon Cooksey 0:fb7af294d5d9 259 /*@} end of group Cortex_M4 */
Simon Cooksey 0:fb7af294d5d9 260
Simon Cooksey 0:fb7af294d5d9 261
Simon Cooksey 0:fb7af294d5d9 262
Simon Cooksey 0:fb7af294d5d9 263 /*******************************************************************************
Simon Cooksey 0:fb7af294d5d9 264 * Register Abstraction
Simon Cooksey 0:fb7af294d5d9 265 Core Register contain:
Simon Cooksey 0:fb7af294d5d9 266 - Core Register
Simon Cooksey 0:fb7af294d5d9 267 - Core NVIC Register
Simon Cooksey 0:fb7af294d5d9 268 - Core SCB Register
Simon Cooksey 0:fb7af294d5d9 269 - Core SysTick Register
Simon Cooksey 0:fb7af294d5d9 270 - Core Debug Register
Simon Cooksey 0:fb7af294d5d9 271 - Core MPU Register
Simon Cooksey 0:fb7af294d5d9 272 - Core FPU Register
Simon Cooksey 0:fb7af294d5d9 273 ******************************************************************************/
Simon Cooksey 0:fb7af294d5d9 274 /** \defgroup CMSIS_core_register Defines and Type Definitions
Simon Cooksey 0:fb7af294d5d9 275 \brief Type definitions and defines for Cortex-M processor based devices.
Simon Cooksey 0:fb7af294d5d9 276 */
Simon Cooksey 0:fb7af294d5d9 277
Simon Cooksey 0:fb7af294d5d9 278 /** \ingroup CMSIS_core_register
Simon Cooksey 0:fb7af294d5d9 279 \defgroup CMSIS_CORE Status and Control Registers
Simon Cooksey 0:fb7af294d5d9 280 \brief Core Register type definitions.
Simon Cooksey 0:fb7af294d5d9 281 @{
Simon Cooksey 0:fb7af294d5d9 282 */
Simon Cooksey 0:fb7af294d5d9 283
Simon Cooksey 0:fb7af294d5d9 284 /** \brief Union type to access the Application Program Status Register (APSR).
Simon Cooksey 0:fb7af294d5d9 285 */
Simon Cooksey 0:fb7af294d5d9 286 typedef union
Simon Cooksey 0:fb7af294d5d9 287 {
Simon Cooksey 0:fb7af294d5d9 288 struct
Simon Cooksey 0:fb7af294d5d9 289 {
Simon Cooksey 0:fb7af294d5d9 290 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
Simon Cooksey 0:fb7af294d5d9 291 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Simon Cooksey 0:fb7af294d5d9 292 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
Simon Cooksey 0:fb7af294d5d9 293 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Simon Cooksey 0:fb7af294d5d9 294 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Simon Cooksey 0:fb7af294d5d9 295 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Simon Cooksey 0:fb7af294d5d9 296 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Simon Cooksey 0:fb7af294d5d9 297 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Simon Cooksey 0:fb7af294d5d9 298 } b; /*!< Structure used for bit access */
Simon Cooksey 0:fb7af294d5d9 299 uint32_t w; /*!< Type used for word access */
Simon Cooksey 0:fb7af294d5d9 300 } APSR_Type;
Simon Cooksey 0:fb7af294d5d9 301
Simon Cooksey 0:fb7af294d5d9 302 /* APSR Register Definitions */
Simon Cooksey 0:fb7af294d5d9 303 #define APSR_N_Pos 31 /*!< APSR: N Position */
Simon Cooksey 0:fb7af294d5d9 304 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Simon Cooksey 0:fb7af294d5d9 305
Simon Cooksey 0:fb7af294d5d9 306 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Simon Cooksey 0:fb7af294d5d9 307 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Simon Cooksey 0:fb7af294d5d9 308
Simon Cooksey 0:fb7af294d5d9 309 #define APSR_C_Pos 29 /*!< APSR: C Position */
Simon Cooksey 0:fb7af294d5d9 310 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Simon Cooksey 0:fb7af294d5d9 311
Simon Cooksey 0:fb7af294d5d9 312 #define APSR_V_Pos 28 /*!< APSR: V Position */
Simon Cooksey 0:fb7af294d5d9 313 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Simon Cooksey 0:fb7af294d5d9 314
Simon Cooksey 0:fb7af294d5d9 315 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
Simon Cooksey 0:fb7af294d5d9 316 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
Simon Cooksey 0:fb7af294d5d9 317
Simon Cooksey 0:fb7af294d5d9 318 #define APSR_GE_Pos 16 /*!< APSR: GE Position */
Simon Cooksey 0:fb7af294d5d9 319 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
Simon Cooksey 0:fb7af294d5d9 320
Simon Cooksey 0:fb7af294d5d9 321
Simon Cooksey 0:fb7af294d5d9 322 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Simon Cooksey 0:fb7af294d5d9 323 */
Simon Cooksey 0:fb7af294d5d9 324 typedef union
Simon Cooksey 0:fb7af294d5d9 325 {
Simon Cooksey 0:fb7af294d5d9 326 struct
Simon Cooksey 0:fb7af294d5d9 327 {
Simon Cooksey 0:fb7af294d5d9 328 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Simon Cooksey 0:fb7af294d5d9 329 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Simon Cooksey 0:fb7af294d5d9 330 } b; /*!< Structure used for bit access */
Simon Cooksey 0:fb7af294d5d9 331 uint32_t w; /*!< Type used for word access */
Simon Cooksey 0:fb7af294d5d9 332 } IPSR_Type;
Simon Cooksey 0:fb7af294d5d9 333
Simon Cooksey 0:fb7af294d5d9 334 /* IPSR Register Definitions */
Simon Cooksey 0:fb7af294d5d9 335 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Simon Cooksey 0:fb7af294d5d9 336 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Simon Cooksey 0:fb7af294d5d9 337
Simon Cooksey 0:fb7af294d5d9 338
Simon Cooksey 0:fb7af294d5d9 339 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Simon Cooksey 0:fb7af294d5d9 340 */
Simon Cooksey 0:fb7af294d5d9 341 typedef union
Simon Cooksey 0:fb7af294d5d9 342 {
Simon Cooksey 0:fb7af294d5d9 343 struct
Simon Cooksey 0:fb7af294d5d9 344 {
Simon Cooksey 0:fb7af294d5d9 345 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Simon Cooksey 0:fb7af294d5d9 346 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
Simon Cooksey 0:fb7af294d5d9 347 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Simon Cooksey 0:fb7af294d5d9 348 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
Simon Cooksey 0:fb7af294d5d9 349 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Simon Cooksey 0:fb7af294d5d9 350 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Simon Cooksey 0:fb7af294d5d9 351 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Simon Cooksey 0:fb7af294d5d9 352 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Simon Cooksey 0:fb7af294d5d9 353 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Simon Cooksey 0:fb7af294d5d9 354 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Simon Cooksey 0:fb7af294d5d9 355 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Simon Cooksey 0:fb7af294d5d9 356 } b; /*!< Structure used for bit access */
Simon Cooksey 0:fb7af294d5d9 357 uint32_t w; /*!< Type used for word access */
Simon Cooksey 0:fb7af294d5d9 358 } xPSR_Type;
Simon Cooksey 0:fb7af294d5d9 359
Simon Cooksey 0:fb7af294d5d9 360 /* xPSR Register Definitions */
Simon Cooksey 0:fb7af294d5d9 361 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Simon Cooksey 0:fb7af294d5d9 362 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Simon Cooksey 0:fb7af294d5d9 363
Simon Cooksey 0:fb7af294d5d9 364 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Simon Cooksey 0:fb7af294d5d9 365 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Simon Cooksey 0:fb7af294d5d9 366
Simon Cooksey 0:fb7af294d5d9 367 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Simon Cooksey 0:fb7af294d5d9 368 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Simon Cooksey 0:fb7af294d5d9 369
Simon Cooksey 0:fb7af294d5d9 370 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Simon Cooksey 0:fb7af294d5d9 371 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Simon Cooksey 0:fb7af294d5d9 372
Simon Cooksey 0:fb7af294d5d9 373 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
Simon Cooksey 0:fb7af294d5d9 374 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
Simon Cooksey 0:fb7af294d5d9 375
Simon Cooksey 0:fb7af294d5d9 376 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
Simon Cooksey 0:fb7af294d5d9 377 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
Simon Cooksey 0:fb7af294d5d9 378
Simon Cooksey 0:fb7af294d5d9 379 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Simon Cooksey 0:fb7af294d5d9 380 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Simon Cooksey 0:fb7af294d5d9 381
Simon Cooksey 0:fb7af294d5d9 382 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
Simon Cooksey 0:fb7af294d5d9 383 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
Simon Cooksey 0:fb7af294d5d9 384
Simon Cooksey 0:fb7af294d5d9 385 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Simon Cooksey 0:fb7af294d5d9 386 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Simon Cooksey 0:fb7af294d5d9 387
Simon Cooksey 0:fb7af294d5d9 388
Simon Cooksey 0:fb7af294d5d9 389 /** \brief Union type to access the Control Registers (CONTROL).
Simon Cooksey 0:fb7af294d5d9 390 */
Simon Cooksey 0:fb7af294d5d9 391 typedef union
Simon Cooksey 0:fb7af294d5d9 392 {
Simon Cooksey 0:fb7af294d5d9 393 struct
Simon Cooksey 0:fb7af294d5d9 394 {
Simon Cooksey 0:fb7af294d5d9 395 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Simon Cooksey 0:fb7af294d5d9 396 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Simon Cooksey 0:fb7af294d5d9 397 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
Simon Cooksey 0:fb7af294d5d9 398 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
Simon Cooksey 0:fb7af294d5d9 399 } b; /*!< Structure used for bit access */
Simon Cooksey 0:fb7af294d5d9 400 uint32_t w; /*!< Type used for word access */
Simon Cooksey 0:fb7af294d5d9 401 } CONTROL_Type;
Simon Cooksey 0:fb7af294d5d9 402
Simon Cooksey 0:fb7af294d5d9 403 /* CONTROL Register Definitions */
Simon Cooksey 0:fb7af294d5d9 404 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
Simon Cooksey 0:fb7af294d5d9 405 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
Simon Cooksey 0:fb7af294d5d9 406
Simon Cooksey 0:fb7af294d5d9 407 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Simon Cooksey 0:fb7af294d5d9 408 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Simon Cooksey 0:fb7af294d5d9 409
Simon Cooksey 0:fb7af294d5d9 410 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Simon Cooksey 0:fb7af294d5d9 411 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Simon Cooksey 0:fb7af294d5d9 412
Simon Cooksey 0:fb7af294d5d9 413 /*@} end of group CMSIS_CORE */
Simon Cooksey 0:fb7af294d5d9 414
Simon Cooksey 0:fb7af294d5d9 415
Simon Cooksey 0:fb7af294d5d9 416 /** \ingroup CMSIS_core_register
Simon Cooksey 0:fb7af294d5d9 417 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Simon Cooksey 0:fb7af294d5d9 418 \brief Type definitions for the NVIC Registers
Simon Cooksey 0:fb7af294d5d9 419 @{
Simon Cooksey 0:fb7af294d5d9 420 */
Simon Cooksey 0:fb7af294d5d9 421
Simon Cooksey 0:fb7af294d5d9 422 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Simon Cooksey 0:fb7af294d5d9 423 */
Simon Cooksey 0:fb7af294d5d9 424 typedef struct
Simon Cooksey 0:fb7af294d5d9 425 {
Simon Cooksey 0:fb7af294d5d9 426 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Simon Cooksey 0:fb7af294d5d9 427 uint32_t RESERVED0[24];
Simon Cooksey 0:fb7af294d5d9 428 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Simon Cooksey 0:fb7af294d5d9 429 uint32_t RSERVED1[24];
Simon Cooksey 0:fb7af294d5d9 430 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Simon Cooksey 0:fb7af294d5d9 431 uint32_t RESERVED2[24];
Simon Cooksey 0:fb7af294d5d9 432 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Simon Cooksey 0:fb7af294d5d9 433 uint32_t RESERVED3[24];
Simon Cooksey 0:fb7af294d5d9 434 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
Simon Cooksey 0:fb7af294d5d9 435 uint32_t RESERVED4[56];
Simon Cooksey 0:fb7af294d5d9 436 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
Simon Cooksey 0:fb7af294d5d9 437 uint32_t RESERVED5[644];
Simon Cooksey 0:fb7af294d5d9 438 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
Simon Cooksey 0:fb7af294d5d9 439 } NVIC_Type;
Simon Cooksey 0:fb7af294d5d9 440
Simon Cooksey 0:fb7af294d5d9 441 /* Software Triggered Interrupt Register Definitions */
Simon Cooksey 0:fb7af294d5d9 442 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
Simon Cooksey 0:fb7af294d5d9 443 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
Simon Cooksey 0:fb7af294d5d9 444
Simon Cooksey 0:fb7af294d5d9 445 /*@} end of group CMSIS_NVIC */
Simon Cooksey 0:fb7af294d5d9 446
Simon Cooksey 0:fb7af294d5d9 447
Simon Cooksey 0:fb7af294d5d9 448 /** \ingroup CMSIS_core_register
Simon Cooksey 0:fb7af294d5d9 449 \defgroup CMSIS_SCB System Control Block (SCB)
Simon Cooksey 0:fb7af294d5d9 450 \brief Type definitions for the System Control Block Registers
Simon Cooksey 0:fb7af294d5d9 451 @{
Simon Cooksey 0:fb7af294d5d9 452 */
Simon Cooksey 0:fb7af294d5d9 453
Simon Cooksey 0:fb7af294d5d9 454 /** \brief Structure type to access the System Control Block (SCB).
Simon Cooksey 0:fb7af294d5d9 455 */
Simon Cooksey 0:fb7af294d5d9 456 typedef struct
Simon Cooksey 0:fb7af294d5d9 457 {
Simon Cooksey 0:fb7af294d5d9 458 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Simon Cooksey 0:fb7af294d5d9 459 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Simon Cooksey 0:fb7af294d5d9 460 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Simon Cooksey 0:fb7af294d5d9 461 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Simon Cooksey 0:fb7af294d5d9 462 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Simon Cooksey 0:fb7af294d5d9 463 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Simon Cooksey 0:fb7af294d5d9 464 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
Simon Cooksey 0:fb7af294d5d9 465 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Simon Cooksey 0:fb7af294d5d9 466 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
Simon Cooksey 0:fb7af294d5d9 467 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
Simon Cooksey 0:fb7af294d5d9 468 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
Simon Cooksey 0:fb7af294d5d9 469 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
Simon Cooksey 0:fb7af294d5d9 470 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
Simon Cooksey 0:fb7af294d5d9 471 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
Simon Cooksey 0:fb7af294d5d9 472 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
Simon Cooksey 0:fb7af294d5d9 473 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
Simon Cooksey 0:fb7af294d5d9 474 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
Simon Cooksey 0:fb7af294d5d9 475 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
Simon Cooksey 0:fb7af294d5d9 476 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
Simon Cooksey 0:fb7af294d5d9 477 uint32_t RESERVED0[5];
Simon Cooksey 0:fb7af294d5d9 478 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
Simon Cooksey 0:fb7af294d5d9 479 } SCB_Type;
Simon Cooksey 0:fb7af294d5d9 480
Simon Cooksey 0:fb7af294d5d9 481 /* SCB CPUID Register Definitions */
Simon Cooksey 0:fb7af294d5d9 482 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Simon Cooksey 0:fb7af294d5d9 483 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Simon Cooksey 0:fb7af294d5d9 484
Simon Cooksey 0:fb7af294d5d9 485 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Simon Cooksey 0:fb7af294d5d9 486 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Simon Cooksey 0:fb7af294d5d9 487
Simon Cooksey 0:fb7af294d5d9 488 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Simon Cooksey 0:fb7af294d5d9 489 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Simon Cooksey 0:fb7af294d5d9 490
Simon Cooksey 0:fb7af294d5d9 491 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Simon Cooksey 0:fb7af294d5d9 492 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Simon Cooksey 0:fb7af294d5d9 493
Simon Cooksey 0:fb7af294d5d9 494 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Simon Cooksey 0:fb7af294d5d9 495 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Simon Cooksey 0:fb7af294d5d9 496
Simon Cooksey 0:fb7af294d5d9 497 /* SCB Interrupt Control State Register Definitions */
Simon Cooksey 0:fb7af294d5d9 498 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Simon Cooksey 0:fb7af294d5d9 499 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Simon Cooksey 0:fb7af294d5d9 500
Simon Cooksey 0:fb7af294d5d9 501 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Simon Cooksey 0:fb7af294d5d9 502 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Simon Cooksey 0:fb7af294d5d9 503
Simon Cooksey 0:fb7af294d5d9 504 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Simon Cooksey 0:fb7af294d5d9 505 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Simon Cooksey 0:fb7af294d5d9 506
Simon Cooksey 0:fb7af294d5d9 507 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Simon Cooksey 0:fb7af294d5d9 508 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Simon Cooksey 0:fb7af294d5d9 509
Simon Cooksey 0:fb7af294d5d9 510 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Simon Cooksey 0:fb7af294d5d9 511 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Simon Cooksey 0:fb7af294d5d9 512
Simon Cooksey 0:fb7af294d5d9 513 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Simon Cooksey 0:fb7af294d5d9 514 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Simon Cooksey 0:fb7af294d5d9 515
Simon Cooksey 0:fb7af294d5d9 516 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Simon Cooksey 0:fb7af294d5d9 517 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Simon Cooksey 0:fb7af294d5d9 518
Simon Cooksey 0:fb7af294d5d9 519 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Simon Cooksey 0:fb7af294d5d9 520 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Simon Cooksey 0:fb7af294d5d9 521
Simon Cooksey 0:fb7af294d5d9 522 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
Simon Cooksey 0:fb7af294d5d9 523 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
Simon Cooksey 0:fb7af294d5d9 524
Simon Cooksey 0:fb7af294d5d9 525 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Simon Cooksey 0:fb7af294d5d9 526 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Simon Cooksey 0:fb7af294d5d9 527
Simon Cooksey 0:fb7af294d5d9 528 /* SCB Vector Table Offset Register Definitions */
Simon Cooksey 0:fb7af294d5d9 529 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
Simon Cooksey 0:fb7af294d5d9 530 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Simon Cooksey 0:fb7af294d5d9 531
Simon Cooksey 0:fb7af294d5d9 532 /* SCB Application Interrupt and Reset Control Register Definitions */
Simon Cooksey 0:fb7af294d5d9 533 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Simon Cooksey 0:fb7af294d5d9 534 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Simon Cooksey 0:fb7af294d5d9 535
Simon Cooksey 0:fb7af294d5d9 536 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Simon Cooksey 0:fb7af294d5d9 537 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Simon Cooksey 0:fb7af294d5d9 538
Simon Cooksey 0:fb7af294d5d9 539 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Simon Cooksey 0:fb7af294d5d9 540 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Simon Cooksey 0:fb7af294d5d9 541
Simon Cooksey 0:fb7af294d5d9 542 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
Simon Cooksey 0:fb7af294d5d9 543 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
Simon Cooksey 0:fb7af294d5d9 544
Simon Cooksey 0:fb7af294d5d9 545 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Simon Cooksey 0:fb7af294d5d9 546 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Simon Cooksey 0:fb7af294d5d9 547
Simon Cooksey 0:fb7af294d5d9 548 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Simon Cooksey 0:fb7af294d5d9 549 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Simon Cooksey 0:fb7af294d5d9 550
Simon Cooksey 0:fb7af294d5d9 551 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
Simon Cooksey 0:fb7af294d5d9 552 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
Simon Cooksey 0:fb7af294d5d9 553
Simon Cooksey 0:fb7af294d5d9 554 /* SCB System Control Register Definitions */
Simon Cooksey 0:fb7af294d5d9 555 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Simon Cooksey 0:fb7af294d5d9 556 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Simon Cooksey 0:fb7af294d5d9 557
Simon Cooksey 0:fb7af294d5d9 558 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Simon Cooksey 0:fb7af294d5d9 559 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Simon Cooksey 0:fb7af294d5d9 560
Simon Cooksey 0:fb7af294d5d9 561 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Simon Cooksey 0:fb7af294d5d9 562 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Simon Cooksey 0:fb7af294d5d9 563
Simon Cooksey 0:fb7af294d5d9 564 /* SCB Configuration Control Register Definitions */
Simon Cooksey 0:fb7af294d5d9 565 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Simon Cooksey 0:fb7af294d5d9 566 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Simon Cooksey 0:fb7af294d5d9 567
Simon Cooksey 0:fb7af294d5d9 568 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
Simon Cooksey 0:fb7af294d5d9 569 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
Simon Cooksey 0:fb7af294d5d9 570
Simon Cooksey 0:fb7af294d5d9 571 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
Simon Cooksey 0:fb7af294d5d9 572 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
Simon Cooksey 0:fb7af294d5d9 573
Simon Cooksey 0:fb7af294d5d9 574 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Simon Cooksey 0:fb7af294d5d9 575 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Simon Cooksey 0:fb7af294d5d9 576
Simon Cooksey 0:fb7af294d5d9 577 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
Simon Cooksey 0:fb7af294d5d9 578 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
Simon Cooksey 0:fb7af294d5d9 579
Simon Cooksey 0:fb7af294d5d9 580 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
Simon Cooksey 0:fb7af294d5d9 581 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
Simon Cooksey 0:fb7af294d5d9 582
Simon Cooksey 0:fb7af294d5d9 583 /* SCB System Handler Control and State Register Definitions */
Simon Cooksey 0:fb7af294d5d9 584 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
Simon Cooksey 0:fb7af294d5d9 585 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
Simon Cooksey 0:fb7af294d5d9 586
Simon Cooksey 0:fb7af294d5d9 587 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
Simon Cooksey 0:fb7af294d5d9 588 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
Simon Cooksey 0:fb7af294d5d9 589
Simon Cooksey 0:fb7af294d5d9 590 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
Simon Cooksey 0:fb7af294d5d9 591 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
Simon Cooksey 0:fb7af294d5d9 592
Simon Cooksey 0:fb7af294d5d9 593 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Simon Cooksey 0:fb7af294d5d9 594 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Simon Cooksey 0:fb7af294d5d9 595
Simon Cooksey 0:fb7af294d5d9 596 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
Simon Cooksey 0:fb7af294d5d9 597 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
Simon Cooksey 0:fb7af294d5d9 598
Simon Cooksey 0:fb7af294d5d9 599 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
Simon Cooksey 0:fb7af294d5d9 600 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
Simon Cooksey 0:fb7af294d5d9 601
Simon Cooksey 0:fb7af294d5d9 602 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
Simon Cooksey 0:fb7af294d5d9 603 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
Simon Cooksey 0:fb7af294d5d9 604
Simon Cooksey 0:fb7af294d5d9 605 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
Simon Cooksey 0:fb7af294d5d9 606 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
Simon Cooksey 0:fb7af294d5d9 607
Simon Cooksey 0:fb7af294d5d9 608 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
Simon Cooksey 0:fb7af294d5d9 609 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
Simon Cooksey 0:fb7af294d5d9 610
Simon Cooksey 0:fb7af294d5d9 611 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
Simon Cooksey 0:fb7af294d5d9 612 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
Simon Cooksey 0:fb7af294d5d9 613
Simon Cooksey 0:fb7af294d5d9 614 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
Simon Cooksey 0:fb7af294d5d9 615 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
Simon Cooksey 0:fb7af294d5d9 616
Simon Cooksey 0:fb7af294d5d9 617 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
Simon Cooksey 0:fb7af294d5d9 618 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
Simon Cooksey 0:fb7af294d5d9 619
Simon Cooksey 0:fb7af294d5d9 620 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
Simon Cooksey 0:fb7af294d5d9 621 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
Simon Cooksey 0:fb7af294d5d9 622
Simon Cooksey 0:fb7af294d5d9 623 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
Simon Cooksey 0:fb7af294d5d9 624 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
Simon Cooksey 0:fb7af294d5d9 625
Simon Cooksey 0:fb7af294d5d9 626 /* SCB Configurable Fault Status Registers Definitions */
Simon Cooksey 0:fb7af294d5d9 627 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
Simon Cooksey 0:fb7af294d5d9 628 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
Simon Cooksey 0:fb7af294d5d9 629
Simon Cooksey 0:fb7af294d5d9 630 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
Simon Cooksey 0:fb7af294d5d9 631 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
Simon Cooksey 0:fb7af294d5d9 632
Simon Cooksey 0:fb7af294d5d9 633 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
Simon Cooksey 0:fb7af294d5d9 634 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
Simon Cooksey 0:fb7af294d5d9 635
Simon Cooksey 0:fb7af294d5d9 636 /* SCB Hard Fault Status Registers Definitions */
Simon Cooksey 0:fb7af294d5d9 637 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
Simon Cooksey 0:fb7af294d5d9 638 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
Simon Cooksey 0:fb7af294d5d9 639
Simon Cooksey 0:fb7af294d5d9 640 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
Simon Cooksey 0:fb7af294d5d9 641 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
Simon Cooksey 0:fb7af294d5d9 642
Simon Cooksey 0:fb7af294d5d9 643 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
Simon Cooksey 0:fb7af294d5d9 644 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
Simon Cooksey 0:fb7af294d5d9 645
Simon Cooksey 0:fb7af294d5d9 646 /* SCB Debug Fault Status Register Definitions */
Simon Cooksey 0:fb7af294d5d9 647 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
Simon Cooksey 0:fb7af294d5d9 648 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
Simon Cooksey 0:fb7af294d5d9 649
Simon Cooksey 0:fb7af294d5d9 650 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
Simon Cooksey 0:fb7af294d5d9 651 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
Simon Cooksey 0:fb7af294d5d9 652
Simon Cooksey 0:fb7af294d5d9 653 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
Simon Cooksey 0:fb7af294d5d9 654 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
Simon Cooksey 0:fb7af294d5d9 655
Simon Cooksey 0:fb7af294d5d9 656 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
Simon Cooksey 0:fb7af294d5d9 657 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
Simon Cooksey 0:fb7af294d5d9 658
Simon Cooksey 0:fb7af294d5d9 659 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
Simon Cooksey 0:fb7af294d5d9 660 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
Simon Cooksey 0:fb7af294d5d9 661
Simon Cooksey 0:fb7af294d5d9 662 /*@} end of group CMSIS_SCB */
Simon Cooksey 0:fb7af294d5d9 663
Simon Cooksey 0:fb7af294d5d9 664
Simon Cooksey 0:fb7af294d5d9 665 /** \ingroup CMSIS_core_register
Simon Cooksey 0:fb7af294d5d9 666 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Simon Cooksey 0:fb7af294d5d9 667 \brief Type definitions for the System Control and ID Register not in the SCB
Simon Cooksey 0:fb7af294d5d9 668 @{
Simon Cooksey 0:fb7af294d5d9 669 */
Simon Cooksey 0:fb7af294d5d9 670
Simon Cooksey 0:fb7af294d5d9 671 /** \brief Structure type to access the System Control and ID Register not in the SCB.
Simon Cooksey 0:fb7af294d5d9 672 */
Simon Cooksey 0:fb7af294d5d9 673 typedef struct
Simon Cooksey 0:fb7af294d5d9 674 {
Simon Cooksey 0:fb7af294d5d9 675 uint32_t RESERVED0[1];
Simon Cooksey 0:fb7af294d5d9 676 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
Simon Cooksey 0:fb7af294d5d9 677 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
Simon Cooksey 0:fb7af294d5d9 678 } SCnSCB_Type;
Simon Cooksey 0:fb7af294d5d9 679
Simon Cooksey 0:fb7af294d5d9 680 /* Interrupt Controller Type Register Definitions */
Simon Cooksey 0:fb7af294d5d9 681 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
Simon Cooksey 0:fb7af294d5d9 682 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
Simon Cooksey 0:fb7af294d5d9 683
Simon Cooksey 0:fb7af294d5d9 684 /* Auxiliary Control Register Definitions */
Simon Cooksey 0:fb7af294d5d9 685 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
Simon Cooksey 0:fb7af294d5d9 686 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
Simon Cooksey 0:fb7af294d5d9 687
Simon Cooksey 0:fb7af294d5d9 688 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
Simon Cooksey 0:fb7af294d5d9 689 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
Simon Cooksey 0:fb7af294d5d9 690
Simon Cooksey 0:fb7af294d5d9 691 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
Simon Cooksey 0:fb7af294d5d9 692 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
Simon Cooksey 0:fb7af294d5d9 693
Simon Cooksey 0:fb7af294d5d9 694 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
Simon Cooksey 0:fb7af294d5d9 695 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
Simon Cooksey 0:fb7af294d5d9 696
Simon Cooksey 0:fb7af294d5d9 697 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
Simon Cooksey 0:fb7af294d5d9 698 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
Simon Cooksey 0:fb7af294d5d9 699
Simon Cooksey 0:fb7af294d5d9 700 /*@} end of group CMSIS_SCnotSCB */
Simon Cooksey 0:fb7af294d5d9 701
Simon Cooksey 0:fb7af294d5d9 702
Simon Cooksey 0:fb7af294d5d9 703 /** \ingroup CMSIS_core_register
Simon Cooksey 0:fb7af294d5d9 704 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Simon Cooksey 0:fb7af294d5d9 705 \brief Type definitions for the System Timer Registers.
Simon Cooksey 0:fb7af294d5d9 706 @{
Simon Cooksey 0:fb7af294d5d9 707 */
Simon Cooksey 0:fb7af294d5d9 708
Simon Cooksey 0:fb7af294d5d9 709 /** \brief Structure type to access the System Timer (SysTick).
Simon Cooksey 0:fb7af294d5d9 710 */
Simon Cooksey 0:fb7af294d5d9 711 typedef struct
Simon Cooksey 0:fb7af294d5d9 712 {
Simon Cooksey 0:fb7af294d5d9 713 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Simon Cooksey 0:fb7af294d5d9 714 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Simon Cooksey 0:fb7af294d5d9 715 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Simon Cooksey 0:fb7af294d5d9 716 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Simon Cooksey 0:fb7af294d5d9 717 } SysTick_Type;
Simon Cooksey 0:fb7af294d5d9 718
Simon Cooksey 0:fb7af294d5d9 719 /* SysTick Control / Status Register Definitions */
Simon Cooksey 0:fb7af294d5d9 720 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Simon Cooksey 0:fb7af294d5d9 721 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Simon Cooksey 0:fb7af294d5d9 722
Simon Cooksey 0:fb7af294d5d9 723 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Simon Cooksey 0:fb7af294d5d9 724 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Simon Cooksey 0:fb7af294d5d9 725
Simon Cooksey 0:fb7af294d5d9 726 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Simon Cooksey 0:fb7af294d5d9 727 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Simon Cooksey 0:fb7af294d5d9 728
Simon Cooksey 0:fb7af294d5d9 729 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Simon Cooksey 0:fb7af294d5d9 730 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Simon Cooksey 0:fb7af294d5d9 731
Simon Cooksey 0:fb7af294d5d9 732 /* SysTick Reload Register Definitions */
Simon Cooksey 0:fb7af294d5d9 733 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Simon Cooksey 0:fb7af294d5d9 734 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Simon Cooksey 0:fb7af294d5d9 735
Simon Cooksey 0:fb7af294d5d9 736 /* SysTick Current Register Definitions */
Simon Cooksey 0:fb7af294d5d9 737 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Simon Cooksey 0:fb7af294d5d9 738 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Simon Cooksey 0:fb7af294d5d9 739
Simon Cooksey 0:fb7af294d5d9 740 /* SysTick Calibration Register Definitions */
Simon Cooksey 0:fb7af294d5d9 741 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Simon Cooksey 0:fb7af294d5d9 742 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Simon Cooksey 0:fb7af294d5d9 743
Simon Cooksey 0:fb7af294d5d9 744 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Simon Cooksey 0:fb7af294d5d9 745 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Simon Cooksey 0:fb7af294d5d9 746
Simon Cooksey 0:fb7af294d5d9 747 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Simon Cooksey 0:fb7af294d5d9 748 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Simon Cooksey 0:fb7af294d5d9 749
Simon Cooksey 0:fb7af294d5d9 750 /*@} end of group CMSIS_SysTick */
Simon Cooksey 0:fb7af294d5d9 751
Simon Cooksey 0:fb7af294d5d9 752
Simon Cooksey 0:fb7af294d5d9 753 /** \ingroup CMSIS_core_register
Simon Cooksey 0:fb7af294d5d9 754 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Simon Cooksey 0:fb7af294d5d9 755 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Simon Cooksey 0:fb7af294d5d9 756 @{
Simon Cooksey 0:fb7af294d5d9 757 */
Simon Cooksey 0:fb7af294d5d9 758
Simon Cooksey 0:fb7af294d5d9 759 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Simon Cooksey 0:fb7af294d5d9 760 */
Simon Cooksey 0:fb7af294d5d9 761 typedef struct
Simon Cooksey 0:fb7af294d5d9 762 {
Simon Cooksey 0:fb7af294d5d9 763 __O union
Simon Cooksey 0:fb7af294d5d9 764 {
Simon Cooksey 0:fb7af294d5d9 765 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
Simon Cooksey 0:fb7af294d5d9 766 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
Simon Cooksey 0:fb7af294d5d9 767 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
Simon Cooksey 0:fb7af294d5d9 768 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
Simon Cooksey 0:fb7af294d5d9 769 uint32_t RESERVED0[864];
Simon Cooksey 0:fb7af294d5d9 770 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
Simon Cooksey 0:fb7af294d5d9 771 uint32_t RESERVED1[15];
Simon Cooksey 0:fb7af294d5d9 772 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
Simon Cooksey 0:fb7af294d5d9 773 uint32_t RESERVED2[15];
Simon Cooksey 0:fb7af294d5d9 774 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
Simon Cooksey 0:fb7af294d5d9 775 uint32_t RESERVED3[29];
Simon Cooksey 0:fb7af294d5d9 776 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
Simon Cooksey 0:fb7af294d5d9 777 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
Simon Cooksey 0:fb7af294d5d9 778 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
Simon Cooksey 0:fb7af294d5d9 779 uint32_t RESERVED4[43];
Simon Cooksey 0:fb7af294d5d9 780 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
Simon Cooksey 0:fb7af294d5d9 781 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
Simon Cooksey 0:fb7af294d5d9 782 uint32_t RESERVED5[6];
Simon Cooksey 0:fb7af294d5d9 783 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
Simon Cooksey 0:fb7af294d5d9 784 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
Simon Cooksey 0:fb7af294d5d9 785 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
Simon Cooksey 0:fb7af294d5d9 786 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
Simon Cooksey 0:fb7af294d5d9 787 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
Simon Cooksey 0:fb7af294d5d9 788 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
Simon Cooksey 0:fb7af294d5d9 789 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
Simon Cooksey 0:fb7af294d5d9 790 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
Simon Cooksey 0:fb7af294d5d9 791 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
Simon Cooksey 0:fb7af294d5d9 792 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
Simon Cooksey 0:fb7af294d5d9 793 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
Simon Cooksey 0:fb7af294d5d9 794 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
Simon Cooksey 0:fb7af294d5d9 795 } ITM_Type;
Simon Cooksey 0:fb7af294d5d9 796
Simon Cooksey 0:fb7af294d5d9 797 /* ITM Trace Privilege Register Definitions */
Simon Cooksey 0:fb7af294d5d9 798 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
Simon Cooksey 0:fb7af294d5d9 799 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
Simon Cooksey 0:fb7af294d5d9 800
Simon Cooksey 0:fb7af294d5d9 801 /* ITM Trace Control Register Definitions */
Simon Cooksey 0:fb7af294d5d9 802 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
Simon Cooksey 0:fb7af294d5d9 803 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
Simon Cooksey 0:fb7af294d5d9 804
Simon Cooksey 0:fb7af294d5d9 805 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
Simon Cooksey 0:fb7af294d5d9 806 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
Simon Cooksey 0:fb7af294d5d9 807
Simon Cooksey 0:fb7af294d5d9 808 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
Simon Cooksey 0:fb7af294d5d9 809 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
Simon Cooksey 0:fb7af294d5d9 810
Simon Cooksey 0:fb7af294d5d9 811 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
Simon Cooksey 0:fb7af294d5d9 812 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
Simon Cooksey 0:fb7af294d5d9 813
Simon Cooksey 0:fb7af294d5d9 814 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
Simon Cooksey 0:fb7af294d5d9 815 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
Simon Cooksey 0:fb7af294d5d9 816
Simon Cooksey 0:fb7af294d5d9 817 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
Simon Cooksey 0:fb7af294d5d9 818 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
Simon Cooksey 0:fb7af294d5d9 819
Simon Cooksey 0:fb7af294d5d9 820 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
Simon Cooksey 0:fb7af294d5d9 821 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
Simon Cooksey 0:fb7af294d5d9 822
Simon Cooksey 0:fb7af294d5d9 823 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
Simon Cooksey 0:fb7af294d5d9 824 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
Simon Cooksey 0:fb7af294d5d9 825
Simon Cooksey 0:fb7af294d5d9 826 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
Simon Cooksey 0:fb7af294d5d9 827 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
Simon Cooksey 0:fb7af294d5d9 828
Simon Cooksey 0:fb7af294d5d9 829 /* ITM Integration Write Register Definitions */
Simon Cooksey 0:fb7af294d5d9 830 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
Simon Cooksey 0:fb7af294d5d9 831 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
Simon Cooksey 0:fb7af294d5d9 832
Simon Cooksey 0:fb7af294d5d9 833 /* ITM Integration Read Register Definitions */
Simon Cooksey 0:fb7af294d5d9 834 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
Simon Cooksey 0:fb7af294d5d9 835 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
Simon Cooksey 0:fb7af294d5d9 836
Simon Cooksey 0:fb7af294d5d9 837 /* ITM Integration Mode Control Register Definitions */
Simon Cooksey 0:fb7af294d5d9 838 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
Simon Cooksey 0:fb7af294d5d9 839 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
Simon Cooksey 0:fb7af294d5d9 840
Simon Cooksey 0:fb7af294d5d9 841 /* ITM Lock Status Register Definitions */
Simon Cooksey 0:fb7af294d5d9 842 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
Simon Cooksey 0:fb7af294d5d9 843 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
Simon Cooksey 0:fb7af294d5d9 844
Simon Cooksey 0:fb7af294d5d9 845 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
Simon Cooksey 0:fb7af294d5d9 846 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
Simon Cooksey 0:fb7af294d5d9 847
Simon Cooksey 0:fb7af294d5d9 848 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
Simon Cooksey 0:fb7af294d5d9 849 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
Simon Cooksey 0:fb7af294d5d9 850
Simon Cooksey 0:fb7af294d5d9 851 /*@}*/ /* end of group CMSIS_ITM */
Simon Cooksey 0:fb7af294d5d9 852
Simon Cooksey 0:fb7af294d5d9 853
Simon Cooksey 0:fb7af294d5d9 854 /** \ingroup CMSIS_core_register
Simon Cooksey 0:fb7af294d5d9 855 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Simon Cooksey 0:fb7af294d5d9 856 \brief Type definitions for the Data Watchpoint and Trace (DWT)
Simon Cooksey 0:fb7af294d5d9 857 @{
Simon Cooksey 0:fb7af294d5d9 858 */
Simon Cooksey 0:fb7af294d5d9 859
Simon Cooksey 0:fb7af294d5d9 860 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Simon Cooksey 0:fb7af294d5d9 861 */
Simon Cooksey 0:fb7af294d5d9 862 typedef struct
Simon Cooksey 0:fb7af294d5d9 863 {
Simon Cooksey 0:fb7af294d5d9 864 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
Simon Cooksey 0:fb7af294d5d9 865 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
Simon Cooksey 0:fb7af294d5d9 866 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
Simon Cooksey 0:fb7af294d5d9 867 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
Simon Cooksey 0:fb7af294d5d9 868 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
Simon Cooksey 0:fb7af294d5d9 869 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
Simon Cooksey 0:fb7af294d5d9 870 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
Simon Cooksey 0:fb7af294d5d9 871 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
Simon Cooksey 0:fb7af294d5d9 872 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
Simon Cooksey 0:fb7af294d5d9 873 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
Simon Cooksey 0:fb7af294d5d9 874 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
Simon Cooksey 0:fb7af294d5d9 875 uint32_t RESERVED0[1];
Simon Cooksey 0:fb7af294d5d9 876 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
Simon Cooksey 0:fb7af294d5d9 877 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
Simon Cooksey 0:fb7af294d5d9 878 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
Simon Cooksey 0:fb7af294d5d9 879 uint32_t RESERVED1[1];
Simon Cooksey 0:fb7af294d5d9 880 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
Simon Cooksey 0:fb7af294d5d9 881 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
Simon Cooksey 0:fb7af294d5d9 882 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
Simon Cooksey 0:fb7af294d5d9 883 uint32_t RESERVED2[1];
Simon Cooksey 0:fb7af294d5d9 884 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
Simon Cooksey 0:fb7af294d5d9 885 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
Simon Cooksey 0:fb7af294d5d9 886 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
Simon Cooksey 0:fb7af294d5d9 887 } DWT_Type;
Simon Cooksey 0:fb7af294d5d9 888
Simon Cooksey 0:fb7af294d5d9 889 /* DWT Control Register Definitions */
Simon Cooksey 0:fb7af294d5d9 890 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
Simon Cooksey 0:fb7af294d5d9 891 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
Simon Cooksey 0:fb7af294d5d9 892
Simon Cooksey 0:fb7af294d5d9 893 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
Simon Cooksey 0:fb7af294d5d9 894 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
Simon Cooksey 0:fb7af294d5d9 895
Simon Cooksey 0:fb7af294d5d9 896 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
Simon Cooksey 0:fb7af294d5d9 897 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
Simon Cooksey 0:fb7af294d5d9 898
Simon Cooksey 0:fb7af294d5d9 899 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
Simon Cooksey 0:fb7af294d5d9 900 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
Simon Cooksey 0:fb7af294d5d9 901
Simon Cooksey 0:fb7af294d5d9 902 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
Simon Cooksey 0:fb7af294d5d9 903 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
Simon Cooksey 0:fb7af294d5d9 904
Simon Cooksey 0:fb7af294d5d9 905 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
Simon Cooksey 0:fb7af294d5d9 906 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
Simon Cooksey 0:fb7af294d5d9 907
Simon Cooksey 0:fb7af294d5d9 908 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
Simon Cooksey 0:fb7af294d5d9 909 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
Simon Cooksey 0:fb7af294d5d9 910
Simon Cooksey 0:fb7af294d5d9 911 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
Simon Cooksey 0:fb7af294d5d9 912 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
Simon Cooksey 0:fb7af294d5d9 913
Simon Cooksey 0:fb7af294d5d9 914 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
Simon Cooksey 0:fb7af294d5d9 915 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
Simon Cooksey 0:fb7af294d5d9 916
Simon Cooksey 0:fb7af294d5d9 917 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
Simon Cooksey 0:fb7af294d5d9 918 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
Simon Cooksey 0:fb7af294d5d9 919
Simon Cooksey 0:fb7af294d5d9 920 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
Simon Cooksey 0:fb7af294d5d9 921 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
Simon Cooksey 0:fb7af294d5d9 922
Simon Cooksey 0:fb7af294d5d9 923 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
Simon Cooksey 0:fb7af294d5d9 924 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
Simon Cooksey 0:fb7af294d5d9 925
Simon Cooksey 0:fb7af294d5d9 926 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
Simon Cooksey 0:fb7af294d5d9 927 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
Simon Cooksey 0:fb7af294d5d9 928
Simon Cooksey 0:fb7af294d5d9 929 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
Simon Cooksey 0:fb7af294d5d9 930 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
Simon Cooksey 0:fb7af294d5d9 931
Simon Cooksey 0:fb7af294d5d9 932 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
Simon Cooksey 0:fb7af294d5d9 933 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
Simon Cooksey 0:fb7af294d5d9 934
Simon Cooksey 0:fb7af294d5d9 935 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
Simon Cooksey 0:fb7af294d5d9 936 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
Simon Cooksey 0:fb7af294d5d9 937
Simon Cooksey 0:fb7af294d5d9 938 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
Simon Cooksey 0:fb7af294d5d9 939 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
Simon Cooksey 0:fb7af294d5d9 940
Simon Cooksey 0:fb7af294d5d9 941 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
Simon Cooksey 0:fb7af294d5d9 942 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
Simon Cooksey 0:fb7af294d5d9 943
Simon Cooksey 0:fb7af294d5d9 944 /* DWT CPI Count Register Definitions */
Simon Cooksey 0:fb7af294d5d9 945 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
Simon Cooksey 0:fb7af294d5d9 946 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
Simon Cooksey 0:fb7af294d5d9 947
Simon Cooksey 0:fb7af294d5d9 948 /* DWT Exception Overhead Count Register Definitions */
Simon Cooksey 0:fb7af294d5d9 949 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
Simon Cooksey 0:fb7af294d5d9 950 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
Simon Cooksey 0:fb7af294d5d9 951
Simon Cooksey 0:fb7af294d5d9 952 /* DWT Sleep Count Register Definitions */
Simon Cooksey 0:fb7af294d5d9 953 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
Simon Cooksey 0:fb7af294d5d9 954 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
Simon Cooksey 0:fb7af294d5d9 955
Simon Cooksey 0:fb7af294d5d9 956 /* DWT LSU Count Register Definitions */
Simon Cooksey 0:fb7af294d5d9 957 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
Simon Cooksey 0:fb7af294d5d9 958 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
Simon Cooksey 0:fb7af294d5d9 959
Simon Cooksey 0:fb7af294d5d9 960 /* DWT Folded-instruction Count Register Definitions */
Simon Cooksey 0:fb7af294d5d9 961 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
Simon Cooksey 0:fb7af294d5d9 962 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
Simon Cooksey 0:fb7af294d5d9 963
Simon Cooksey 0:fb7af294d5d9 964 /* DWT Comparator Mask Register Definitions */
Simon Cooksey 0:fb7af294d5d9 965 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
Simon Cooksey 0:fb7af294d5d9 966 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
Simon Cooksey 0:fb7af294d5d9 967
Simon Cooksey 0:fb7af294d5d9 968 /* DWT Comparator Function Register Definitions */
Simon Cooksey 0:fb7af294d5d9 969 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
Simon Cooksey 0:fb7af294d5d9 970 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
Simon Cooksey 0:fb7af294d5d9 971
Simon Cooksey 0:fb7af294d5d9 972 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
Simon Cooksey 0:fb7af294d5d9 973 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
Simon Cooksey 0:fb7af294d5d9 974
Simon Cooksey 0:fb7af294d5d9 975 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
Simon Cooksey 0:fb7af294d5d9 976 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
Simon Cooksey 0:fb7af294d5d9 977
Simon Cooksey 0:fb7af294d5d9 978 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
Simon Cooksey 0:fb7af294d5d9 979 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
Simon Cooksey 0:fb7af294d5d9 980
Simon Cooksey 0:fb7af294d5d9 981 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
Simon Cooksey 0:fb7af294d5d9 982 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
Simon Cooksey 0:fb7af294d5d9 983
Simon Cooksey 0:fb7af294d5d9 984 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
Simon Cooksey 0:fb7af294d5d9 985 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
Simon Cooksey 0:fb7af294d5d9 986
Simon Cooksey 0:fb7af294d5d9 987 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
Simon Cooksey 0:fb7af294d5d9 988 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
Simon Cooksey 0:fb7af294d5d9 989
Simon Cooksey 0:fb7af294d5d9 990 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
Simon Cooksey 0:fb7af294d5d9 991 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
Simon Cooksey 0:fb7af294d5d9 992
Simon Cooksey 0:fb7af294d5d9 993 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
Simon Cooksey 0:fb7af294d5d9 994 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
Simon Cooksey 0:fb7af294d5d9 995
Simon Cooksey 0:fb7af294d5d9 996 /*@}*/ /* end of group CMSIS_DWT */
Simon Cooksey 0:fb7af294d5d9 997
Simon Cooksey 0:fb7af294d5d9 998
Simon Cooksey 0:fb7af294d5d9 999 /** \ingroup CMSIS_core_register
Simon Cooksey 0:fb7af294d5d9 1000 \defgroup CMSIS_TPI Trace Port Interface (TPI)
Simon Cooksey 0:fb7af294d5d9 1001 \brief Type definitions for the Trace Port Interface (TPI)
Simon Cooksey 0:fb7af294d5d9 1002 @{
Simon Cooksey 0:fb7af294d5d9 1003 */
Simon Cooksey 0:fb7af294d5d9 1004
Simon Cooksey 0:fb7af294d5d9 1005 /** \brief Structure type to access the Trace Port Interface Register (TPI).
Simon Cooksey 0:fb7af294d5d9 1006 */
Simon Cooksey 0:fb7af294d5d9 1007 typedef struct
Simon Cooksey 0:fb7af294d5d9 1008 {
Simon Cooksey 0:fb7af294d5d9 1009 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
Simon Cooksey 0:fb7af294d5d9 1010 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
Simon Cooksey 0:fb7af294d5d9 1011 uint32_t RESERVED0[2];
Simon Cooksey 0:fb7af294d5d9 1012 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
Simon Cooksey 0:fb7af294d5d9 1013 uint32_t RESERVED1[55];
Simon Cooksey 0:fb7af294d5d9 1014 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
Simon Cooksey 0:fb7af294d5d9 1015 uint32_t RESERVED2[131];
Simon Cooksey 0:fb7af294d5d9 1016 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
Simon Cooksey 0:fb7af294d5d9 1017 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
Simon Cooksey 0:fb7af294d5d9 1018 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
Simon Cooksey 0:fb7af294d5d9 1019 uint32_t RESERVED3[759];
Simon Cooksey 0:fb7af294d5d9 1020 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
Simon Cooksey 0:fb7af294d5d9 1021 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
Simon Cooksey 0:fb7af294d5d9 1022 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
Simon Cooksey 0:fb7af294d5d9 1023 uint32_t RESERVED4[1];
Simon Cooksey 0:fb7af294d5d9 1024 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
Simon Cooksey 0:fb7af294d5d9 1025 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
Simon Cooksey 0:fb7af294d5d9 1026 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
Simon Cooksey 0:fb7af294d5d9 1027 uint32_t RESERVED5[39];
Simon Cooksey 0:fb7af294d5d9 1028 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
Simon Cooksey 0:fb7af294d5d9 1029 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
Simon Cooksey 0:fb7af294d5d9 1030 uint32_t RESERVED7[8];
Simon Cooksey 0:fb7af294d5d9 1031 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
Simon Cooksey 0:fb7af294d5d9 1032 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
Simon Cooksey 0:fb7af294d5d9 1033 } TPI_Type;
Simon Cooksey 0:fb7af294d5d9 1034
Simon Cooksey 0:fb7af294d5d9 1035 /* TPI Asynchronous Clock Prescaler Register Definitions */
Simon Cooksey 0:fb7af294d5d9 1036 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
Simon Cooksey 0:fb7af294d5d9 1037 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
Simon Cooksey 0:fb7af294d5d9 1038
Simon Cooksey 0:fb7af294d5d9 1039 /* TPI Selected Pin Protocol Register Definitions */
Simon Cooksey 0:fb7af294d5d9 1040 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
Simon Cooksey 0:fb7af294d5d9 1041 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
Simon Cooksey 0:fb7af294d5d9 1042
Simon Cooksey 0:fb7af294d5d9 1043 /* TPI Formatter and Flush Status Register Definitions */
Simon Cooksey 0:fb7af294d5d9 1044 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
Simon Cooksey 0:fb7af294d5d9 1045 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
Simon Cooksey 0:fb7af294d5d9 1046
Simon Cooksey 0:fb7af294d5d9 1047 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
Simon Cooksey 0:fb7af294d5d9 1048 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
Simon Cooksey 0:fb7af294d5d9 1049
Simon Cooksey 0:fb7af294d5d9 1050 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
Simon Cooksey 0:fb7af294d5d9 1051 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
Simon Cooksey 0:fb7af294d5d9 1052
Simon Cooksey 0:fb7af294d5d9 1053 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
Simon Cooksey 0:fb7af294d5d9 1054 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
Simon Cooksey 0:fb7af294d5d9 1055
Simon Cooksey 0:fb7af294d5d9 1056 /* TPI Formatter and Flush Control Register Definitions */
Simon Cooksey 0:fb7af294d5d9 1057 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
Simon Cooksey 0:fb7af294d5d9 1058 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
Simon Cooksey 0:fb7af294d5d9 1059
Simon Cooksey 0:fb7af294d5d9 1060 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
Simon Cooksey 0:fb7af294d5d9 1061 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
Simon Cooksey 0:fb7af294d5d9 1062
Simon Cooksey 0:fb7af294d5d9 1063 /* TPI TRIGGER Register Definitions */
Simon Cooksey 0:fb7af294d5d9 1064 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
Simon Cooksey 0:fb7af294d5d9 1065 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
Simon Cooksey 0:fb7af294d5d9 1066
Simon Cooksey 0:fb7af294d5d9 1067 /* TPI Integration ETM Data Register Definitions (FIFO0) */
Simon Cooksey 0:fb7af294d5d9 1068 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
Simon Cooksey 0:fb7af294d5d9 1069 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
Simon Cooksey 0:fb7af294d5d9 1070
Simon Cooksey 0:fb7af294d5d9 1071 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
Simon Cooksey 0:fb7af294d5d9 1072 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
Simon Cooksey 0:fb7af294d5d9 1073
Simon Cooksey 0:fb7af294d5d9 1074 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
Simon Cooksey 0:fb7af294d5d9 1075 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
Simon Cooksey 0:fb7af294d5d9 1076
Simon Cooksey 0:fb7af294d5d9 1077 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
Simon Cooksey 0:fb7af294d5d9 1078 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
Simon Cooksey 0:fb7af294d5d9 1079
Simon Cooksey 0:fb7af294d5d9 1080 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
Simon Cooksey 0:fb7af294d5d9 1081 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
Simon Cooksey 0:fb7af294d5d9 1082
Simon Cooksey 0:fb7af294d5d9 1083 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
Simon Cooksey 0:fb7af294d5d9 1084 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
Simon Cooksey 0:fb7af294d5d9 1085
Simon Cooksey 0:fb7af294d5d9 1086 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
Simon Cooksey 0:fb7af294d5d9 1087 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
Simon Cooksey 0:fb7af294d5d9 1088
Simon Cooksey 0:fb7af294d5d9 1089 /* TPI ITATBCTR2 Register Definitions */
Simon Cooksey 0:fb7af294d5d9 1090 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
Simon Cooksey 0:fb7af294d5d9 1091 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
Simon Cooksey 0:fb7af294d5d9 1092
Simon Cooksey 0:fb7af294d5d9 1093 /* TPI Integration ITM Data Register Definitions (FIFO1) */
Simon Cooksey 0:fb7af294d5d9 1094 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
Simon Cooksey 0:fb7af294d5d9 1095 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
Simon Cooksey 0:fb7af294d5d9 1096
Simon Cooksey 0:fb7af294d5d9 1097 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
Simon Cooksey 0:fb7af294d5d9 1098 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
Simon Cooksey 0:fb7af294d5d9 1099
Simon Cooksey 0:fb7af294d5d9 1100 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
Simon Cooksey 0:fb7af294d5d9 1101 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
Simon Cooksey 0:fb7af294d5d9 1102
Simon Cooksey 0:fb7af294d5d9 1103 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
Simon Cooksey 0:fb7af294d5d9 1104 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
Simon Cooksey 0:fb7af294d5d9 1105
Simon Cooksey 0:fb7af294d5d9 1106 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
Simon Cooksey 0:fb7af294d5d9 1107 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
Simon Cooksey 0:fb7af294d5d9 1108
Simon Cooksey 0:fb7af294d5d9 1109 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
Simon Cooksey 0:fb7af294d5d9 1110 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
Simon Cooksey 0:fb7af294d5d9 1111
Simon Cooksey 0:fb7af294d5d9 1112 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
Simon Cooksey 0:fb7af294d5d9 1113 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
Simon Cooksey 0:fb7af294d5d9 1114
Simon Cooksey 0:fb7af294d5d9 1115 /* TPI ITATBCTR0 Register Definitions */
Simon Cooksey 0:fb7af294d5d9 1116 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
Simon Cooksey 0:fb7af294d5d9 1117 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
Simon Cooksey 0:fb7af294d5d9 1118
Simon Cooksey 0:fb7af294d5d9 1119 /* TPI Integration Mode Control Register Definitions */
Simon Cooksey 0:fb7af294d5d9 1120 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
Simon Cooksey 0:fb7af294d5d9 1121 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
Simon Cooksey 0:fb7af294d5d9 1122
Simon Cooksey 0:fb7af294d5d9 1123 /* TPI DEVID Register Definitions */
Simon Cooksey 0:fb7af294d5d9 1124 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
Simon Cooksey 0:fb7af294d5d9 1125 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
Simon Cooksey 0:fb7af294d5d9 1126
Simon Cooksey 0:fb7af294d5d9 1127 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
Simon Cooksey 0:fb7af294d5d9 1128 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
Simon Cooksey 0:fb7af294d5d9 1129
Simon Cooksey 0:fb7af294d5d9 1130 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
Simon Cooksey 0:fb7af294d5d9 1131 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
Simon Cooksey 0:fb7af294d5d9 1132
Simon Cooksey 0:fb7af294d5d9 1133 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
Simon Cooksey 0:fb7af294d5d9 1134 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
Simon Cooksey 0:fb7af294d5d9 1135
Simon Cooksey 0:fb7af294d5d9 1136 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
Simon Cooksey 0:fb7af294d5d9 1137 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
Simon Cooksey 0:fb7af294d5d9 1138
Simon Cooksey 0:fb7af294d5d9 1139 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
Simon Cooksey 0:fb7af294d5d9 1140 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
Simon Cooksey 0:fb7af294d5d9 1141
Simon Cooksey 0:fb7af294d5d9 1142 /* TPI DEVTYPE Register Definitions */
Simon Cooksey 0:fb7af294d5d9 1143 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
Simon Cooksey 0:fb7af294d5d9 1144 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
Simon Cooksey 0:fb7af294d5d9 1145
Simon Cooksey 0:fb7af294d5d9 1146 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
Simon Cooksey 0:fb7af294d5d9 1147 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
Simon Cooksey 0:fb7af294d5d9 1148
Simon Cooksey 0:fb7af294d5d9 1149 /*@}*/ /* end of group CMSIS_TPI */
Simon Cooksey 0:fb7af294d5d9 1150
Simon Cooksey 0:fb7af294d5d9 1151
Simon Cooksey 0:fb7af294d5d9 1152 #if (__MPU_PRESENT == 1)
Simon Cooksey 0:fb7af294d5d9 1153 /** \ingroup CMSIS_core_register
Simon Cooksey 0:fb7af294d5d9 1154 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Simon Cooksey 0:fb7af294d5d9 1155 \brief Type definitions for the Memory Protection Unit (MPU)
Simon Cooksey 0:fb7af294d5d9 1156 @{
Simon Cooksey 0:fb7af294d5d9 1157 */
Simon Cooksey 0:fb7af294d5d9 1158
Simon Cooksey 0:fb7af294d5d9 1159 /** \brief Structure type to access the Memory Protection Unit (MPU).
Simon Cooksey 0:fb7af294d5d9 1160 */
Simon Cooksey 0:fb7af294d5d9 1161 typedef struct
Simon Cooksey 0:fb7af294d5d9 1162 {
Simon Cooksey 0:fb7af294d5d9 1163 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Simon Cooksey 0:fb7af294d5d9 1164 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Simon Cooksey 0:fb7af294d5d9 1165 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Simon Cooksey 0:fb7af294d5d9 1166 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Simon Cooksey 0:fb7af294d5d9 1167 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Simon Cooksey 0:fb7af294d5d9 1168 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
Simon Cooksey 0:fb7af294d5d9 1169 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
Simon Cooksey 0:fb7af294d5d9 1170 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
Simon Cooksey 0:fb7af294d5d9 1171 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
Simon Cooksey 0:fb7af294d5d9 1172 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
Simon Cooksey 0:fb7af294d5d9 1173 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
Simon Cooksey 0:fb7af294d5d9 1174 } MPU_Type;
Simon Cooksey 0:fb7af294d5d9 1175
Simon Cooksey 0:fb7af294d5d9 1176 /* MPU Type Register */
Simon Cooksey 0:fb7af294d5d9 1177 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Simon Cooksey 0:fb7af294d5d9 1178 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Simon Cooksey 0:fb7af294d5d9 1179
Simon Cooksey 0:fb7af294d5d9 1180 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Simon Cooksey 0:fb7af294d5d9 1181 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Simon Cooksey 0:fb7af294d5d9 1182
Simon Cooksey 0:fb7af294d5d9 1183 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Simon Cooksey 0:fb7af294d5d9 1184 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Simon Cooksey 0:fb7af294d5d9 1185
Simon Cooksey 0:fb7af294d5d9 1186 /* MPU Control Register */
Simon Cooksey 0:fb7af294d5d9 1187 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Simon Cooksey 0:fb7af294d5d9 1188 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Simon Cooksey 0:fb7af294d5d9 1189
Simon Cooksey 0:fb7af294d5d9 1190 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Simon Cooksey 0:fb7af294d5d9 1191 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Simon Cooksey 0:fb7af294d5d9 1192
Simon Cooksey 0:fb7af294d5d9 1193 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Simon Cooksey 0:fb7af294d5d9 1194 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Simon Cooksey 0:fb7af294d5d9 1195
Simon Cooksey 0:fb7af294d5d9 1196 /* MPU Region Number Register */
Simon Cooksey 0:fb7af294d5d9 1197 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Simon Cooksey 0:fb7af294d5d9 1198 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Simon Cooksey 0:fb7af294d5d9 1199
Simon Cooksey 0:fb7af294d5d9 1200 /* MPU Region Base Address Register */
Simon Cooksey 0:fb7af294d5d9 1201 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
Simon Cooksey 0:fb7af294d5d9 1202 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Simon Cooksey 0:fb7af294d5d9 1203
Simon Cooksey 0:fb7af294d5d9 1204 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Simon Cooksey 0:fb7af294d5d9 1205 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Simon Cooksey 0:fb7af294d5d9 1206
Simon Cooksey 0:fb7af294d5d9 1207 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Simon Cooksey 0:fb7af294d5d9 1208 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Simon Cooksey 0:fb7af294d5d9 1209
Simon Cooksey 0:fb7af294d5d9 1210 /* MPU Region Attribute and Size Register */
Simon Cooksey 0:fb7af294d5d9 1211 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Simon Cooksey 0:fb7af294d5d9 1212 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Simon Cooksey 0:fb7af294d5d9 1213
Simon Cooksey 0:fb7af294d5d9 1214 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Simon Cooksey 0:fb7af294d5d9 1215 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Simon Cooksey 0:fb7af294d5d9 1216
Simon Cooksey 0:fb7af294d5d9 1217 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Simon Cooksey 0:fb7af294d5d9 1218 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Simon Cooksey 0:fb7af294d5d9 1219
Simon Cooksey 0:fb7af294d5d9 1220 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Simon Cooksey 0:fb7af294d5d9 1221 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Simon Cooksey 0:fb7af294d5d9 1222
Simon Cooksey 0:fb7af294d5d9 1223 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Simon Cooksey 0:fb7af294d5d9 1224 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Simon Cooksey 0:fb7af294d5d9 1225
Simon Cooksey 0:fb7af294d5d9 1226 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Simon Cooksey 0:fb7af294d5d9 1227 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Simon Cooksey 0:fb7af294d5d9 1228
Simon Cooksey 0:fb7af294d5d9 1229 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Simon Cooksey 0:fb7af294d5d9 1230 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Simon Cooksey 0:fb7af294d5d9 1231
Simon Cooksey 0:fb7af294d5d9 1232 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Simon Cooksey 0:fb7af294d5d9 1233 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Simon Cooksey 0:fb7af294d5d9 1234
Simon Cooksey 0:fb7af294d5d9 1235 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Simon Cooksey 0:fb7af294d5d9 1236 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Simon Cooksey 0:fb7af294d5d9 1237
Simon Cooksey 0:fb7af294d5d9 1238 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Simon Cooksey 0:fb7af294d5d9 1239 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Simon Cooksey 0:fb7af294d5d9 1240
Simon Cooksey 0:fb7af294d5d9 1241 /*@} end of group CMSIS_MPU */
Simon Cooksey 0:fb7af294d5d9 1242 #endif
Simon Cooksey 0:fb7af294d5d9 1243
Simon Cooksey 0:fb7af294d5d9 1244
Simon Cooksey 0:fb7af294d5d9 1245 #if (__FPU_PRESENT == 1)
Simon Cooksey 0:fb7af294d5d9 1246 /** \ingroup CMSIS_core_register
Simon Cooksey 0:fb7af294d5d9 1247 \defgroup CMSIS_FPU Floating Point Unit (FPU)
Simon Cooksey 0:fb7af294d5d9 1248 \brief Type definitions for the Floating Point Unit (FPU)
Simon Cooksey 0:fb7af294d5d9 1249 @{
Simon Cooksey 0:fb7af294d5d9 1250 */
Simon Cooksey 0:fb7af294d5d9 1251
Simon Cooksey 0:fb7af294d5d9 1252 /** \brief Structure type to access the Floating Point Unit (FPU).
Simon Cooksey 0:fb7af294d5d9 1253 */
Simon Cooksey 0:fb7af294d5d9 1254 typedef struct
Simon Cooksey 0:fb7af294d5d9 1255 {
Simon Cooksey 0:fb7af294d5d9 1256 uint32_t RESERVED0[1];
Simon Cooksey 0:fb7af294d5d9 1257 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
Simon Cooksey 0:fb7af294d5d9 1258 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
Simon Cooksey 0:fb7af294d5d9 1259 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
Simon Cooksey 0:fb7af294d5d9 1260 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
Simon Cooksey 0:fb7af294d5d9 1261 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
Simon Cooksey 0:fb7af294d5d9 1262 } FPU_Type;
Simon Cooksey 0:fb7af294d5d9 1263
Simon Cooksey 0:fb7af294d5d9 1264 /* Floating-Point Context Control Register */
Simon Cooksey 0:fb7af294d5d9 1265 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
Simon Cooksey 0:fb7af294d5d9 1266 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
Simon Cooksey 0:fb7af294d5d9 1267
Simon Cooksey 0:fb7af294d5d9 1268 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
Simon Cooksey 0:fb7af294d5d9 1269 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
Simon Cooksey 0:fb7af294d5d9 1270
Simon Cooksey 0:fb7af294d5d9 1271 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
Simon Cooksey 0:fb7af294d5d9 1272 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
Simon Cooksey 0:fb7af294d5d9 1273
Simon Cooksey 0:fb7af294d5d9 1274 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
Simon Cooksey 0:fb7af294d5d9 1275 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
Simon Cooksey 0:fb7af294d5d9 1276
Simon Cooksey 0:fb7af294d5d9 1277 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
Simon Cooksey 0:fb7af294d5d9 1278 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
Simon Cooksey 0:fb7af294d5d9 1279
Simon Cooksey 0:fb7af294d5d9 1280 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
Simon Cooksey 0:fb7af294d5d9 1281 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
Simon Cooksey 0:fb7af294d5d9 1282
Simon Cooksey 0:fb7af294d5d9 1283 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
Simon Cooksey 0:fb7af294d5d9 1284 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
Simon Cooksey 0:fb7af294d5d9 1285
Simon Cooksey 0:fb7af294d5d9 1286 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
Simon Cooksey 0:fb7af294d5d9 1287 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
Simon Cooksey 0:fb7af294d5d9 1288
Simon Cooksey 0:fb7af294d5d9 1289 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
Simon Cooksey 0:fb7af294d5d9 1290 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
Simon Cooksey 0:fb7af294d5d9 1291
Simon Cooksey 0:fb7af294d5d9 1292 /* Floating-Point Context Address Register */
Simon Cooksey 0:fb7af294d5d9 1293 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
Simon Cooksey 0:fb7af294d5d9 1294 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
Simon Cooksey 0:fb7af294d5d9 1295
Simon Cooksey 0:fb7af294d5d9 1296 /* Floating-Point Default Status Control Register */
Simon Cooksey 0:fb7af294d5d9 1297 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
Simon Cooksey 0:fb7af294d5d9 1298 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
Simon Cooksey 0:fb7af294d5d9 1299
Simon Cooksey 0:fb7af294d5d9 1300 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
Simon Cooksey 0:fb7af294d5d9 1301 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
Simon Cooksey 0:fb7af294d5d9 1302
Simon Cooksey 0:fb7af294d5d9 1303 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
Simon Cooksey 0:fb7af294d5d9 1304 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
Simon Cooksey 0:fb7af294d5d9 1305
Simon Cooksey 0:fb7af294d5d9 1306 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
Simon Cooksey 0:fb7af294d5d9 1307 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
Simon Cooksey 0:fb7af294d5d9 1308
Simon Cooksey 0:fb7af294d5d9 1309 /* Media and FP Feature Register 0 */
Simon Cooksey 0:fb7af294d5d9 1310 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
Simon Cooksey 0:fb7af294d5d9 1311 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
Simon Cooksey 0:fb7af294d5d9 1312
Simon Cooksey 0:fb7af294d5d9 1313 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
Simon Cooksey 0:fb7af294d5d9 1314 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
Simon Cooksey 0:fb7af294d5d9 1315
Simon Cooksey 0:fb7af294d5d9 1316 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
Simon Cooksey 0:fb7af294d5d9 1317 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
Simon Cooksey 0:fb7af294d5d9 1318
Simon Cooksey 0:fb7af294d5d9 1319 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
Simon Cooksey 0:fb7af294d5d9 1320 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
Simon Cooksey 0:fb7af294d5d9 1321
Simon Cooksey 0:fb7af294d5d9 1322 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
Simon Cooksey 0:fb7af294d5d9 1323 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
Simon Cooksey 0:fb7af294d5d9 1324
Simon Cooksey 0:fb7af294d5d9 1325 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
Simon Cooksey 0:fb7af294d5d9 1326 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
Simon Cooksey 0:fb7af294d5d9 1327
Simon Cooksey 0:fb7af294d5d9 1328 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
Simon Cooksey 0:fb7af294d5d9 1329 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
Simon Cooksey 0:fb7af294d5d9 1330
Simon Cooksey 0:fb7af294d5d9 1331 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
Simon Cooksey 0:fb7af294d5d9 1332 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
Simon Cooksey 0:fb7af294d5d9 1333
Simon Cooksey 0:fb7af294d5d9 1334 /* Media and FP Feature Register 1 */
Simon Cooksey 0:fb7af294d5d9 1335 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
Simon Cooksey 0:fb7af294d5d9 1336 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
Simon Cooksey 0:fb7af294d5d9 1337
Simon Cooksey 0:fb7af294d5d9 1338 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
Simon Cooksey 0:fb7af294d5d9 1339 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
Simon Cooksey 0:fb7af294d5d9 1340
Simon Cooksey 0:fb7af294d5d9 1341 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
Simon Cooksey 0:fb7af294d5d9 1342 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
Simon Cooksey 0:fb7af294d5d9 1343
Simon Cooksey 0:fb7af294d5d9 1344 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
Simon Cooksey 0:fb7af294d5d9 1345 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
Simon Cooksey 0:fb7af294d5d9 1346
Simon Cooksey 0:fb7af294d5d9 1347 /*@} end of group CMSIS_FPU */
Simon Cooksey 0:fb7af294d5d9 1348 #endif
Simon Cooksey 0:fb7af294d5d9 1349
Simon Cooksey 0:fb7af294d5d9 1350
Simon Cooksey 0:fb7af294d5d9 1351 /** \ingroup CMSIS_core_register
Simon Cooksey 0:fb7af294d5d9 1352 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Simon Cooksey 0:fb7af294d5d9 1353 \brief Type definitions for the Core Debug Registers
Simon Cooksey 0:fb7af294d5d9 1354 @{
Simon Cooksey 0:fb7af294d5d9 1355 */
Simon Cooksey 0:fb7af294d5d9 1356
Simon Cooksey 0:fb7af294d5d9 1357 /** \brief Structure type to access the Core Debug Register (CoreDebug).
Simon Cooksey 0:fb7af294d5d9 1358 */
Simon Cooksey 0:fb7af294d5d9 1359 typedef struct
Simon Cooksey 0:fb7af294d5d9 1360 {
Simon Cooksey 0:fb7af294d5d9 1361 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
Simon Cooksey 0:fb7af294d5d9 1362 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
Simon Cooksey 0:fb7af294d5d9 1363 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
Simon Cooksey 0:fb7af294d5d9 1364 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
Simon Cooksey 0:fb7af294d5d9 1365 } CoreDebug_Type;
Simon Cooksey 0:fb7af294d5d9 1366
Simon Cooksey 0:fb7af294d5d9 1367 /* Debug Halting Control and Status Register */
Simon Cooksey 0:fb7af294d5d9 1368 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
Simon Cooksey 0:fb7af294d5d9 1369 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
Simon Cooksey 0:fb7af294d5d9 1370
Simon Cooksey 0:fb7af294d5d9 1371 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
Simon Cooksey 0:fb7af294d5d9 1372 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
Simon Cooksey 0:fb7af294d5d9 1373
Simon Cooksey 0:fb7af294d5d9 1374 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
Simon Cooksey 0:fb7af294d5d9 1375 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
Simon Cooksey 0:fb7af294d5d9 1376
Simon Cooksey 0:fb7af294d5d9 1377 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
Simon Cooksey 0:fb7af294d5d9 1378 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
Simon Cooksey 0:fb7af294d5d9 1379
Simon Cooksey 0:fb7af294d5d9 1380 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
Simon Cooksey 0:fb7af294d5d9 1381 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
Simon Cooksey 0:fb7af294d5d9 1382
Simon Cooksey 0:fb7af294d5d9 1383 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
Simon Cooksey 0:fb7af294d5d9 1384 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
Simon Cooksey 0:fb7af294d5d9 1385
Simon Cooksey 0:fb7af294d5d9 1386 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
Simon Cooksey 0:fb7af294d5d9 1387 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
Simon Cooksey 0:fb7af294d5d9 1388
Simon Cooksey 0:fb7af294d5d9 1389 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
Simon Cooksey 0:fb7af294d5d9 1390 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
Simon Cooksey 0:fb7af294d5d9 1391
Simon Cooksey 0:fb7af294d5d9 1392 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
Simon Cooksey 0:fb7af294d5d9 1393 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
Simon Cooksey 0:fb7af294d5d9 1394
Simon Cooksey 0:fb7af294d5d9 1395 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
Simon Cooksey 0:fb7af294d5d9 1396 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
Simon Cooksey 0:fb7af294d5d9 1397
Simon Cooksey 0:fb7af294d5d9 1398 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
Simon Cooksey 0:fb7af294d5d9 1399 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
Simon Cooksey 0:fb7af294d5d9 1400
Simon Cooksey 0:fb7af294d5d9 1401 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Simon Cooksey 0:fb7af294d5d9 1402 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
Simon Cooksey 0:fb7af294d5d9 1403
Simon Cooksey 0:fb7af294d5d9 1404 /* Debug Core Register Selector Register */
Simon Cooksey 0:fb7af294d5d9 1405 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
Simon Cooksey 0:fb7af294d5d9 1406 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
Simon Cooksey 0:fb7af294d5d9 1407
Simon Cooksey 0:fb7af294d5d9 1408 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
Simon Cooksey 0:fb7af294d5d9 1409 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
Simon Cooksey 0:fb7af294d5d9 1410
Simon Cooksey 0:fb7af294d5d9 1411 /* Debug Exception and Monitor Control Register */
Simon Cooksey 0:fb7af294d5d9 1412 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
Simon Cooksey 0:fb7af294d5d9 1413 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
Simon Cooksey 0:fb7af294d5d9 1414
Simon Cooksey 0:fb7af294d5d9 1415 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
Simon Cooksey 0:fb7af294d5d9 1416 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
Simon Cooksey 0:fb7af294d5d9 1417
Simon Cooksey 0:fb7af294d5d9 1418 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
Simon Cooksey 0:fb7af294d5d9 1419 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
Simon Cooksey 0:fb7af294d5d9 1420
Simon Cooksey 0:fb7af294d5d9 1421 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
Simon Cooksey 0:fb7af294d5d9 1422 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
Simon Cooksey 0:fb7af294d5d9 1423
Simon Cooksey 0:fb7af294d5d9 1424 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
Simon Cooksey 0:fb7af294d5d9 1425 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
Simon Cooksey 0:fb7af294d5d9 1426
Simon Cooksey 0:fb7af294d5d9 1427 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
Simon Cooksey 0:fb7af294d5d9 1428 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
Simon Cooksey 0:fb7af294d5d9 1429
Simon Cooksey 0:fb7af294d5d9 1430 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
Simon Cooksey 0:fb7af294d5d9 1431 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
Simon Cooksey 0:fb7af294d5d9 1432
Simon Cooksey 0:fb7af294d5d9 1433 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
Simon Cooksey 0:fb7af294d5d9 1434 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
Simon Cooksey 0:fb7af294d5d9 1435
Simon Cooksey 0:fb7af294d5d9 1436 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
Simon Cooksey 0:fb7af294d5d9 1437 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
Simon Cooksey 0:fb7af294d5d9 1438
Simon Cooksey 0:fb7af294d5d9 1439 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
Simon Cooksey 0:fb7af294d5d9 1440 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
Simon Cooksey 0:fb7af294d5d9 1441
Simon Cooksey 0:fb7af294d5d9 1442 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
Simon Cooksey 0:fb7af294d5d9 1443 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
Simon Cooksey 0:fb7af294d5d9 1444
Simon Cooksey 0:fb7af294d5d9 1445 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
Simon Cooksey 0:fb7af294d5d9 1446 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
Simon Cooksey 0:fb7af294d5d9 1447
Simon Cooksey 0:fb7af294d5d9 1448 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
Simon Cooksey 0:fb7af294d5d9 1449 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
Simon Cooksey 0:fb7af294d5d9 1450
Simon Cooksey 0:fb7af294d5d9 1451 /*@} end of group CMSIS_CoreDebug */
Simon Cooksey 0:fb7af294d5d9 1452
Simon Cooksey 0:fb7af294d5d9 1453
Simon Cooksey 0:fb7af294d5d9 1454 /** \ingroup CMSIS_core_register
Simon Cooksey 0:fb7af294d5d9 1455 \defgroup CMSIS_core_base Core Definitions
Simon Cooksey 0:fb7af294d5d9 1456 \brief Definitions for base addresses, unions, and structures.
Simon Cooksey 0:fb7af294d5d9 1457 @{
Simon Cooksey 0:fb7af294d5d9 1458 */
Simon Cooksey 0:fb7af294d5d9 1459
Simon Cooksey 0:fb7af294d5d9 1460 /* Memory mapping of Cortex-M4 Hardware */
Simon Cooksey 0:fb7af294d5d9 1461 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Simon Cooksey 0:fb7af294d5d9 1462 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
Simon Cooksey 0:fb7af294d5d9 1463 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
Simon Cooksey 0:fb7af294d5d9 1464 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
Simon Cooksey 0:fb7af294d5d9 1465 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
Simon Cooksey 0:fb7af294d5d9 1466 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Simon Cooksey 0:fb7af294d5d9 1467 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Simon Cooksey 0:fb7af294d5d9 1468 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Simon Cooksey 0:fb7af294d5d9 1469
Simon Cooksey 0:fb7af294d5d9 1470 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
Simon Cooksey 0:fb7af294d5d9 1471 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Simon Cooksey 0:fb7af294d5d9 1472 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Simon Cooksey 0:fb7af294d5d9 1473 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Simon Cooksey 0:fb7af294d5d9 1474 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
Simon Cooksey 0:fb7af294d5d9 1475 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
Simon Cooksey 0:fb7af294d5d9 1476 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
Simon Cooksey 0:fb7af294d5d9 1477 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
Simon Cooksey 0:fb7af294d5d9 1478
Simon Cooksey 0:fb7af294d5d9 1479 #if (__MPU_PRESENT == 1)
Simon Cooksey 0:fb7af294d5d9 1480 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Simon Cooksey 0:fb7af294d5d9 1481 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Simon Cooksey 0:fb7af294d5d9 1482 #endif
Simon Cooksey 0:fb7af294d5d9 1483
Simon Cooksey 0:fb7af294d5d9 1484 #if (__FPU_PRESENT == 1)
Simon Cooksey 0:fb7af294d5d9 1485 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
Simon Cooksey 0:fb7af294d5d9 1486 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
Simon Cooksey 0:fb7af294d5d9 1487 #endif
Simon Cooksey 0:fb7af294d5d9 1488
Simon Cooksey 0:fb7af294d5d9 1489 /*@} */
Simon Cooksey 0:fb7af294d5d9 1490
Simon Cooksey 0:fb7af294d5d9 1491
Simon Cooksey 0:fb7af294d5d9 1492
Simon Cooksey 0:fb7af294d5d9 1493 /*******************************************************************************
Simon Cooksey 0:fb7af294d5d9 1494 * Hardware Abstraction Layer
Simon Cooksey 0:fb7af294d5d9 1495 Core Function Interface contains:
Simon Cooksey 0:fb7af294d5d9 1496 - Core NVIC Functions
Simon Cooksey 0:fb7af294d5d9 1497 - Core SysTick Functions
Simon Cooksey 0:fb7af294d5d9 1498 - Core Debug Functions
Simon Cooksey 0:fb7af294d5d9 1499 - Core Register Access Functions
Simon Cooksey 0:fb7af294d5d9 1500 ******************************************************************************/
Simon Cooksey 0:fb7af294d5d9 1501 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Simon Cooksey 0:fb7af294d5d9 1502 */
Simon Cooksey 0:fb7af294d5d9 1503
Simon Cooksey 0:fb7af294d5d9 1504
Simon Cooksey 0:fb7af294d5d9 1505
Simon Cooksey 0:fb7af294d5d9 1506 /* ########################## NVIC functions #################################### */
Simon Cooksey 0:fb7af294d5d9 1507 /** \ingroup CMSIS_Core_FunctionInterface
Simon Cooksey 0:fb7af294d5d9 1508 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Simon Cooksey 0:fb7af294d5d9 1509 \brief Functions that manage interrupts and exceptions via the NVIC.
Simon Cooksey 0:fb7af294d5d9 1510 @{
Simon Cooksey 0:fb7af294d5d9 1511 */
Simon Cooksey 0:fb7af294d5d9 1512
Simon Cooksey 0:fb7af294d5d9 1513 #ifdef CMSIS_NVIC_VIRTUAL
Simon Cooksey 0:fb7af294d5d9 1514 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Simon Cooksey 0:fb7af294d5d9 1515 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Simon Cooksey 0:fb7af294d5d9 1516 #endif
Simon Cooksey 0:fb7af294d5d9 1517 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Simon Cooksey 0:fb7af294d5d9 1518 #else
Simon Cooksey 0:fb7af294d5d9 1519 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
Simon Cooksey 0:fb7af294d5d9 1520 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
Simon Cooksey 0:fb7af294d5d9 1521 #define NVIC_EnableIRQ __NVIC_EnableIRQ
Simon Cooksey 0:fb7af294d5d9 1522 #define NVIC_DisableIRQ __NVIC_DisableIRQ
Simon Cooksey 0:fb7af294d5d9 1523 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Simon Cooksey 0:fb7af294d5d9 1524 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Simon Cooksey 0:fb7af294d5d9 1525 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Simon Cooksey 0:fb7af294d5d9 1526 #define NVIC_GetActive __NVIC_GetActive
Simon Cooksey 0:fb7af294d5d9 1527 #define NVIC_SetPriority __NVIC_SetPriority
Simon Cooksey 0:fb7af294d5d9 1528 #define NVIC_GetPriority __NVIC_GetPriority
Simon Cooksey 0:fb7af294d5d9 1529 #define NVIC_SystemReset __NVIC_SystemReset
Simon Cooksey 0:fb7af294d5d9 1530 #endif /* CMSIS_NVIC_VIRTUAL */
Simon Cooksey 0:fb7af294d5d9 1531
Simon Cooksey 0:fb7af294d5d9 1532 #ifdef CMSIS_VECTAB_VIRTUAL
Simon Cooksey 0:fb7af294d5d9 1533 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Simon Cooksey 0:fb7af294d5d9 1534 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Simon Cooksey 0:fb7af294d5d9 1535 #endif
Simon Cooksey 0:fb7af294d5d9 1536 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Simon Cooksey 0:fb7af294d5d9 1537 #else
Simon Cooksey 0:fb7af294d5d9 1538 #define NVIC_SetVector __NVIC_SetVector
Simon Cooksey 0:fb7af294d5d9 1539 #define NVIC_GetVector __NVIC_GetVector
Simon Cooksey 0:fb7af294d5d9 1540 #endif /* CMSIS_VECTAB_VIRTUAL */
Simon Cooksey 0:fb7af294d5d9 1541
Simon Cooksey 0:fb7af294d5d9 1542
Simon Cooksey 0:fb7af294d5d9 1543 /** \brief Set Priority Grouping
Simon Cooksey 0:fb7af294d5d9 1544
Simon Cooksey 0:fb7af294d5d9 1545 The function sets the priority grouping field using the required unlock sequence.
Simon Cooksey 0:fb7af294d5d9 1546 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Simon Cooksey 0:fb7af294d5d9 1547 Only values from 0..7 are used.
Simon Cooksey 0:fb7af294d5d9 1548 In case of a conflict between priority grouping and available
Simon Cooksey 0:fb7af294d5d9 1549 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Simon Cooksey 0:fb7af294d5d9 1550
Simon Cooksey 0:fb7af294d5d9 1551 \param [in] PriorityGroup Priority grouping field.
Simon Cooksey 0:fb7af294d5d9 1552 */
Simon Cooksey 0:fb7af294d5d9 1553 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Simon Cooksey 0:fb7af294d5d9 1554 {
Simon Cooksey 0:fb7af294d5d9 1555 uint32_t reg_value;
Simon Cooksey 0:fb7af294d5d9 1556 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Simon Cooksey 0:fb7af294d5d9 1557
Simon Cooksey 0:fb7af294d5d9 1558 reg_value = SCB->AIRCR; /* read old register configuration */
Simon Cooksey 0:fb7af294d5d9 1559 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Simon Cooksey 0:fb7af294d5d9 1560 reg_value = (reg_value |
Simon Cooksey 0:fb7af294d5d9 1561 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Simon Cooksey 0:fb7af294d5d9 1562 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
Simon Cooksey 0:fb7af294d5d9 1563 SCB->AIRCR = reg_value;
Simon Cooksey 0:fb7af294d5d9 1564 }
Simon Cooksey 0:fb7af294d5d9 1565
Simon Cooksey 0:fb7af294d5d9 1566
Simon Cooksey 0:fb7af294d5d9 1567 /** \brief Get Priority Grouping
Simon Cooksey 0:fb7af294d5d9 1568
Simon Cooksey 0:fb7af294d5d9 1569 The function reads the priority grouping field from the NVIC Interrupt Controller.
Simon Cooksey 0:fb7af294d5d9 1570
Simon Cooksey 0:fb7af294d5d9 1571 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Simon Cooksey 0:fb7af294d5d9 1572 */
Simon Cooksey 0:fb7af294d5d9 1573 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Simon Cooksey 0:fb7af294d5d9 1574 {
Simon Cooksey 0:fb7af294d5d9 1575 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Simon Cooksey 0:fb7af294d5d9 1576 }
Simon Cooksey 0:fb7af294d5d9 1577
Simon Cooksey 0:fb7af294d5d9 1578
Simon Cooksey 0:fb7af294d5d9 1579 /** \brief Enable External Interrupt
Simon Cooksey 0:fb7af294d5d9 1580
Simon Cooksey 0:fb7af294d5d9 1581 The function enables a device-specific interrupt in the NVIC interrupt controller.
Simon Cooksey 0:fb7af294d5d9 1582
Simon Cooksey 0:fb7af294d5d9 1583 \param [in] IRQn External interrupt number. Value cannot be negative.
Simon Cooksey 0:fb7af294d5d9 1584 */
Simon Cooksey 0:fb7af294d5d9 1585 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Simon Cooksey 0:fb7af294d5d9 1586 {
Simon Cooksey 0:fb7af294d5d9 1587 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Simon Cooksey 0:fb7af294d5d9 1588 }
Simon Cooksey 0:fb7af294d5d9 1589
Simon Cooksey 0:fb7af294d5d9 1590
Simon Cooksey 0:fb7af294d5d9 1591 /** \brief Disable External Interrupt
Simon Cooksey 0:fb7af294d5d9 1592
Simon Cooksey 0:fb7af294d5d9 1593 The function disables a device-specific interrupt in the NVIC interrupt controller.
Simon Cooksey 0:fb7af294d5d9 1594
Simon Cooksey 0:fb7af294d5d9 1595 \param [in] IRQn External interrupt number. Value cannot be negative.
Simon Cooksey 0:fb7af294d5d9 1596 */
Simon Cooksey 0:fb7af294d5d9 1597 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Simon Cooksey 0:fb7af294d5d9 1598 {
Simon Cooksey 0:fb7af294d5d9 1599 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Simon Cooksey 0:fb7af294d5d9 1600 }
Simon Cooksey 0:fb7af294d5d9 1601
Simon Cooksey 0:fb7af294d5d9 1602
Simon Cooksey 0:fb7af294d5d9 1603 /** \brief Get Pending Interrupt
Simon Cooksey 0:fb7af294d5d9 1604
Simon Cooksey 0:fb7af294d5d9 1605 The function reads the pending register in the NVIC and returns the pending bit
Simon Cooksey 0:fb7af294d5d9 1606 for the specified interrupt.
Simon Cooksey 0:fb7af294d5d9 1607
Simon Cooksey 0:fb7af294d5d9 1608 \param [in] IRQn Interrupt number.
Simon Cooksey 0:fb7af294d5d9 1609
Simon Cooksey 0:fb7af294d5d9 1610 \return 0 Interrupt status is not pending.
Simon Cooksey 0:fb7af294d5d9 1611 \return 1 Interrupt status is pending.
Simon Cooksey 0:fb7af294d5d9 1612 */
Simon Cooksey 0:fb7af294d5d9 1613 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Simon Cooksey 0:fb7af294d5d9 1614 {
Simon Cooksey 0:fb7af294d5d9 1615 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Simon Cooksey 0:fb7af294d5d9 1616 }
Simon Cooksey 0:fb7af294d5d9 1617
Simon Cooksey 0:fb7af294d5d9 1618
Simon Cooksey 0:fb7af294d5d9 1619 /** \brief Set Pending Interrupt
Simon Cooksey 0:fb7af294d5d9 1620
Simon Cooksey 0:fb7af294d5d9 1621 The function sets the pending bit of an external interrupt.
Simon Cooksey 0:fb7af294d5d9 1622
Simon Cooksey 0:fb7af294d5d9 1623 \param [in] IRQn Interrupt number. Value cannot be negative.
Simon Cooksey 0:fb7af294d5d9 1624 */
Simon Cooksey 0:fb7af294d5d9 1625 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Simon Cooksey 0:fb7af294d5d9 1626 {
Simon Cooksey 0:fb7af294d5d9 1627 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Simon Cooksey 0:fb7af294d5d9 1628 }
Simon Cooksey 0:fb7af294d5d9 1629
Simon Cooksey 0:fb7af294d5d9 1630
Simon Cooksey 0:fb7af294d5d9 1631 /** \brief Clear Pending Interrupt
Simon Cooksey 0:fb7af294d5d9 1632
Simon Cooksey 0:fb7af294d5d9 1633 The function clears the pending bit of an external interrupt.
Simon Cooksey 0:fb7af294d5d9 1634
Simon Cooksey 0:fb7af294d5d9 1635 \param [in] IRQn External interrupt number. Value cannot be negative.
Simon Cooksey 0:fb7af294d5d9 1636 */
Simon Cooksey 0:fb7af294d5d9 1637 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Simon Cooksey 0:fb7af294d5d9 1638 {
Simon Cooksey 0:fb7af294d5d9 1639 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Simon Cooksey 0:fb7af294d5d9 1640 }
Simon Cooksey 0:fb7af294d5d9 1641
Simon Cooksey 0:fb7af294d5d9 1642
Simon Cooksey 0:fb7af294d5d9 1643 /** \brief Get Active Interrupt
Simon Cooksey 0:fb7af294d5d9 1644
Simon Cooksey 0:fb7af294d5d9 1645 The function reads the active register in NVIC and returns the active bit.
Simon Cooksey 0:fb7af294d5d9 1646
Simon Cooksey 0:fb7af294d5d9 1647 \param [in] IRQn Interrupt number.
Simon Cooksey 0:fb7af294d5d9 1648
Simon Cooksey 0:fb7af294d5d9 1649 \return 0 Interrupt status is not active.
Simon Cooksey 0:fb7af294d5d9 1650 \return 1 Interrupt status is active.
Simon Cooksey 0:fb7af294d5d9 1651 */
Simon Cooksey 0:fb7af294d5d9 1652 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Simon Cooksey 0:fb7af294d5d9 1653 {
Simon Cooksey 0:fb7af294d5d9 1654 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Simon Cooksey 0:fb7af294d5d9 1655 }
Simon Cooksey 0:fb7af294d5d9 1656
Simon Cooksey 0:fb7af294d5d9 1657
Simon Cooksey 0:fb7af294d5d9 1658 /** \brief Set Interrupt Priority
Simon Cooksey 0:fb7af294d5d9 1659
Simon Cooksey 0:fb7af294d5d9 1660 The function sets the priority of an interrupt.
Simon Cooksey 0:fb7af294d5d9 1661
Simon Cooksey 0:fb7af294d5d9 1662 \note The priority cannot be set for every core interrupt.
Simon Cooksey 0:fb7af294d5d9 1663
Simon Cooksey 0:fb7af294d5d9 1664 \param [in] IRQn Interrupt number.
Simon Cooksey 0:fb7af294d5d9 1665 \param [in] priority Priority to set.
Simon Cooksey 0:fb7af294d5d9 1666 */
Simon Cooksey 0:fb7af294d5d9 1667 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Simon Cooksey 0:fb7af294d5d9 1668 {
Simon Cooksey 0:fb7af294d5d9 1669 if((int32_t)IRQn < 0) {
Simon Cooksey 0:fb7af294d5d9 1670 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Simon Cooksey 0:fb7af294d5d9 1671 }
Simon Cooksey 0:fb7af294d5d9 1672 else {
Simon Cooksey 0:fb7af294d5d9 1673 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Simon Cooksey 0:fb7af294d5d9 1674 }
Simon Cooksey 0:fb7af294d5d9 1675 }
Simon Cooksey 0:fb7af294d5d9 1676
Simon Cooksey 0:fb7af294d5d9 1677
Simon Cooksey 0:fb7af294d5d9 1678 /** \brief Get Interrupt Priority
Simon Cooksey 0:fb7af294d5d9 1679
Simon Cooksey 0:fb7af294d5d9 1680 The function reads the priority of an interrupt. The interrupt
Simon Cooksey 0:fb7af294d5d9 1681 number can be positive to specify an external (device specific)
Simon Cooksey 0:fb7af294d5d9 1682 interrupt, or negative to specify an internal (core) interrupt.
Simon Cooksey 0:fb7af294d5d9 1683
Simon Cooksey 0:fb7af294d5d9 1684
Simon Cooksey 0:fb7af294d5d9 1685 \param [in] IRQn Interrupt number.
Simon Cooksey 0:fb7af294d5d9 1686 \return Interrupt Priority. Value is aligned automatically to the implemented
Simon Cooksey 0:fb7af294d5d9 1687 priority bits of the microcontroller.
Simon Cooksey 0:fb7af294d5d9 1688 */
Simon Cooksey 0:fb7af294d5d9 1689 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Simon Cooksey 0:fb7af294d5d9 1690 {
Simon Cooksey 0:fb7af294d5d9 1691
Simon Cooksey 0:fb7af294d5d9 1692 if((int32_t)IRQn < 0) {
Simon Cooksey 0:fb7af294d5d9 1693 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Simon Cooksey 0:fb7af294d5d9 1694 }
Simon Cooksey 0:fb7af294d5d9 1695 else {
Simon Cooksey 0:fb7af294d5d9 1696 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Simon Cooksey 0:fb7af294d5d9 1697 }
Simon Cooksey 0:fb7af294d5d9 1698 }
Simon Cooksey 0:fb7af294d5d9 1699
Simon Cooksey 0:fb7af294d5d9 1700
Simon Cooksey 0:fb7af294d5d9 1701 /** \brief Encode Priority
Simon Cooksey 0:fb7af294d5d9 1702
Simon Cooksey 0:fb7af294d5d9 1703 The function encodes the priority for an interrupt with the given priority group,
Simon Cooksey 0:fb7af294d5d9 1704 preemptive priority value, and subpriority value.
Simon Cooksey 0:fb7af294d5d9 1705 In case of a conflict between priority grouping and available
Simon Cooksey 0:fb7af294d5d9 1706 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Simon Cooksey 0:fb7af294d5d9 1707
Simon Cooksey 0:fb7af294d5d9 1708 \param [in] PriorityGroup Used priority group.
Simon Cooksey 0:fb7af294d5d9 1709 \param [in] PreemptPriority Preemptive priority value (starting from 0).
Simon Cooksey 0:fb7af294d5d9 1710 \param [in] SubPriority Subpriority value (starting from 0).
Simon Cooksey 0:fb7af294d5d9 1711 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Simon Cooksey 0:fb7af294d5d9 1712 */
Simon Cooksey 0:fb7af294d5d9 1713 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Simon Cooksey 0:fb7af294d5d9 1714 {
Simon Cooksey 0:fb7af294d5d9 1715 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Simon Cooksey 0:fb7af294d5d9 1716 uint32_t PreemptPriorityBits;
Simon Cooksey 0:fb7af294d5d9 1717 uint32_t SubPriorityBits;
Simon Cooksey 0:fb7af294d5d9 1718
Simon Cooksey 0:fb7af294d5d9 1719 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Simon Cooksey 0:fb7af294d5d9 1720 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Simon Cooksey 0:fb7af294d5d9 1721
Simon Cooksey 0:fb7af294d5d9 1722 return (
Simon Cooksey 0:fb7af294d5d9 1723 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
Simon Cooksey 0:fb7af294d5d9 1724 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Simon Cooksey 0:fb7af294d5d9 1725 );
Simon Cooksey 0:fb7af294d5d9 1726 }
Simon Cooksey 0:fb7af294d5d9 1727
Simon Cooksey 0:fb7af294d5d9 1728
Simon Cooksey 0:fb7af294d5d9 1729 /** \brief Decode Priority
Simon Cooksey 0:fb7af294d5d9 1730
Simon Cooksey 0:fb7af294d5d9 1731 The function decodes an interrupt priority value with a given priority group to
Simon Cooksey 0:fb7af294d5d9 1732 preemptive priority value and subpriority value.
Simon Cooksey 0:fb7af294d5d9 1733 In case of a conflict between priority grouping and available
Simon Cooksey 0:fb7af294d5d9 1734 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Simon Cooksey 0:fb7af294d5d9 1735
Simon Cooksey 0:fb7af294d5d9 1736 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Simon Cooksey 0:fb7af294d5d9 1737 \param [in] PriorityGroup Used priority group.
Simon Cooksey 0:fb7af294d5d9 1738 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
Simon Cooksey 0:fb7af294d5d9 1739 \param [out] pSubPriority Subpriority value (starting from 0).
Simon Cooksey 0:fb7af294d5d9 1740 */
Simon Cooksey 0:fb7af294d5d9 1741 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Simon Cooksey 0:fb7af294d5d9 1742 {
Simon Cooksey 0:fb7af294d5d9 1743 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Simon Cooksey 0:fb7af294d5d9 1744 uint32_t PreemptPriorityBits;
Simon Cooksey 0:fb7af294d5d9 1745 uint32_t SubPriorityBits;
Simon Cooksey 0:fb7af294d5d9 1746
Simon Cooksey 0:fb7af294d5d9 1747 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Simon Cooksey 0:fb7af294d5d9 1748 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Simon Cooksey 0:fb7af294d5d9 1749
Simon Cooksey 0:fb7af294d5d9 1750 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Simon Cooksey 0:fb7af294d5d9 1751 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Simon Cooksey 0:fb7af294d5d9 1752 }
Simon Cooksey 0:fb7af294d5d9 1753
Simon Cooksey 0:fb7af294d5d9 1754
Simon Cooksey 0:fb7af294d5d9 1755 /** \brief System Reset
Simon Cooksey 0:fb7af294d5d9 1756
Simon Cooksey 0:fb7af294d5d9 1757 The function initiates a system reset request to reset the MCU.
Simon Cooksey 0:fb7af294d5d9 1758 */
Simon Cooksey 0:fb7af294d5d9 1759 __STATIC_INLINE void __NVIC_SystemReset(void)
Simon Cooksey 0:fb7af294d5d9 1760 {
Simon Cooksey 0:fb7af294d5d9 1761 __DSB(); /* Ensure all outstanding memory accesses included
Simon Cooksey 0:fb7af294d5d9 1762 buffered write are completed before reset */
Simon Cooksey 0:fb7af294d5d9 1763 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Simon Cooksey 0:fb7af294d5d9 1764 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
Simon Cooksey 0:fb7af294d5d9 1765 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Simon Cooksey 0:fb7af294d5d9 1766 __DSB(); /* Ensure completion of memory access */
Simon Cooksey 0:fb7af294d5d9 1767 while(1) { __NOP(); } /* wait until reset */
Simon Cooksey 0:fb7af294d5d9 1768 }
Simon Cooksey 0:fb7af294d5d9 1769
Simon Cooksey 0:fb7af294d5d9 1770 /*@} end of CMSIS_Core_NVICFunctions */
Simon Cooksey 0:fb7af294d5d9 1771
Simon Cooksey 0:fb7af294d5d9 1772
Simon Cooksey 0:fb7af294d5d9 1773
Simon Cooksey 0:fb7af294d5d9 1774 /* ################################## SysTick function ############################################ */
Simon Cooksey 0:fb7af294d5d9 1775 /** \ingroup CMSIS_Core_FunctionInterface
Simon Cooksey 0:fb7af294d5d9 1776 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Simon Cooksey 0:fb7af294d5d9 1777 \brief Functions that configure the System.
Simon Cooksey 0:fb7af294d5d9 1778 @{
Simon Cooksey 0:fb7af294d5d9 1779 */
Simon Cooksey 0:fb7af294d5d9 1780
Simon Cooksey 0:fb7af294d5d9 1781 #if (__Vendor_SysTickConfig == 0)
Simon Cooksey 0:fb7af294d5d9 1782
Simon Cooksey 0:fb7af294d5d9 1783 /** \brief System Tick Configuration
Simon Cooksey 0:fb7af294d5d9 1784
Simon Cooksey 0:fb7af294d5d9 1785 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Simon Cooksey 0:fb7af294d5d9 1786 Counter is in free running mode to generate periodic interrupts.
Simon Cooksey 0:fb7af294d5d9 1787
Simon Cooksey 0:fb7af294d5d9 1788 \param [in] ticks Number of ticks between two interrupts.
Simon Cooksey 0:fb7af294d5d9 1789
Simon Cooksey 0:fb7af294d5d9 1790 \return 0 Function succeeded.
Simon Cooksey 0:fb7af294d5d9 1791 \return 1 Function failed.
Simon Cooksey 0:fb7af294d5d9 1792
Simon Cooksey 0:fb7af294d5d9 1793 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Simon Cooksey 0:fb7af294d5d9 1794 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Simon Cooksey 0:fb7af294d5d9 1795 must contain a vendor-specific implementation of this function.
Simon Cooksey 0:fb7af294d5d9 1796
Simon Cooksey 0:fb7af294d5d9 1797 */
Simon Cooksey 0:fb7af294d5d9 1798 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Simon Cooksey 0:fb7af294d5d9 1799 {
Simon Cooksey 0:fb7af294d5d9 1800 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Simon Cooksey 0:fb7af294d5d9 1801
Simon Cooksey 0:fb7af294d5d9 1802 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Simon Cooksey 0:fb7af294d5d9 1803 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Simon Cooksey 0:fb7af294d5d9 1804 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Simon Cooksey 0:fb7af294d5d9 1805 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Simon Cooksey 0:fb7af294d5d9 1806 SysTick_CTRL_TICKINT_Msk |
Simon Cooksey 0:fb7af294d5d9 1807 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Simon Cooksey 0:fb7af294d5d9 1808 return (0UL); /* Function successful */
Simon Cooksey 0:fb7af294d5d9 1809 }
Simon Cooksey 0:fb7af294d5d9 1810
Simon Cooksey 0:fb7af294d5d9 1811 #endif
Simon Cooksey 0:fb7af294d5d9 1812
Simon Cooksey 0:fb7af294d5d9 1813 /*@} end of CMSIS_Core_SysTickFunctions */
Simon Cooksey 0:fb7af294d5d9 1814
Simon Cooksey 0:fb7af294d5d9 1815
Simon Cooksey 0:fb7af294d5d9 1816
Simon Cooksey 0:fb7af294d5d9 1817 /* ##################################### Debug In/Output function ########################################### */
Simon Cooksey 0:fb7af294d5d9 1818 /** \ingroup CMSIS_Core_FunctionInterface
Simon Cooksey 0:fb7af294d5d9 1819 \defgroup CMSIS_core_DebugFunctions ITM Functions
Simon Cooksey 0:fb7af294d5d9 1820 \brief Functions that access the ITM debug interface.
Simon Cooksey 0:fb7af294d5d9 1821 @{
Simon Cooksey 0:fb7af294d5d9 1822 */
Simon Cooksey 0:fb7af294d5d9 1823
Simon Cooksey 0:fb7af294d5d9 1824 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
Simon Cooksey 0:fb7af294d5d9 1825 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
Simon Cooksey 0:fb7af294d5d9 1826
Simon Cooksey 0:fb7af294d5d9 1827
Simon Cooksey 0:fb7af294d5d9 1828 /** \brief ITM Send Character
Simon Cooksey 0:fb7af294d5d9 1829
Simon Cooksey 0:fb7af294d5d9 1830 The function transmits a character via the ITM channel 0, and
Simon Cooksey 0:fb7af294d5d9 1831 \li Just returns when no debugger is connected that has booked the output.
Simon Cooksey 0:fb7af294d5d9 1832 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Simon Cooksey 0:fb7af294d5d9 1833
Simon Cooksey 0:fb7af294d5d9 1834 \param [in] ch Character to transmit.
Simon Cooksey 0:fb7af294d5d9 1835
Simon Cooksey 0:fb7af294d5d9 1836 \returns Character to transmit.
Simon Cooksey 0:fb7af294d5d9 1837 */
Simon Cooksey 0:fb7af294d5d9 1838 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Simon Cooksey 0:fb7af294d5d9 1839 {
Simon Cooksey 0:fb7af294d5d9 1840 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Simon Cooksey 0:fb7af294d5d9 1841 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Simon Cooksey 0:fb7af294d5d9 1842 {
Simon Cooksey 0:fb7af294d5d9 1843 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Simon Cooksey 0:fb7af294d5d9 1844 ITM->PORT[0].u8 = (uint8_t)ch;
Simon Cooksey 0:fb7af294d5d9 1845 }
Simon Cooksey 0:fb7af294d5d9 1846 return (ch);
Simon Cooksey 0:fb7af294d5d9 1847 }
Simon Cooksey 0:fb7af294d5d9 1848
Simon Cooksey 0:fb7af294d5d9 1849
Simon Cooksey 0:fb7af294d5d9 1850 /** \brief ITM Receive Character
Simon Cooksey 0:fb7af294d5d9 1851
Simon Cooksey 0:fb7af294d5d9 1852 The function inputs a character via the external variable \ref ITM_RxBuffer.
Simon Cooksey 0:fb7af294d5d9 1853
Simon Cooksey 0:fb7af294d5d9 1854 \return Received character.
Simon Cooksey 0:fb7af294d5d9 1855 \return -1 No character pending.
Simon Cooksey 0:fb7af294d5d9 1856 */
Simon Cooksey 0:fb7af294d5d9 1857 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Simon Cooksey 0:fb7af294d5d9 1858 int32_t ch = -1; /* no character available */
Simon Cooksey 0:fb7af294d5d9 1859
Simon Cooksey 0:fb7af294d5d9 1860 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Simon Cooksey 0:fb7af294d5d9 1861 ch = ITM_RxBuffer;
Simon Cooksey 0:fb7af294d5d9 1862 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Simon Cooksey 0:fb7af294d5d9 1863 }
Simon Cooksey 0:fb7af294d5d9 1864
Simon Cooksey 0:fb7af294d5d9 1865 return (ch);
Simon Cooksey 0:fb7af294d5d9 1866 }
Simon Cooksey 0:fb7af294d5d9 1867
Simon Cooksey 0:fb7af294d5d9 1868
Simon Cooksey 0:fb7af294d5d9 1869 /** \brief ITM Check Character
Simon Cooksey 0:fb7af294d5d9 1870
Simon Cooksey 0:fb7af294d5d9 1871 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Simon Cooksey 0:fb7af294d5d9 1872
Simon Cooksey 0:fb7af294d5d9 1873 \return 0 No character available.
Simon Cooksey 0:fb7af294d5d9 1874 \return 1 Character available.
Simon Cooksey 0:fb7af294d5d9 1875 */
Simon Cooksey 0:fb7af294d5d9 1876 __STATIC_INLINE int32_t ITM_CheckChar (void) {
Simon Cooksey 0:fb7af294d5d9 1877
Simon Cooksey 0:fb7af294d5d9 1878 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Simon Cooksey 0:fb7af294d5d9 1879 return (0); /* no character available */
Simon Cooksey 0:fb7af294d5d9 1880 } else {
Simon Cooksey 0:fb7af294d5d9 1881 return (1); /* character available */
Simon Cooksey 0:fb7af294d5d9 1882 }
Simon Cooksey 0:fb7af294d5d9 1883 }
Simon Cooksey 0:fb7af294d5d9 1884
Simon Cooksey 0:fb7af294d5d9 1885 /*@} end of CMSIS_core_DebugFunctions */
Simon Cooksey 0:fb7af294d5d9 1886
Simon Cooksey 0:fb7af294d5d9 1887
Simon Cooksey 0:fb7af294d5d9 1888
Simon Cooksey 0:fb7af294d5d9 1889
Simon Cooksey 0:fb7af294d5d9 1890 #ifdef __cplusplus
Simon Cooksey 0:fb7af294d5d9 1891 }
Simon Cooksey 0:fb7af294d5d9 1892 #endif
Simon Cooksey 0:fb7af294d5d9 1893
Simon Cooksey 0:fb7af294d5d9 1894 #endif /* __CORE_CM4_H_DEPENDANT */
Simon Cooksey 0:fb7af294d5d9 1895
Simon Cooksey 0:fb7af294d5d9 1896 #endif /* __CMSIS_GENERIC */