Simon Cooksey / mbed-os

Pinned to some recent date

cmsis/core_caFunc.h@0:fb7af294d5d9, 2016-11-17 (annotated)

Committer:
Simon Cooksey
Date:
Thu Nov 17 16:43:53 2016 +0000
Revision:
0:fb7af294d5d9
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Simon Cooksey 0:fb7af294d5d9 1 /**************************************************************************//**
Simon Cooksey 0:fb7af294d5d9 2 * @file core_caFunc.h
Simon Cooksey 0:fb7af294d5d9 3 * @brief CMSIS Cortex-A Core Function Access Header File
Simon Cooksey 0:fb7af294d5d9 4 * @version V3.10
Simon Cooksey 0:fb7af294d5d9 5 * @date 30 Oct 2013
Simon Cooksey 0:fb7af294d5d9 6 *
Simon Cooksey 0:fb7af294d5d9 7 * @note
Simon Cooksey 0:fb7af294d5d9 8 *
Simon Cooksey 0:fb7af294d5d9 9 ******************************************************************************/
Simon Cooksey 0:fb7af294d5d9 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Simon Cooksey 0:fb7af294d5d9 11
Simon Cooksey 0:fb7af294d5d9 12 All rights reserved.
Simon Cooksey 0:fb7af294d5d9 13 Redistribution and use in source and binary forms, with or without
Simon Cooksey 0:fb7af294d5d9 14 modification, are permitted provided that the following conditions are met:
Simon Cooksey 0:fb7af294d5d9 15 - Redistributions of source code must retain the above copyright
Simon Cooksey 0:fb7af294d5d9 16 notice, this list of conditions and the following disclaimer.
Simon Cooksey 0:fb7af294d5d9 17 - Redistributions in binary form must reproduce the above copyright
Simon Cooksey 0:fb7af294d5d9 18 notice, this list of conditions and the following disclaimer in the
Simon Cooksey 0:fb7af294d5d9 19 documentation and/or other materials provided with the distribution.
Simon Cooksey 0:fb7af294d5d9 20 - Neither the name of ARM nor the names of its contributors may be used
Simon Cooksey 0:fb7af294d5d9 21 to endorse or promote products derived from this software without
Simon Cooksey 0:fb7af294d5d9 22 specific prior written permission.
Simon Cooksey 0:fb7af294d5d9 23 *
Simon Cooksey 0:fb7af294d5d9 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Simon Cooksey 0:fb7af294d5d9 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Simon Cooksey 0:fb7af294d5d9 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Simon Cooksey 0:fb7af294d5d9 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Simon Cooksey 0:fb7af294d5d9 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Simon Cooksey 0:fb7af294d5d9 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Simon Cooksey 0:fb7af294d5d9 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Simon Cooksey 0:fb7af294d5d9 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Simon Cooksey 0:fb7af294d5d9 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Simon Cooksey 0:fb7af294d5d9 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Simon Cooksey 0:fb7af294d5d9 34 POSSIBILITY OF SUCH DAMAGE.
Simon Cooksey 0:fb7af294d5d9 35 ---------------------------------------------------------------------------*/
Simon Cooksey 0:fb7af294d5d9 36
Simon Cooksey 0:fb7af294d5d9 37
Simon Cooksey 0:fb7af294d5d9 38 #ifndef __CORE_CAFUNC_H__
Simon Cooksey 0:fb7af294d5d9 39 #define __CORE_CAFUNC_H__
Simon Cooksey 0:fb7af294d5d9 40
Simon Cooksey 0:fb7af294d5d9 41
Simon Cooksey 0:fb7af294d5d9 42 /* ########################### Core Function Access ########################### */
Simon Cooksey 0:fb7af294d5d9 43 /** \ingroup CMSIS_Core_FunctionInterface
Simon Cooksey 0:fb7af294d5d9 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Simon Cooksey 0:fb7af294d5d9 45 @{
Simon Cooksey 0:fb7af294d5d9 46 */
Simon Cooksey 0:fb7af294d5d9 47
Simon Cooksey 0:fb7af294d5d9 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Simon Cooksey 0:fb7af294d5d9 49 /* ARM armcc specific functions */
Simon Cooksey 0:fb7af294d5d9 50
Simon Cooksey 0:fb7af294d5d9 51 #if (__ARMCC_VERSION < 400677)
Simon Cooksey 0:fb7af294d5d9 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Simon Cooksey 0:fb7af294d5d9 53 #endif
Simon Cooksey 0:fb7af294d5d9 54
Simon Cooksey 0:fb7af294d5d9 55 #define MODE_USR 0x10
Simon Cooksey 0:fb7af294d5d9 56 #define MODE_FIQ 0x11
Simon Cooksey 0:fb7af294d5d9 57 #define MODE_IRQ 0x12
Simon Cooksey 0:fb7af294d5d9 58 #define MODE_SVC 0x13
Simon Cooksey 0:fb7af294d5d9 59 #define MODE_MON 0x16
Simon Cooksey 0:fb7af294d5d9 60 #define MODE_ABT 0x17
Simon Cooksey 0:fb7af294d5d9 61 #define MODE_HYP 0x1A
Simon Cooksey 0:fb7af294d5d9 62 #define MODE_UND 0x1B
Simon Cooksey 0:fb7af294d5d9 63 #define MODE_SYS 0x1F
Simon Cooksey 0:fb7af294d5d9 64
Simon Cooksey 0:fb7af294d5d9 65 /** \brief Get APSR Register
Simon Cooksey 0:fb7af294d5d9 66
Simon Cooksey 0:fb7af294d5d9 67 This function returns the content of the APSR Register.
Simon Cooksey 0:fb7af294d5d9 68
Simon Cooksey 0:fb7af294d5d9 69 \return APSR Register value
Simon Cooksey 0:fb7af294d5d9 70 */
Simon Cooksey 0:fb7af294d5d9 71 __STATIC_INLINE uint32_t __get_APSR(void)
Simon Cooksey 0:fb7af294d5d9 72 {
Simon Cooksey 0:fb7af294d5d9 73 register uint32_t __regAPSR __ASM("apsr");
Simon Cooksey 0:fb7af294d5d9 74 return(__regAPSR);
Simon Cooksey 0:fb7af294d5d9 75 }
Simon Cooksey 0:fb7af294d5d9 76
Simon Cooksey 0:fb7af294d5d9 77
Simon Cooksey 0:fb7af294d5d9 78 /** \brief Get CPSR Register
Simon Cooksey 0:fb7af294d5d9 79
Simon Cooksey 0:fb7af294d5d9 80 This function returns the content of the CPSR Register.
Simon Cooksey 0:fb7af294d5d9 81
Simon Cooksey 0:fb7af294d5d9 82 \return CPSR Register value
Simon Cooksey 0:fb7af294d5d9 83 */
Simon Cooksey 0:fb7af294d5d9 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Simon Cooksey 0:fb7af294d5d9 85 {
Simon Cooksey 0:fb7af294d5d9 86 register uint32_t __regCPSR __ASM("cpsr");
Simon Cooksey 0:fb7af294d5d9 87 return(__regCPSR);
Simon Cooksey 0:fb7af294d5d9 88 }
Simon Cooksey 0:fb7af294d5d9 89
Simon Cooksey 0:fb7af294d5d9 90 /** \brief Set Stack Pointer
Simon Cooksey 0:fb7af294d5d9 91
Simon Cooksey 0:fb7af294d5d9 92 This function assigns the given value to the current stack pointer.
Simon Cooksey 0:fb7af294d5d9 93
Simon Cooksey 0:fb7af294d5d9 94 \param [in] topOfStack Stack Pointer value to set
Simon Cooksey 0:fb7af294d5d9 95 */
Simon Cooksey 0:fb7af294d5d9 96 register uint32_t __regSP __ASM("sp");
Simon Cooksey 0:fb7af294d5d9 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Simon Cooksey 0:fb7af294d5d9 98 {
Simon Cooksey 0:fb7af294d5d9 99 __regSP = topOfStack;
Simon Cooksey 0:fb7af294d5d9 100 }
Simon Cooksey 0:fb7af294d5d9 101
Simon Cooksey 0:fb7af294d5d9 102
Simon Cooksey 0:fb7af294d5d9 103 /** \brief Get link register
Simon Cooksey 0:fb7af294d5d9 104
Simon Cooksey 0:fb7af294d5d9 105 This function returns the value of the link register
Simon Cooksey 0:fb7af294d5d9 106
Simon Cooksey 0:fb7af294d5d9 107 \return Value of link register
Simon Cooksey 0:fb7af294d5d9 108 */
Simon Cooksey 0:fb7af294d5d9 109 register uint32_t __reglr __ASM("lr");
Simon Cooksey 0:fb7af294d5d9 110 __STATIC_INLINE uint32_t __get_LR(void)
Simon Cooksey 0:fb7af294d5d9 111 {
Simon Cooksey 0:fb7af294d5d9 112 return(__reglr);
Simon Cooksey 0:fb7af294d5d9 113 }
Simon Cooksey 0:fb7af294d5d9 114
Simon Cooksey 0:fb7af294d5d9 115 /** \brief Set link register
Simon Cooksey 0:fb7af294d5d9 116
Simon Cooksey 0:fb7af294d5d9 117 This function sets the value of the link register
Simon Cooksey 0:fb7af294d5d9 118
Simon Cooksey 0:fb7af294d5d9 119 \param [in] lr LR value to set
Simon Cooksey 0:fb7af294d5d9 120 */
Simon Cooksey 0:fb7af294d5d9 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Simon Cooksey 0:fb7af294d5d9 122 {
Simon Cooksey 0:fb7af294d5d9 123 __reglr = lr;
Simon Cooksey 0:fb7af294d5d9 124 }
Simon Cooksey 0:fb7af294d5d9 125
Simon Cooksey 0:fb7af294d5d9 126 /** \brief Set Process Stack Pointer
Simon Cooksey 0:fb7af294d5d9 127
Simon Cooksey 0:fb7af294d5d9 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Simon Cooksey 0:fb7af294d5d9 129
Simon Cooksey 0:fb7af294d5d9 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Simon Cooksey 0:fb7af294d5d9 131 */
Simon Cooksey 0:fb7af294d5d9 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Simon Cooksey 0:fb7af294d5d9 133 {
Simon Cooksey 0:fb7af294d5d9 134 ARM
Simon Cooksey 0:fb7af294d5d9 135 PRESERVE8
Simon Cooksey 0:fb7af294d5d9 136
Simon Cooksey 0:fb7af294d5d9 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Simon Cooksey 0:fb7af294d5d9 138 MRS R1, CPSR
Simon Cooksey 0:fb7af294d5d9 139 CPS #MODE_SYS ;no effect in USR mode
Simon Cooksey 0:fb7af294d5d9 140 MOV SP, R0
Simon Cooksey 0:fb7af294d5d9 141 MSR CPSR_c, R1 ;no effect in USR mode
Simon Cooksey 0:fb7af294d5d9 142 ISB
Simon Cooksey 0:fb7af294d5d9 143 BX LR
Simon Cooksey 0:fb7af294d5d9 144
Simon Cooksey 0:fb7af294d5d9 145 }
Simon Cooksey 0:fb7af294d5d9 146
Simon Cooksey 0:fb7af294d5d9 147 /** \brief Set User Mode
Simon Cooksey 0:fb7af294d5d9 148
Simon Cooksey 0:fb7af294d5d9 149 This function changes the processor state to User Mode
Simon Cooksey 0:fb7af294d5d9 150 */
Simon Cooksey 0:fb7af294d5d9 151 __STATIC_ASM void __set_CPS_USR(void)
Simon Cooksey 0:fb7af294d5d9 152 {
Simon Cooksey 0:fb7af294d5d9 153 ARM
Simon Cooksey 0:fb7af294d5d9 154
Simon Cooksey 0:fb7af294d5d9 155 CPS #MODE_USR
Simon Cooksey 0:fb7af294d5d9 156 BX LR
Simon Cooksey 0:fb7af294d5d9 157 }
Simon Cooksey 0:fb7af294d5d9 158
Simon Cooksey 0:fb7af294d5d9 159
Simon Cooksey 0:fb7af294d5d9 160 /** \brief Enable FIQ
Simon Cooksey 0:fb7af294d5d9 161
Simon Cooksey 0:fb7af294d5d9 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Simon Cooksey 0:fb7af294d5d9 163 Can only be executed in Privileged modes.
Simon Cooksey 0:fb7af294d5d9 164 */
Simon Cooksey 0:fb7af294d5d9 165 #define __enable_fault_irq __enable_fiq
Simon Cooksey 0:fb7af294d5d9 166
Simon Cooksey 0:fb7af294d5d9 167
Simon Cooksey 0:fb7af294d5d9 168 /** \brief Disable FIQ
Simon Cooksey 0:fb7af294d5d9 169
Simon Cooksey 0:fb7af294d5d9 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Simon Cooksey 0:fb7af294d5d9 171 Can only be executed in Privileged modes.
Simon Cooksey 0:fb7af294d5d9 172 */
Simon Cooksey 0:fb7af294d5d9 173 #define __disable_fault_irq __disable_fiq
Simon Cooksey 0:fb7af294d5d9 174
Simon Cooksey 0:fb7af294d5d9 175
Simon Cooksey 0:fb7af294d5d9 176 /** \brief Get FPSCR
Simon Cooksey 0:fb7af294d5d9 177
Simon Cooksey 0:fb7af294d5d9 178 This function returns the current value of the Floating Point Status/Control register.
Simon Cooksey 0:fb7af294d5d9 179
Simon Cooksey 0:fb7af294d5d9 180 \return Floating Point Status/Control register value
Simon Cooksey 0:fb7af294d5d9 181 */
Simon Cooksey 0:fb7af294d5d9 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Simon Cooksey 0:fb7af294d5d9 183 {
Simon Cooksey 0:fb7af294d5d9 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Simon Cooksey 0:fb7af294d5d9 185 register uint32_t __regfpscr __ASM("fpscr");
Simon Cooksey 0:fb7af294d5d9 186 return(__regfpscr);
Simon Cooksey 0:fb7af294d5d9 187 #else
Simon Cooksey 0:fb7af294d5d9 188 return(0);
Simon Cooksey 0:fb7af294d5d9 189 #endif
Simon Cooksey 0:fb7af294d5d9 190 }
Simon Cooksey 0:fb7af294d5d9 191
Simon Cooksey 0:fb7af294d5d9 192
Simon Cooksey 0:fb7af294d5d9 193 /** \brief Set FPSCR
Simon Cooksey 0:fb7af294d5d9 194
Simon Cooksey 0:fb7af294d5d9 195 This function assigns the given value to the Floating Point Status/Control register.
Simon Cooksey 0:fb7af294d5d9 196
Simon Cooksey 0:fb7af294d5d9 197 \param [in] fpscr Floating Point Status/Control value to set
Simon Cooksey 0:fb7af294d5d9 198 */
Simon Cooksey 0:fb7af294d5d9 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Simon Cooksey 0:fb7af294d5d9 200 {
Simon Cooksey 0:fb7af294d5d9 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Simon Cooksey 0:fb7af294d5d9 202 register uint32_t __regfpscr __ASM("fpscr");
Simon Cooksey 0:fb7af294d5d9 203 __regfpscr = (fpscr);
Simon Cooksey 0:fb7af294d5d9 204 #endif
Simon Cooksey 0:fb7af294d5d9 205 }
Simon Cooksey 0:fb7af294d5d9 206
Simon Cooksey 0:fb7af294d5d9 207 /** \brief Get FPEXC
Simon Cooksey 0:fb7af294d5d9 208
Simon Cooksey 0:fb7af294d5d9 209 This function returns the current value of the Floating Point Exception Control register.
Simon Cooksey 0:fb7af294d5d9 210
Simon Cooksey 0:fb7af294d5d9 211 \return Floating Point Exception Control register value
Simon Cooksey 0:fb7af294d5d9 212 */
Simon Cooksey 0:fb7af294d5d9 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Simon Cooksey 0:fb7af294d5d9 214 {
Simon Cooksey 0:fb7af294d5d9 215 #if (__FPU_PRESENT == 1)
Simon Cooksey 0:fb7af294d5d9 216 register uint32_t __regfpexc __ASM("fpexc");
Simon Cooksey 0:fb7af294d5d9 217 return(__regfpexc);
Simon Cooksey 0:fb7af294d5d9 218 #else
Simon Cooksey 0:fb7af294d5d9 219 return(0);
Simon Cooksey 0:fb7af294d5d9 220 #endif
Simon Cooksey 0:fb7af294d5d9 221 }
Simon Cooksey 0:fb7af294d5d9 222
Simon Cooksey 0:fb7af294d5d9 223
Simon Cooksey 0:fb7af294d5d9 224 /** \brief Set FPEXC
Simon Cooksey 0:fb7af294d5d9 225
Simon Cooksey 0:fb7af294d5d9 226 This function assigns the given value to the Floating Point Exception Control register.
Simon Cooksey 0:fb7af294d5d9 227
Simon Cooksey 0:fb7af294d5d9 228 \param [in] fpscr Floating Point Exception Control value to set
Simon Cooksey 0:fb7af294d5d9 229 */
Simon Cooksey 0:fb7af294d5d9 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Simon Cooksey 0:fb7af294d5d9 231 {
Simon Cooksey 0:fb7af294d5d9 232 #if (__FPU_PRESENT == 1)
Simon Cooksey 0:fb7af294d5d9 233 register uint32_t __regfpexc __ASM("fpexc");
Simon Cooksey 0:fb7af294d5d9 234 __regfpexc = (fpexc);
Simon Cooksey 0:fb7af294d5d9 235 #endif
Simon Cooksey 0:fb7af294d5d9 236 }
Simon Cooksey 0:fb7af294d5d9 237
Simon Cooksey 0:fb7af294d5d9 238 /** \brief Get CPACR
Simon Cooksey 0:fb7af294d5d9 239
Simon Cooksey 0:fb7af294d5d9 240 This function returns the current value of the Coprocessor Access Control register.
Simon Cooksey 0:fb7af294d5d9 241
Simon Cooksey 0:fb7af294d5d9 242 \return Coprocessor Access Control register value
Simon Cooksey 0:fb7af294d5d9 243 */
Simon Cooksey 0:fb7af294d5d9 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Simon Cooksey 0:fb7af294d5d9 245 {
Simon Cooksey 0:fb7af294d5d9 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Simon Cooksey 0:fb7af294d5d9 247 return __regCPACR;
Simon Cooksey 0:fb7af294d5d9 248 }
Simon Cooksey 0:fb7af294d5d9 249
Simon Cooksey 0:fb7af294d5d9 250 /** \brief Set CPACR
Simon Cooksey 0:fb7af294d5d9 251
Simon Cooksey 0:fb7af294d5d9 252 This function assigns the given value to the Coprocessor Access Control register.
Simon Cooksey 0:fb7af294d5d9 253
Simon Cooksey 0:fb7af294d5d9 254 \param [in] cpacr Coprocessor Acccess Control value to set
Simon Cooksey 0:fb7af294d5d9 255 */
Simon Cooksey 0:fb7af294d5d9 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Simon Cooksey 0:fb7af294d5d9 257 {
Simon Cooksey 0:fb7af294d5d9 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Simon Cooksey 0:fb7af294d5d9 259 __regCPACR = cpacr;
Simon Cooksey 0:fb7af294d5d9 260 __ISB();
Simon Cooksey 0:fb7af294d5d9 261 }
Simon Cooksey 0:fb7af294d5d9 262
Simon Cooksey 0:fb7af294d5d9 263 /** \brief Get CBAR
Simon Cooksey 0:fb7af294d5d9 264
Simon Cooksey 0:fb7af294d5d9 265 This function returns the value of the Configuration Base Address register.
Simon Cooksey 0:fb7af294d5d9 266
Simon Cooksey 0:fb7af294d5d9 267 \return Configuration Base Address register value
Simon Cooksey 0:fb7af294d5d9 268 */
Simon Cooksey 0:fb7af294d5d9 269 __STATIC_INLINE uint32_t __get_CBAR() {
Simon Cooksey 0:fb7af294d5d9 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Simon Cooksey 0:fb7af294d5d9 271 return(__regCBAR);
Simon Cooksey 0:fb7af294d5d9 272 }
Simon Cooksey 0:fb7af294d5d9 273
Simon Cooksey 0:fb7af294d5d9 274 /** \brief Get TTBR0
Simon Cooksey 0:fb7af294d5d9 275
Simon Cooksey 0:fb7af294d5d9 276 This function returns the value of the Translation Table Base Register 0.
Simon Cooksey 0:fb7af294d5d9 277
Simon Cooksey 0:fb7af294d5d9 278 \return Translation Table Base Register 0 value
Simon Cooksey 0:fb7af294d5d9 279 */
Simon Cooksey 0:fb7af294d5d9 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Simon Cooksey 0:fb7af294d5d9 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Simon Cooksey 0:fb7af294d5d9 282 return(__regTTBR0);
Simon Cooksey 0:fb7af294d5d9 283 }
Simon Cooksey 0:fb7af294d5d9 284
Simon Cooksey 0:fb7af294d5d9 285 /** \brief Set TTBR0
Simon Cooksey 0:fb7af294d5d9 286
Simon Cooksey 0:fb7af294d5d9 287 This function assigns the given value to the Translation Table Base Register 0.
Simon Cooksey 0:fb7af294d5d9 288
Simon Cooksey 0:fb7af294d5d9 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Simon Cooksey 0:fb7af294d5d9 290 */
Simon Cooksey 0:fb7af294d5d9 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Simon Cooksey 0:fb7af294d5d9 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Simon Cooksey 0:fb7af294d5d9 293 __regTTBR0 = ttbr0;
Simon Cooksey 0:fb7af294d5d9 294 __ISB();
Simon Cooksey 0:fb7af294d5d9 295 }
Simon Cooksey 0:fb7af294d5d9 296
Simon Cooksey 0:fb7af294d5d9 297 /** \brief Get DACR
Simon Cooksey 0:fb7af294d5d9 298
Simon Cooksey 0:fb7af294d5d9 299 This function returns the value of the Domain Access Control Register.
Simon Cooksey 0:fb7af294d5d9 300
Simon Cooksey 0:fb7af294d5d9 301 \return Domain Access Control Register value
Simon Cooksey 0:fb7af294d5d9 302 */
Simon Cooksey 0:fb7af294d5d9 303 __STATIC_INLINE uint32_t __get_DACR() {
Simon Cooksey 0:fb7af294d5d9 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Simon Cooksey 0:fb7af294d5d9 305 return(__regDACR);
Simon Cooksey 0:fb7af294d5d9 306 }
Simon Cooksey 0:fb7af294d5d9 307
Simon Cooksey 0:fb7af294d5d9 308 /** \brief Set DACR
Simon Cooksey 0:fb7af294d5d9 309
Simon Cooksey 0:fb7af294d5d9 310 This function assigns the given value to the Domain Access Control Register.
Simon Cooksey 0:fb7af294d5d9 311
Simon Cooksey 0:fb7af294d5d9 312 \param [in] dacr Domain Access Control Register value to set
Simon Cooksey 0:fb7af294d5d9 313 */
Simon Cooksey 0:fb7af294d5d9 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Simon Cooksey 0:fb7af294d5d9 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Simon Cooksey 0:fb7af294d5d9 316 __regDACR = dacr;
Simon Cooksey 0:fb7af294d5d9 317 __ISB();
Simon Cooksey 0:fb7af294d5d9 318 }
Simon Cooksey 0:fb7af294d5d9 319
Simon Cooksey 0:fb7af294d5d9 320 /******************************** Cache and BTAC enable ****************************************************/
Simon Cooksey 0:fb7af294d5d9 321
Simon Cooksey 0:fb7af294d5d9 322 /** \brief Set SCTLR
Simon Cooksey 0:fb7af294d5d9 323
Simon Cooksey 0:fb7af294d5d9 324 This function assigns the given value to the System Control Register.
Simon Cooksey 0:fb7af294d5d9 325
Simon Cooksey 0:fb7af294d5d9 326 \param [in] sctlr System Control Register value to set
Simon Cooksey 0:fb7af294d5d9 327 */
Simon Cooksey 0:fb7af294d5d9 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Simon Cooksey 0:fb7af294d5d9 329 {
Simon Cooksey 0:fb7af294d5d9 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Simon Cooksey 0:fb7af294d5d9 331 __regSCTLR = sctlr;
Simon Cooksey 0:fb7af294d5d9 332 }
Simon Cooksey 0:fb7af294d5d9 333
Simon Cooksey 0:fb7af294d5d9 334 /** \brief Get SCTLR
Simon Cooksey 0:fb7af294d5d9 335
Simon Cooksey 0:fb7af294d5d9 336 This function returns the value of the System Control Register.
Simon Cooksey 0:fb7af294d5d9 337
Simon Cooksey 0:fb7af294d5d9 338 \return System Control Register value
Simon Cooksey 0:fb7af294d5d9 339 */
Simon Cooksey 0:fb7af294d5d9 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Simon Cooksey 0:fb7af294d5d9 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Simon Cooksey 0:fb7af294d5d9 342 return(__regSCTLR);
Simon Cooksey 0:fb7af294d5d9 343 }
Simon Cooksey 0:fb7af294d5d9 344
Simon Cooksey 0:fb7af294d5d9 345 /** \brief Enable Caches
Simon Cooksey 0:fb7af294d5d9 346
Simon Cooksey 0:fb7af294d5d9 347 Enable Caches
Simon Cooksey 0:fb7af294d5d9 348 */
Simon Cooksey 0:fb7af294d5d9 349 __STATIC_INLINE void __enable_caches(void) {
Simon Cooksey 0:fb7af294d5d9 350 // Set I bit 12 to enable I Cache
Simon Cooksey 0:fb7af294d5d9 351 // Set C bit 2 to enable D Cache
Simon Cooksey 0:fb7af294d5d9 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Simon Cooksey 0:fb7af294d5d9 353 }
Simon Cooksey 0:fb7af294d5d9 354
Simon Cooksey 0:fb7af294d5d9 355 /** \brief Disable Caches
Simon Cooksey 0:fb7af294d5d9 356
Simon Cooksey 0:fb7af294d5d9 357 Disable Caches
Simon Cooksey 0:fb7af294d5d9 358 */
Simon Cooksey 0:fb7af294d5d9 359 __STATIC_INLINE void __disable_caches(void) {
Simon Cooksey 0:fb7af294d5d9 360 // Clear I bit 12 to disable I Cache
Simon Cooksey 0:fb7af294d5d9 361 // Clear C bit 2 to disable D Cache
Simon Cooksey 0:fb7af294d5d9 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Simon Cooksey 0:fb7af294d5d9 363 __ISB();
Simon Cooksey 0:fb7af294d5d9 364 }
Simon Cooksey 0:fb7af294d5d9 365
Simon Cooksey 0:fb7af294d5d9 366 /** \brief Enable BTAC
Simon Cooksey 0:fb7af294d5d9 367
Simon Cooksey 0:fb7af294d5d9 368 Enable BTAC
Simon Cooksey 0:fb7af294d5d9 369 */
Simon Cooksey 0:fb7af294d5d9 370 __STATIC_INLINE void __enable_btac(void) {
Simon Cooksey 0:fb7af294d5d9 371 // Set Z bit 11 to enable branch prediction
Simon Cooksey 0:fb7af294d5d9 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Simon Cooksey 0:fb7af294d5d9 373 __ISB();
Simon Cooksey 0:fb7af294d5d9 374 }
Simon Cooksey 0:fb7af294d5d9 375
Simon Cooksey 0:fb7af294d5d9 376 /** \brief Disable BTAC
Simon Cooksey 0:fb7af294d5d9 377
Simon Cooksey 0:fb7af294d5d9 378 Disable BTAC
Simon Cooksey 0:fb7af294d5d9 379 */
Simon Cooksey 0:fb7af294d5d9 380 __STATIC_INLINE void __disable_btac(void) {
Simon Cooksey 0:fb7af294d5d9 381 // Clear Z bit 11 to disable branch prediction
Simon Cooksey 0:fb7af294d5d9 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Simon Cooksey 0:fb7af294d5d9 383 }
Simon Cooksey 0:fb7af294d5d9 384
Simon Cooksey 0:fb7af294d5d9 385
Simon Cooksey 0:fb7af294d5d9 386 /** \brief Enable MMU
Simon Cooksey 0:fb7af294d5d9 387
Simon Cooksey 0:fb7af294d5d9 388 Enable MMU
Simon Cooksey 0:fb7af294d5d9 389 */
Simon Cooksey 0:fb7af294d5d9 390 __STATIC_INLINE void __enable_mmu(void) {
Simon Cooksey 0:fb7af294d5d9 391 // Set M bit 0 to enable the MMU
Simon Cooksey 0:fb7af294d5d9 392 // Set AFE bit to enable simplified access permissions model
Simon Cooksey 0:fb7af294d5d9 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Simon Cooksey 0:fb7af294d5d9 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Simon Cooksey 0:fb7af294d5d9 395 __ISB();
Simon Cooksey 0:fb7af294d5d9 396 }
Simon Cooksey 0:fb7af294d5d9 397
Simon Cooksey 0:fb7af294d5d9 398 /** \brief Disable MMU
Simon Cooksey 0:fb7af294d5d9 399
Simon Cooksey 0:fb7af294d5d9 400 Disable MMU
Simon Cooksey 0:fb7af294d5d9 401 */
Simon Cooksey 0:fb7af294d5d9 402 __STATIC_INLINE void __disable_mmu(void) {
Simon Cooksey 0:fb7af294d5d9 403 // Clear M bit 0 to disable the MMU
Simon Cooksey 0:fb7af294d5d9 404 __set_SCTLR( __get_SCTLR() & ~1);
Simon Cooksey 0:fb7af294d5d9 405 __ISB();
Simon Cooksey 0:fb7af294d5d9 406 }
Simon Cooksey 0:fb7af294d5d9 407
Simon Cooksey 0:fb7af294d5d9 408 /******************************** TLB maintenance operations ************************************************/
Simon Cooksey 0:fb7af294d5d9 409 /** \brief Invalidate the whole tlb
Simon Cooksey 0:fb7af294d5d9 410
Simon Cooksey 0:fb7af294d5d9 411 TLBIALL. Invalidate the whole tlb
Simon Cooksey 0:fb7af294d5d9 412 */
Simon Cooksey 0:fb7af294d5d9 413
Simon Cooksey 0:fb7af294d5d9 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Simon Cooksey 0:fb7af294d5d9 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Simon Cooksey 0:fb7af294d5d9 416 __TLBIALL = 0;
Simon Cooksey 0:fb7af294d5d9 417 __DSB();
Simon Cooksey 0:fb7af294d5d9 418 __ISB();
Simon Cooksey 0:fb7af294d5d9 419 }
Simon Cooksey 0:fb7af294d5d9 420
Simon Cooksey 0:fb7af294d5d9 421 /******************************** BTB maintenance operations ************************************************/
Simon Cooksey 0:fb7af294d5d9 422 /** \brief Invalidate entire branch predictor array
Simon Cooksey 0:fb7af294d5d9 423
Simon Cooksey 0:fb7af294d5d9 424 BPIALL. Branch Predictor Invalidate All.
Simon Cooksey 0:fb7af294d5d9 425 */
Simon Cooksey 0:fb7af294d5d9 426
Simon Cooksey 0:fb7af294d5d9 427 __STATIC_INLINE void __v7_inv_btac(void) {
Simon Cooksey 0:fb7af294d5d9 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Simon Cooksey 0:fb7af294d5d9 429 __BPIALL = 0;
Simon Cooksey 0:fb7af294d5d9 430 __DSB(); //ensure completion of the invalidation
Simon Cooksey 0:fb7af294d5d9 431 __ISB(); //ensure instruction fetch path sees new state
Simon Cooksey 0:fb7af294d5d9 432 }
Simon Cooksey 0:fb7af294d5d9 433
Simon Cooksey 0:fb7af294d5d9 434
Simon Cooksey 0:fb7af294d5d9 435 /******************************** L1 cache operations ******************************************************/
Simon Cooksey 0:fb7af294d5d9 436
Simon Cooksey 0:fb7af294d5d9 437 /** \brief Invalidate the whole I$
Simon Cooksey 0:fb7af294d5d9 438
Simon Cooksey 0:fb7af294d5d9 439 ICIALLU. Instruction Cache Invalidate All to PoU
Simon Cooksey 0:fb7af294d5d9 440 */
Simon Cooksey 0:fb7af294d5d9 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Simon Cooksey 0:fb7af294d5d9 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Simon Cooksey 0:fb7af294d5d9 443 __ICIALLU = 0;
Simon Cooksey 0:fb7af294d5d9 444 __DSB(); //ensure completion of the invalidation
Simon Cooksey 0:fb7af294d5d9 445 __ISB(); //ensure instruction fetch path sees new I cache state
Simon Cooksey 0:fb7af294d5d9 446 }
Simon Cooksey 0:fb7af294d5d9 447
Simon Cooksey 0:fb7af294d5d9 448 /** \brief Clean D$ by MVA
Simon Cooksey 0:fb7af294d5d9 449
Simon Cooksey 0:fb7af294d5d9 450 DCCMVAC. Data cache clean by MVA to PoC
Simon Cooksey 0:fb7af294d5d9 451 */
Simon Cooksey 0:fb7af294d5d9 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Simon Cooksey 0:fb7af294d5d9 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Simon Cooksey 0:fb7af294d5d9 454 __DCCMVAC = (uint32_t)va;
Simon Cooksey 0:fb7af294d5d9 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Simon Cooksey 0:fb7af294d5d9 456 }
Simon Cooksey 0:fb7af294d5d9 457
Simon Cooksey 0:fb7af294d5d9 458 /** \brief Invalidate D$ by MVA
Simon Cooksey 0:fb7af294d5d9 459
Simon Cooksey 0:fb7af294d5d9 460 DCIMVAC. Data cache invalidate by MVA to PoC
Simon Cooksey 0:fb7af294d5d9 461 */
Simon Cooksey 0:fb7af294d5d9 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Simon Cooksey 0:fb7af294d5d9 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Simon Cooksey 0:fb7af294d5d9 464 __DCIMVAC = (uint32_t)va;
Simon Cooksey 0:fb7af294d5d9 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Simon Cooksey 0:fb7af294d5d9 466 }
Simon Cooksey 0:fb7af294d5d9 467
Simon Cooksey 0:fb7af294d5d9 468 /** \brief Clean and Invalidate D$ by MVA
Simon Cooksey 0:fb7af294d5d9 469
Simon Cooksey 0:fb7af294d5d9 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Simon Cooksey 0:fb7af294d5d9 471 */
Simon Cooksey 0:fb7af294d5d9 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Simon Cooksey 0:fb7af294d5d9 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Simon Cooksey 0:fb7af294d5d9 474 __DCCIMVAC = (uint32_t)va;
Simon Cooksey 0:fb7af294d5d9 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Simon Cooksey 0:fb7af294d5d9 476 }
Simon Cooksey 0:fb7af294d5d9 477
Simon Cooksey 0:fb7af294d5d9 478 /** \brief Clean and Invalidate the entire data or unified cache
Simon Cooksey 0:fb7af294d5d9 479
Simon Cooksey 0:fb7af294d5d9 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Simon Cooksey 0:fb7af294d5d9 481 */
Simon Cooksey 0:fb7af294d5d9 482 #pragma push
Simon Cooksey 0:fb7af294d5d9 483 #pragma arm
Simon Cooksey 0:fb7af294d5d9 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Simon Cooksey 0:fb7af294d5d9 485 ARM
Simon Cooksey 0:fb7af294d5d9 486
Simon Cooksey 0:fb7af294d5d9 487 PUSH {R4-R11}
Simon Cooksey 0:fb7af294d5d9 488
Simon Cooksey 0:fb7af294d5d9 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Simon Cooksey 0:fb7af294d5d9 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Simon Cooksey 0:fb7af294d5d9 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Simon Cooksey 0:fb7af294d5d9 492 BEQ Finished // If 0, no need to clean
Simon Cooksey 0:fb7af294d5d9 493
Simon Cooksey 0:fb7af294d5d9 494 MOV R10, #0 // R10 holds current cache level << 1
Simon Cooksey 0:fb7af294d5d9 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Simon Cooksey 0:fb7af294d5d9 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Simon Cooksey 0:fb7af294d5d9 497 AND R1, R1, #7 // Isolate those lower 3 bits
Simon Cooksey 0:fb7af294d5d9 498 CMP R1, #2
Simon Cooksey 0:fb7af294d5d9 499 BLT Skip // No cache or only instruction cache at this level
Simon Cooksey 0:fb7af294d5d9 500
Simon Cooksey 0:fb7af294d5d9 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Simon Cooksey 0:fb7af294d5d9 502 ISB // ISB to sync the change to the CacheSizeID reg
Simon Cooksey 0:fb7af294d5d9 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Simon Cooksey 0:fb7af294d5d9 504 AND R2, R1, #7 // Extract the line length field
Simon Cooksey 0:fb7af294d5d9 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Simon Cooksey 0:fb7af294d5d9 506 LDR R4, =0x3FF
Simon Cooksey 0:fb7af294d5d9 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Simon Cooksey 0:fb7af294d5d9 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Simon Cooksey 0:fb7af294d5d9 509 LDR R7, =0x7FFF
Simon Cooksey 0:fb7af294d5d9 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Simon Cooksey 0:fb7af294d5d9 511
Simon Cooksey 0:fb7af294d5d9 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Simon Cooksey 0:fb7af294d5d9 513
Simon Cooksey 0:fb7af294d5d9 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Simon Cooksey 0:fb7af294d5d9 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Simon Cooksey 0:fb7af294d5d9 516 CMP R0, #0
Simon Cooksey 0:fb7af294d5d9 517 BNE Dccsw
Simon Cooksey 0:fb7af294d5d9 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Simon Cooksey 0:fb7af294d5d9 519 B cont
Simon Cooksey 0:fb7af294d5d9 520 Dccsw CMP R0, #1
Simon Cooksey 0:fb7af294d5d9 521 BNE Dccisw
Simon Cooksey 0:fb7af294d5d9 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Simon Cooksey 0:fb7af294d5d9 523 B cont
Simon Cooksey 0:fb7af294d5d9 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Simon Cooksey 0:fb7af294d5d9 525 cont SUBS R9, R9, #1 // Decrement the Way number
Simon Cooksey 0:fb7af294d5d9 526 BGE Loop3
Simon Cooksey 0:fb7af294d5d9 527 SUBS R7, R7, #1 // Decrement the Set number
Simon Cooksey 0:fb7af294d5d9 528 BGE Loop2
Simon Cooksey 0:fb7af294d5d9 529 Skip ADD R10, R10, #2 // Increment the cache number
Simon Cooksey 0:fb7af294d5d9 530 CMP R3, R10
Simon Cooksey 0:fb7af294d5d9 531 BGT Loop1
Simon Cooksey 0:fb7af294d5d9 532
Simon Cooksey 0:fb7af294d5d9 533 Finished
Simon Cooksey 0:fb7af294d5d9 534 DSB
Simon Cooksey 0:fb7af294d5d9 535 POP {R4-R11}
Simon Cooksey 0:fb7af294d5d9 536 BX lr
Simon Cooksey 0:fb7af294d5d9 537
Simon Cooksey 0:fb7af294d5d9 538 }
Simon Cooksey 0:fb7af294d5d9 539 #pragma pop
Simon Cooksey 0:fb7af294d5d9 540
Simon Cooksey 0:fb7af294d5d9 541
Simon Cooksey 0:fb7af294d5d9 542 /** \brief Invalidate the whole D$
Simon Cooksey 0:fb7af294d5d9 543
Simon Cooksey 0:fb7af294d5d9 544 DCISW. Invalidate by Set/Way
Simon Cooksey 0:fb7af294d5d9 545 */
Simon Cooksey 0:fb7af294d5d9 546
Simon Cooksey 0:fb7af294d5d9 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Simon Cooksey 0:fb7af294d5d9 548 __v7_all_cache(0);
Simon Cooksey 0:fb7af294d5d9 549 }
Simon Cooksey 0:fb7af294d5d9 550
Simon Cooksey 0:fb7af294d5d9 551 /** \brief Clean the whole D$
Simon Cooksey 0:fb7af294d5d9 552
Simon Cooksey 0:fb7af294d5d9 553 DCCSW. Clean by Set/Way
Simon Cooksey 0:fb7af294d5d9 554 */
Simon Cooksey 0:fb7af294d5d9 555
Simon Cooksey 0:fb7af294d5d9 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Simon Cooksey 0:fb7af294d5d9 557 __v7_all_cache(1);
Simon Cooksey 0:fb7af294d5d9 558 }
Simon Cooksey 0:fb7af294d5d9 559
Simon Cooksey 0:fb7af294d5d9 560 /** \brief Clean and invalidate the whole D$
Simon Cooksey 0:fb7af294d5d9 561
Simon Cooksey 0:fb7af294d5d9 562 DCCISW. Clean and Invalidate by Set/Way
Simon Cooksey 0:fb7af294d5d9 563 */
Simon Cooksey 0:fb7af294d5d9 564
Simon Cooksey 0:fb7af294d5d9 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Simon Cooksey 0:fb7af294d5d9 566 __v7_all_cache(2);
Simon Cooksey 0:fb7af294d5d9 567 }
Simon Cooksey 0:fb7af294d5d9 568
Simon Cooksey 0:fb7af294d5d9 569 #include "core_ca_mmu.h"
Simon Cooksey 0:fb7af294d5d9 570
Simon Cooksey 0:fb7af294d5d9 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Simon Cooksey 0:fb7af294d5d9 572
Simon Cooksey 0:fb7af294d5d9 573 #define __inline inline
Simon Cooksey 0:fb7af294d5d9 574
Simon Cooksey 0:fb7af294d5d9 575 inline static uint32_t __disable_irq_iar() {
Simon Cooksey 0:fb7af294d5d9 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
Simon Cooksey 0:fb7af294d5d9 577 __disable_irq();
Simon Cooksey 0:fb7af294d5d9 578 return irq_dis;
Simon Cooksey 0:fb7af294d5d9 579 }
Simon Cooksey 0:fb7af294d5d9 580
Simon Cooksey 0:fb7af294d5d9 581 #define MODE_USR 0x10
Simon Cooksey 0:fb7af294d5d9 582 #define MODE_FIQ 0x11
Simon Cooksey 0:fb7af294d5d9 583 #define MODE_IRQ 0x12
Simon Cooksey 0:fb7af294d5d9 584 #define MODE_SVC 0x13
Simon Cooksey 0:fb7af294d5d9 585 #define MODE_MON 0x16
Simon Cooksey 0:fb7af294d5d9 586 #define MODE_ABT 0x17
Simon Cooksey 0:fb7af294d5d9 587 #define MODE_HYP 0x1A
Simon Cooksey 0:fb7af294d5d9 588 #define MODE_UND 0x1B
Simon Cooksey 0:fb7af294d5d9 589 #define MODE_SYS 0x1F
Simon Cooksey 0:fb7af294d5d9 590
Simon Cooksey 0:fb7af294d5d9 591 /** \brief Set Process Stack Pointer
Simon Cooksey 0:fb7af294d5d9 592
Simon Cooksey 0:fb7af294d5d9 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Simon Cooksey 0:fb7af294d5d9 594
Simon Cooksey 0:fb7af294d5d9 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Simon Cooksey 0:fb7af294d5d9 596 */
Simon Cooksey 0:fb7af294d5d9 597 // from rt_CMSIS.c
Simon Cooksey 0:fb7af294d5d9 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
Simon Cooksey 0:fb7af294d5d9 599 __asm(
Simon Cooksey 0:fb7af294d5d9 600 " ARM\n"
Simon Cooksey 0:fb7af294d5d9 601 // " PRESERVE8\n"
Simon Cooksey 0:fb7af294d5d9 602
Simon Cooksey 0:fb7af294d5d9 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
Simon Cooksey 0:fb7af294d5d9 604 " MRS R1, CPSR \n"
Simon Cooksey 0:fb7af294d5d9 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
Simon Cooksey 0:fb7af294d5d9 606 " MOV SP, R0 \n"
Simon Cooksey 0:fb7af294d5d9 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
Simon Cooksey 0:fb7af294d5d9 608 " ISB \n"
Simon Cooksey 0:fb7af294d5d9 609 " BX LR \n");
Simon Cooksey 0:fb7af294d5d9 610 }
Simon Cooksey 0:fb7af294d5d9 611
Simon Cooksey 0:fb7af294d5d9 612 /** \brief Set User Mode
Simon Cooksey 0:fb7af294d5d9 613
Simon Cooksey 0:fb7af294d5d9 614 This function changes the processor state to User Mode
Simon Cooksey 0:fb7af294d5d9 615 */
Simon Cooksey 0:fb7af294d5d9 616 // from rt_CMSIS.c
Simon Cooksey 0:fb7af294d5d9 617 __arm static inline void __set_CPS_USR(void) {
Simon Cooksey 0:fb7af294d5d9 618 __asm(
Simon Cooksey 0:fb7af294d5d9 619 " ARM \n"
Simon Cooksey 0:fb7af294d5d9 620
Simon Cooksey 0:fb7af294d5d9 621 " CPS #0x10 \n" // MODE_USR
Simon Cooksey 0:fb7af294d5d9 622 " BX LR\n");
Simon Cooksey 0:fb7af294d5d9 623 }
Simon Cooksey 0:fb7af294d5d9 624
Simon Cooksey 0:fb7af294d5d9 625 /** \brief Set TTBR0
Simon Cooksey 0:fb7af294d5d9 626
Simon Cooksey 0:fb7af294d5d9 627 This function assigns the given value to the Translation Table Base Register 0.
Simon Cooksey 0:fb7af294d5d9 628
Simon Cooksey 0:fb7af294d5d9 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
Simon Cooksey 0:fb7af294d5d9 630 */
Simon Cooksey 0:fb7af294d5d9 631 // from mmu_Renesas_RZ_A1.c
Simon Cooksey 0:fb7af294d5d9 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Simon Cooksey 0:fb7af294d5d9 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
Simon Cooksey 0:fb7af294d5d9 634 __ISB();
Simon Cooksey 0:fb7af294d5d9 635 }
Simon Cooksey 0:fb7af294d5d9 636
Simon Cooksey 0:fb7af294d5d9 637 /** \brief Set DACR
Simon Cooksey 0:fb7af294d5d9 638
Simon Cooksey 0:fb7af294d5d9 639 This function assigns the given value to the Domain Access Control Register.
Simon Cooksey 0:fb7af294d5d9 640
Simon Cooksey 0:fb7af294d5d9 641 \param [in] dacr Domain Access Control Register value to set
Simon Cooksey 0:fb7af294d5d9 642 */
Simon Cooksey 0:fb7af294d5d9 643 // from mmu_Renesas_RZ_A1.c
Simon Cooksey 0:fb7af294d5d9 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Simon Cooksey 0:fb7af294d5d9 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
Simon Cooksey 0:fb7af294d5d9 646 __ISB();
Simon Cooksey 0:fb7af294d5d9 647 }
Simon Cooksey 0:fb7af294d5d9 648
Simon Cooksey 0:fb7af294d5d9 649
Simon Cooksey 0:fb7af294d5d9 650 /******************************** Cache and BTAC enable ****************************************************/
Simon Cooksey 0:fb7af294d5d9 651 /** \brief Set SCTLR
Simon Cooksey 0:fb7af294d5d9 652
Simon Cooksey 0:fb7af294d5d9 653 This function assigns the given value to the System Control Register.
Simon Cooksey 0:fb7af294d5d9 654
Simon Cooksey 0:fb7af294d5d9 655 \param [in] sctlr System Control Register value to set
Simon Cooksey 0:fb7af294d5d9 656 */
Simon Cooksey 0:fb7af294d5d9 657 // from __enable_mmu()
Simon Cooksey 0:fb7af294d5d9 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
Simon Cooksey 0:fb7af294d5d9 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
Simon Cooksey 0:fb7af294d5d9 660 }
Simon Cooksey 0:fb7af294d5d9 661
Simon Cooksey 0:fb7af294d5d9 662 /** \brief Get SCTLR
Simon Cooksey 0:fb7af294d5d9 663
Simon Cooksey 0:fb7af294d5d9 664 This function returns the value of the System Control Register.
Simon Cooksey 0:fb7af294d5d9 665
Simon Cooksey 0:fb7af294d5d9 666 \return System Control Register value
Simon Cooksey 0:fb7af294d5d9 667 */
Simon Cooksey 0:fb7af294d5d9 668 // from __enable_mmu()
Simon Cooksey 0:fb7af294d5d9 669 __STATIC_INLINE uint32_t __get_SCTLR() {
Simon Cooksey 0:fb7af294d5d9 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
Simon Cooksey 0:fb7af294d5d9 671 return __regSCTLR;
Simon Cooksey 0:fb7af294d5d9 672 }
Simon Cooksey 0:fb7af294d5d9 673
Simon Cooksey 0:fb7af294d5d9 674 /** \brief Enable Caches
Simon Cooksey 0:fb7af294d5d9 675
Simon Cooksey 0:fb7af294d5d9 676 Enable Caches
Simon Cooksey 0:fb7af294d5d9 677 */
Simon Cooksey 0:fb7af294d5d9 678 // from system_Renesas_RZ_A1.c
Simon Cooksey 0:fb7af294d5d9 679 __STATIC_INLINE void __enable_caches(void) {
Simon Cooksey 0:fb7af294d5d9 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Simon Cooksey 0:fb7af294d5d9 681 }
Simon Cooksey 0:fb7af294d5d9 682
Simon Cooksey 0:fb7af294d5d9 683 /** \brief Enable BTAC
Simon Cooksey 0:fb7af294d5d9 684
Simon Cooksey 0:fb7af294d5d9 685 Enable BTAC
Simon Cooksey 0:fb7af294d5d9 686 */
Simon Cooksey 0:fb7af294d5d9 687 // from system_Renesas_RZ_A1.c
Simon Cooksey 0:fb7af294d5d9 688 __STATIC_INLINE void __enable_btac(void) {
Simon Cooksey 0:fb7af294d5d9 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
Simon Cooksey 0:fb7af294d5d9 690 __ISB();
Simon Cooksey 0:fb7af294d5d9 691 }
Simon Cooksey 0:fb7af294d5d9 692
Simon Cooksey 0:fb7af294d5d9 693 /** \brief Enable MMU
Simon Cooksey 0:fb7af294d5d9 694
Simon Cooksey 0:fb7af294d5d9 695 Enable MMU
Simon Cooksey 0:fb7af294d5d9 696 */
Simon Cooksey 0:fb7af294d5d9 697 // from system_Renesas_RZ_A1.c
Simon Cooksey 0:fb7af294d5d9 698 __STATIC_INLINE void __enable_mmu(void) {
Simon Cooksey 0:fb7af294d5d9 699 // Set M bit 0 to enable the MMU
Simon Cooksey 0:fb7af294d5d9 700 // Set AFE bit to enable simplified access permissions model
Simon Cooksey 0:fb7af294d5d9 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Simon Cooksey 0:fb7af294d5d9 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Simon Cooksey 0:fb7af294d5d9 703 __ISB();
Simon Cooksey 0:fb7af294d5d9 704 }
Simon Cooksey 0:fb7af294d5d9 705
Simon Cooksey 0:fb7af294d5d9 706 /******************************** TLB maintenance operations ************************************************/
Simon Cooksey 0:fb7af294d5d9 707 /** \brief Invalidate the whole tlb
Simon Cooksey 0:fb7af294d5d9 708
Simon Cooksey 0:fb7af294d5d9 709 TLBIALL. Invalidate the whole tlb
Simon Cooksey 0:fb7af294d5d9 710 */
Simon Cooksey 0:fb7af294d5d9 711 // from system_Renesas_RZ_A1.c
Simon Cooksey 0:fb7af294d5d9 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Simon Cooksey 0:fb7af294d5d9 713 uint32_t val = 0;
Simon Cooksey 0:fb7af294d5d9 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
Simon Cooksey 0:fb7af294d5d9 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
Simon Cooksey 0:fb7af294d5d9 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
Simon Cooksey 0:fb7af294d5d9 717 __DSB();
Simon Cooksey 0:fb7af294d5d9 718 __ISB();
Simon Cooksey 0:fb7af294d5d9 719 }
Simon Cooksey 0:fb7af294d5d9 720
Simon Cooksey 0:fb7af294d5d9 721 /******************************** BTB maintenance operations ************************************************/
Simon Cooksey 0:fb7af294d5d9 722 /** \brief Invalidate entire branch predictor array
Simon Cooksey 0:fb7af294d5d9 723
Simon Cooksey 0:fb7af294d5d9 724 BPIALL. Branch Predictor Invalidate All.
Simon Cooksey 0:fb7af294d5d9 725 */
Simon Cooksey 0:fb7af294d5d9 726 // from system_Renesas_RZ_A1.c
Simon Cooksey 0:fb7af294d5d9 727 __STATIC_INLINE void __v7_inv_btac(void) {
Simon Cooksey 0:fb7af294d5d9 728 uint32_t val = 0;
Simon Cooksey 0:fb7af294d5d9 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
Simon Cooksey 0:fb7af294d5d9 730 __DSB(); //ensure completion of the invalidation
Simon Cooksey 0:fb7af294d5d9 731 __ISB(); //ensure instruction fetch path sees new state
Simon Cooksey 0:fb7af294d5d9 732 }
Simon Cooksey 0:fb7af294d5d9 733
Simon Cooksey 0:fb7af294d5d9 734
Simon Cooksey 0:fb7af294d5d9 735 /******************************** L1 cache operations ******************************************************/
Simon Cooksey 0:fb7af294d5d9 736
Simon Cooksey 0:fb7af294d5d9 737 /** \brief Invalidate the whole I$
Simon Cooksey 0:fb7af294d5d9 738
Simon Cooksey 0:fb7af294d5d9 739 ICIALLU. Instruction Cache Invalidate All to PoU
Simon Cooksey 0:fb7af294d5d9 740 */
Simon Cooksey 0:fb7af294d5d9 741 // from system_Renesas_RZ_A1.c
Simon Cooksey 0:fb7af294d5d9 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
Simon Cooksey 0:fb7af294d5d9 743 uint32_t val = 0;
Simon Cooksey 0:fb7af294d5d9 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
Simon Cooksey 0:fb7af294d5d9 745 __DSB(); //ensure completion of the invalidation
Simon Cooksey 0:fb7af294d5d9 746 __ISB(); //ensure instruction fetch path sees new I cache state
Simon Cooksey 0:fb7af294d5d9 747 }
Simon Cooksey 0:fb7af294d5d9 748
Simon Cooksey 0:fb7af294d5d9 749 // from __v7_inv_dcache_all()
Simon Cooksey 0:fb7af294d5d9 750 __arm static inline void __v7_all_cache(uint32_t op) {
Simon Cooksey 0:fb7af294d5d9 751 __asm(
Simon Cooksey 0:fb7af294d5d9 752 " ARM \n"
Simon Cooksey 0:fb7af294d5d9 753
Simon Cooksey 0:fb7af294d5d9 754 " PUSH {R4-R11} \n"
Simon Cooksey 0:fb7af294d5d9 755
Simon Cooksey 0:fb7af294d5d9 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
Simon Cooksey 0:fb7af294d5d9 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
Simon Cooksey 0:fb7af294d5d9 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
Simon Cooksey 0:fb7af294d5d9 759 " BEQ Finished\n" // If 0, no need to clean
Simon Cooksey 0:fb7af294d5d9 760
Simon Cooksey 0:fb7af294d5d9 761 " MOV R10, #0\n" // R10 holds current cache level << 1
Simon Cooksey 0:fb7af294d5d9 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
Simon Cooksey 0:fb7af294d5d9 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
Simon Cooksey 0:fb7af294d5d9 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
Simon Cooksey 0:fb7af294d5d9 765 " CMP R1, #2 \n"
Simon Cooksey 0:fb7af294d5d9 766 " BLT Skip \n" // No cache or only instruction cache at this level
Simon Cooksey 0:fb7af294d5d9 767
Simon Cooksey 0:fb7af294d5d9 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
Simon Cooksey 0:fb7af294d5d9 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
Simon Cooksey 0:fb7af294d5d9 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
Simon Cooksey 0:fb7af294d5d9 771 " AND R2, R1, #7 \n" // Extract the line length field
Simon Cooksey 0:fb7af294d5d9 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
Simon Cooksey 0:fb7af294d5d9 773 " movw R4, #0x3FF \n"
Simon Cooksey 0:fb7af294d5d9 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
Simon Cooksey 0:fb7af294d5d9 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
Simon Cooksey 0:fb7af294d5d9 776 " movw R7, #0x7FFF \n"
Simon Cooksey 0:fb7af294d5d9 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
Simon Cooksey 0:fb7af294d5d9 778
Simon Cooksey 0:fb7af294d5d9 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
Simon Cooksey 0:fb7af294d5d9 780
Simon Cooksey 0:fb7af294d5d9 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
Simon Cooksey 0:fb7af294d5d9 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
Simon Cooksey 0:fb7af294d5d9 783 " CMP R0, #0 \n"
Simon Cooksey 0:fb7af294d5d9 784 " BNE Dccsw \n"
Simon Cooksey 0:fb7af294d5d9 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
Simon Cooksey 0:fb7af294d5d9 786 " B cont \n"
Simon Cooksey 0:fb7af294d5d9 787 "Dccsw: CMP R0, #1 \n"
Simon Cooksey 0:fb7af294d5d9 788 " BNE Dccisw \n"
Simon Cooksey 0:fb7af294d5d9 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
Simon Cooksey 0:fb7af294d5d9 790 " B cont \n"
Simon Cooksey 0:fb7af294d5d9 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
Simon Cooksey 0:fb7af294d5d9 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
Simon Cooksey 0:fb7af294d5d9 793 " BGE Loop3 \n"
Simon Cooksey 0:fb7af294d5d9 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
Simon Cooksey 0:fb7af294d5d9 795 " BGE Loop2 \n"
Simon Cooksey 0:fb7af294d5d9 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
Simon Cooksey 0:fb7af294d5d9 797 " CMP R3, R10 \n"
Simon Cooksey 0:fb7af294d5d9 798 " BGT Loop1 \n"
Simon Cooksey 0:fb7af294d5d9 799
Simon Cooksey 0:fb7af294d5d9 800 "Finished: \n"
Simon Cooksey 0:fb7af294d5d9 801 " DSB \n"
Simon Cooksey 0:fb7af294d5d9 802 " POP {R4-R11} \n"
Simon Cooksey 0:fb7af294d5d9 803 " BX lr \n" );
Simon Cooksey 0:fb7af294d5d9 804 }
Simon Cooksey 0:fb7af294d5d9 805
Simon Cooksey 0:fb7af294d5d9 806 /** \brief Invalidate the whole D$
Simon Cooksey 0:fb7af294d5d9 807
Simon Cooksey 0:fb7af294d5d9 808 DCISW. Invalidate by Set/Way
Simon Cooksey 0:fb7af294d5d9 809 */
Simon Cooksey 0:fb7af294d5d9 810 // from system_Renesas_RZ_A1.c
Simon Cooksey 0:fb7af294d5d9 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Simon Cooksey 0:fb7af294d5d9 812 __v7_all_cache(0);
Simon Cooksey 0:fb7af294d5d9 813 }
Simon Cooksey 0:fb7af294d5d9 814 /** \brief Clean and Invalidate D$ by MVA
Simon Cooksey 0:fb7af294d5d9 815
Simon Cooksey 0:fb7af294d5d9 816 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Simon Cooksey 0:fb7af294d5d9 817 */
Simon Cooksey 0:fb7af294d5d9 818 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Simon Cooksey 0:fb7af294d5d9 819 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
Simon Cooksey 0:fb7af294d5d9 820 __DMB();
Simon Cooksey 0:fb7af294d5d9 821 }
Simon Cooksey 0:fb7af294d5d9 822
Simon Cooksey 0:fb7af294d5d9 823 #include "core_ca_mmu.h"
Simon Cooksey 0:fb7af294d5d9 824
Simon Cooksey 0:fb7af294d5d9 825 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Simon Cooksey 0:fb7af294d5d9 826 /* GNU gcc specific functions */
Simon Cooksey 0:fb7af294d5d9 827
Simon Cooksey 0:fb7af294d5d9 828 #define MODE_USR 0x10
Simon Cooksey 0:fb7af294d5d9 829 #define MODE_FIQ 0x11
Simon Cooksey 0:fb7af294d5d9 830 #define MODE_IRQ 0x12
Simon Cooksey 0:fb7af294d5d9 831 #define MODE_SVC 0x13
Simon Cooksey 0:fb7af294d5d9 832 #define MODE_MON 0x16
Simon Cooksey 0:fb7af294d5d9 833 #define MODE_ABT 0x17
Simon Cooksey 0:fb7af294d5d9 834 #define MODE_HYP 0x1A
Simon Cooksey 0:fb7af294d5d9 835 #define MODE_UND 0x1B
Simon Cooksey 0:fb7af294d5d9 836 #define MODE_SYS 0x1F
Simon Cooksey 0:fb7af294d5d9 837
Simon Cooksey 0:fb7af294d5d9 838
Simon Cooksey 0:fb7af294d5d9 839 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Simon Cooksey 0:fb7af294d5d9 840 {
Simon Cooksey 0:fb7af294d5d9 841 __ASM volatile ("cpsie i");
Simon Cooksey 0:fb7af294d5d9 842 }
Simon Cooksey 0:fb7af294d5d9 843
Simon Cooksey 0:fb7af294d5d9 844 /** \brief Disable IRQ Interrupts
Simon Cooksey 0:fb7af294d5d9 845
Simon Cooksey 0:fb7af294d5d9 846 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Simon Cooksey 0:fb7af294d5d9 847 Can only be executed in Privileged modes.
Simon Cooksey 0:fb7af294d5d9 848 */
Simon Cooksey 0:fb7af294d5d9 849 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Simon Cooksey 0:fb7af294d5d9 850 {
Simon Cooksey 0:fb7af294d5d9 851 uint32_t result;
Simon Cooksey 0:fb7af294d5d9 852
Simon Cooksey 0:fb7af294d5d9 853 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Simon Cooksey 0:fb7af294d5d9 854 __ASM volatile ("cpsid i");
Simon Cooksey 0:fb7af294d5d9 855 return(result & 0x80);
Simon Cooksey 0:fb7af294d5d9 856 }
Simon Cooksey 0:fb7af294d5d9 857
Simon Cooksey 0:fb7af294d5d9 858
Simon Cooksey 0:fb7af294d5d9 859 /** \brief Get APSR Register
Simon Cooksey 0:fb7af294d5d9 860
Simon Cooksey 0:fb7af294d5d9 861 This function returns the content of the APSR Register.
Simon Cooksey 0:fb7af294d5d9 862
Simon Cooksey 0:fb7af294d5d9 863 \return APSR Register value
Simon Cooksey 0:fb7af294d5d9 864 */
Simon Cooksey 0:fb7af294d5d9 865 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Simon Cooksey 0:fb7af294d5d9 866 {
Simon Cooksey 0:fb7af294d5d9 867 #if 1
Simon Cooksey 0:fb7af294d5d9 868 register uint32_t __regAPSR;
Simon Cooksey 0:fb7af294d5d9 869 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Simon Cooksey 0:fb7af294d5d9 870 #else
Simon Cooksey 0:fb7af294d5d9 871 register uint32_t __regAPSR __ASM("apsr");
Simon Cooksey 0:fb7af294d5d9 872 #endif
Simon Cooksey 0:fb7af294d5d9 873 return(__regAPSR);
Simon Cooksey 0:fb7af294d5d9 874 }
Simon Cooksey 0:fb7af294d5d9 875
Simon Cooksey 0:fb7af294d5d9 876
Simon Cooksey 0:fb7af294d5d9 877 /** \brief Get CPSR Register
Simon Cooksey 0:fb7af294d5d9 878
Simon Cooksey 0:fb7af294d5d9 879 This function returns the content of the CPSR Register.
Simon Cooksey 0:fb7af294d5d9 880
Simon Cooksey 0:fb7af294d5d9 881 \return CPSR Register value
Simon Cooksey 0:fb7af294d5d9 882 */
Simon Cooksey 0:fb7af294d5d9 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Simon Cooksey 0:fb7af294d5d9 884 {
Simon Cooksey 0:fb7af294d5d9 885 #if 1
Simon Cooksey 0:fb7af294d5d9 886 register uint32_t __regCPSR;
Simon Cooksey 0:fb7af294d5d9 887 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Simon Cooksey 0:fb7af294d5d9 888 #else
Simon Cooksey 0:fb7af294d5d9 889 register uint32_t __regCPSR __ASM("cpsr");
Simon Cooksey 0:fb7af294d5d9 890 #endif
Simon Cooksey 0:fb7af294d5d9 891 return(__regCPSR);
Simon Cooksey 0:fb7af294d5d9 892 }
Simon Cooksey 0:fb7af294d5d9 893
Simon Cooksey 0:fb7af294d5d9 894 #if 0
Simon Cooksey 0:fb7af294d5d9 895 /** \brief Set Stack Pointer
Simon Cooksey 0:fb7af294d5d9 896
Simon Cooksey 0:fb7af294d5d9 897 This function assigns the given value to the current stack pointer.
Simon Cooksey 0:fb7af294d5d9 898
Simon Cooksey 0:fb7af294d5d9 899 \param [in] topOfStack Stack Pointer value to set
Simon Cooksey 0:fb7af294d5d9 900 */
Simon Cooksey 0:fb7af294d5d9 901 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Simon Cooksey 0:fb7af294d5d9 902 {
Simon Cooksey 0:fb7af294d5d9 903 register uint32_t __regSP __ASM("sp");
Simon Cooksey 0:fb7af294d5d9 904 __regSP = topOfStack;
Simon Cooksey 0:fb7af294d5d9 905 }
Simon Cooksey 0:fb7af294d5d9 906 #endif
Simon Cooksey 0:fb7af294d5d9 907
Simon Cooksey 0:fb7af294d5d9 908 /** \brief Get link register
Simon Cooksey 0:fb7af294d5d9 909
Simon Cooksey 0:fb7af294d5d9 910 This function returns the value of the link register
Simon Cooksey 0:fb7af294d5d9 911
Simon Cooksey 0:fb7af294d5d9 912 \return Value of link register
Simon Cooksey 0:fb7af294d5d9 913 */
Simon Cooksey 0:fb7af294d5d9 914 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Simon Cooksey 0:fb7af294d5d9 915 {
Simon Cooksey 0:fb7af294d5d9 916 register uint32_t __reglr __ASM("lr");
Simon Cooksey 0:fb7af294d5d9 917 return(__reglr);
Simon Cooksey 0:fb7af294d5d9 918 }
Simon Cooksey 0:fb7af294d5d9 919
Simon Cooksey 0:fb7af294d5d9 920 #if 0
Simon Cooksey 0:fb7af294d5d9 921 /** \brief Set link register
Simon Cooksey 0:fb7af294d5d9 922
Simon Cooksey 0:fb7af294d5d9 923 This function sets the value of the link register
Simon Cooksey 0:fb7af294d5d9 924
Simon Cooksey 0:fb7af294d5d9 925 \param [in] lr LR value to set
Simon Cooksey 0:fb7af294d5d9 926 */
Simon Cooksey 0:fb7af294d5d9 927 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Simon Cooksey 0:fb7af294d5d9 928 {
Simon Cooksey 0:fb7af294d5d9 929 register uint32_t __reglr __ASM("lr");
Simon Cooksey 0:fb7af294d5d9 930 __reglr = lr;
Simon Cooksey 0:fb7af294d5d9 931 }
Simon Cooksey 0:fb7af294d5d9 932 #endif
Simon Cooksey 0:fb7af294d5d9 933
Simon Cooksey 0:fb7af294d5d9 934 /** \brief Set Process Stack Pointer
Simon Cooksey 0:fb7af294d5d9 935
Simon Cooksey 0:fb7af294d5d9 936 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Simon Cooksey 0:fb7af294d5d9 937
Simon Cooksey 0:fb7af294d5d9 938 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Simon Cooksey 0:fb7af294d5d9 939 */
Simon Cooksey 0:fb7af294d5d9 940 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Simon Cooksey 0:fb7af294d5d9 941 {
Simon Cooksey 0:fb7af294d5d9 942 __asm__ volatile (
Simon Cooksey 0:fb7af294d5d9 943 ".ARM;"
Simon Cooksey 0:fb7af294d5d9 944 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Simon Cooksey 0:fb7af294d5d9 945
Simon Cooksey 0:fb7af294d5d9 946 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Simon Cooksey 0:fb7af294d5d9 947 "MRS R1, CPSR;"
Simon Cooksey 0:fb7af294d5d9 948 "CPS %0;" /* ;no effect in USR mode */
Simon Cooksey 0:fb7af294d5d9 949 "MOV SP, R0;"
Simon Cooksey 0:fb7af294d5d9 950 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Simon Cooksey 0:fb7af294d5d9 951 "ISB;"
Simon Cooksey 0:fb7af294d5d9 952 //"BX LR;"
Simon Cooksey 0:fb7af294d5d9 953 :
Simon Cooksey 0:fb7af294d5d9 954 : "i"(MODE_SYS)
Simon Cooksey 0:fb7af294d5d9 955 : "r0", "r1");
Simon Cooksey 0:fb7af294d5d9 956 return;
Simon Cooksey 0:fb7af294d5d9 957 }
Simon Cooksey 0:fb7af294d5d9 958
Simon Cooksey 0:fb7af294d5d9 959 /** \brief Set User Mode
Simon Cooksey 0:fb7af294d5d9 960
Simon Cooksey 0:fb7af294d5d9 961 This function changes the processor state to User Mode
Simon Cooksey 0:fb7af294d5d9 962 */
Simon Cooksey 0:fb7af294d5d9 963 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Simon Cooksey 0:fb7af294d5d9 964 {
Simon Cooksey 0:fb7af294d5d9 965 __asm__ volatile (
Simon Cooksey 0:fb7af294d5d9 966 ".ARM;"
Simon Cooksey 0:fb7af294d5d9 967
Simon Cooksey 0:fb7af294d5d9 968 "CPS %0;"
Simon Cooksey 0:fb7af294d5d9 969 //"BX LR;"
Simon Cooksey 0:fb7af294d5d9 970 :
Simon Cooksey 0:fb7af294d5d9 971 : "i"(MODE_USR)
Simon Cooksey 0:fb7af294d5d9 972 : );
Simon Cooksey 0:fb7af294d5d9 973 return;
Simon Cooksey 0:fb7af294d5d9 974 }
Simon Cooksey 0:fb7af294d5d9 975
Simon Cooksey 0:fb7af294d5d9 976
Simon Cooksey 0:fb7af294d5d9 977 /** \brief Enable FIQ
Simon Cooksey 0:fb7af294d5d9 978
Simon Cooksey 0:fb7af294d5d9 979 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Simon Cooksey 0:fb7af294d5d9 980 Can only be executed in Privileged modes.
Simon Cooksey 0:fb7af294d5d9 981 */
Simon Cooksey 0:fb7af294d5d9 982 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Simon Cooksey 0:fb7af294d5d9 983
Simon Cooksey 0:fb7af294d5d9 984
Simon Cooksey 0:fb7af294d5d9 985 /** \brief Disable FIQ
Simon Cooksey 0:fb7af294d5d9 986
Simon Cooksey 0:fb7af294d5d9 987 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Simon Cooksey 0:fb7af294d5d9 988 Can only be executed in Privileged modes.
Simon Cooksey 0:fb7af294d5d9 989 */
Simon Cooksey 0:fb7af294d5d9 990 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Simon Cooksey 0:fb7af294d5d9 991
Simon Cooksey 0:fb7af294d5d9 992
Simon Cooksey 0:fb7af294d5d9 993 /** \brief Get FPSCR
Simon Cooksey 0:fb7af294d5d9 994
Simon Cooksey 0:fb7af294d5d9 995 This function returns the current value of the Floating Point Status/Control register.
Simon Cooksey 0:fb7af294d5d9 996
Simon Cooksey 0:fb7af294d5d9 997 \return Floating Point Status/Control register value
Simon Cooksey 0:fb7af294d5d9 998 */
Simon Cooksey 0:fb7af294d5d9 999 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Simon Cooksey 0:fb7af294d5d9 1000 {
Simon Cooksey 0:fb7af294d5d9 1001 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Simon Cooksey 0:fb7af294d5d9 1002 #if 1
Simon Cooksey 0:fb7af294d5d9 1003 uint32_t result;
Simon Cooksey 0:fb7af294d5d9 1004
Simon Cooksey 0:fb7af294d5d9 1005 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Simon Cooksey 0:fb7af294d5d9 1006 return (result);
Simon Cooksey 0:fb7af294d5d9 1007 #else
Simon Cooksey 0:fb7af294d5d9 1008 register uint32_t __regfpscr __ASM("fpscr");
Simon Cooksey 0:fb7af294d5d9 1009 return(__regfpscr);
Simon Cooksey 0:fb7af294d5d9 1010 #endif
Simon Cooksey 0:fb7af294d5d9 1011 #else
Simon Cooksey 0:fb7af294d5d9 1012 return(0);
Simon Cooksey 0:fb7af294d5d9 1013 #endif
Simon Cooksey 0:fb7af294d5d9 1014 }
Simon Cooksey 0:fb7af294d5d9 1015
Simon Cooksey 0:fb7af294d5d9 1016
Simon Cooksey 0:fb7af294d5d9 1017 /** \brief Set FPSCR
Simon Cooksey 0:fb7af294d5d9 1018
Simon Cooksey 0:fb7af294d5d9 1019 This function assigns the given value to the Floating Point Status/Control register.
Simon Cooksey 0:fb7af294d5d9 1020
Simon Cooksey 0:fb7af294d5d9 1021 \param [in] fpscr Floating Point Status/Control value to set
Simon Cooksey 0:fb7af294d5d9 1022 */
Simon Cooksey 0:fb7af294d5d9 1023 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Simon Cooksey 0:fb7af294d5d9 1024 {
Simon Cooksey 0:fb7af294d5d9 1025 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Simon Cooksey 0:fb7af294d5d9 1026 #if 1
Simon Cooksey 0:fb7af294d5d9 1027 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Simon Cooksey 0:fb7af294d5d9 1028 #else
Simon Cooksey 0:fb7af294d5d9 1029 register uint32_t __regfpscr __ASM("fpscr");
Simon Cooksey 0:fb7af294d5d9 1030 __regfpscr = (fpscr);
Simon Cooksey 0:fb7af294d5d9 1031 #endif
Simon Cooksey 0:fb7af294d5d9 1032 #endif
Simon Cooksey 0:fb7af294d5d9 1033 }
Simon Cooksey 0:fb7af294d5d9 1034
Simon Cooksey 0:fb7af294d5d9 1035 /** \brief Get FPEXC
Simon Cooksey 0:fb7af294d5d9 1036
Simon Cooksey 0:fb7af294d5d9 1037 This function returns the current value of the Floating Point Exception Control register.
Simon Cooksey 0:fb7af294d5d9 1038
Simon Cooksey 0:fb7af294d5d9 1039 \return Floating Point Exception Control register value
Simon Cooksey 0:fb7af294d5d9 1040 */
Simon Cooksey 0:fb7af294d5d9 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Simon Cooksey 0:fb7af294d5d9 1042 {
Simon Cooksey 0:fb7af294d5d9 1043 #if (__FPU_PRESENT == 1)
Simon Cooksey 0:fb7af294d5d9 1044 #if 1
Simon Cooksey 0:fb7af294d5d9 1045 uint32_t result;
Simon Cooksey 0:fb7af294d5d9 1046
Simon Cooksey 0:fb7af294d5d9 1047 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Simon Cooksey 0:fb7af294d5d9 1048 return (result);
Simon Cooksey 0:fb7af294d5d9 1049 #else
Simon Cooksey 0:fb7af294d5d9 1050 register uint32_t __regfpexc __ASM("fpexc");
Simon Cooksey 0:fb7af294d5d9 1051 return(__regfpexc);
Simon Cooksey 0:fb7af294d5d9 1052 #endif
Simon Cooksey 0:fb7af294d5d9 1053 #else
Simon Cooksey 0:fb7af294d5d9 1054 return(0);
Simon Cooksey 0:fb7af294d5d9 1055 #endif
Simon Cooksey 0:fb7af294d5d9 1056 }
Simon Cooksey 0:fb7af294d5d9 1057
Simon Cooksey 0:fb7af294d5d9 1058
Simon Cooksey 0:fb7af294d5d9 1059 /** \brief Set FPEXC
Simon Cooksey 0:fb7af294d5d9 1060
Simon Cooksey 0:fb7af294d5d9 1061 This function assigns the given value to the Floating Point Exception Control register.
Simon Cooksey 0:fb7af294d5d9 1062
Simon Cooksey 0:fb7af294d5d9 1063 \param [in] fpscr Floating Point Exception Control value to set
Simon Cooksey 0:fb7af294d5d9 1064 */
Simon Cooksey 0:fb7af294d5d9 1065 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Simon Cooksey 0:fb7af294d5d9 1066 {
Simon Cooksey 0:fb7af294d5d9 1067 #if (__FPU_PRESENT == 1)
Simon Cooksey 0:fb7af294d5d9 1068 #if 1
Simon Cooksey 0:fb7af294d5d9 1069 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Simon Cooksey 0:fb7af294d5d9 1070 #else
Simon Cooksey 0:fb7af294d5d9 1071 register uint32_t __regfpexc __ASM("fpexc");
Simon Cooksey 0:fb7af294d5d9 1072 __regfpexc = (fpexc);
Simon Cooksey 0:fb7af294d5d9 1073 #endif
Simon Cooksey 0:fb7af294d5d9 1074 #endif
Simon Cooksey 0:fb7af294d5d9 1075 }
Simon Cooksey 0:fb7af294d5d9 1076
Simon Cooksey 0:fb7af294d5d9 1077 /** \brief Get CPACR
Simon Cooksey 0:fb7af294d5d9 1078
Simon Cooksey 0:fb7af294d5d9 1079 This function returns the current value of the Coprocessor Access Control register.
Simon Cooksey 0:fb7af294d5d9 1080
Simon Cooksey 0:fb7af294d5d9 1081 \return Coprocessor Access Control register value
Simon Cooksey 0:fb7af294d5d9 1082 */
Simon Cooksey 0:fb7af294d5d9 1083 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Simon Cooksey 0:fb7af294d5d9 1084 {
Simon Cooksey 0:fb7af294d5d9 1085 #if 1
Simon Cooksey 0:fb7af294d5d9 1086 register uint32_t __regCPACR;
Simon Cooksey 0:fb7af294d5d9 1087 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Simon Cooksey 0:fb7af294d5d9 1088 #else
Simon Cooksey 0:fb7af294d5d9 1089 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Simon Cooksey 0:fb7af294d5d9 1090 #endif
Simon Cooksey 0:fb7af294d5d9 1091 return __regCPACR;
Simon Cooksey 0:fb7af294d5d9 1092 }
Simon Cooksey 0:fb7af294d5d9 1093
Simon Cooksey 0:fb7af294d5d9 1094 /** \brief Set CPACR
Simon Cooksey 0:fb7af294d5d9 1095
Simon Cooksey 0:fb7af294d5d9 1096 This function assigns the given value to the Coprocessor Access Control register.
Simon Cooksey 0:fb7af294d5d9 1097
Simon Cooksey 0:fb7af294d5d9 1098 \param [in] cpacr Coprocessor Acccess Control value to set
Simon Cooksey 0:fb7af294d5d9 1099 */
Simon Cooksey 0:fb7af294d5d9 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Simon Cooksey 0:fb7af294d5d9 1101 {
Simon Cooksey 0:fb7af294d5d9 1102 #if 1
Simon Cooksey 0:fb7af294d5d9 1103 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Simon Cooksey 0:fb7af294d5d9 1104 #else
Simon Cooksey 0:fb7af294d5d9 1105 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Simon Cooksey 0:fb7af294d5d9 1106 __regCPACR = cpacr;
Simon Cooksey 0:fb7af294d5d9 1107 #endif
Simon Cooksey 0:fb7af294d5d9 1108 __ISB();
Simon Cooksey 0:fb7af294d5d9 1109 }
Simon Cooksey 0:fb7af294d5d9 1110
Simon Cooksey 0:fb7af294d5d9 1111 /** \brief Get CBAR
Simon Cooksey 0:fb7af294d5d9 1112
Simon Cooksey 0:fb7af294d5d9 1113 This function returns the value of the Configuration Base Address register.
Simon Cooksey 0:fb7af294d5d9 1114
Simon Cooksey 0:fb7af294d5d9 1115 \return Configuration Base Address register value
Simon Cooksey 0:fb7af294d5d9 1116 */
Simon Cooksey 0:fb7af294d5d9 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Simon Cooksey 0:fb7af294d5d9 1118 #if 1
Simon Cooksey 0:fb7af294d5d9 1119 register uint32_t __regCBAR;
Simon Cooksey 0:fb7af294d5d9 1120 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Simon Cooksey 0:fb7af294d5d9 1121 #else
Simon Cooksey 0:fb7af294d5d9 1122 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Simon Cooksey 0:fb7af294d5d9 1123 #endif
Simon Cooksey 0:fb7af294d5d9 1124 return(__regCBAR);
Simon Cooksey 0:fb7af294d5d9 1125 }
Simon Cooksey 0:fb7af294d5d9 1126
Simon Cooksey 0:fb7af294d5d9 1127 /** \brief Get TTBR0
Simon Cooksey 0:fb7af294d5d9 1128
Simon Cooksey 0:fb7af294d5d9 1129 This function returns the value of the Translation Table Base Register 0.
Simon Cooksey 0:fb7af294d5d9 1130
Simon Cooksey 0:fb7af294d5d9 1131 \return Translation Table Base Register 0 value
Simon Cooksey 0:fb7af294d5d9 1132 */
Simon Cooksey 0:fb7af294d5d9 1133 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Simon Cooksey 0:fb7af294d5d9 1134 #if 1
Simon Cooksey 0:fb7af294d5d9 1135 register uint32_t __regTTBR0;
Simon Cooksey 0:fb7af294d5d9 1136 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Simon Cooksey 0:fb7af294d5d9 1137 #else
Simon Cooksey 0:fb7af294d5d9 1138 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Simon Cooksey 0:fb7af294d5d9 1139 #endif
Simon Cooksey 0:fb7af294d5d9 1140 return(__regTTBR0);
Simon Cooksey 0:fb7af294d5d9 1141 }
Simon Cooksey 0:fb7af294d5d9 1142
Simon Cooksey 0:fb7af294d5d9 1143 /** \brief Set TTBR0
Simon Cooksey 0:fb7af294d5d9 1144
Simon Cooksey 0:fb7af294d5d9 1145 This function assigns the given value to the Translation Table Base Register 0.
Simon Cooksey 0:fb7af294d5d9 1146
Simon Cooksey 0:fb7af294d5d9 1147 \param [in] ttbr0 Translation Table Base Register 0 value to set
Simon Cooksey 0:fb7af294d5d9 1148 */
Simon Cooksey 0:fb7af294d5d9 1149 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Simon Cooksey 0:fb7af294d5d9 1150 #if 1
Simon Cooksey 0:fb7af294d5d9 1151 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Simon Cooksey 0:fb7af294d5d9 1152 #else
Simon Cooksey 0:fb7af294d5d9 1153 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Simon Cooksey 0:fb7af294d5d9 1154 __regTTBR0 = ttbr0;
Simon Cooksey 0:fb7af294d5d9 1155 #endif
Simon Cooksey 0:fb7af294d5d9 1156 __ISB();
Simon Cooksey 0:fb7af294d5d9 1157 }
Simon Cooksey 0:fb7af294d5d9 1158
Simon Cooksey 0:fb7af294d5d9 1159 /** \brief Get DACR
Simon Cooksey 0:fb7af294d5d9 1160
Simon Cooksey 0:fb7af294d5d9 1161 This function returns the value of the Domain Access Control Register.
Simon Cooksey 0:fb7af294d5d9 1162
Simon Cooksey 0:fb7af294d5d9 1163 \return Domain Access Control Register value
Simon Cooksey 0:fb7af294d5d9 1164 */
Simon Cooksey 0:fb7af294d5d9 1165 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Simon Cooksey 0:fb7af294d5d9 1166 #if 1
Simon Cooksey 0:fb7af294d5d9 1167 register uint32_t __regDACR;
Simon Cooksey 0:fb7af294d5d9 1168 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Simon Cooksey 0:fb7af294d5d9 1169 #else
Simon Cooksey 0:fb7af294d5d9 1170 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Simon Cooksey 0:fb7af294d5d9 1171 #endif
Simon Cooksey 0:fb7af294d5d9 1172 return(__regDACR);
Simon Cooksey 0:fb7af294d5d9 1173 }
Simon Cooksey 0:fb7af294d5d9 1174
Simon Cooksey 0:fb7af294d5d9 1175 /** \brief Set DACR
Simon Cooksey 0:fb7af294d5d9 1176
Simon Cooksey 0:fb7af294d5d9 1177 This function assigns the given value to the Domain Access Control Register.
Simon Cooksey 0:fb7af294d5d9 1178
Simon Cooksey 0:fb7af294d5d9 1179 \param [in] dacr Domain Access Control Register value to set
Simon Cooksey 0:fb7af294d5d9 1180 */
Simon Cooksey 0:fb7af294d5d9 1181 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Simon Cooksey 0:fb7af294d5d9 1182 #if 1
Simon Cooksey 0:fb7af294d5d9 1183 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Simon Cooksey 0:fb7af294d5d9 1184 #else
Simon Cooksey 0:fb7af294d5d9 1185 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Simon Cooksey 0:fb7af294d5d9 1186 __regDACR = dacr;
Simon Cooksey 0:fb7af294d5d9 1187 #endif
Simon Cooksey 0:fb7af294d5d9 1188 __ISB();
Simon Cooksey 0:fb7af294d5d9 1189 }
Simon Cooksey 0:fb7af294d5d9 1190
Simon Cooksey 0:fb7af294d5d9 1191 /******************************** Cache and BTAC enable ****************************************************/
Simon Cooksey 0:fb7af294d5d9 1192
Simon Cooksey 0:fb7af294d5d9 1193 /** \brief Set SCTLR
Simon Cooksey 0:fb7af294d5d9 1194
Simon Cooksey 0:fb7af294d5d9 1195 This function assigns the given value to the System Control Register.
Simon Cooksey 0:fb7af294d5d9 1196
Simon Cooksey 0:fb7af294d5d9 1197 \param [in] sctlr System Control Register value to set
Simon Cooksey 0:fb7af294d5d9 1198 */
Simon Cooksey 0:fb7af294d5d9 1199 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Simon Cooksey 0:fb7af294d5d9 1200 {
Simon Cooksey 0:fb7af294d5d9 1201 #if 1
Simon Cooksey 0:fb7af294d5d9 1202 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Simon Cooksey 0:fb7af294d5d9 1203 #else
Simon Cooksey 0:fb7af294d5d9 1204 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Simon Cooksey 0:fb7af294d5d9 1205 __regSCTLR = sctlr;
Simon Cooksey 0:fb7af294d5d9 1206 #endif
Simon Cooksey 0:fb7af294d5d9 1207 }
Simon Cooksey 0:fb7af294d5d9 1208
Simon Cooksey 0:fb7af294d5d9 1209 /** \brief Get SCTLR
Simon Cooksey 0:fb7af294d5d9 1210
Simon Cooksey 0:fb7af294d5d9 1211 This function returns the value of the System Control Register.
Simon Cooksey 0:fb7af294d5d9 1212
Simon Cooksey 0:fb7af294d5d9 1213 \return System Control Register value
Simon Cooksey 0:fb7af294d5d9 1214 */
Simon Cooksey 0:fb7af294d5d9 1215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Simon Cooksey 0:fb7af294d5d9 1216 #if 1
Simon Cooksey 0:fb7af294d5d9 1217 register uint32_t __regSCTLR;
Simon Cooksey 0:fb7af294d5d9 1218 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Simon Cooksey 0:fb7af294d5d9 1219 #else
Simon Cooksey 0:fb7af294d5d9 1220 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Simon Cooksey 0:fb7af294d5d9 1221 #endif
Simon Cooksey 0:fb7af294d5d9 1222 return(__regSCTLR);
Simon Cooksey 0:fb7af294d5d9 1223 }
Simon Cooksey 0:fb7af294d5d9 1224
Simon Cooksey 0:fb7af294d5d9 1225 /** \brief Enable Caches
Simon Cooksey 0:fb7af294d5d9 1226
Simon Cooksey 0:fb7af294d5d9 1227 Enable Caches
Simon Cooksey 0:fb7af294d5d9 1228 */
Simon Cooksey 0:fb7af294d5d9 1229 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Simon Cooksey 0:fb7af294d5d9 1230 // Set I bit 12 to enable I Cache
Simon Cooksey 0:fb7af294d5d9 1231 // Set C bit 2 to enable D Cache
Simon Cooksey 0:fb7af294d5d9 1232 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Simon Cooksey 0:fb7af294d5d9 1233 }
Simon Cooksey 0:fb7af294d5d9 1234
Simon Cooksey 0:fb7af294d5d9 1235 /** \brief Disable Caches
Simon Cooksey 0:fb7af294d5d9 1236
Simon Cooksey 0:fb7af294d5d9 1237 Disable Caches
Simon Cooksey 0:fb7af294d5d9 1238 */
Simon Cooksey 0:fb7af294d5d9 1239 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Simon Cooksey 0:fb7af294d5d9 1240 // Clear I bit 12 to disable I Cache
Simon Cooksey 0:fb7af294d5d9 1241 // Clear C bit 2 to disable D Cache
Simon Cooksey 0:fb7af294d5d9 1242 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Simon Cooksey 0:fb7af294d5d9 1243 __ISB();
Simon Cooksey 0:fb7af294d5d9 1244 }
Simon Cooksey 0:fb7af294d5d9 1245
Simon Cooksey 0:fb7af294d5d9 1246 /** \brief Enable BTAC
Simon Cooksey 0:fb7af294d5d9 1247
Simon Cooksey 0:fb7af294d5d9 1248 Enable BTAC
Simon Cooksey 0:fb7af294d5d9 1249 */
Simon Cooksey 0:fb7af294d5d9 1250 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Simon Cooksey 0:fb7af294d5d9 1251 // Set Z bit 11 to enable branch prediction
Simon Cooksey 0:fb7af294d5d9 1252 __set_SCTLR( __get_SCTLR() | (1 << 11));
Simon Cooksey 0:fb7af294d5d9 1253 __ISB();
Simon Cooksey 0:fb7af294d5d9 1254 }
Simon Cooksey 0:fb7af294d5d9 1255
Simon Cooksey 0:fb7af294d5d9 1256 /** \brief Disable BTAC
Simon Cooksey 0:fb7af294d5d9 1257
Simon Cooksey 0:fb7af294d5d9 1258 Disable BTAC
Simon Cooksey 0:fb7af294d5d9 1259 */
Simon Cooksey 0:fb7af294d5d9 1260 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Simon Cooksey 0:fb7af294d5d9 1261 // Clear Z bit 11 to disable branch prediction
Simon Cooksey 0:fb7af294d5d9 1262 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Simon Cooksey 0:fb7af294d5d9 1263 }
Simon Cooksey 0:fb7af294d5d9 1264
Simon Cooksey 0:fb7af294d5d9 1265
Simon Cooksey 0:fb7af294d5d9 1266 /** \brief Enable MMU
Simon Cooksey 0:fb7af294d5d9 1267
Simon Cooksey 0:fb7af294d5d9 1268 Enable MMU
Simon Cooksey 0:fb7af294d5d9 1269 */
Simon Cooksey 0:fb7af294d5d9 1270 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Simon Cooksey 0:fb7af294d5d9 1271 // Set M bit 0 to enable the MMU
Simon Cooksey 0:fb7af294d5d9 1272 // Set AFE bit to enable simplified access permissions model
Simon Cooksey 0:fb7af294d5d9 1273 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Simon Cooksey 0:fb7af294d5d9 1274 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Simon Cooksey 0:fb7af294d5d9 1275 __ISB();
Simon Cooksey 0:fb7af294d5d9 1276 }
Simon Cooksey 0:fb7af294d5d9 1277
Simon Cooksey 0:fb7af294d5d9 1278 /** \brief Disable MMU
Simon Cooksey 0:fb7af294d5d9 1279
Simon Cooksey 0:fb7af294d5d9 1280 Disable MMU
Simon Cooksey 0:fb7af294d5d9 1281 */
Simon Cooksey 0:fb7af294d5d9 1282 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Simon Cooksey 0:fb7af294d5d9 1283 // Clear M bit 0 to disable the MMU
Simon Cooksey 0:fb7af294d5d9 1284 __set_SCTLR( __get_SCTLR() & ~1);
Simon Cooksey 0:fb7af294d5d9 1285 __ISB();
Simon Cooksey 0:fb7af294d5d9 1286 }
Simon Cooksey 0:fb7af294d5d9 1287
Simon Cooksey 0:fb7af294d5d9 1288 /******************************** TLB maintenance operations ************************************************/
Simon Cooksey 0:fb7af294d5d9 1289 /** \brief Invalidate the whole tlb
Simon Cooksey 0:fb7af294d5d9 1290
Simon Cooksey 0:fb7af294d5d9 1291 TLBIALL. Invalidate the whole tlb
Simon Cooksey 0:fb7af294d5d9 1292 */
Simon Cooksey 0:fb7af294d5d9 1293
Simon Cooksey 0:fb7af294d5d9 1294 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Simon Cooksey 0:fb7af294d5d9 1295 #if 1
Simon Cooksey 0:fb7af294d5d9 1296 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Simon Cooksey 0:fb7af294d5d9 1297 #else
Simon Cooksey 0:fb7af294d5d9 1298 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Simon Cooksey 0:fb7af294d5d9 1299 __TLBIALL = 0;
Simon Cooksey 0:fb7af294d5d9 1300 #endif
Simon Cooksey 0:fb7af294d5d9 1301 __DSB();
Simon Cooksey 0:fb7af294d5d9 1302 __ISB();
Simon Cooksey 0:fb7af294d5d9 1303 }
Simon Cooksey 0:fb7af294d5d9 1304
Simon Cooksey 0:fb7af294d5d9 1305 /******************************** BTB maintenance operations ************************************************/
Simon Cooksey 0:fb7af294d5d9 1306 /** \brief Invalidate entire branch predictor array
Simon Cooksey 0:fb7af294d5d9 1307
Simon Cooksey 0:fb7af294d5d9 1308 BPIALL. Branch Predictor Invalidate All.
Simon Cooksey 0:fb7af294d5d9 1309 */
Simon Cooksey 0:fb7af294d5d9 1310
Simon Cooksey 0:fb7af294d5d9 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Simon Cooksey 0:fb7af294d5d9 1312 #if 1
Simon Cooksey 0:fb7af294d5d9 1313 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Simon Cooksey 0:fb7af294d5d9 1314 #else
Simon Cooksey 0:fb7af294d5d9 1315 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Simon Cooksey 0:fb7af294d5d9 1316 __BPIALL = 0;
Simon Cooksey 0:fb7af294d5d9 1317 #endif
Simon Cooksey 0:fb7af294d5d9 1318 __DSB(); //ensure completion of the invalidation
Simon Cooksey 0:fb7af294d5d9 1319 __ISB(); //ensure instruction fetch path sees new state
Simon Cooksey 0:fb7af294d5d9 1320 }
Simon Cooksey 0:fb7af294d5d9 1321
Simon Cooksey 0:fb7af294d5d9 1322
Simon Cooksey 0:fb7af294d5d9 1323 /******************************** L1 cache operations ******************************************************/
Simon Cooksey 0:fb7af294d5d9 1324
Simon Cooksey 0:fb7af294d5d9 1325 /** \brief Invalidate the whole I$
Simon Cooksey 0:fb7af294d5d9 1326
Simon Cooksey 0:fb7af294d5d9 1327 ICIALLU. Instruction Cache Invalidate All to PoU
Simon Cooksey 0:fb7af294d5d9 1328 */
Simon Cooksey 0:fb7af294d5d9 1329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Simon Cooksey 0:fb7af294d5d9 1330 #if 1
Simon Cooksey 0:fb7af294d5d9 1331 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Simon Cooksey 0:fb7af294d5d9 1332 #else
Simon Cooksey 0:fb7af294d5d9 1333 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Simon Cooksey 0:fb7af294d5d9 1334 __ICIALLU = 0;
Simon Cooksey 0:fb7af294d5d9 1335 #endif
Simon Cooksey 0:fb7af294d5d9 1336 __DSB(); //ensure completion of the invalidation
Simon Cooksey 0:fb7af294d5d9 1337 __ISB(); //ensure instruction fetch path sees new I cache state
Simon Cooksey 0:fb7af294d5d9 1338 }
Simon Cooksey 0:fb7af294d5d9 1339
Simon Cooksey 0:fb7af294d5d9 1340 /** \brief Clean D$ by MVA
Simon Cooksey 0:fb7af294d5d9 1341
Simon Cooksey 0:fb7af294d5d9 1342 DCCMVAC. Data cache clean by MVA to PoC
Simon Cooksey 0:fb7af294d5d9 1343 */
Simon Cooksey 0:fb7af294d5d9 1344 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Simon Cooksey 0:fb7af294d5d9 1345 #if 1
Simon Cooksey 0:fb7af294d5d9 1346 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Simon Cooksey 0:fb7af294d5d9 1347 #else
Simon Cooksey 0:fb7af294d5d9 1348 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Simon Cooksey 0:fb7af294d5d9 1349 __DCCMVAC = (uint32_t)va;
Simon Cooksey 0:fb7af294d5d9 1350 #endif
Simon Cooksey 0:fb7af294d5d9 1351 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Simon Cooksey 0:fb7af294d5d9 1352 }
Simon Cooksey 0:fb7af294d5d9 1353
Simon Cooksey 0:fb7af294d5d9 1354 /** \brief Invalidate D$ by MVA
Simon Cooksey 0:fb7af294d5d9 1355
Simon Cooksey 0:fb7af294d5d9 1356 DCIMVAC. Data cache invalidate by MVA to PoC
Simon Cooksey 0:fb7af294d5d9 1357 */
Simon Cooksey 0:fb7af294d5d9 1358 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Simon Cooksey 0:fb7af294d5d9 1359 #if 1
Simon Cooksey 0:fb7af294d5d9 1360 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Simon Cooksey 0:fb7af294d5d9 1361 #else
Simon Cooksey 0:fb7af294d5d9 1362 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Simon Cooksey 0:fb7af294d5d9 1363 __DCIMVAC = (uint32_t)va;
Simon Cooksey 0:fb7af294d5d9 1364 #endif
Simon Cooksey 0:fb7af294d5d9 1365 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Simon Cooksey 0:fb7af294d5d9 1366 }
Simon Cooksey 0:fb7af294d5d9 1367
Simon Cooksey 0:fb7af294d5d9 1368 /** \brief Clean and Invalidate D$ by MVA
Simon Cooksey 0:fb7af294d5d9 1369
Simon Cooksey 0:fb7af294d5d9 1370 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Simon Cooksey 0:fb7af294d5d9 1371 */
Simon Cooksey 0:fb7af294d5d9 1372 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Simon Cooksey 0:fb7af294d5d9 1373 #if 1
Simon Cooksey 0:fb7af294d5d9 1374 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Simon Cooksey 0:fb7af294d5d9 1375 #else
Simon Cooksey 0:fb7af294d5d9 1376 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Simon Cooksey 0:fb7af294d5d9 1377 __DCCIMVAC = (uint32_t)va;
Simon Cooksey 0:fb7af294d5d9 1378 #endif
Simon Cooksey 0:fb7af294d5d9 1379 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Simon Cooksey 0:fb7af294d5d9 1380 }
Simon Cooksey 0:fb7af294d5d9 1381
Simon Cooksey 0:fb7af294d5d9 1382 /** \brief Clean and Invalidate the entire data or unified cache
Simon Cooksey 0:fb7af294d5d9 1383
Simon Cooksey 0:fb7af294d5d9 1384 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Simon Cooksey 0:fb7af294d5d9 1385 */
Simon Cooksey 0:fb7af294d5d9 1386 extern void __v7_all_cache(uint32_t op);
Simon Cooksey 0:fb7af294d5d9 1387
Simon Cooksey 0:fb7af294d5d9 1388
Simon Cooksey 0:fb7af294d5d9 1389 /** \brief Invalidate the whole D$
Simon Cooksey 0:fb7af294d5d9 1390
Simon Cooksey 0:fb7af294d5d9 1391 DCISW. Invalidate by Set/Way
Simon Cooksey 0:fb7af294d5d9 1392 */
Simon Cooksey 0:fb7af294d5d9 1393
Simon Cooksey 0:fb7af294d5d9 1394 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Simon Cooksey 0:fb7af294d5d9 1395 __v7_all_cache(0);
Simon Cooksey 0:fb7af294d5d9 1396 }
Simon Cooksey 0:fb7af294d5d9 1397
Simon Cooksey 0:fb7af294d5d9 1398 /** \brief Clean the whole D$
Simon Cooksey 0:fb7af294d5d9 1399
Simon Cooksey 0:fb7af294d5d9 1400 DCCSW. Clean by Set/Way
Simon Cooksey 0:fb7af294d5d9 1401 */
Simon Cooksey 0:fb7af294d5d9 1402
Simon Cooksey 0:fb7af294d5d9 1403 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Simon Cooksey 0:fb7af294d5d9 1404 __v7_all_cache(1);
Simon Cooksey 0:fb7af294d5d9 1405 }
Simon Cooksey 0:fb7af294d5d9 1406
Simon Cooksey 0:fb7af294d5d9 1407 /** \brief Clean and invalidate the whole D$
Simon Cooksey 0:fb7af294d5d9 1408
Simon Cooksey 0:fb7af294d5d9 1409 DCCISW. Clean and Invalidate by Set/Way
Simon Cooksey 0:fb7af294d5d9 1410 */
Simon Cooksey 0:fb7af294d5d9 1411
Simon Cooksey 0:fb7af294d5d9 1412 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Simon Cooksey 0:fb7af294d5d9 1413 __v7_all_cache(2);
Simon Cooksey 0:fb7af294d5d9 1414 }
Simon Cooksey 0:fb7af294d5d9 1415
Simon Cooksey 0:fb7af294d5d9 1416 #include "core_ca_mmu.h"
Simon Cooksey 0:fb7af294d5d9 1417
Simon Cooksey 0:fb7af294d5d9 1418 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Simon Cooksey 0:fb7af294d5d9 1419
Simon Cooksey 0:fb7af294d5d9 1420 #error TASKING Compiler support not implemented for Cortex-A
Simon Cooksey 0:fb7af294d5d9 1421
Simon Cooksey 0:fb7af294d5d9 1422 #endif
Simon Cooksey 0:fb7af294d5d9 1423
Simon Cooksey 0:fb7af294d5d9 1424 /*@} end of CMSIS_Core_RegAccFunctions */
Simon Cooksey 0:fb7af294d5d9 1425
Simon Cooksey 0:fb7af294d5d9 1426
Simon Cooksey 0:fb7af294d5d9 1427 #endif /* __CORE_CAFUNC_H__ */