Diff: C12832_lcd.cpp

Revision:

2:bdc53502af17

Parent:

1:66dd8afbfd06

Child:

3:468cdccff7af

diff -r 66dd8afbfd06 -r bdc53502af17 C12832_lcd.cpp
--- a/C12832_lcd.cpp	Tue Oct 16 17:50:37 2012 +0000
+++ b/C12832_lcd.cpp	Thu Oct 18 20:54:09 2012 +0000
@@ -80,7 +80,7 @@
 {
     contrast = o;
     wr_cmd(0x81);      //  set volume
-    wr_cmd(o & 0x2F);
+    wr_cmd(o & 0x3F);
 }
 
 unsigned int C12832_LCD::get_contrast(void)
@@ -95,10 +95,14 @@
 {
     _A0 = 0;
     _CS = 0;
+#if defined TARGET_LPC1768     // fast without mbed lib
     LPC_SSP1->DR = cmd;
     do {
     } while ((LPC_SSP1->SR & 0x10) == 0x10); // wait for SPI1 idle
-    _CS = 1;
+#else
+    _spi.write(cmd);
+#endif
+_CS = 1;
 }
 
 // write data to lcd controller
@@ -107,9 +111,13 @@
 {
     _A0 = 1;
     _CS = 0;
+#if defined TARGET_LPC1768     // fast without mbed lib
     LPC_SSP1->DR = dat;
     do {
     } while ((LPC_SSP1->SR & 0x10) == 0x10); // wait for SPI1 idle
+#else
+    _spi.write(dat);
+#endif
     _CS = 1;
 }
 
@@ -147,12 +155,14 @@
 
     wr_cmd(0xA6);     // display normal
 
-    //setup DMA channel 0
+    
+#if defined TARGET_LPC1768          //setup DMA channel 0       
     LPC_SC->PCONP |= (1UL << 29);   // Power up the GPDMA
-    LPC_GPDMA->DMACConfig = 1;          // enable DMA controller
+    LPC_GPDMA->DMACConfig = 1;      // enable DMA controller
     LPC_GPDMA->DMACIntTCClear = 0x1;
     LPC_GPDMA->DMACIntErrClr = 0x1;
     LPC_GPDMACH0->DMACCLLI = 0;
+#endif
     // clear and update LCD
     memset(buffer,0x00,512);  // clear display buffer
     copy_to_lcd();
@@ -180,12 +190,16 @@
 
 void C12832_LCD::copy_to_lcd(void)
 {
+#ifndef TARGET_LPC1768 
+    int i;
+#endif
     //page 0
     wr_cmd(0x00);      // set column low nibble 0
     wr_cmd(0x10);      // set column hi  nibble 0
     wr_cmd(0xB0);      // set page address  0
+    _A0 = 1;
+#if defined TARGET_LPC1768     
     _CS = 0;
-    _A0 = 1;
     // start 128 byte DMA transfer to SPI1
     LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP1->DR; // we send to SSP1
     LPC_SSP1->DMACR = 0x2;  // Enable SSP1 for DMA.
@@ -200,13 +214,19 @@
     do {
     } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI1 not idle
     _CS = 1;
+#else  // no DMA
+    for(i=0;i<128;i++){
+        wr_dat(buffer[i]);
+        }
+#endif 
 
     // page 1
     wr_cmd(0x00);      // set column low nibble 0
     wr_cmd(0x10);      // set column hi  nibble 0
     wr_cmd(0xB1);      // set page address  1
+    _A0 = 1;
+#if defined TARGET_LPC1768         
     _CS = 0;
-    _A0 = 1;
     // start 128 byte DMA transfer to SPI1
     LPC_GPDMA->DMACIntTCClear = 0x1;
     LPC_GPDMA->DMACIntErrClr = 0x1;
@@ -219,13 +239,19 @@
     do {
     } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI1 not idle
     _CS = 1;
+#else // no DMA
+    for(i=128;i<256;i++){
+        wr_dat(buffer[i]);
+        }
+#endif     
 
     //page 2
     wr_cmd(0x00);      // set column low nibble 0
     wr_cmd(0x10);      // set column hi  nibble 0
     wr_cmd(0xB2);      // set page address  2
+    _A0 = 1;
+#if defined TARGET_LPC1768      
     _CS = 0;
-    _A0 = 1;
     // start 128 byte DMA transfer to SPI1
     LPC_GPDMA->DMACIntTCClear = 0x1;
     LPC_GPDMA->DMACIntErrClr = 0x1;
@@ -238,13 +264,20 @@
     do {
     } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI1 not idle
     _CS = 1;
-    
+#else // no DMA
+    for(i=256;i<384;i++){
+        wr_dat(buffer[i]);
+        }
+#endif         
+
     //page 3
     wr_cmd(0x00);      // set column low nibble 0
     wr_cmd(0x10);      // set column hi  nibble 0
     wr_cmd(0xB3);      // set page address  3
-    _CS = 0;
     _A0 = 1;
+    
+     _CS = 0;
+#if defined TARGET_LPC1768     
     // start 128 byte DMA transfer to SPI1
     LPC_GPDMA->DMACIntTCClear = 0x1;
     LPC_GPDMA->DMACIntErrClr = 0x1;
@@ -257,6 +290,11 @@
     do {
     } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI1 not idle
     _CS = 1;
+#else // no DMA
+    for(i=384;i<512;i++){
+        wr_dat(buffer[i]);
+        }
+#endif   
 }
 
 void C12832_LCD::cls(void)