MyUSBHost library
Fork of USBHost by
USBHost/USBHALHost_RZ_A1.cpp@30:d3b77affed28, 2015-03-31 (annotated)
- Committer:
- mbed_official
- Date:
- Tue Mar 31 16:15:42 2015 +0100
- Revision:
- 30:d3b77affed28
- Parent:
- 28:8e62b6403505
Synchronized with git revision 251f3f8b55a4dc98b831c80e032464ed45cce309
Full URL: https://github.com/mbedmicro/mbed/commit/251f3f8b55a4dc98b831c80e032464ed45cce309/
[RZ/A1H]Add some function(USB 2port, NVIC wrapper) and modify some settings(OS, Terminal).
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 27:4206883f4cb7 | 1 | /* mbed USBHost Library |
mbed_official | 27:4206883f4cb7 | 2 | * Copyright (c) 2006-2013 ARM Limited |
mbed_official | 27:4206883f4cb7 | 3 | * |
mbed_official | 27:4206883f4cb7 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
mbed_official | 27:4206883f4cb7 | 5 | * you may not use this file except in compliance with the License. |
mbed_official | 27:4206883f4cb7 | 6 | * You may obtain a copy of the License at |
mbed_official | 27:4206883f4cb7 | 7 | * |
mbed_official | 27:4206883f4cb7 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
mbed_official | 27:4206883f4cb7 | 9 | * |
mbed_official | 27:4206883f4cb7 | 10 | * Unless required by applicable law or agreed to in writing, software |
mbed_official | 27:4206883f4cb7 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
mbed_official | 27:4206883f4cb7 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
mbed_official | 27:4206883f4cb7 | 13 | * See the License for the specific language governing permissions and |
mbed_official | 27:4206883f4cb7 | 14 | * limitations under the License. |
mbed_official | 27:4206883f4cb7 | 15 | */ |
mbed_official | 27:4206883f4cb7 | 16 | |
mbed_official | 27:4206883f4cb7 | 17 | #if defined(TARGET_RZ_A1H) |
mbed_official | 27:4206883f4cb7 | 18 | |
mbed_official | 27:4206883f4cb7 | 19 | #include "mbed.h" |
mbed_official | 27:4206883f4cb7 | 20 | #include "USBHALHost.h" |
mbed_official | 27:4206883f4cb7 | 21 | #include "dbg.h" |
mbed_official | 27:4206883f4cb7 | 22 | |
mbed_official | 27:4206883f4cb7 | 23 | #include "ohci_wrapp_RZ_A1.h" |
mbed_official | 27:4206883f4cb7 | 24 | |
mbed_official | 27:4206883f4cb7 | 25 | |
mbed_official | 27:4206883f4cb7 | 26 | #define HCCA_SIZE sizeof(HCCA) |
mbed_official | 27:4206883f4cb7 | 27 | #define ED_SIZE sizeof(HCED) |
mbed_official | 27:4206883f4cb7 | 28 | #define TD_SIZE sizeof(HCTD) |
mbed_official | 27:4206883f4cb7 | 29 | |
mbed_official | 27:4206883f4cb7 | 30 | #define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE)) |
mbed_official | 27:4206883f4cb7 | 31 | #define ALIGNE_MSK (0x0000000F) |
mbed_official | 27:4206883f4cb7 | 32 | |
mbed_official | 27:4206883f4cb7 | 33 | static volatile uint8_t usb_buf[TOTAL_SIZE + ALIGNE_MSK]; //16 bytes aligned! |
mbed_official | 27:4206883f4cb7 | 34 | |
mbed_official | 27:4206883f4cb7 | 35 | USBHALHost * USBHALHost::instHost; |
mbed_official | 27:4206883f4cb7 | 36 | |
mbed_official | 27:4206883f4cb7 | 37 | USBHALHost::USBHALHost() { |
mbed_official | 27:4206883f4cb7 | 38 | instHost = this; |
mbed_official | 27:4206883f4cb7 | 39 | memInit(); |
mbed_official | 27:4206883f4cb7 | 40 | memset((void*)usb_hcca, 0, HCCA_SIZE); |
mbed_official | 27:4206883f4cb7 | 41 | for (int i = 0; i < MAX_ENDPOINT; i++) { |
mbed_official | 27:4206883f4cb7 | 42 | edBufAlloc[i] = false; |
mbed_official | 27:4206883f4cb7 | 43 | } |
mbed_official | 27:4206883f4cb7 | 44 | for (int i = 0; i < MAX_TD; i++) { |
mbed_official | 27:4206883f4cb7 | 45 | tdBufAlloc[i] = false; |
mbed_official | 27:4206883f4cb7 | 46 | } |
mbed_official | 27:4206883f4cb7 | 47 | } |
mbed_official | 27:4206883f4cb7 | 48 | |
mbed_official | 27:4206883f4cb7 | 49 | void USBHALHost::init() { |
mbed_official | 30:d3b77affed28 | 50 | ohciwrapp_init(&_usbisr); |
mbed_official | 27:4206883f4cb7 | 51 | |
mbed_official | 27:4206883f4cb7 | 52 | ohciwrapp_reg_w(OHCI_REG_CONTROL, 1); // HARDWARE RESET |
mbed_official | 27:4206883f4cb7 | 53 | ohciwrapp_reg_w(OHCI_REG_CONTROLHEADED, 0); // Initialize Control list head to Zero |
mbed_official | 27:4206883f4cb7 | 54 | ohciwrapp_reg_w(OHCI_REG_BULKHEADED, 0); // Initialize Bulk list head to Zero |
mbed_official | 27:4206883f4cb7 | 55 | |
mbed_official | 27:4206883f4cb7 | 56 | // Wait 100 ms before apply reset |
mbed_official | 27:4206883f4cb7 | 57 | wait_ms(100); |
mbed_official | 27:4206883f4cb7 | 58 | |
mbed_official | 27:4206883f4cb7 | 59 | // software reset |
mbed_official | 27:4206883f4cb7 | 60 | ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_HCR); |
mbed_official | 27:4206883f4cb7 | 61 | |
mbed_official | 27:4206883f4cb7 | 62 | // Write Fm Interval and Largest Data Packet Counter |
mbed_official | 27:4206883f4cb7 | 63 | ohciwrapp_reg_w(OHCI_REG_FMINTERVAL, DEFAULT_FMINTERVAL); |
mbed_official | 27:4206883f4cb7 | 64 | ohciwrapp_reg_w(OHCI_REG_PERIODICSTART, FI * 90 / 100); |
mbed_official | 27:4206883f4cb7 | 65 | |
mbed_official | 27:4206883f4cb7 | 66 | // Put HC in operational state |
mbed_official | 27:4206883f4cb7 | 67 | ohciwrapp_reg_w(OHCI_REG_CONTROL, (ohciwrapp_reg_r(OHCI_REG_CONTROL) & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER); |
mbed_official | 27:4206883f4cb7 | 68 | // Set Global Power |
mbed_official | 27:4206883f4cb7 | 69 | ohciwrapp_reg_w(OHCI_REG_RHSTATUS, OR_RH_STATUS_LPSC); |
mbed_official | 27:4206883f4cb7 | 70 | |
mbed_official | 27:4206883f4cb7 | 71 | ohciwrapp_reg_w(OHCI_REG_HCCA, (uint32_t)(usb_hcca)); |
mbed_official | 27:4206883f4cb7 | 72 | |
mbed_official | 27:4206883f4cb7 | 73 | // Clear Interrrupt Status |
mbed_official | 27:4206883f4cb7 | 74 | ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, ohciwrapp_reg_r(OHCI_REG_INTERRUPTSTATUS)); |
mbed_official | 27:4206883f4cb7 | 75 | |
mbed_official | 27:4206883f4cb7 | 76 | ohciwrapp_reg_w(OHCI_REG_INTERRUPTENABLE, OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC); |
mbed_official | 27:4206883f4cb7 | 77 | |
mbed_official | 27:4206883f4cb7 | 78 | // Enable the USB Interrupt |
mbed_official | 27:4206883f4cb7 | 79 | ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_CSC); |
mbed_official | 27:4206883f4cb7 | 80 | ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC); |
mbed_official | 27:4206883f4cb7 | 81 | |
mbed_official | 27:4206883f4cb7 | 82 | // Check for any connected devices |
mbed_official | 27:4206883f4cb7 | 83 | if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CCS) { |
mbed_official | 27:4206883f4cb7 | 84 | //Device connected |
mbed_official | 27:4206883f4cb7 | 85 | wait_ms(150); |
mbed_official | 27:4206883f4cb7 | 86 | USB_DBG("Device connected (%08x)\n\r", ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1)); |
mbed_official | 27:4206883f4cb7 | 87 | deviceConnected(0, 1, ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_LSDA); |
mbed_official | 27:4206883f4cb7 | 88 | } |
mbed_official | 27:4206883f4cb7 | 89 | } |
mbed_official | 27:4206883f4cb7 | 90 | |
mbed_official | 27:4206883f4cb7 | 91 | uint32_t USBHALHost::controlHeadED() { |
mbed_official | 27:4206883f4cb7 | 92 | return ohciwrapp_reg_r(OHCI_REG_CONTROLHEADED); |
mbed_official | 27:4206883f4cb7 | 93 | } |
mbed_official | 27:4206883f4cb7 | 94 | |
mbed_official | 27:4206883f4cb7 | 95 | uint32_t USBHALHost::bulkHeadED() { |
mbed_official | 27:4206883f4cb7 | 96 | return ohciwrapp_reg_r(OHCI_REG_BULKHEADED); |
mbed_official | 27:4206883f4cb7 | 97 | } |
mbed_official | 27:4206883f4cb7 | 98 | |
mbed_official | 27:4206883f4cb7 | 99 | uint32_t USBHALHost::interruptHeadED() { |
mbed_official | 27:4206883f4cb7 | 100 | return usb_hcca->IntTable[0]; |
mbed_official | 27:4206883f4cb7 | 101 | } |
mbed_official | 27:4206883f4cb7 | 102 | |
mbed_official | 27:4206883f4cb7 | 103 | void USBHALHost::updateBulkHeadED(uint32_t addr) { |
mbed_official | 27:4206883f4cb7 | 104 | ohciwrapp_reg_w(OHCI_REG_BULKHEADED, addr); |
mbed_official | 27:4206883f4cb7 | 105 | } |
mbed_official | 27:4206883f4cb7 | 106 | |
mbed_official | 27:4206883f4cb7 | 107 | |
mbed_official | 27:4206883f4cb7 | 108 | void USBHALHost::updateControlHeadED(uint32_t addr) { |
mbed_official | 27:4206883f4cb7 | 109 | ohciwrapp_reg_w(OHCI_REG_CONTROLHEADED, addr); |
mbed_official | 27:4206883f4cb7 | 110 | } |
mbed_official | 27:4206883f4cb7 | 111 | |
mbed_official | 27:4206883f4cb7 | 112 | void USBHALHost::updateInterruptHeadED(uint32_t addr) { |
mbed_official | 27:4206883f4cb7 | 113 | usb_hcca->IntTable[0] = addr; |
mbed_official | 27:4206883f4cb7 | 114 | } |
mbed_official | 27:4206883f4cb7 | 115 | |
mbed_official | 27:4206883f4cb7 | 116 | |
mbed_official | 27:4206883f4cb7 | 117 | void USBHALHost::enableList(ENDPOINT_TYPE type) { |
mbed_official | 27:4206883f4cb7 | 118 | uint32_t wk_data; |
mbed_official | 27:4206883f4cb7 | 119 | |
mbed_official | 27:4206883f4cb7 | 120 | switch(type) { |
mbed_official | 27:4206883f4cb7 | 121 | case CONTROL_ENDPOINT: |
mbed_official | 27:4206883f4cb7 | 122 | ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_CLF); |
mbed_official | 27:4206883f4cb7 | 123 | wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_CLE); |
mbed_official | 27:4206883f4cb7 | 124 | ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data); |
mbed_official | 27:4206883f4cb7 | 125 | break; |
mbed_official | 27:4206883f4cb7 | 126 | case ISOCHRONOUS_ENDPOINT: |
mbed_official | 27:4206883f4cb7 | 127 | break; |
mbed_official | 27:4206883f4cb7 | 128 | case BULK_ENDPOINT: |
mbed_official | 27:4206883f4cb7 | 129 | ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_BLF); |
mbed_official | 27:4206883f4cb7 | 130 | wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_BLE); |
mbed_official | 27:4206883f4cb7 | 131 | ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data); |
mbed_official | 27:4206883f4cb7 | 132 | break; |
mbed_official | 27:4206883f4cb7 | 133 | case INTERRUPT_ENDPOINT: |
mbed_official | 27:4206883f4cb7 | 134 | wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_PLE); |
mbed_official | 27:4206883f4cb7 | 135 | ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data); |
mbed_official | 27:4206883f4cb7 | 136 | break; |
mbed_official | 27:4206883f4cb7 | 137 | } |
mbed_official | 27:4206883f4cb7 | 138 | } |
mbed_official | 27:4206883f4cb7 | 139 | |
mbed_official | 27:4206883f4cb7 | 140 | |
mbed_official | 27:4206883f4cb7 | 141 | bool USBHALHost::disableList(ENDPOINT_TYPE type) { |
mbed_official | 27:4206883f4cb7 | 142 | uint32_t wk_data; |
mbed_official | 27:4206883f4cb7 | 143 | |
mbed_official | 27:4206883f4cb7 | 144 | switch(type) { |
mbed_official | 27:4206883f4cb7 | 145 | case CONTROL_ENDPOINT: |
mbed_official | 27:4206883f4cb7 | 146 | wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL); |
mbed_official | 27:4206883f4cb7 | 147 | if(wk_data & OR_CONTROL_CLE) { |
mbed_official | 27:4206883f4cb7 | 148 | wk_data &= ~OR_CONTROL_CLE; |
mbed_official | 27:4206883f4cb7 | 149 | ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data); |
mbed_official | 27:4206883f4cb7 | 150 | return true; |
mbed_official | 27:4206883f4cb7 | 151 | } |
mbed_official | 27:4206883f4cb7 | 152 | return false; |
mbed_official | 27:4206883f4cb7 | 153 | case ISOCHRONOUS_ENDPOINT: |
mbed_official | 27:4206883f4cb7 | 154 | return false; |
mbed_official | 27:4206883f4cb7 | 155 | case BULK_ENDPOINT: |
mbed_official | 27:4206883f4cb7 | 156 | wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL); |
mbed_official | 27:4206883f4cb7 | 157 | if(wk_data & OR_CONTROL_BLE) { |
mbed_official | 27:4206883f4cb7 | 158 | wk_data &= ~OR_CONTROL_BLE; |
mbed_official | 27:4206883f4cb7 | 159 | ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data); |
mbed_official | 27:4206883f4cb7 | 160 | return true; |
mbed_official | 27:4206883f4cb7 | 161 | } |
mbed_official | 27:4206883f4cb7 | 162 | return false; |
mbed_official | 27:4206883f4cb7 | 163 | case INTERRUPT_ENDPOINT: |
mbed_official | 27:4206883f4cb7 | 164 | wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL); |
mbed_official | 27:4206883f4cb7 | 165 | if(wk_data & OR_CONTROL_PLE) { |
mbed_official | 27:4206883f4cb7 | 166 | wk_data &= ~OR_CONTROL_PLE; |
mbed_official | 27:4206883f4cb7 | 167 | ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data); |
mbed_official | 27:4206883f4cb7 | 168 | return true; |
mbed_official | 27:4206883f4cb7 | 169 | } |
mbed_official | 27:4206883f4cb7 | 170 | return false; |
mbed_official | 27:4206883f4cb7 | 171 | } |
mbed_official | 27:4206883f4cb7 | 172 | return false; |
mbed_official | 27:4206883f4cb7 | 173 | } |
mbed_official | 27:4206883f4cb7 | 174 | |
mbed_official | 27:4206883f4cb7 | 175 | |
mbed_official | 27:4206883f4cb7 | 176 | void USBHALHost::memInit() { |
mbed_official | 27:4206883f4cb7 | 177 | volatile uint8_t *p_wk_buf = (uint8_t *)(((uint32_t)usb_buf + ALIGNE_MSK) & ~ALIGNE_MSK); |
mbed_official | 27:4206883f4cb7 | 178 | |
mbed_official | 27:4206883f4cb7 | 179 | usb_hcca = (volatile HCCA *)p_wk_buf; |
mbed_official | 27:4206883f4cb7 | 180 | usb_edBuf = (volatile uint8_t *)(p_wk_buf + HCCA_SIZE); |
mbed_official | 27:4206883f4cb7 | 181 | usb_tdBuf = (volatile uint8_t *)(p_wk_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE)); |
mbed_official | 27:4206883f4cb7 | 182 | } |
mbed_official | 27:4206883f4cb7 | 183 | |
mbed_official | 27:4206883f4cb7 | 184 | volatile uint8_t * USBHALHost::getED() { |
mbed_official | 27:4206883f4cb7 | 185 | for (int i = 0; i < MAX_ENDPOINT; i++) { |
mbed_official | 27:4206883f4cb7 | 186 | if ( !edBufAlloc[i] ) { |
mbed_official | 27:4206883f4cb7 | 187 | edBufAlloc[i] = true; |
mbed_official | 27:4206883f4cb7 | 188 | return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE); |
mbed_official | 27:4206883f4cb7 | 189 | } |
mbed_official | 27:4206883f4cb7 | 190 | } |
mbed_official | 27:4206883f4cb7 | 191 | perror("Could not allocate ED\r\n"); |
mbed_official | 27:4206883f4cb7 | 192 | return NULL; //Could not alloc ED |
mbed_official | 27:4206883f4cb7 | 193 | } |
mbed_official | 27:4206883f4cb7 | 194 | |
mbed_official | 27:4206883f4cb7 | 195 | volatile uint8_t * USBHALHost::getTD() { |
mbed_official | 27:4206883f4cb7 | 196 | int i; |
mbed_official | 27:4206883f4cb7 | 197 | for (i = 0; i < MAX_TD; i++) { |
mbed_official | 27:4206883f4cb7 | 198 | if ( !tdBufAlloc[i] ) { |
mbed_official | 27:4206883f4cb7 | 199 | tdBufAlloc[i] = true; |
mbed_official | 27:4206883f4cb7 | 200 | return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE); |
mbed_official | 27:4206883f4cb7 | 201 | } |
mbed_official | 27:4206883f4cb7 | 202 | } |
mbed_official | 27:4206883f4cb7 | 203 | perror("Could not allocate TD\r\n"); |
mbed_official | 27:4206883f4cb7 | 204 | return NULL; //Could not alloc TD |
mbed_official | 27:4206883f4cb7 | 205 | } |
mbed_official | 27:4206883f4cb7 | 206 | |
mbed_official | 27:4206883f4cb7 | 207 | |
mbed_official | 27:4206883f4cb7 | 208 | void USBHALHost::freeED(volatile uint8_t * ed) { |
mbed_official | 27:4206883f4cb7 | 209 | int i; |
mbed_official | 27:4206883f4cb7 | 210 | i = (ed - usb_edBuf) / ED_SIZE; |
mbed_official | 27:4206883f4cb7 | 211 | edBufAlloc[i] = false; |
mbed_official | 27:4206883f4cb7 | 212 | } |
mbed_official | 27:4206883f4cb7 | 213 | |
mbed_official | 27:4206883f4cb7 | 214 | void USBHALHost::freeTD(volatile uint8_t * td) { |
mbed_official | 27:4206883f4cb7 | 215 | int i; |
mbed_official | 27:4206883f4cb7 | 216 | i = (td - usb_tdBuf) / TD_SIZE; |
mbed_official | 27:4206883f4cb7 | 217 | tdBufAlloc[i] = false; |
mbed_official | 27:4206883f4cb7 | 218 | } |
mbed_official | 27:4206883f4cb7 | 219 | |
mbed_official | 27:4206883f4cb7 | 220 | |
mbed_official | 27:4206883f4cb7 | 221 | void USBHALHost::resetRootHub() { |
mbed_official | 27:4206883f4cb7 | 222 | // Initiate port reset |
mbed_official | 27:4206883f4cb7 | 223 | ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRS); |
mbed_official | 27:4206883f4cb7 | 224 | |
mbed_official | 27:4206883f4cb7 | 225 | while (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_PRS); |
mbed_official | 27:4206883f4cb7 | 226 | |
mbed_official | 27:4206883f4cb7 | 227 | // ...and clear port reset signal |
mbed_official | 27:4206883f4cb7 | 228 | ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC); |
mbed_official | 27:4206883f4cb7 | 229 | } |
mbed_official | 27:4206883f4cb7 | 230 | |
mbed_official | 27:4206883f4cb7 | 231 | |
mbed_official | 27:4206883f4cb7 | 232 | void USBHALHost::_usbisr(void) { |
mbed_official | 27:4206883f4cb7 | 233 | if (instHost) { |
mbed_official | 27:4206883f4cb7 | 234 | instHost->UsbIrqhandler(); |
mbed_official | 27:4206883f4cb7 | 235 | } |
mbed_official | 27:4206883f4cb7 | 236 | } |
mbed_official | 27:4206883f4cb7 | 237 | |
mbed_official | 27:4206883f4cb7 | 238 | void USBHALHost::UsbIrqhandler() { |
mbed_official | 27:4206883f4cb7 | 239 | uint32_t int_status = ohciwrapp_reg_r(OHCI_REG_INTERRUPTSTATUS) & ohciwrapp_reg_r(OHCI_REG_INTERRUPTENABLE); |
mbed_official | 28:8e62b6403505 | 240 | uint32_t data; |
mbed_official | 27:4206883f4cb7 | 241 | |
mbed_official | 27:4206883f4cb7 | 242 | if (int_status != 0) { //Is there something to actually process? |
mbed_official | 27:4206883f4cb7 | 243 | // Root hub status change interrupt |
mbed_official | 27:4206883f4cb7 | 244 | if (int_status & OR_INTR_STATUS_RHSC) { |
mbed_official | 27:4206883f4cb7 | 245 | if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CSC) { |
mbed_official | 27:4206883f4cb7 | 246 | if (ohciwrapp_reg_r(OHCI_REG_RHSTATUS) & OR_RH_STATUS_DRWE) { |
mbed_official | 27:4206883f4cb7 | 247 | // When DRWE is on, Connect Status Change |
mbed_official | 27:4206883f4cb7 | 248 | // means a remote wakeup event. |
mbed_official | 27:4206883f4cb7 | 249 | } else { |
mbed_official | 27:4206883f4cb7 | 250 | |
mbed_official | 27:4206883f4cb7 | 251 | //Root device connected |
mbed_official | 27:4206883f4cb7 | 252 | if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CCS) { |
mbed_official | 27:4206883f4cb7 | 253 | |
mbed_official | 27:4206883f4cb7 | 254 | // wait 150ms to avoid bounce |
mbed_official | 27:4206883f4cb7 | 255 | wait_ms(150); |
mbed_official | 27:4206883f4cb7 | 256 | |
mbed_official | 27:4206883f4cb7 | 257 | //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed |
mbed_official | 28:8e62b6403505 | 258 | data = ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_LSDA; |
mbed_official | 28:8e62b6403505 | 259 | deviceConnected(0, 1, data); |
mbed_official | 27:4206883f4cb7 | 260 | } |
mbed_official | 27:4206883f4cb7 | 261 | |
mbed_official | 27:4206883f4cb7 | 262 | //Root device disconnected |
mbed_official | 27:4206883f4cb7 | 263 | else { |
mbed_official | 27:4206883f4cb7 | 264 | |
mbed_official | 27:4206883f4cb7 | 265 | if (!(int_status & OR_INTR_STATUS_WDH)) { |
mbed_official | 27:4206883f4cb7 | 266 | usb_hcca->DoneHead = 0; |
mbed_official | 27:4206883f4cb7 | 267 | } |
mbed_official | 27:4206883f4cb7 | 268 | |
mbed_official | 27:4206883f4cb7 | 269 | deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE); |
mbed_official | 27:4206883f4cb7 | 270 | |
mbed_official | 27:4206883f4cb7 | 271 | if (int_status & OR_INTR_STATUS_WDH) { |
mbed_official | 27:4206883f4cb7 | 272 | usb_hcca->DoneHead = 0; |
mbed_official | 27:4206883f4cb7 | 273 | ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_WDH); |
mbed_official | 27:4206883f4cb7 | 274 | } |
mbed_official | 27:4206883f4cb7 | 275 | } |
mbed_official | 27:4206883f4cb7 | 276 | } |
mbed_official | 27:4206883f4cb7 | 277 | ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_CSC); |
mbed_official | 27:4206883f4cb7 | 278 | } |
mbed_official | 27:4206883f4cb7 | 279 | if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_PRSC) { |
mbed_official | 27:4206883f4cb7 | 280 | ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC); |
mbed_official | 27:4206883f4cb7 | 281 | } |
mbed_official | 27:4206883f4cb7 | 282 | ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_RHSC); |
mbed_official | 27:4206883f4cb7 | 283 | } |
mbed_official | 27:4206883f4cb7 | 284 | |
mbed_official | 27:4206883f4cb7 | 285 | // Writeback Done Head interrupt |
mbed_official | 27:4206883f4cb7 | 286 | if (int_status & OR_INTR_STATUS_WDH) { |
mbed_official | 27:4206883f4cb7 | 287 | transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE); |
mbed_official | 27:4206883f4cb7 | 288 | ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_WDH); |
mbed_official | 27:4206883f4cb7 | 289 | } |
mbed_official | 27:4206883f4cb7 | 290 | } |
mbed_official | 27:4206883f4cb7 | 291 | } |
mbed_official | 27:4206883f4cb7 | 292 | #endif |