clement lignie / configure_ax12_test_bras_module

config AX12

Fork of configure_ax12_test_bras_module by CRAC Team

mbed/LPC1768/core_cmFunc.h@0:c03cffe402df, 2016-02-03 (annotated)

Committer:
slowness
Date:
Wed Feb 03 14:01:53 2016 +0000
Revision:
0:c03cffe402df
Pour configurer les AX12 avec la carte NXP1768 sur les Pin 9 et 10

Who changed what in which revision?

UserRevisionLine numberNew contents of line
slowness 0:c03cffe402df 1 /**************************************************************************//**
slowness 0:c03cffe402df 2 * @file core_cmFunc.h
slowness 0:c03cffe402df 3 * @brief CMSIS Cortex-M Core Function Access Header File
slowness 0:c03cffe402df 4 * @version V3.00
slowness 0:c03cffe402df 5 * @date 09. December 2011
slowness 0:c03cffe402df 6 *
slowness 0:c03cffe402df 7 * @note
slowness 0:c03cffe402df 8 * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
slowness 0:c03cffe402df 9 *
slowness 0:c03cffe402df 10 * @par
slowness 0:c03cffe402df 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
slowness 0:c03cffe402df 12 * processor based microcontrollers. This file can be freely distributed
slowness 0:c03cffe402df 13 * within development tools that are supporting such ARM based processors.
slowness 0:c03cffe402df 14 *
slowness 0:c03cffe402df 15 * @par
slowness 0:c03cffe402df 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
slowness 0:c03cffe402df 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
slowness 0:c03cffe402df 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
slowness 0:c03cffe402df 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
slowness 0:c03cffe402df 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
slowness 0:c03cffe402df 21 *
slowness 0:c03cffe402df 22 ******************************************************************************/
slowness 0:c03cffe402df 23
slowness 0:c03cffe402df 24 #ifndef __CORE_CMFUNC_H
slowness 0:c03cffe402df 25 #define __CORE_CMFUNC_H
slowness 0:c03cffe402df 26
slowness 0:c03cffe402df 27
slowness 0:c03cffe402df 28 /* ########################### Core Function Access ########################### */
slowness 0:c03cffe402df 29 /** \ingroup CMSIS_Core_FunctionInterface
slowness 0:c03cffe402df 30 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
slowness 0:c03cffe402df 31 @{
slowness 0:c03cffe402df 32 */
slowness 0:c03cffe402df 33
slowness 0:c03cffe402df 34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
slowness 0:c03cffe402df 35 /* ARM armcc specific functions */
slowness 0:c03cffe402df 36
slowness 0:c03cffe402df 37 #if (__ARMCC_VERSION < 400677)
slowness 0:c03cffe402df 38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
slowness 0:c03cffe402df 39 #endif
slowness 0:c03cffe402df 40
slowness 0:c03cffe402df 41 /* intrinsic void __enable_irq(); */
slowness 0:c03cffe402df 42 /* intrinsic void __disable_irq(); */
slowness 0:c03cffe402df 43
slowness 0:c03cffe402df 44 /** \brief Get Control Register
slowness 0:c03cffe402df 45
slowness 0:c03cffe402df 46 This function returns the content of the Control Register.
slowness 0:c03cffe402df 47
slowness 0:c03cffe402df 48 \return Control Register value
slowness 0:c03cffe402df 49 */
slowness 0:c03cffe402df 50 static __INLINE uint32_t __get_CONTROL(void)
slowness 0:c03cffe402df 51 {
slowness 0:c03cffe402df 52 register uint32_t __regControl __ASM("control");
slowness 0:c03cffe402df 53 return(__regControl);
slowness 0:c03cffe402df 54 }
slowness 0:c03cffe402df 55
slowness 0:c03cffe402df 56
slowness 0:c03cffe402df 57 /** \brief Set Control Register
slowness 0:c03cffe402df 58
slowness 0:c03cffe402df 59 This function writes the given value to the Control Register.
slowness 0:c03cffe402df 60
slowness 0:c03cffe402df 61 \param [in] control Control Register value to set
slowness 0:c03cffe402df 62 */
slowness 0:c03cffe402df 63 static __INLINE void __set_CONTROL(uint32_t control)
slowness 0:c03cffe402df 64 {
slowness 0:c03cffe402df 65 register uint32_t __regControl __ASM("control");
slowness 0:c03cffe402df 66 __regControl = control;
slowness 0:c03cffe402df 67 }
slowness 0:c03cffe402df 68
slowness 0:c03cffe402df 69
slowness 0:c03cffe402df 70 /** \brief Get IPSR Register
slowness 0:c03cffe402df 71
slowness 0:c03cffe402df 72 This function returns the content of the IPSR Register.
slowness 0:c03cffe402df 73
slowness 0:c03cffe402df 74 \return IPSR Register value
slowness 0:c03cffe402df 75 */
slowness 0:c03cffe402df 76 static __INLINE uint32_t __get_IPSR(void)
slowness 0:c03cffe402df 77 {
slowness 0:c03cffe402df 78 register uint32_t __regIPSR __ASM("ipsr");
slowness 0:c03cffe402df 79 return(__regIPSR);
slowness 0:c03cffe402df 80 }
slowness 0:c03cffe402df 81
slowness 0:c03cffe402df 82
slowness 0:c03cffe402df 83 /** \brief Get APSR Register
slowness 0:c03cffe402df 84
slowness 0:c03cffe402df 85 This function returns the content of the APSR Register.
slowness 0:c03cffe402df 86
slowness 0:c03cffe402df 87 \return APSR Register value
slowness 0:c03cffe402df 88 */
slowness 0:c03cffe402df 89 static __INLINE uint32_t __get_APSR(void)
slowness 0:c03cffe402df 90 {
slowness 0:c03cffe402df 91 register uint32_t __regAPSR __ASM("apsr");
slowness 0:c03cffe402df 92 return(__regAPSR);
slowness 0:c03cffe402df 93 }
slowness 0:c03cffe402df 94
slowness 0:c03cffe402df 95
slowness 0:c03cffe402df 96 /** \brief Get xPSR Register
slowness 0:c03cffe402df 97
slowness 0:c03cffe402df 98 This function returns the content of the xPSR Register.
slowness 0:c03cffe402df 99
slowness 0:c03cffe402df 100 \return xPSR Register value
slowness 0:c03cffe402df 101 */
slowness 0:c03cffe402df 102 static __INLINE uint32_t __get_xPSR(void)
slowness 0:c03cffe402df 103 {
slowness 0:c03cffe402df 104 register uint32_t __regXPSR __ASM("xpsr");
slowness 0:c03cffe402df 105 return(__regXPSR);
slowness 0:c03cffe402df 106 }
slowness 0:c03cffe402df 107
slowness 0:c03cffe402df 108
slowness 0:c03cffe402df 109 /** \brief Get Process Stack Pointer
slowness 0:c03cffe402df 110
slowness 0:c03cffe402df 111 This function returns the current value of the Process Stack Pointer (PSP).
slowness 0:c03cffe402df 112
slowness 0:c03cffe402df 113 \return PSP Register value
slowness 0:c03cffe402df 114 */
slowness 0:c03cffe402df 115 static __INLINE uint32_t __get_PSP(void)
slowness 0:c03cffe402df 116 {
slowness 0:c03cffe402df 117 register uint32_t __regProcessStackPointer __ASM("psp");
slowness 0:c03cffe402df 118 return(__regProcessStackPointer);
slowness 0:c03cffe402df 119 }
slowness 0:c03cffe402df 120
slowness 0:c03cffe402df 121
slowness 0:c03cffe402df 122 /** \brief Set Process Stack Pointer
slowness 0:c03cffe402df 123
slowness 0:c03cffe402df 124 This function assigns the given value to the Process Stack Pointer (PSP).
slowness 0:c03cffe402df 125
slowness 0:c03cffe402df 126 \param [in] topOfProcStack Process Stack Pointer value to set
slowness 0:c03cffe402df 127 */
slowness 0:c03cffe402df 128 static __INLINE void __set_PSP(uint32_t topOfProcStack)
slowness 0:c03cffe402df 129 {
slowness 0:c03cffe402df 130 register uint32_t __regProcessStackPointer __ASM("psp");
slowness 0:c03cffe402df 131 __regProcessStackPointer = topOfProcStack;
slowness 0:c03cffe402df 132 }
slowness 0:c03cffe402df 133
slowness 0:c03cffe402df 134
slowness 0:c03cffe402df 135 /** \brief Get Main Stack Pointer
slowness 0:c03cffe402df 136
slowness 0:c03cffe402df 137 This function returns the current value of the Main Stack Pointer (MSP).
slowness 0:c03cffe402df 138
slowness 0:c03cffe402df 139 \return MSP Register value
slowness 0:c03cffe402df 140 */
slowness 0:c03cffe402df 141 static __INLINE uint32_t __get_MSP(void)
slowness 0:c03cffe402df 142 {
slowness 0:c03cffe402df 143 register uint32_t __regMainStackPointer __ASM("msp");
slowness 0:c03cffe402df 144 return(__regMainStackPointer);
slowness 0:c03cffe402df 145 }
slowness 0:c03cffe402df 146
slowness 0:c03cffe402df 147
slowness 0:c03cffe402df 148 /** \brief Set Main Stack Pointer
slowness 0:c03cffe402df 149
slowness 0:c03cffe402df 150 This function assigns the given value to the Main Stack Pointer (MSP).
slowness 0:c03cffe402df 151
slowness 0:c03cffe402df 152 \param [in] topOfMainStack Main Stack Pointer value to set
slowness 0:c03cffe402df 153 */
slowness 0:c03cffe402df 154 static __INLINE void __set_MSP(uint32_t topOfMainStack)
slowness 0:c03cffe402df 155 {
slowness 0:c03cffe402df 156 register uint32_t __regMainStackPointer __ASM("msp");
slowness 0:c03cffe402df 157 __regMainStackPointer = topOfMainStack;
slowness 0:c03cffe402df 158 }
slowness 0:c03cffe402df 159
slowness 0:c03cffe402df 160
slowness 0:c03cffe402df 161 /** \brief Get Priority Mask
slowness 0:c03cffe402df 162
slowness 0:c03cffe402df 163 This function returns the current state of the priority mask bit from the Priority Mask Register.
slowness 0:c03cffe402df 164
slowness 0:c03cffe402df 165 \return Priority Mask value
slowness 0:c03cffe402df 166 */
slowness 0:c03cffe402df 167 static __INLINE uint32_t __get_PRIMASK(void)
slowness 0:c03cffe402df 168 {
slowness 0:c03cffe402df 169 register uint32_t __regPriMask __ASM("primask");
slowness 0:c03cffe402df 170 return(__regPriMask);
slowness 0:c03cffe402df 171 }
slowness 0:c03cffe402df 172
slowness 0:c03cffe402df 173
slowness 0:c03cffe402df 174 /** \brief Set Priority Mask
slowness 0:c03cffe402df 175
slowness 0:c03cffe402df 176 This function assigns the given value to the Priority Mask Register.
slowness 0:c03cffe402df 177
slowness 0:c03cffe402df 178 \param [in] priMask Priority Mask
slowness 0:c03cffe402df 179 */
slowness 0:c03cffe402df 180 static __INLINE void __set_PRIMASK(uint32_t priMask)
slowness 0:c03cffe402df 181 {
slowness 0:c03cffe402df 182 register uint32_t __regPriMask __ASM("primask");
slowness 0:c03cffe402df 183 __regPriMask = (priMask);
slowness 0:c03cffe402df 184 }
slowness 0:c03cffe402df 185
slowness 0:c03cffe402df 186
slowness 0:c03cffe402df 187 #if (__CORTEX_M >= 0x03)
slowness 0:c03cffe402df 188
slowness 0:c03cffe402df 189 /** \brief Enable FIQ
slowness 0:c03cffe402df 190
slowness 0:c03cffe402df 191 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
slowness 0:c03cffe402df 192 Can only be executed in Privileged modes.
slowness 0:c03cffe402df 193 */
slowness 0:c03cffe402df 194 #define __enable_fault_irq __enable_fiq
slowness 0:c03cffe402df 195
slowness 0:c03cffe402df 196
slowness 0:c03cffe402df 197 /** \brief Disable FIQ
slowness 0:c03cffe402df 198
slowness 0:c03cffe402df 199 This function disables FIQ interrupts by setting the F-bit in the CPSR.
slowness 0:c03cffe402df 200 Can only be executed in Privileged modes.
slowness 0:c03cffe402df 201 */
slowness 0:c03cffe402df 202 #define __disable_fault_irq __disable_fiq
slowness 0:c03cffe402df 203
slowness 0:c03cffe402df 204
slowness 0:c03cffe402df 205 /** \brief Get Base Priority
slowness 0:c03cffe402df 206
slowness 0:c03cffe402df 207 This function returns the current value of the Base Priority register.
slowness 0:c03cffe402df 208
slowness 0:c03cffe402df 209 \return Base Priority register value
slowness 0:c03cffe402df 210 */
slowness 0:c03cffe402df 211 static __INLINE uint32_t __get_BASEPRI(void)
slowness 0:c03cffe402df 212 {
slowness 0:c03cffe402df 213 register uint32_t __regBasePri __ASM("basepri");
slowness 0:c03cffe402df 214 return(__regBasePri);
slowness 0:c03cffe402df 215 }
slowness 0:c03cffe402df 216
slowness 0:c03cffe402df 217
slowness 0:c03cffe402df 218 /** \brief Set Base Priority
slowness 0:c03cffe402df 219
slowness 0:c03cffe402df 220 This function assigns the given value to the Base Priority register.
slowness 0:c03cffe402df 221
slowness 0:c03cffe402df 222 \param [in] basePri Base Priority value to set
slowness 0:c03cffe402df 223 */
slowness 0:c03cffe402df 224 static __INLINE void __set_BASEPRI(uint32_t basePri)
slowness 0:c03cffe402df 225 {
slowness 0:c03cffe402df 226 register uint32_t __regBasePri __ASM("basepri");
slowness 0:c03cffe402df 227 __regBasePri = (basePri & 0xff);
slowness 0:c03cffe402df 228 }
slowness 0:c03cffe402df 229
slowness 0:c03cffe402df 230
slowness 0:c03cffe402df 231 /** \brief Get Fault Mask
slowness 0:c03cffe402df 232
slowness 0:c03cffe402df 233 This function returns the current value of the Fault Mask register.
slowness 0:c03cffe402df 234
slowness 0:c03cffe402df 235 \return Fault Mask register value
slowness 0:c03cffe402df 236 */
slowness 0:c03cffe402df 237 static __INLINE uint32_t __get_FAULTMASK(void)
slowness 0:c03cffe402df 238 {
slowness 0:c03cffe402df 239 register uint32_t __regFaultMask __ASM("faultmask");
slowness 0:c03cffe402df 240 return(__regFaultMask);
slowness 0:c03cffe402df 241 }
slowness 0:c03cffe402df 242
slowness 0:c03cffe402df 243
slowness 0:c03cffe402df 244 /** \brief Set Fault Mask
slowness 0:c03cffe402df 245
slowness 0:c03cffe402df 246 This function assigns the given value to the Fault Mask register.
slowness 0:c03cffe402df 247
slowness 0:c03cffe402df 248 \param [in] faultMask Fault Mask value to set
slowness 0:c03cffe402df 249 */
slowness 0:c03cffe402df 250 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
slowness 0:c03cffe402df 251 {
slowness 0:c03cffe402df 252 register uint32_t __regFaultMask __ASM("faultmask");
slowness 0:c03cffe402df 253 __regFaultMask = (faultMask & (uint32_t)1);
slowness 0:c03cffe402df 254 }
slowness 0:c03cffe402df 255
slowness 0:c03cffe402df 256 #endif /* (__CORTEX_M >= 0x03) */
slowness 0:c03cffe402df 257
slowness 0:c03cffe402df 258
slowness 0:c03cffe402df 259 #if (__CORTEX_M == 0x04)
slowness 0:c03cffe402df 260
slowness 0:c03cffe402df 261 /** \brief Get FPSCR
slowness 0:c03cffe402df 262
slowness 0:c03cffe402df 263 This function returns the current value of the Floating Point Status/Control register.
slowness 0:c03cffe402df 264
slowness 0:c03cffe402df 265 \return Floating Point Status/Control register value
slowness 0:c03cffe402df 266 */
slowness 0:c03cffe402df 267 static __INLINE uint32_t __get_FPSCR(void)
slowness 0:c03cffe402df 268 {
slowness 0:c03cffe402df 269 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
slowness 0:c03cffe402df 270 register uint32_t __regfpscr __ASM("fpscr");
slowness 0:c03cffe402df 271 return(__regfpscr);
slowness 0:c03cffe402df 272 #else
slowness 0:c03cffe402df 273 return(0);
slowness 0:c03cffe402df 274 #endif
slowness 0:c03cffe402df 275 }
slowness 0:c03cffe402df 276
slowness 0:c03cffe402df 277
slowness 0:c03cffe402df 278 /** \brief Set FPSCR
slowness 0:c03cffe402df 279
slowness 0:c03cffe402df 280 This function assigns the given value to the Floating Point Status/Control register.
slowness 0:c03cffe402df 281
slowness 0:c03cffe402df 282 \param [in] fpscr Floating Point Status/Control value to set
slowness 0:c03cffe402df 283 */
slowness 0:c03cffe402df 284 static __INLINE void __set_FPSCR(uint32_t fpscr)
slowness 0:c03cffe402df 285 {
slowness 0:c03cffe402df 286 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
slowness 0:c03cffe402df 287 register uint32_t __regfpscr __ASM("fpscr");
slowness 0:c03cffe402df 288 __regfpscr = (fpscr);
slowness 0:c03cffe402df 289 #endif
slowness 0:c03cffe402df 290 }
slowness 0:c03cffe402df 291
slowness 0:c03cffe402df 292 #endif /* (__CORTEX_M == 0x04) */
slowness 0:c03cffe402df 293
slowness 0:c03cffe402df 294
slowness 0:c03cffe402df 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
slowness 0:c03cffe402df 296 /* IAR iccarm specific functions */
slowness 0:c03cffe402df 297
slowness 0:c03cffe402df 298 #include <cmsis_iar.h>
slowness 0:c03cffe402df 299
slowness 0:c03cffe402df 300 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
slowness 0:c03cffe402df 301 /* GNU gcc specific functions */
slowness 0:c03cffe402df 302
slowness 0:c03cffe402df 303 /** \brief Enable IRQ Interrupts
slowness 0:c03cffe402df 304
slowness 0:c03cffe402df 305 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
slowness 0:c03cffe402df 306 Can only be executed in Privileged modes.
slowness 0:c03cffe402df 307 */
slowness 0:c03cffe402df 308 __attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
slowness 0:c03cffe402df 309 {
slowness 0:c03cffe402df 310 __ASM volatile ("cpsie i");
slowness 0:c03cffe402df 311 }
slowness 0:c03cffe402df 312
slowness 0:c03cffe402df 313
slowness 0:c03cffe402df 314 /** \brief Disable IRQ Interrupts
slowness 0:c03cffe402df 315
slowness 0:c03cffe402df 316 This function disables IRQ interrupts by setting the I-bit in the CPSR.
slowness 0:c03cffe402df 317 Can only be executed in Privileged modes.
slowness 0:c03cffe402df 318 */
slowness 0:c03cffe402df 319 __attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
slowness 0:c03cffe402df 320 {
slowness 0:c03cffe402df 321 __ASM volatile ("cpsid i");
slowness 0:c03cffe402df 322 }
slowness 0:c03cffe402df 323
slowness 0:c03cffe402df 324
slowness 0:c03cffe402df 325 /** \brief Get Control Register
slowness 0:c03cffe402df 326
slowness 0:c03cffe402df 327 This function returns the content of the Control Register.
slowness 0:c03cffe402df 328
slowness 0:c03cffe402df 329 \return Control Register value
slowness 0:c03cffe402df 330 */
slowness 0:c03cffe402df 331 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
slowness 0:c03cffe402df 332 {
slowness 0:c03cffe402df 333 uint32_t result;
slowness 0:c03cffe402df 334
slowness 0:c03cffe402df 335 __ASM volatile ("MRS %0, control" : "=r" (result) );
slowness 0:c03cffe402df 336 return(result);
slowness 0:c03cffe402df 337 }
slowness 0:c03cffe402df 338
slowness 0:c03cffe402df 339
slowness 0:c03cffe402df 340 /** \brief Set Control Register
slowness 0:c03cffe402df 341
slowness 0:c03cffe402df 342 This function writes the given value to the Control Register.
slowness 0:c03cffe402df 343
slowness 0:c03cffe402df 344 \param [in] control Control Register value to set
slowness 0:c03cffe402df 345 */
slowness 0:c03cffe402df 346 __attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
slowness 0:c03cffe402df 347 {
slowness 0:c03cffe402df 348 __ASM volatile ("MSR control, %0" : : "r" (control) );
slowness 0:c03cffe402df 349 }
slowness 0:c03cffe402df 350
slowness 0:c03cffe402df 351
slowness 0:c03cffe402df 352 /** \brief Get IPSR Register
slowness 0:c03cffe402df 353
slowness 0:c03cffe402df 354 This function returns the content of the IPSR Register.
slowness 0:c03cffe402df 355
slowness 0:c03cffe402df 356 \return IPSR Register value
slowness 0:c03cffe402df 357 */
slowness 0:c03cffe402df 358 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
slowness 0:c03cffe402df 359 {
slowness 0:c03cffe402df 360 uint32_t result;
slowness 0:c03cffe402df 361
slowness 0:c03cffe402df 362 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
slowness 0:c03cffe402df 363 return(result);
slowness 0:c03cffe402df 364 }
slowness 0:c03cffe402df 365
slowness 0:c03cffe402df 366
slowness 0:c03cffe402df 367 /** \brief Get APSR Register
slowness 0:c03cffe402df 368
slowness 0:c03cffe402df 369 This function returns the content of the APSR Register.
slowness 0:c03cffe402df 370
slowness 0:c03cffe402df 371 \return APSR Register value
slowness 0:c03cffe402df 372 */
slowness 0:c03cffe402df 373 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
slowness 0:c03cffe402df 374 {
slowness 0:c03cffe402df 375 uint32_t result;
slowness 0:c03cffe402df 376
slowness 0:c03cffe402df 377 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
slowness 0:c03cffe402df 378 return(result);
slowness 0:c03cffe402df 379 }
slowness 0:c03cffe402df 380
slowness 0:c03cffe402df 381
slowness 0:c03cffe402df 382 /** \brief Get xPSR Register
slowness 0:c03cffe402df 383
slowness 0:c03cffe402df 384 This function returns the content of the xPSR Register.
slowness 0:c03cffe402df 385
slowness 0:c03cffe402df 386 \return xPSR Register value
slowness 0:c03cffe402df 387 */
slowness 0:c03cffe402df 388 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
slowness 0:c03cffe402df 389 {
slowness 0:c03cffe402df 390 uint32_t result;
slowness 0:c03cffe402df 391
slowness 0:c03cffe402df 392 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
slowness 0:c03cffe402df 393 return(result);
slowness 0:c03cffe402df 394 }
slowness 0:c03cffe402df 395
slowness 0:c03cffe402df 396
slowness 0:c03cffe402df 397 /** \brief Get Process Stack Pointer
slowness 0:c03cffe402df 398
slowness 0:c03cffe402df 399 This function returns the current value of the Process Stack Pointer (PSP).
slowness 0:c03cffe402df 400
slowness 0:c03cffe402df 401 \return PSP Register value
slowness 0:c03cffe402df 402 */
slowness 0:c03cffe402df 403 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
slowness 0:c03cffe402df 404 {
slowness 0:c03cffe402df 405 register uint32_t result;
slowness 0:c03cffe402df 406
slowness 0:c03cffe402df 407 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
slowness 0:c03cffe402df 408 return(result);
slowness 0:c03cffe402df 409 }
slowness 0:c03cffe402df 410
slowness 0:c03cffe402df 411
slowness 0:c03cffe402df 412 /** \brief Set Process Stack Pointer
slowness 0:c03cffe402df 413
slowness 0:c03cffe402df 414 This function assigns the given value to the Process Stack Pointer (PSP).
slowness 0:c03cffe402df 415
slowness 0:c03cffe402df 416 \param [in] topOfProcStack Process Stack Pointer value to set
slowness 0:c03cffe402df 417 */
slowness 0:c03cffe402df 418 __attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
slowness 0:c03cffe402df 419 {
slowness 0:c03cffe402df 420 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
slowness 0:c03cffe402df 421 }
slowness 0:c03cffe402df 422
slowness 0:c03cffe402df 423
slowness 0:c03cffe402df 424 /** \brief Get Main Stack Pointer
slowness 0:c03cffe402df 425
slowness 0:c03cffe402df 426 This function returns the current value of the Main Stack Pointer (MSP).
slowness 0:c03cffe402df 427
slowness 0:c03cffe402df 428 \return MSP Register value
slowness 0:c03cffe402df 429 */
slowness 0:c03cffe402df 430 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
slowness 0:c03cffe402df 431 {
slowness 0:c03cffe402df 432 register uint32_t result;
slowness 0:c03cffe402df 433
slowness 0:c03cffe402df 434 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
slowness 0:c03cffe402df 435 return(result);
slowness 0:c03cffe402df 436 }
slowness 0:c03cffe402df 437
slowness 0:c03cffe402df 438
slowness 0:c03cffe402df 439 /** \brief Set Main Stack Pointer
slowness 0:c03cffe402df 440
slowness 0:c03cffe402df 441 This function assigns the given value to the Main Stack Pointer (MSP).
slowness 0:c03cffe402df 442
slowness 0:c03cffe402df 443 \param [in] topOfMainStack Main Stack Pointer value to set
slowness 0:c03cffe402df 444 */
slowness 0:c03cffe402df 445 __attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
slowness 0:c03cffe402df 446 {
slowness 0:c03cffe402df 447 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
slowness 0:c03cffe402df 448 }
slowness 0:c03cffe402df 449
slowness 0:c03cffe402df 450
slowness 0:c03cffe402df 451 /** \brief Get Priority Mask
slowness 0:c03cffe402df 452
slowness 0:c03cffe402df 453 This function returns the current state of the priority mask bit from the Priority Mask Register.
slowness 0:c03cffe402df 454
slowness 0:c03cffe402df 455 \return Priority Mask value
slowness 0:c03cffe402df 456 */
slowness 0:c03cffe402df 457 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
slowness 0:c03cffe402df 458 {
slowness 0:c03cffe402df 459 uint32_t result;
slowness 0:c03cffe402df 460
slowness 0:c03cffe402df 461 __ASM volatile ("MRS %0, primask" : "=r" (result) );
slowness 0:c03cffe402df 462 return(result);
slowness 0:c03cffe402df 463 }
slowness 0:c03cffe402df 464
slowness 0:c03cffe402df 465
slowness 0:c03cffe402df 466 /** \brief Set Priority Mask
slowness 0:c03cffe402df 467
slowness 0:c03cffe402df 468 This function assigns the given value to the Priority Mask Register.
slowness 0:c03cffe402df 469
slowness 0:c03cffe402df 470 \param [in] priMask Priority Mask
slowness 0:c03cffe402df 471 */
slowness 0:c03cffe402df 472 __attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
slowness 0:c03cffe402df 473 {
slowness 0:c03cffe402df 474 __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
slowness 0:c03cffe402df 475 }
slowness 0:c03cffe402df 476
slowness 0:c03cffe402df 477
slowness 0:c03cffe402df 478 #if (__CORTEX_M >= 0x03)
slowness 0:c03cffe402df 479
slowness 0:c03cffe402df 480 /** \brief Enable FIQ
slowness 0:c03cffe402df 481
slowness 0:c03cffe402df 482 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
slowness 0:c03cffe402df 483 Can only be executed in Privileged modes.
slowness 0:c03cffe402df 484 */
slowness 0:c03cffe402df 485 __attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
slowness 0:c03cffe402df 486 {
slowness 0:c03cffe402df 487 __ASM volatile ("cpsie f");
slowness 0:c03cffe402df 488 }
slowness 0:c03cffe402df 489
slowness 0:c03cffe402df 490
slowness 0:c03cffe402df 491 /** \brief Disable FIQ
slowness 0:c03cffe402df 492
slowness 0:c03cffe402df 493 This function disables FIQ interrupts by setting the F-bit in the CPSR.
slowness 0:c03cffe402df 494 Can only be executed in Privileged modes.
slowness 0:c03cffe402df 495 */
slowness 0:c03cffe402df 496 __attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
slowness 0:c03cffe402df 497 {
slowness 0:c03cffe402df 498 __ASM volatile ("cpsid f");
slowness 0:c03cffe402df 499 }
slowness 0:c03cffe402df 500
slowness 0:c03cffe402df 501
slowness 0:c03cffe402df 502 /** \brief Get Base Priority
slowness 0:c03cffe402df 503
slowness 0:c03cffe402df 504 This function returns the current value of the Base Priority register.
slowness 0:c03cffe402df 505
slowness 0:c03cffe402df 506 \return Base Priority register value
slowness 0:c03cffe402df 507 */
slowness 0:c03cffe402df 508 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
slowness 0:c03cffe402df 509 {
slowness 0:c03cffe402df 510 uint32_t result;
slowness 0:c03cffe402df 511
slowness 0:c03cffe402df 512 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
slowness 0:c03cffe402df 513 return(result);
slowness 0:c03cffe402df 514 }
slowness 0:c03cffe402df 515
slowness 0:c03cffe402df 516
slowness 0:c03cffe402df 517 /** \brief Set Base Priority
slowness 0:c03cffe402df 518
slowness 0:c03cffe402df 519 This function assigns the given value to the Base Priority register.
slowness 0:c03cffe402df 520
slowness 0:c03cffe402df 521 \param [in] basePri Base Priority value to set
slowness 0:c03cffe402df 522 */
slowness 0:c03cffe402df 523 __attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
slowness 0:c03cffe402df 524 {
slowness 0:c03cffe402df 525 __ASM volatile ("MSR basepri, %0" : : "r" (value) );
slowness 0:c03cffe402df 526 }
slowness 0:c03cffe402df 527
slowness 0:c03cffe402df 528
slowness 0:c03cffe402df 529 /** \brief Get Fault Mask
slowness 0:c03cffe402df 530
slowness 0:c03cffe402df 531 This function returns the current value of the Fault Mask register.
slowness 0:c03cffe402df 532
slowness 0:c03cffe402df 533 \return Fault Mask register value
slowness 0:c03cffe402df 534 */
slowness 0:c03cffe402df 535 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
slowness 0:c03cffe402df 536 {
slowness 0:c03cffe402df 537 uint32_t result;
slowness 0:c03cffe402df 538
slowness 0:c03cffe402df 539 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
slowness 0:c03cffe402df 540 return(result);
slowness 0:c03cffe402df 541 }
slowness 0:c03cffe402df 542
slowness 0:c03cffe402df 543
slowness 0:c03cffe402df 544 /** \brief Set Fault Mask
slowness 0:c03cffe402df 545
slowness 0:c03cffe402df 546 This function assigns the given value to the Fault Mask register.
slowness 0:c03cffe402df 547
slowness 0:c03cffe402df 548 \param [in] faultMask Fault Mask value to set
slowness 0:c03cffe402df 549 */
slowness 0:c03cffe402df 550 __attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
slowness 0:c03cffe402df 551 {
slowness 0:c03cffe402df 552 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
slowness 0:c03cffe402df 553 }
slowness 0:c03cffe402df 554
slowness 0:c03cffe402df 555 #endif /* (__CORTEX_M >= 0x03) */
slowness 0:c03cffe402df 556
slowness 0:c03cffe402df 557
slowness 0:c03cffe402df 558 #if (__CORTEX_M == 0x04)
slowness 0:c03cffe402df 559
slowness 0:c03cffe402df 560 /** \brief Get FPSCR
slowness 0:c03cffe402df 561
slowness 0:c03cffe402df 562 This function returns the current value of the Floating Point Status/Control register.
slowness 0:c03cffe402df 563
slowness 0:c03cffe402df 564 \return Floating Point Status/Control register value
slowness 0:c03cffe402df 565 */
slowness 0:c03cffe402df 566 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
slowness 0:c03cffe402df 567 {
slowness 0:c03cffe402df 568 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
slowness 0:c03cffe402df 569 uint32_t result;
slowness 0:c03cffe402df 570
slowness 0:c03cffe402df 571 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
slowness 0:c03cffe402df 572 return(result);
slowness 0:c03cffe402df 573 #else
slowness 0:c03cffe402df 574 return(0);
slowness 0:c03cffe402df 575 #endif
slowness 0:c03cffe402df 576 }
slowness 0:c03cffe402df 577
slowness 0:c03cffe402df 578
slowness 0:c03cffe402df 579 /** \brief Set FPSCR
slowness 0:c03cffe402df 580
slowness 0:c03cffe402df 581 This function assigns the given value to the Floating Point Status/Control register.
slowness 0:c03cffe402df 582
slowness 0:c03cffe402df 583 \param [in] fpscr Floating Point Status/Control value to set
slowness 0:c03cffe402df 584 */
slowness 0:c03cffe402df 585 __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
slowness 0:c03cffe402df 586 {
slowness 0:c03cffe402df 587 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
slowness 0:c03cffe402df 588 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
slowness 0:c03cffe402df 589 #endif
slowness 0:c03cffe402df 590 }
slowness 0:c03cffe402df 591
slowness 0:c03cffe402df 592 #endif /* (__CORTEX_M == 0x04) */
slowness 0:c03cffe402df 593
slowness 0:c03cffe402df 594
slowness 0:c03cffe402df 595 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
slowness 0:c03cffe402df 596 /* TASKING carm specific functions */
slowness 0:c03cffe402df 597
slowness 0:c03cffe402df 598 /*
slowness 0:c03cffe402df 599 * The CMSIS functions have been implemented as intrinsics in the compiler.
slowness 0:c03cffe402df 600 * Please use "carm -?i" to get an up to date list of all instrinsics,
slowness 0:c03cffe402df 601 * Including the CMSIS ones.
slowness 0:c03cffe402df 602 */
slowness 0:c03cffe402df 603
slowness 0:c03cffe402df 604 #endif
slowness 0:c03cffe402df 605
slowness 0:c03cffe402df 606 /*@} end of CMSIS_Core_RegAccFunctions */
slowness 0:c03cffe402df 607
slowness 0:c03cffe402df 608
slowness 0:c03cffe402df 609 #endif /* __CORE_CMFUNC_H */