clement lignie / configure_ax12_test_bras_module

config AX12

Fork of configure_ax12_test_bras_module by CRAC Team

mbed/LPC1768/core_cm3.h@2:91b6646ea994, 2017-02-01 (annotated)

Committer:
clementlignie
Date:
Wed Feb 01 13:42:30 2017 +0000
Revision:
2:91b6646ea994
Parent:
0:c03cffe402df 
config AX12

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slowness 0:c03cffe402df 1 /**************************************************************************//**
slowness 0:c03cffe402df 2 * @file core_cm3.h
slowness 0:c03cffe402df 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
slowness 0:c03cffe402df 4 * @version V3.01
slowness 0:c03cffe402df 5 * @date 06. March 2012
slowness 0:c03cffe402df 6 *
slowness 0:c03cffe402df 7 * @note
slowness 0:c03cffe402df 8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
slowness 0:c03cffe402df 9 *
slowness 0:c03cffe402df 10 * @par
slowness 0:c03cffe402df 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
slowness 0:c03cffe402df 12 * processor based microcontrollers. This file can be freely distributed
slowness 0:c03cffe402df 13 * within development tools that are supporting such ARM based processors.
slowness 0:c03cffe402df 14 *
slowness 0:c03cffe402df 15 * @par
slowness 0:c03cffe402df 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
slowness 0:c03cffe402df 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
slowness 0:c03cffe402df 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
slowness 0:c03cffe402df 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
slowness 0:c03cffe402df 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
slowness 0:c03cffe402df 21 *
slowness 0:c03cffe402df 22 ******************************************************************************/
slowness 0:c03cffe402df 23 #if defined ( __ICCARM__ )
slowness 0:c03cffe402df 24 #pragma system_include /* treat file as system include file for MISRA check */
slowness 0:c03cffe402df 25 #endif
slowness 0:c03cffe402df 26
slowness 0:c03cffe402df 27 #ifdef __cplusplus
slowness 0:c03cffe402df 28 extern "C" {
slowness 0:c03cffe402df 29 #endif
slowness 0:c03cffe402df 30
slowness 0:c03cffe402df 31 #ifndef __CORE_CM3_H_GENERIC
slowness 0:c03cffe402df 32 #define __CORE_CM3_H_GENERIC
slowness 0:c03cffe402df 33
slowness 0:c03cffe402df 34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
slowness 0:c03cffe402df 35 CMSIS violates the following MISRA-C:2004 rules:
slowness 0:c03cffe402df 36
slowness 0:c03cffe402df 37 \li Required Rule 8.5, object/function definition in header file.<br>
slowness 0:c03cffe402df 38 Function definitions in header files are used to allow 'inlining'.
slowness 0:c03cffe402df 39
slowness 0:c03cffe402df 40 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
slowness 0:c03cffe402df 41 Unions are used for effective representation of core registers.
slowness 0:c03cffe402df 42
slowness 0:c03cffe402df 43 \li Advisory Rule 19.7, Function-like macro defined.<br>
slowness 0:c03cffe402df 44 Function-like macros are used to allow more efficient code.
slowness 0:c03cffe402df 45 */
slowness 0:c03cffe402df 46
slowness 0:c03cffe402df 47
slowness 0:c03cffe402df 48 /*******************************************************************************
slowness 0:c03cffe402df 49 * CMSIS definitions
slowness 0:c03cffe402df 50 ******************************************************************************/
slowness 0:c03cffe402df 51 /** \ingroup Cortex_M3
slowness 0:c03cffe402df 52 @{
slowness 0:c03cffe402df 53 */
slowness 0:c03cffe402df 54
slowness 0:c03cffe402df 55 /* CMSIS CM3 definitions */
slowness 0:c03cffe402df 56 #define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
slowness 0:c03cffe402df 57 #define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
slowness 0:c03cffe402df 58 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
slowness 0:c03cffe402df 59 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
slowness 0:c03cffe402df 60
slowness 0:c03cffe402df 61 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
slowness 0:c03cffe402df 62
slowness 0:c03cffe402df 63
slowness 0:c03cffe402df 64 #if defined ( __CC_ARM )
slowness 0:c03cffe402df 65 #define __ASM __asm /*!< asm keyword for ARM Compiler */
slowness 0:c03cffe402df 66 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
slowness 0:c03cffe402df 67 #define __STATIC_INLINE static __inline
slowness 0:c03cffe402df 68
slowness 0:c03cffe402df 69 #elif defined ( __ICCARM__ )
slowness 0:c03cffe402df 70 #define __ASM __asm /*!< asm keyword for IAR Compiler */
slowness 0:c03cffe402df 71 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
slowness 0:c03cffe402df 72 #define __STATIC_INLINE static inline
slowness 0:c03cffe402df 73
slowness 0:c03cffe402df 74 #elif defined ( __TMS470__ )
slowness 0:c03cffe402df 75 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
slowness 0:c03cffe402df 76 #define __STATIC_INLINE static inline
slowness 0:c03cffe402df 77
slowness 0:c03cffe402df 78 #elif defined ( __GNUC__ )
slowness 0:c03cffe402df 79 #define __ASM __asm /*!< asm keyword for GNU Compiler */
slowness 0:c03cffe402df 80 #define __INLINE inline /*!< inline keyword for GNU Compiler */
slowness 0:c03cffe402df 81 #define __STATIC_INLINE static inline
slowness 0:c03cffe402df 82
slowness 0:c03cffe402df 83 #elif defined ( __TASKING__ )
slowness 0:c03cffe402df 84 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
slowness 0:c03cffe402df 85 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
slowness 0:c03cffe402df 86 #define __STATIC_INLINE static inline
slowness 0:c03cffe402df 87
slowness 0:c03cffe402df 88 #endif
slowness 0:c03cffe402df 89
slowness 0:c03cffe402df 90 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
slowness 0:c03cffe402df 91 */
slowness 0:c03cffe402df 92 #define __FPU_USED 0
slowness 0:c03cffe402df 93
slowness 0:c03cffe402df 94 #if defined ( __CC_ARM )
slowness 0:c03cffe402df 95 #if defined __TARGET_FPU_VFP
slowness 0:c03cffe402df 96 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
slowness 0:c03cffe402df 97 #endif
slowness 0:c03cffe402df 98
slowness 0:c03cffe402df 99 #elif defined ( __ICCARM__ )
slowness 0:c03cffe402df 100 #if defined __ARMVFP__
slowness 0:c03cffe402df 101 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
slowness 0:c03cffe402df 102 #endif
slowness 0:c03cffe402df 103
slowness 0:c03cffe402df 104 #elif defined ( __TMS470__ )
slowness 0:c03cffe402df 105 #if defined __TI__VFP_SUPPORT____
slowness 0:c03cffe402df 106 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
slowness 0:c03cffe402df 107 #endif
slowness 0:c03cffe402df 108
slowness 0:c03cffe402df 109 #elif defined ( __GNUC__ )
slowness 0:c03cffe402df 110 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
slowness 0:c03cffe402df 111 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
slowness 0:c03cffe402df 112 #endif
slowness 0:c03cffe402df 113
slowness 0:c03cffe402df 114 #elif defined ( __TASKING__ )
slowness 0:c03cffe402df 115 /* add preprocessor checks */
slowness 0:c03cffe402df 116 #endif
slowness 0:c03cffe402df 117
slowness 0:c03cffe402df 118 #include <stdint.h> /* standard types definitions */
slowness 0:c03cffe402df 119 #include <core_cmInstr.h> /* Core Instruction Access */
slowness 0:c03cffe402df 120 #include <core_cmFunc.h> /* Core Function Access */
slowness 0:c03cffe402df 121
slowness 0:c03cffe402df 122 #endif /* __CORE_CM3_H_GENERIC */
slowness 0:c03cffe402df 123
slowness 0:c03cffe402df 124 #ifndef __CMSIS_GENERIC
slowness 0:c03cffe402df 125
slowness 0:c03cffe402df 126 #ifndef __CORE_CM3_H_DEPENDANT
slowness 0:c03cffe402df 127 #define __CORE_CM3_H_DEPENDANT
slowness 0:c03cffe402df 128
slowness 0:c03cffe402df 129 /* check device defines and use defaults */
slowness 0:c03cffe402df 130 #if defined __CHECK_DEVICE_DEFINES
slowness 0:c03cffe402df 131 #ifndef __CM3_REV
slowness 0:c03cffe402df 132 #define __CM3_REV 0x0200
slowness 0:c03cffe402df 133 #warning "__CM3_REV not defined in device header file; using default!"
slowness 0:c03cffe402df 134 #endif
slowness 0:c03cffe402df 135
slowness 0:c03cffe402df 136 #ifndef __MPU_PRESENT
slowness 0:c03cffe402df 137 #define __MPU_PRESENT 0
slowness 0:c03cffe402df 138 #warning "__MPU_PRESENT not defined in device header file; using default!"
slowness 0:c03cffe402df 139 #endif
slowness 0:c03cffe402df 140
slowness 0:c03cffe402df 141 #ifndef __NVIC_PRIO_BITS
slowness 0:c03cffe402df 142 #define __NVIC_PRIO_BITS 4
slowness 0:c03cffe402df 143 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
slowness 0:c03cffe402df 144 #endif
slowness 0:c03cffe402df 145
slowness 0:c03cffe402df 146 #ifndef __Vendor_SysTickConfig
slowness 0:c03cffe402df 147 #define __Vendor_SysTickConfig 0
slowness 0:c03cffe402df 148 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
slowness 0:c03cffe402df 149 #endif
slowness 0:c03cffe402df 150 #endif
slowness 0:c03cffe402df 151
slowness 0:c03cffe402df 152 /* IO definitions (access restrictions to peripheral registers) */
slowness 0:c03cffe402df 153 /**
slowness 0:c03cffe402df 154 \defgroup CMSIS_glob_defs CMSIS Global Defines
slowness 0:c03cffe402df 155
slowness 0:c03cffe402df 156 <strong>IO Type Qualifiers</strong> are used
slowness 0:c03cffe402df 157 \li to specify the access to peripheral variables.
slowness 0:c03cffe402df 158 \li for automatic generation of peripheral register debug information.
slowness 0:c03cffe402df 159 */
slowness 0:c03cffe402df 160 #ifdef __cplusplus
slowness 0:c03cffe402df 161 #define __I volatile /*!< Defines 'read only' permissions */
slowness 0:c03cffe402df 162 #else
slowness 0:c03cffe402df 163 #define __I volatile const /*!< Defines 'read only' permissions */
slowness 0:c03cffe402df 164 #endif
slowness 0:c03cffe402df 165 #define __O volatile /*!< Defines 'write only' permissions */
slowness 0:c03cffe402df 166 #define __IO volatile /*!< Defines 'read / write' permissions */
slowness 0:c03cffe402df 167
slowness 0:c03cffe402df 168 /*@} end of group Cortex_M3 */
slowness 0:c03cffe402df 169
slowness 0:c03cffe402df 170
slowness 0:c03cffe402df 171
slowness 0:c03cffe402df 172 /*******************************************************************************
slowness 0:c03cffe402df 173 * Register Abstraction
slowness 0:c03cffe402df 174 Core Register contain:
slowness 0:c03cffe402df 175 - Core Register
slowness 0:c03cffe402df 176 - Core NVIC Register
slowness 0:c03cffe402df 177 - Core SCB Register
slowness 0:c03cffe402df 178 - Core SysTick Register
slowness 0:c03cffe402df 179 - Core Debug Register
slowness 0:c03cffe402df 180 - Core MPU Register
slowness 0:c03cffe402df 181 ******************************************************************************/
slowness 0:c03cffe402df 182 /** \defgroup CMSIS_core_register Defines and Type Definitions
slowness 0:c03cffe402df 183 \brief Type definitions and defines for Cortex-M processor based devices.
slowness 0:c03cffe402df 184 */
slowness 0:c03cffe402df 185
slowness 0:c03cffe402df 186 /** \ingroup CMSIS_core_register
slowness 0:c03cffe402df 187 \defgroup CMSIS_CORE Status and Control Registers
slowness 0:c03cffe402df 188 \brief Core Register type definitions.
slowness 0:c03cffe402df 189 @{
slowness 0:c03cffe402df 190 */
slowness 0:c03cffe402df 191
slowness 0:c03cffe402df 192 /** \brief Union type to access the Application Program Status Register (APSR).
slowness 0:c03cffe402df 193 */
slowness 0:c03cffe402df 194 typedef union
slowness 0:c03cffe402df 195 {
slowness 0:c03cffe402df 196 struct
slowness 0:c03cffe402df 197 {
slowness 0:c03cffe402df 198 #if (__CORTEX_M != 0x04)
slowness 0:c03cffe402df 199 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
slowness 0:c03cffe402df 200 #else
slowness 0:c03cffe402df 201 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
slowness 0:c03cffe402df 202 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
slowness 0:c03cffe402df 203 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
slowness 0:c03cffe402df 204 #endif
slowness 0:c03cffe402df 205 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
slowness 0:c03cffe402df 206 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
slowness 0:c03cffe402df 207 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
slowness 0:c03cffe402df 208 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
slowness 0:c03cffe402df 209 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
slowness 0:c03cffe402df 210 } b; /*!< Structure used for bit access */
slowness 0:c03cffe402df 211 uint32_t w; /*!< Type used for word access */
slowness 0:c03cffe402df 212 } APSR_Type;
slowness 0:c03cffe402df 213
slowness 0:c03cffe402df 214
slowness 0:c03cffe402df 215 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
slowness 0:c03cffe402df 216 */
slowness 0:c03cffe402df 217 typedef union
slowness 0:c03cffe402df 218 {
slowness 0:c03cffe402df 219 struct
slowness 0:c03cffe402df 220 {
slowness 0:c03cffe402df 221 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
slowness 0:c03cffe402df 222 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
slowness 0:c03cffe402df 223 } b; /*!< Structure used for bit access */
slowness 0:c03cffe402df 224 uint32_t w; /*!< Type used for word access */
slowness 0:c03cffe402df 225 } IPSR_Type;
slowness 0:c03cffe402df 226
slowness 0:c03cffe402df 227
slowness 0:c03cffe402df 228 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
slowness 0:c03cffe402df 229 */
slowness 0:c03cffe402df 230 typedef union
slowness 0:c03cffe402df 231 {
slowness 0:c03cffe402df 232 struct
slowness 0:c03cffe402df 233 {
slowness 0:c03cffe402df 234 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
slowness 0:c03cffe402df 235 #if (__CORTEX_M != 0x04)
slowness 0:c03cffe402df 236 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
slowness 0:c03cffe402df 237 #else
slowness 0:c03cffe402df 238 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
slowness 0:c03cffe402df 239 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
slowness 0:c03cffe402df 240 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
slowness 0:c03cffe402df 241 #endif
slowness 0:c03cffe402df 242 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
slowness 0:c03cffe402df 243 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
slowness 0:c03cffe402df 244 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
slowness 0:c03cffe402df 245 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
slowness 0:c03cffe402df 246 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
slowness 0:c03cffe402df 247 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
slowness 0:c03cffe402df 248 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
slowness 0:c03cffe402df 249 } b; /*!< Structure used for bit access */
slowness 0:c03cffe402df 250 uint32_t w; /*!< Type used for word access */
slowness 0:c03cffe402df 251 } xPSR_Type;
slowness 0:c03cffe402df 252
slowness 0:c03cffe402df 253
slowness 0:c03cffe402df 254 /** \brief Union type to access the Control Registers (CONTROL).
slowness 0:c03cffe402df 255 */
slowness 0:c03cffe402df 256 typedef union
slowness 0:c03cffe402df 257 {
slowness 0:c03cffe402df 258 struct
slowness 0:c03cffe402df 259 {
slowness 0:c03cffe402df 260 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
slowness 0:c03cffe402df 261 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
slowness 0:c03cffe402df 262 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
slowness 0:c03cffe402df 263 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
slowness 0:c03cffe402df 264 } b; /*!< Structure used for bit access */
slowness 0:c03cffe402df 265 uint32_t w; /*!< Type used for word access */
slowness 0:c03cffe402df 266 } CONTROL_Type;
slowness 0:c03cffe402df 267
slowness 0:c03cffe402df 268 /*@} end of group CMSIS_CORE */
slowness 0:c03cffe402df 269
slowness 0:c03cffe402df 270
slowness 0:c03cffe402df 271 /** \ingroup CMSIS_core_register
slowness 0:c03cffe402df 272 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
slowness 0:c03cffe402df 273 \brief Type definitions for the NVIC Registers
slowness 0:c03cffe402df 274 @{
slowness 0:c03cffe402df 275 */
slowness 0:c03cffe402df 276
slowness 0:c03cffe402df 277 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
slowness 0:c03cffe402df 278 */
slowness 0:c03cffe402df 279 typedef struct
slowness 0:c03cffe402df 280 {
slowness 0:c03cffe402df 281 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
slowness 0:c03cffe402df 282 uint32_t RESERVED0[24];
slowness 0:c03cffe402df 283 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
slowness 0:c03cffe402df 284 uint32_t RSERVED1[24];
slowness 0:c03cffe402df 285 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
slowness 0:c03cffe402df 286 uint32_t RESERVED2[24];
slowness 0:c03cffe402df 287 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
slowness 0:c03cffe402df 288 uint32_t RESERVED3[24];
slowness 0:c03cffe402df 289 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
slowness 0:c03cffe402df 290 uint32_t RESERVED4[56];
slowness 0:c03cffe402df 291 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
slowness 0:c03cffe402df 292 uint32_t RESERVED5[644];
slowness 0:c03cffe402df 293 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
slowness 0:c03cffe402df 294 } NVIC_Type;
slowness 0:c03cffe402df 295
slowness 0:c03cffe402df 296 /* Software Triggered Interrupt Register Definitions */
slowness 0:c03cffe402df 297 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
slowness 0:c03cffe402df 298 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
slowness 0:c03cffe402df 299
slowness 0:c03cffe402df 300 /*@} end of group CMSIS_NVIC */
slowness 0:c03cffe402df 301
slowness 0:c03cffe402df 302
slowness 0:c03cffe402df 303 /** \ingroup CMSIS_core_register
slowness 0:c03cffe402df 304 \defgroup CMSIS_SCB System Control Block (SCB)
slowness 0:c03cffe402df 305 \brief Type definitions for the System Control Block Registers
slowness 0:c03cffe402df 306 @{
slowness 0:c03cffe402df 307 */
slowness 0:c03cffe402df 308
slowness 0:c03cffe402df 309 /** \brief Structure type to access the System Control Block (SCB).
slowness 0:c03cffe402df 310 */
slowness 0:c03cffe402df 311 typedef struct
slowness 0:c03cffe402df 312 {
slowness 0:c03cffe402df 313 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
slowness 0:c03cffe402df 314 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
slowness 0:c03cffe402df 315 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
slowness 0:c03cffe402df 316 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
slowness 0:c03cffe402df 317 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
slowness 0:c03cffe402df 318 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
slowness 0:c03cffe402df 319 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
slowness 0:c03cffe402df 320 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
slowness 0:c03cffe402df 321 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
slowness 0:c03cffe402df 322 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
slowness 0:c03cffe402df 323 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
slowness 0:c03cffe402df 324 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
slowness 0:c03cffe402df 325 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
slowness 0:c03cffe402df 326 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
slowness 0:c03cffe402df 327 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
slowness 0:c03cffe402df 328 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
slowness 0:c03cffe402df 329 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
slowness 0:c03cffe402df 330 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
slowness 0:c03cffe402df 331 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
slowness 0:c03cffe402df 332 uint32_t RESERVED0[5];
slowness 0:c03cffe402df 333 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
slowness 0:c03cffe402df 334 } SCB_Type;
slowness 0:c03cffe402df 335
slowness 0:c03cffe402df 336 /* SCB CPUID Register Definitions */
slowness 0:c03cffe402df 337 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
slowness 0:c03cffe402df 338 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
slowness 0:c03cffe402df 339
slowness 0:c03cffe402df 340 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
slowness 0:c03cffe402df 341 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
slowness 0:c03cffe402df 342
slowness 0:c03cffe402df 343 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
slowness 0:c03cffe402df 344 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
slowness 0:c03cffe402df 345
slowness 0:c03cffe402df 346 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
slowness 0:c03cffe402df 347 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
slowness 0:c03cffe402df 348
slowness 0:c03cffe402df 349 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
slowness 0:c03cffe402df 350 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
slowness 0:c03cffe402df 351
slowness 0:c03cffe402df 352 /* SCB Interrupt Control State Register Definitions */
slowness 0:c03cffe402df 353 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
slowness 0:c03cffe402df 354 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
slowness 0:c03cffe402df 355
slowness 0:c03cffe402df 356 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
slowness 0:c03cffe402df 357 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
slowness 0:c03cffe402df 358
slowness 0:c03cffe402df 359 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
slowness 0:c03cffe402df 360 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
slowness 0:c03cffe402df 361
slowness 0:c03cffe402df 362 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
slowness 0:c03cffe402df 363 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
slowness 0:c03cffe402df 364
slowness 0:c03cffe402df 365 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
slowness 0:c03cffe402df 366 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
slowness 0:c03cffe402df 367
slowness 0:c03cffe402df 368 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
slowness 0:c03cffe402df 369 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
slowness 0:c03cffe402df 370
slowness 0:c03cffe402df 371 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
slowness 0:c03cffe402df 372 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
slowness 0:c03cffe402df 373
slowness 0:c03cffe402df 374 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
slowness 0:c03cffe402df 375 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
slowness 0:c03cffe402df 376
slowness 0:c03cffe402df 377 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
slowness 0:c03cffe402df 378 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
slowness 0:c03cffe402df 379
slowness 0:c03cffe402df 380 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
slowness 0:c03cffe402df 381 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
slowness 0:c03cffe402df 382
slowness 0:c03cffe402df 383 /* SCB Vector Table Offset Register Definitions */
slowness 0:c03cffe402df 384 #if (__CM3_REV < 0x0201) /* core r2p1 */
slowness 0:c03cffe402df 385 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
slowness 0:c03cffe402df 386 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
slowness 0:c03cffe402df 387
slowness 0:c03cffe402df 388 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
slowness 0:c03cffe402df 389 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
slowness 0:c03cffe402df 390 #else
slowness 0:c03cffe402df 391 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
slowness 0:c03cffe402df 392 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
slowness 0:c03cffe402df 393 #endif
slowness 0:c03cffe402df 394
slowness 0:c03cffe402df 395 /* SCB Application Interrupt and Reset Control Register Definitions */
slowness 0:c03cffe402df 396 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
slowness 0:c03cffe402df 397 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
slowness 0:c03cffe402df 398
slowness 0:c03cffe402df 399 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
slowness 0:c03cffe402df 400 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
slowness 0:c03cffe402df 401
slowness 0:c03cffe402df 402 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
slowness 0:c03cffe402df 403 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
slowness 0:c03cffe402df 404
slowness 0:c03cffe402df 405 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
slowness 0:c03cffe402df 406 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
slowness 0:c03cffe402df 407
slowness 0:c03cffe402df 408 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
slowness 0:c03cffe402df 409 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
slowness 0:c03cffe402df 410
slowness 0:c03cffe402df 411 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
slowness 0:c03cffe402df 412 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
slowness 0:c03cffe402df 413
slowness 0:c03cffe402df 414 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
slowness 0:c03cffe402df 415 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
slowness 0:c03cffe402df 416
slowness 0:c03cffe402df 417 /* SCB System Control Register Definitions */
slowness 0:c03cffe402df 418 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
slowness 0:c03cffe402df 419 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
slowness 0:c03cffe402df 420
slowness 0:c03cffe402df 421 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
slowness 0:c03cffe402df 422 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
slowness 0:c03cffe402df 423
slowness 0:c03cffe402df 424 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
slowness 0:c03cffe402df 425 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
slowness 0:c03cffe402df 426
slowness 0:c03cffe402df 427 /* SCB Configuration Control Register Definitions */
slowness 0:c03cffe402df 428 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
slowness 0:c03cffe402df 429 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
slowness 0:c03cffe402df 430
slowness 0:c03cffe402df 431 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
slowness 0:c03cffe402df 432 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
slowness 0:c03cffe402df 433
slowness 0:c03cffe402df 434 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
slowness 0:c03cffe402df 435 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
slowness 0:c03cffe402df 436
slowness 0:c03cffe402df 437 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
slowness 0:c03cffe402df 438 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
slowness 0:c03cffe402df 439
slowness 0:c03cffe402df 440 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
slowness 0:c03cffe402df 441 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
slowness 0:c03cffe402df 442
slowness 0:c03cffe402df 443 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
slowness 0:c03cffe402df 444 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
slowness 0:c03cffe402df 445
slowness 0:c03cffe402df 446 /* SCB System Handler Control and State Register Definitions */
slowness 0:c03cffe402df 447 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
slowness 0:c03cffe402df 448 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
slowness 0:c03cffe402df 449
slowness 0:c03cffe402df 450 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
slowness 0:c03cffe402df 451 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
slowness 0:c03cffe402df 452
slowness 0:c03cffe402df 453 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
slowness 0:c03cffe402df 454 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
slowness 0:c03cffe402df 455
slowness 0:c03cffe402df 456 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
slowness 0:c03cffe402df 457 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
slowness 0:c03cffe402df 458
slowness 0:c03cffe402df 459 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
slowness 0:c03cffe402df 460 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
slowness 0:c03cffe402df 461
slowness 0:c03cffe402df 462 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
slowness 0:c03cffe402df 463 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
slowness 0:c03cffe402df 464
slowness 0:c03cffe402df 465 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
slowness 0:c03cffe402df 466 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
slowness 0:c03cffe402df 467
slowness 0:c03cffe402df 468 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
slowness 0:c03cffe402df 469 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
slowness 0:c03cffe402df 470
slowness 0:c03cffe402df 471 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
slowness 0:c03cffe402df 472 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
slowness 0:c03cffe402df 473
slowness 0:c03cffe402df 474 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
slowness 0:c03cffe402df 475 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
slowness 0:c03cffe402df 476
slowness 0:c03cffe402df 477 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
slowness 0:c03cffe402df 478 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
slowness 0:c03cffe402df 479
slowness 0:c03cffe402df 480 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
slowness 0:c03cffe402df 481 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
slowness 0:c03cffe402df 482
slowness 0:c03cffe402df 483 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
slowness 0:c03cffe402df 484 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
slowness 0:c03cffe402df 485
slowness 0:c03cffe402df 486 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
slowness 0:c03cffe402df 487 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
slowness 0:c03cffe402df 488
slowness 0:c03cffe402df 489 /* SCB Configurable Fault Status Registers Definitions */
slowness 0:c03cffe402df 490 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
slowness 0:c03cffe402df 491 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
slowness 0:c03cffe402df 492
slowness 0:c03cffe402df 493 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
slowness 0:c03cffe402df 494 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
slowness 0:c03cffe402df 495
slowness 0:c03cffe402df 496 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
slowness 0:c03cffe402df 497 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
slowness 0:c03cffe402df 498
slowness 0:c03cffe402df 499 /* SCB Hard Fault Status Registers Definitions */
slowness 0:c03cffe402df 500 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
slowness 0:c03cffe402df 501 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
slowness 0:c03cffe402df 502
slowness 0:c03cffe402df 503 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
slowness 0:c03cffe402df 504 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
slowness 0:c03cffe402df 505
slowness 0:c03cffe402df 506 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
slowness 0:c03cffe402df 507 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
slowness 0:c03cffe402df 508
slowness 0:c03cffe402df 509 /* SCB Debug Fault Status Register Definitions */
slowness 0:c03cffe402df 510 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
slowness 0:c03cffe402df 511 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
slowness 0:c03cffe402df 512
slowness 0:c03cffe402df 513 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
slowness 0:c03cffe402df 514 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
slowness 0:c03cffe402df 515
slowness 0:c03cffe402df 516 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
slowness 0:c03cffe402df 517 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
slowness 0:c03cffe402df 518
slowness 0:c03cffe402df 519 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
slowness 0:c03cffe402df 520 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
slowness 0:c03cffe402df 521
slowness 0:c03cffe402df 522 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
slowness 0:c03cffe402df 523 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
slowness 0:c03cffe402df 524
slowness 0:c03cffe402df 525 /*@} end of group CMSIS_SCB */
slowness 0:c03cffe402df 526
slowness 0:c03cffe402df 527
slowness 0:c03cffe402df 528 /** \ingroup CMSIS_core_register
slowness 0:c03cffe402df 529 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
slowness 0:c03cffe402df 530 \brief Type definitions for the System Control and ID Register not in the SCB
slowness 0:c03cffe402df 531 @{
slowness 0:c03cffe402df 532 */
slowness 0:c03cffe402df 533
slowness 0:c03cffe402df 534 /** \brief Structure type to access the System Control and ID Register not in the SCB.
slowness 0:c03cffe402df 535 */
slowness 0:c03cffe402df 536 typedef struct
slowness 0:c03cffe402df 537 {
slowness 0:c03cffe402df 538 uint32_t RESERVED0[1];
slowness 0:c03cffe402df 539 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
slowness 0:c03cffe402df 540 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
slowness 0:c03cffe402df 541 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
slowness 0:c03cffe402df 542 #else
slowness 0:c03cffe402df 543 uint32_t RESERVED1[1];
slowness 0:c03cffe402df 544 #endif
slowness 0:c03cffe402df 545 } SCnSCB_Type;
slowness 0:c03cffe402df 546
slowness 0:c03cffe402df 547 /* Interrupt Controller Type Register Definitions */
slowness 0:c03cffe402df 548 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
slowness 0:c03cffe402df 549 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
slowness 0:c03cffe402df 550
slowness 0:c03cffe402df 551 /* Auxiliary Control Register Definitions */
slowness 0:c03cffe402df 552
slowness 0:c03cffe402df 553 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
slowness 0:c03cffe402df 554 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
slowness 0:c03cffe402df 555
slowness 0:c03cffe402df 556 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
slowness 0:c03cffe402df 557 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
slowness 0:c03cffe402df 558
slowness 0:c03cffe402df 559 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
slowness 0:c03cffe402df 560 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
slowness 0:c03cffe402df 561
slowness 0:c03cffe402df 562 /*@} end of group CMSIS_SCnotSCB */
slowness 0:c03cffe402df 563
slowness 0:c03cffe402df 564
slowness 0:c03cffe402df 565 /** \ingroup CMSIS_core_register
slowness 0:c03cffe402df 566 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
slowness 0:c03cffe402df 567 \brief Type definitions for the System Timer Registers.
slowness 0:c03cffe402df 568 @{
slowness 0:c03cffe402df 569 */
slowness 0:c03cffe402df 570
slowness 0:c03cffe402df 571 /** \brief Structure type to access the System Timer (SysTick).
slowness 0:c03cffe402df 572 */
slowness 0:c03cffe402df 573 typedef struct
slowness 0:c03cffe402df 574 {
slowness 0:c03cffe402df 575 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
slowness 0:c03cffe402df 576 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
slowness 0:c03cffe402df 577 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
slowness 0:c03cffe402df 578 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
slowness 0:c03cffe402df 579 } SysTick_Type;
slowness 0:c03cffe402df 580
slowness 0:c03cffe402df 581 /* SysTick Control / Status Register Definitions */
slowness 0:c03cffe402df 582 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
slowness 0:c03cffe402df 583 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
slowness 0:c03cffe402df 584
slowness 0:c03cffe402df 585 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
slowness 0:c03cffe402df 586 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
slowness 0:c03cffe402df 587
slowness 0:c03cffe402df 588 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
slowness 0:c03cffe402df 589 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
slowness 0:c03cffe402df 590
slowness 0:c03cffe402df 591 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
slowness 0:c03cffe402df 592 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
slowness 0:c03cffe402df 593
slowness 0:c03cffe402df 594 /* SysTick Reload Register Definitions */
slowness 0:c03cffe402df 595 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
slowness 0:c03cffe402df 596 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
slowness 0:c03cffe402df 597
slowness 0:c03cffe402df 598 /* SysTick Current Register Definitions */
slowness 0:c03cffe402df 599 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
slowness 0:c03cffe402df 600 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
slowness 0:c03cffe402df 601
slowness 0:c03cffe402df 602 /* SysTick Calibration Register Definitions */
slowness 0:c03cffe402df 603 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
slowness 0:c03cffe402df 604 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
slowness 0:c03cffe402df 605
slowness 0:c03cffe402df 606 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
slowness 0:c03cffe402df 607 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
slowness 0:c03cffe402df 608
slowness 0:c03cffe402df 609 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
slowness 0:c03cffe402df 610 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
slowness 0:c03cffe402df 611
slowness 0:c03cffe402df 612 /*@} end of group CMSIS_SysTick */
slowness 0:c03cffe402df 613
slowness 0:c03cffe402df 614
slowness 0:c03cffe402df 615 /** \ingroup CMSIS_core_register
slowness 0:c03cffe402df 616 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
slowness 0:c03cffe402df 617 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
slowness 0:c03cffe402df 618 @{
slowness 0:c03cffe402df 619 */
slowness 0:c03cffe402df 620
slowness 0:c03cffe402df 621 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
slowness 0:c03cffe402df 622 */
slowness 0:c03cffe402df 623 typedef struct
slowness 0:c03cffe402df 624 {
slowness 0:c03cffe402df 625 __O union
slowness 0:c03cffe402df 626 {
slowness 0:c03cffe402df 627 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
slowness 0:c03cffe402df 628 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
slowness 0:c03cffe402df 629 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
slowness 0:c03cffe402df 630 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
slowness 0:c03cffe402df 631 uint32_t RESERVED0[864];
slowness 0:c03cffe402df 632 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
slowness 0:c03cffe402df 633 uint32_t RESERVED1[15];
slowness 0:c03cffe402df 634 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
slowness 0:c03cffe402df 635 uint32_t RESERVED2[15];
slowness 0:c03cffe402df 636 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
slowness 0:c03cffe402df 637 } ITM_Type;
slowness 0:c03cffe402df 638
slowness 0:c03cffe402df 639 /* ITM Trace Privilege Register Definitions */
slowness 0:c03cffe402df 640 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
slowness 0:c03cffe402df 641 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
slowness 0:c03cffe402df 642
slowness 0:c03cffe402df 643 /* ITM Trace Control Register Definitions */
slowness 0:c03cffe402df 644 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
slowness 0:c03cffe402df 645 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
slowness 0:c03cffe402df 646
slowness 0:c03cffe402df 647 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
slowness 0:c03cffe402df 648 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
slowness 0:c03cffe402df 649
slowness 0:c03cffe402df 650 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
slowness 0:c03cffe402df 651 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
slowness 0:c03cffe402df 652
slowness 0:c03cffe402df 653 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
slowness 0:c03cffe402df 654 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
slowness 0:c03cffe402df 655
slowness 0:c03cffe402df 656 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
slowness 0:c03cffe402df 657 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
slowness 0:c03cffe402df 658
slowness 0:c03cffe402df 659 #define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */
slowness 0:c03cffe402df 660 #define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */
slowness 0:c03cffe402df 661
slowness 0:c03cffe402df 662 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
slowness 0:c03cffe402df 663 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
slowness 0:c03cffe402df 664
slowness 0:c03cffe402df 665 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
slowness 0:c03cffe402df 666 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
slowness 0:c03cffe402df 667
slowness 0:c03cffe402df 668 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
slowness 0:c03cffe402df 669 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
slowness 0:c03cffe402df 670
slowness 0:c03cffe402df 671 /*@}*/ /* end of group CMSIS_ITM */
slowness 0:c03cffe402df 672
slowness 0:c03cffe402df 673
slowness 0:c03cffe402df 674 /** \ingroup CMSIS_core_register
slowness 0:c03cffe402df 675 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
slowness 0:c03cffe402df 676 \brief Type definitions for the Data Watchpoint and Trace (DWT)
slowness 0:c03cffe402df 677 @{
slowness 0:c03cffe402df 678 */
slowness 0:c03cffe402df 679
slowness 0:c03cffe402df 680 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
slowness 0:c03cffe402df 681 */
slowness 0:c03cffe402df 682 typedef struct
slowness 0:c03cffe402df 683 {
slowness 0:c03cffe402df 684 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
slowness 0:c03cffe402df 685 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
slowness 0:c03cffe402df 686 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
slowness 0:c03cffe402df 687 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
slowness 0:c03cffe402df 688 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
slowness 0:c03cffe402df 689 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
slowness 0:c03cffe402df 690 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
slowness 0:c03cffe402df 691 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
slowness 0:c03cffe402df 692 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
slowness 0:c03cffe402df 693 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
slowness 0:c03cffe402df 694 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
slowness 0:c03cffe402df 695 uint32_t RESERVED0[1];
slowness 0:c03cffe402df 696 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
slowness 0:c03cffe402df 697 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
slowness 0:c03cffe402df 698 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
slowness 0:c03cffe402df 699 uint32_t RESERVED1[1];
slowness 0:c03cffe402df 700 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
slowness 0:c03cffe402df 701 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
slowness 0:c03cffe402df 702 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
slowness 0:c03cffe402df 703 uint32_t RESERVED2[1];
slowness 0:c03cffe402df 704 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
slowness 0:c03cffe402df 705 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
slowness 0:c03cffe402df 706 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
slowness 0:c03cffe402df 707 } DWT_Type;
slowness 0:c03cffe402df 708
slowness 0:c03cffe402df 709 /* DWT Control Register Definitions */
slowness 0:c03cffe402df 710 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
slowness 0:c03cffe402df 711 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
slowness 0:c03cffe402df 712
slowness 0:c03cffe402df 713 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
slowness 0:c03cffe402df 714 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
slowness 0:c03cffe402df 715
slowness 0:c03cffe402df 716 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
slowness 0:c03cffe402df 717 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
slowness 0:c03cffe402df 718
slowness 0:c03cffe402df 719 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
slowness 0:c03cffe402df 720 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
slowness 0:c03cffe402df 721
slowness 0:c03cffe402df 722 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
slowness 0:c03cffe402df 723 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
slowness 0:c03cffe402df 724
slowness 0:c03cffe402df 725 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
slowness 0:c03cffe402df 726 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
slowness 0:c03cffe402df 727
slowness 0:c03cffe402df 728 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
slowness 0:c03cffe402df 729 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
slowness 0:c03cffe402df 730
slowness 0:c03cffe402df 731 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
slowness 0:c03cffe402df 732 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
slowness 0:c03cffe402df 733
slowness 0:c03cffe402df 734 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
slowness 0:c03cffe402df 735 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
slowness 0:c03cffe402df 736
slowness 0:c03cffe402df 737 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
slowness 0:c03cffe402df 738 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
slowness 0:c03cffe402df 739
slowness 0:c03cffe402df 740 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
slowness 0:c03cffe402df 741 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
slowness 0:c03cffe402df 742
slowness 0:c03cffe402df 743 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
slowness 0:c03cffe402df 744 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
slowness 0:c03cffe402df 745
slowness 0:c03cffe402df 746 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
slowness 0:c03cffe402df 747 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
slowness 0:c03cffe402df 748
slowness 0:c03cffe402df 749 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
slowness 0:c03cffe402df 750 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
slowness 0:c03cffe402df 751
slowness 0:c03cffe402df 752 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
slowness 0:c03cffe402df 753 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
slowness 0:c03cffe402df 754
slowness 0:c03cffe402df 755 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
slowness 0:c03cffe402df 756 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
slowness 0:c03cffe402df 757
slowness 0:c03cffe402df 758 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
slowness 0:c03cffe402df 759 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
slowness 0:c03cffe402df 760
slowness 0:c03cffe402df 761 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
slowness 0:c03cffe402df 762 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
slowness 0:c03cffe402df 763
slowness 0:c03cffe402df 764 /* DWT CPI Count Register Definitions */
slowness 0:c03cffe402df 765 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
slowness 0:c03cffe402df 766 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
slowness 0:c03cffe402df 767
slowness 0:c03cffe402df 768 /* DWT Exception Overhead Count Register Definitions */
slowness 0:c03cffe402df 769 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
slowness 0:c03cffe402df 770 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
slowness 0:c03cffe402df 771
slowness 0:c03cffe402df 772 /* DWT Sleep Count Register Definitions */
slowness 0:c03cffe402df 773 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
slowness 0:c03cffe402df 774 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
slowness 0:c03cffe402df 775
slowness 0:c03cffe402df 776 /* DWT LSU Count Register Definitions */
slowness 0:c03cffe402df 777 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
slowness 0:c03cffe402df 778 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
slowness 0:c03cffe402df 779
slowness 0:c03cffe402df 780 /* DWT Folded-instruction Count Register Definitions */
slowness 0:c03cffe402df 781 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
slowness 0:c03cffe402df 782 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
slowness 0:c03cffe402df 783
slowness 0:c03cffe402df 784 /* DWT Comparator Mask Register Definitions */
slowness 0:c03cffe402df 785 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
slowness 0:c03cffe402df 786 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
slowness 0:c03cffe402df 787
slowness 0:c03cffe402df 788 /* DWT Comparator Function Register Definitions */
slowness 0:c03cffe402df 789 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
slowness 0:c03cffe402df 790 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
slowness 0:c03cffe402df 791
slowness 0:c03cffe402df 792 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
slowness 0:c03cffe402df 793 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
slowness 0:c03cffe402df 794
slowness 0:c03cffe402df 795 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
slowness 0:c03cffe402df 796 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
slowness 0:c03cffe402df 797
slowness 0:c03cffe402df 798 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
slowness 0:c03cffe402df 799 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
slowness 0:c03cffe402df 800
slowness 0:c03cffe402df 801 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
slowness 0:c03cffe402df 802 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
slowness 0:c03cffe402df 803
slowness 0:c03cffe402df 804 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
slowness 0:c03cffe402df 805 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
slowness 0:c03cffe402df 806
slowness 0:c03cffe402df 807 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
slowness 0:c03cffe402df 808 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
slowness 0:c03cffe402df 809
slowness 0:c03cffe402df 810 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
slowness 0:c03cffe402df 811 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
slowness 0:c03cffe402df 812
slowness 0:c03cffe402df 813 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
slowness 0:c03cffe402df 814 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
slowness 0:c03cffe402df 815
slowness 0:c03cffe402df 816 /*@}*/ /* end of group CMSIS_DWT */
slowness 0:c03cffe402df 817
slowness 0:c03cffe402df 818
slowness 0:c03cffe402df 819 /** \ingroup CMSIS_core_register
slowness 0:c03cffe402df 820 \defgroup CMSIS_TPI Trace Port Interface (TPI)
slowness 0:c03cffe402df 821 \brief Type definitions for the Trace Port Interface (TPI)
slowness 0:c03cffe402df 822 @{
slowness 0:c03cffe402df 823 */
slowness 0:c03cffe402df 824
slowness 0:c03cffe402df 825 /** \brief Structure type to access the Trace Port Interface Register (TPI).
slowness 0:c03cffe402df 826 */
slowness 0:c03cffe402df 827 typedef struct
slowness 0:c03cffe402df 828 {
slowness 0:c03cffe402df 829 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
slowness 0:c03cffe402df 830 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
slowness 0:c03cffe402df 831 uint32_t RESERVED0[2];
slowness 0:c03cffe402df 832 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
slowness 0:c03cffe402df 833 uint32_t RESERVED1[55];
slowness 0:c03cffe402df 834 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
slowness 0:c03cffe402df 835 uint32_t RESERVED2[131];
slowness 0:c03cffe402df 836 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
slowness 0:c03cffe402df 837 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
slowness 0:c03cffe402df 838 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
slowness 0:c03cffe402df 839 uint32_t RESERVED3[759];
slowness 0:c03cffe402df 840 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
slowness 0:c03cffe402df 841 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
slowness 0:c03cffe402df 842 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
slowness 0:c03cffe402df 843 uint32_t RESERVED4[1];
slowness 0:c03cffe402df 844 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
slowness 0:c03cffe402df 845 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
slowness 0:c03cffe402df 846 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
slowness 0:c03cffe402df 847 uint32_t RESERVED5[39];
slowness 0:c03cffe402df 848 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
slowness 0:c03cffe402df 849 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
slowness 0:c03cffe402df 850 uint32_t RESERVED7[8];
slowness 0:c03cffe402df 851 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
slowness 0:c03cffe402df 852 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
slowness 0:c03cffe402df 853 } TPI_Type;
slowness 0:c03cffe402df 854
slowness 0:c03cffe402df 855 /* TPI Asynchronous Clock Prescaler Register Definitions */
slowness 0:c03cffe402df 856 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
slowness 0:c03cffe402df 857 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
slowness 0:c03cffe402df 858
slowness 0:c03cffe402df 859 /* TPI Selected Pin Protocol Register Definitions */
slowness 0:c03cffe402df 860 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
slowness 0:c03cffe402df 861 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
slowness 0:c03cffe402df 862
slowness 0:c03cffe402df 863 /* TPI Formatter and Flush Status Register Definitions */
slowness 0:c03cffe402df 864 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
slowness 0:c03cffe402df 865 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
slowness 0:c03cffe402df 866
slowness 0:c03cffe402df 867 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
slowness 0:c03cffe402df 868 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
slowness 0:c03cffe402df 869
slowness 0:c03cffe402df 870 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
slowness 0:c03cffe402df 871 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
slowness 0:c03cffe402df 872
slowness 0:c03cffe402df 873 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
slowness 0:c03cffe402df 874 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
slowness 0:c03cffe402df 875
slowness 0:c03cffe402df 876 /* TPI Formatter and Flush Control Register Definitions */
slowness 0:c03cffe402df 877 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
slowness 0:c03cffe402df 878 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
slowness 0:c03cffe402df 879
slowness 0:c03cffe402df 880 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
slowness 0:c03cffe402df 881 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
slowness 0:c03cffe402df 882
slowness 0:c03cffe402df 883 /* TPI TRIGGER Register Definitions */
slowness 0:c03cffe402df 884 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
slowness 0:c03cffe402df 885 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
slowness 0:c03cffe402df 886
slowness 0:c03cffe402df 887 /* TPI Integration ETM Data Register Definitions (FIFO0) */
slowness 0:c03cffe402df 888 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
slowness 0:c03cffe402df 889 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
slowness 0:c03cffe402df 890
slowness 0:c03cffe402df 891 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
slowness 0:c03cffe402df 892 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
slowness 0:c03cffe402df 893
slowness 0:c03cffe402df 894 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
slowness 0:c03cffe402df 895 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
slowness 0:c03cffe402df 896
slowness 0:c03cffe402df 897 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
slowness 0:c03cffe402df 898 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
slowness 0:c03cffe402df 899
slowness 0:c03cffe402df 900 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
slowness 0:c03cffe402df 901 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
slowness 0:c03cffe402df 902
slowness 0:c03cffe402df 903 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
slowness 0:c03cffe402df 904 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
slowness 0:c03cffe402df 905
slowness 0:c03cffe402df 906 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
slowness 0:c03cffe402df 907 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
slowness 0:c03cffe402df 908
slowness 0:c03cffe402df 909 /* TPI ITATBCTR2 Register Definitions */
slowness 0:c03cffe402df 910 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
slowness 0:c03cffe402df 911 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
slowness 0:c03cffe402df 912
slowness 0:c03cffe402df 913 /* TPI Integration ITM Data Register Definitions (FIFO1) */
slowness 0:c03cffe402df 914 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
slowness 0:c03cffe402df 915 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
slowness 0:c03cffe402df 916
slowness 0:c03cffe402df 917 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
slowness 0:c03cffe402df 918 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
slowness 0:c03cffe402df 919
slowness 0:c03cffe402df 920 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
slowness 0:c03cffe402df 921 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
slowness 0:c03cffe402df 922
slowness 0:c03cffe402df 923 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
slowness 0:c03cffe402df 924 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
slowness 0:c03cffe402df 925
slowness 0:c03cffe402df 926 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
slowness 0:c03cffe402df 927 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
slowness 0:c03cffe402df 928
slowness 0:c03cffe402df 929 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
slowness 0:c03cffe402df 930 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
slowness 0:c03cffe402df 931
slowness 0:c03cffe402df 932 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
slowness 0:c03cffe402df 933 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
slowness 0:c03cffe402df 934
slowness 0:c03cffe402df 935 /* TPI ITATBCTR0 Register Definitions */
slowness 0:c03cffe402df 936 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
slowness 0:c03cffe402df 937 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
slowness 0:c03cffe402df 938
slowness 0:c03cffe402df 939 /* TPI Integration Mode Control Register Definitions */
slowness 0:c03cffe402df 940 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
slowness 0:c03cffe402df 941 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
slowness 0:c03cffe402df 942
slowness 0:c03cffe402df 943 /* TPI DEVID Register Definitions */
slowness 0:c03cffe402df 944 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
slowness 0:c03cffe402df 945 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
slowness 0:c03cffe402df 946
slowness 0:c03cffe402df 947 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
slowness 0:c03cffe402df 948 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
slowness 0:c03cffe402df 949
slowness 0:c03cffe402df 950 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
slowness 0:c03cffe402df 951 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
slowness 0:c03cffe402df 952
slowness 0:c03cffe402df 953 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
slowness 0:c03cffe402df 954 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
slowness 0:c03cffe402df 955
slowness 0:c03cffe402df 956 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
slowness 0:c03cffe402df 957 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
slowness 0:c03cffe402df 958
slowness 0:c03cffe402df 959 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
slowness 0:c03cffe402df 960 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
slowness 0:c03cffe402df 961
slowness 0:c03cffe402df 962 /* TPI DEVTYPE Register Definitions */
slowness 0:c03cffe402df 963 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
slowness 0:c03cffe402df 964 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
slowness 0:c03cffe402df 965
slowness 0:c03cffe402df 966 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
slowness 0:c03cffe402df 967 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
slowness 0:c03cffe402df 968
slowness 0:c03cffe402df 969 /*@}*/ /* end of group CMSIS_TPI */
slowness 0:c03cffe402df 970
slowness 0:c03cffe402df 971
slowness 0:c03cffe402df 972 #if (__MPU_PRESENT == 1)
slowness 0:c03cffe402df 973 /** \ingroup CMSIS_core_register
slowness 0:c03cffe402df 974 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
slowness 0:c03cffe402df 975 \brief Type definitions for the Memory Protection Unit (MPU)
slowness 0:c03cffe402df 976 @{
slowness 0:c03cffe402df 977 */
slowness 0:c03cffe402df 978
slowness 0:c03cffe402df 979 /** \brief Structure type to access the Memory Protection Unit (MPU).
slowness 0:c03cffe402df 980 */
slowness 0:c03cffe402df 981 typedef struct
slowness 0:c03cffe402df 982 {
slowness 0:c03cffe402df 983 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
slowness 0:c03cffe402df 984 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
slowness 0:c03cffe402df 985 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
slowness 0:c03cffe402df 986 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
slowness 0:c03cffe402df 987 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
slowness 0:c03cffe402df 988 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
slowness 0:c03cffe402df 989 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
slowness 0:c03cffe402df 990 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
slowness 0:c03cffe402df 991 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
slowness 0:c03cffe402df 992 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
slowness 0:c03cffe402df 993 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
slowness 0:c03cffe402df 994 } MPU_Type;
slowness 0:c03cffe402df 995
slowness 0:c03cffe402df 996 /* MPU Type Register */
slowness 0:c03cffe402df 997 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
slowness 0:c03cffe402df 998 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
slowness 0:c03cffe402df 999
slowness 0:c03cffe402df 1000 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
slowness 0:c03cffe402df 1001 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
slowness 0:c03cffe402df 1002
slowness 0:c03cffe402df 1003 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
slowness 0:c03cffe402df 1004 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
slowness 0:c03cffe402df 1005
slowness 0:c03cffe402df 1006 /* MPU Control Register */
slowness 0:c03cffe402df 1007 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
slowness 0:c03cffe402df 1008 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
slowness 0:c03cffe402df 1009
slowness 0:c03cffe402df 1010 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
slowness 0:c03cffe402df 1011 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
slowness 0:c03cffe402df 1012
slowness 0:c03cffe402df 1013 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
slowness 0:c03cffe402df 1014 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
slowness 0:c03cffe402df 1015
slowness 0:c03cffe402df 1016 /* MPU Region Number Register */
slowness 0:c03cffe402df 1017 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
slowness 0:c03cffe402df 1018 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
slowness 0:c03cffe402df 1019
slowness 0:c03cffe402df 1020 /* MPU Region Base Address Register */
slowness 0:c03cffe402df 1021 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
slowness 0:c03cffe402df 1022 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
slowness 0:c03cffe402df 1023
slowness 0:c03cffe402df 1024 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
slowness 0:c03cffe402df 1025 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
slowness 0:c03cffe402df 1026
slowness 0:c03cffe402df 1027 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
slowness 0:c03cffe402df 1028 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
slowness 0:c03cffe402df 1029
slowness 0:c03cffe402df 1030 /* MPU Region Attribute and Size Register */
slowness 0:c03cffe402df 1031 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
slowness 0:c03cffe402df 1032 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
slowness 0:c03cffe402df 1033
slowness 0:c03cffe402df 1034 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
slowness 0:c03cffe402df 1035 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
slowness 0:c03cffe402df 1036
slowness 0:c03cffe402df 1037 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
slowness 0:c03cffe402df 1038 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
slowness 0:c03cffe402df 1039
slowness 0:c03cffe402df 1040 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
slowness 0:c03cffe402df 1041 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
slowness 0:c03cffe402df 1042
slowness 0:c03cffe402df 1043 /*@} end of group CMSIS_MPU */
slowness 0:c03cffe402df 1044 #endif
slowness 0:c03cffe402df 1045
slowness 0:c03cffe402df 1046
slowness 0:c03cffe402df 1047 /** \ingroup CMSIS_core_register
slowness 0:c03cffe402df 1048 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
slowness 0:c03cffe402df 1049 \brief Type definitions for the Core Debug Registers
slowness 0:c03cffe402df 1050 @{
slowness 0:c03cffe402df 1051 */
slowness 0:c03cffe402df 1052
slowness 0:c03cffe402df 1053 /** \brief Structure type to access the Core Debug Register (CoreDebug).
slowness 0:c03cffe402df 1054 */
slowness 0:c03cffe402df 1055 typedef struct
slowness 0:c03cffe402df 1056 {
slowness 0:c03cffe402df 1057 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
slowness 0:c03cffe402df 1058 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
slowness 0:c03cffe402df 1059 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
slowness 0:c03cffe402df 1060 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
slowness 0:c03cffe402df 1061 } CoreDebug_Type;
slowness 0:c03cffe402df 1062
slowness 0:c03cffe402df 1063 /* Debug Halting Control and Status Register */
slowness 0:c03cffe402df 1064 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
slowness 0:c03cffe402df 1065 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
slowness 0:c03cffe402df 1066
slowness 0:c03cffe402df 1067 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
slowness 0:c03cffe402df 1068 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
slowness 0:c03cffe402df 1069
slowness 0:c03cffe402df 1070 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
slowness 0:c03cffe402df 1071 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
slowness 0:c03cffe402df 1072
slowness 0:c03cffe402df 1073 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
slowness 0:c03cffe402df 1074 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
slowness 0:c03cffe402df 1075
slowness 0:c03cffe402df 1076 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
slowness 0:c03cffe402df 1077 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
slowness 0:c03cffe402df 1078
slowness 0:c03cffe402df 1079 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
slowness 0:c03cffe402df 1080 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
slowness 0:c03cffe402df 1081
slowness 0:c03cffe402df 1082 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
slowness 0:c03cffe402df 1083 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
slowness 0:c03cffe402df 1084
slowness 0:c03cffe402df 1085 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
slowness 0:c03cffe402df 1086 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
slowness 0:c03cffe402df 1087
slowness 0:c03cffe402df 1088 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
slowness 0:c03cffe402df 1089 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
slowness 0:c03cffe402df 1090
slowness 0:c03cffe402df 1091 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
slowness 0:c03cffe402df 1092 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
slowness 0:c03cffe402df 1093
slowness 0:c03cffe402df 1094 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
slowness 0:c03cffe402df 1095 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
slowness 0:c03cffe402df 1096
slowness 0:c03cffe402df 1097 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
slowness 0:c03cffe402df 1098 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
slowness 0:c03cffe402df 1099
slowness 0:c03cffe402df 1100 /* Debug Core Register Selector Register */
slowness 0:c03cffe402df 1101 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
slowness 0:c03cffe402df 1102 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
slowness 0:c03cffe402df 1103
slowness 0:c03cffe402df 1104 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
slowness 0:c03cffe402df 1105 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
slowness 0:c03cffe402df 1106
slowness 0:c03cffe402df 1107 /* Debug Exception and Monitor Control Register */
slowness 0:c03cffe402df 1108 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
slowness 0:c03cffe402df 1109 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
slowness 0:c03cffe402df 1110
slowness 0:c03cffe402df 1111 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
slowness 0:c03cffe402df 1112 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
slowness 0:c03cffe402df 1113
slowness 0:c03cffe402df 1114 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
slowness 0:c03cffe402df 1115 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
slowness 0:c03cffe402df 1116
slowness 0:c03cffe402df 1117 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
slowness 0:c03cffe402df 1118 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
slowness 0:c03cffe402df 1119
slowness 0:c03cffe402df 1120 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
slowness 0:c03cffe402df 1121 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
slowness 0:c03cffe402df 1122
slowness 0:c03cffe402df 1123 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
slowness 0:c03cffe402df 1124 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
slowness 0:c03cffe402df 1125
slowness 0:c03cffe402df 1126 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
slowness 0:c03cffe402df 1127 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
slowness 0:c03cffe402df 1128
slowness 0:c03cffe402df 1129 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
slowness 0:c03cffe402df 1130 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
slowness 0:c03cffe402df 1131
slowness 0:c03cffe402df 1132 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
slowness 0:c03cffe402df 1133 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
slowness 0:c03cffe402df 1134
slowness 0:c03cffe402df 1135 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
slowness 0:c03cffe402df 1136 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
slowness 0:c03cffe402df 1137
slowness 0:c03cffe402df 1138 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
slowness 0:c03cffe402df 1139 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
slowness 0:c03cffe402df 1140
slowness 0:c03cffe402df 1141 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
slowness 0:c03cffe402df 1142 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
slowness 0:c03cffe402df 1143
slowness 0:c03cffe402df 1144 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
slowness 0:c03cffe402df 1145 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
slowness 0:c03cffe402df 1146
slowness 0:c03cffe402df 1147 /*@} end of group CMSIS_CoreDebug */
slowness 0:c03cffe402df 1148
slowness 0:c03cffe402df 1149
slowness 0:c03cffe402df 1150 /** \ingroup CMSIS_core_register
slowness 0:c03cffe402df 1151 \defgroup CMSIS_core_base Core Definitions
slowness 0:c03cffe402df 1152 \brief Definitions for base addresses, unions, and structures.
slowness 0:c03cffe402df 1153 @{
slowness 0:c03cffe402df 1154 */
slowness 0:c03cffe402df 1155
slowness 0:c03cffe402df 1156 /* Memory mapping of Cortex-M3 Hardware */
slowness 0:c03cffe402df 1157 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
slowness 0:c03cffe402df 1158 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
slowness 0:c03cffe402df 1159 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
slowness 0:c03cffe402df 1160 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
slowness 0:c03cffe402df 1161 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
slowness 0:c03cffe402df 1162 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
slowness 0:c03cffe402df 1163 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
slowness 0:c03cffe402df 1164 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
slowness 0:c03cffe402df 1165
slowness 0:c03cffe402df 1166 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
slowness 0:c03cffe402df 1167 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
slowness 0:c03cffe402df 1168 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
slowness 0:c03cffe402df 1169 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
slowness 0:c03cffe402df 1170 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
slowness 0:c03cffe402df 1171 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
slowness 0:c03cffe402df 1172 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
slowness 0:c03cffe402df 1173 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
slowness 0:c03cffe402df 1174
slowness 0:c03cffe402df 1175 #if (__MPU_PRESENT == 1)
slowness 0:c03cffe402df 1176 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
slowness 0:c03cffe402df 1177 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
slowness 0:c03cffe402df 1178 #endif
slowness 0:c03cffe402df 1179
slowness 0:c03cffe402df 1180 /*@} */
slowness 0:c03cffe402df 1181
slowness 0:c03cffe402df 1182
slowness 0:c03cffe402df 1183
slowness 0:c03cffe402df 1184 /*******************************************************************************
slowness 0:c03cffe402df 1185 * Hardware Abstraction Layer
slowness 0:c03cffe402df 1186 Core Function Interface contains:
slowness 0:c03cffe402df 1187 - Core NVIC Functions
slowness 0:c03cffe402df 1188 - Core SysTick Functions
slowness 0:c03cffe402df 1189 - Core Debug Functions
slowness 0:c03cffe402df 1190 - Core Register Access Functions
slowness 0:c03cffe402df 1191 ******************************************************************************/
slowness 0:c03cffe402df 1192 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
slowness 0:c03cffe402df 1193 */
slowness 0:c03cffe402df 1194
slowness 0:c03cffe402df 1195
slowness 0:c03cffe402df 1196
slowness 0:c03cffe402df 1197 /* ########################## NVIC functions #################################### */
slowness 0:c03cffe402df 1198 /** \ingroup CMSIS_Core_FunctionInterface
slowness 0:c03cffe402df 1199 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
slowness 0:c03cffe402df 1200 \brief Functions that manage interrupts and exceptions via the NVIC.
slowness 0:c03cffe402df 1201 @{
slowness 0:c03cffe402df 1202 */
slowness 0:c03cffe402df 1203
slowness 0:c03cffe402df 1204 /** \brief Set Priority Grouping
slowness 0:c03cffe402df 1205
slowness 0:c03cffe402df 1206 The function sets the priority grouping field using the required unlock sequence.
slowness 0:c03cffe402df 1207 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
slowness 0:c03cffe402df 1208 Only values from 0..7 are used.
slowness 0:c03cffe402df 1209 In case of a conflict between priority grouping and available
slowness 0:c03cffe402df 1210 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
slowness 0:c03cffe402df 1211
slowness 0:c03cffe402df 1212 \param [in] PriorityGroup Priority grouping field.
slowness 0:c03cffe402df 1213 */
slowness 0:c03cffe402df 1214 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
slowness 0:c03cffe402df 1215 {
slowness 0:c03cffe402df 1216 uint32_t reg_value;
slowness 0:c03cffe402df 1217 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
slowness 0:c03cffe402df 1218
slowness 0:c03cffe402df 1219 reg_value = SCB->AIRCR; /* read old register configuration */
slowness 0:c03cffe402df 1220 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
slowness 0:c03cffe402df 1221 reg_value = (reg_value |
slowness 0:c03cffe402df 1222 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
slowness 0:c03cffe402df 1223 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
slowness 0:c03cffe402df 1224 SCB->AIRCR = reg_value;
slowness 0:c03cffe402df 1225 }
slowness 0:c03cffe402df 1226
slowness 0:c03cffe402df 1227
slowness 0:c03cffe402df 1228 /** \brief Get Priority Grouping
slowness 0:c03cffe402df 1229
slowness 0:c03cffe402df 1230 The function reads the priority grouping field from the NVIC Interrupt Controller.
slowness 0:c03cffe402df 1231
slowness 0:c03cffe402df 1232 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
slowness 0:c03cffe402df 1233 */
slowness 0:c03cffe402df 1234 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
slowness 0:c03cffe402df 1235 {
slowness 0:c03cffe402df 1236 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
slowness 0:c03cffe402df 1237 }
slowness 0:c03cffe402df 1238
slowness 0:c03cffe402df 1239
slowness 0:c03cffe402df 1240 /** \brief Enable External Interrupt
slowness 0:c03cffe402df 1241
slowness 0:c03cffe402df 1242 The function enables a device-specific interrupt in the NVIC interrupt controller.
slowness 0:c03cffe402df 1243
slowness 0:c03cffe402df 1244 \param [in] IRQn External interrupt number. Value cannot be negative.
slowness 0:c03cffe402df 1245 */
slowness 0:c03cffe402df 1246 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
slowness 0:c03cffe402df 1247 {
slowness 0:c03cffe402df 1248 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
slowness 0:c03cffe402df 1249 }
slowness 0:c03cffe402df 1250
slowness 0:c03cffe402df 1251
slowness 0:c03cffe402df 1252 /** \brief Disable External Interrupt
slowness 0:c03cffe402df 1253
slowness 0:c03cffe402df 1254 The function disables a device-specific interrupt in the NVIC interrupt controller.
slowness 0:c03cffe402df 1255
slowness 0:c03cffe402df 1256 \param [in] IRQn External interrupt number. Value cannot be negative.
slowness 0:c03cffe402df 1257 */
slowness 0:c03cffe402df 1258 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
slowness 0:c03cffe402df 1259 {
slowness 0:c03cffe402df 1260 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
slowness 0:c03cffe402df 1261 }
slowness 0:c03cffe402df 1262
slowness 0:c03cffe402df 1263
slowness 0:c03cffe402df 1264 /** \brief Get Pending Interrupt
slowness 0:c03cffe402df 1265
slowness 0:c03cffe402df 1266 The function reads the pending register in the NVIC and returns the pending bit
slowness 0:c03cffe402df 1267 for the specified interrupt.
slowness 0:c03cffe402df 1268
slowness 0:c03cffe402df 1269 \param [in] IRQn Interrupt number.
slowness 0:c03cffe402df 1270
slowness 0:c03cffe402df 1271 \return 0 Interrupt status is not pending.
slowness 0:c03cffe402df 1272 \return 1 Interrupt status is pending.
slowness 0:c03cffe402df 1273 */
slowness 0:c03cffe402df 1274 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
slowness 0:c03cffe402df 1275 {
slowness 0:c03cffe402df 1276 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
slowness 0:c03cffe402df 1277 }
slowness 0:c03cffe402df 1278
slowness 0:c03cffe402df 1279
slowness 0:c03cffe402df 1280 /** \brief Set Pending Interrupt
slowness 0:c03cffe402df 1281
slowness 0:c03cffe402df 1282 The function sets the pending bit of an external interrupt.
slowness 0:c03cffe402df 1283
slowness 0:c03cffe402df 1284 \param [in] IRQn Interrupt number. Value cannot be negative.
slowness 0:c03cffe402df 1285 */
slowness 0:c03cffe402df 1286 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
slowness 0:c03cffe402df 1287 {
slowness 0:c03cffe402df 1288 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
slowness 0:c03cffe402df 1289 }
slowness 0:c03cffe402df 1290
slowness 0:c03cffe402df 1291
slowness 0:c03cffe402df 1292 /** \brief Clear Pending Interrupt
slowness 0:c03cffe402df 1293
slowness 0:c03cffe402df 1294 The function clears the pending bit of an external interrupt.
slowness 0:c03cffe402df 1295
slowness 0:c03cffe402df 1296 \param [in] IRQn External interrupt number. Value cannot be negative.
slowness 0:c03cffe402df 1297 */
slowness 0:c03cffe402df 1298 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
slowness 0:c03cffe402df 1299 {
slowness 0:c03cffe402df 1300 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
slowness 0:c03cffe402df 1301 }
slowness 0:c03cffe402df 1302
slowness 0:c03cffe402df 1303
slowness 0:c03cffe402df 1304 /** \brief Get Active Interrupt
slowness 0:c03cffe402df 1305
slowness 0:c03cffe402df 1306 The function reads the active register in NVIC and returns the active bit.
slowness 0:c03cffe402df 1307
slowness 0:c03cffe402df 1308 \param [in] IRQn Interrupt number.
slowness 0:c03cffe402df 1309
slowness 0:c03cffe402df 1310 \return 0 Interrupt status is not active.
slowness 0:c03cffe402df 1311 \return 1 Interrupt status is active.
slowness 0:c03cffe402df 1312 */
slowness 0:c03cffe402df 1313 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
slowness 0:c03cffe402df 1314 {
slowness 0:c03cffe402df 1315 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
slowness 0:c03cffe402df 1316 }
slowness 0:c03cffe402df 1317
slowness 0:c03cffe402df 1318
slowness 0:c03cffe402df 1319 /** \brief Set Interrupt Priority
slowness 0:c03cffe402df 1320
slowness 0:c03cffe402df 1321 The function sets the priority of an interrupt.
slowness 0:c03cffe402df 1322
slowness 0:c03cffe402df 1323 \note The priority cannot be set for every core interrupt.
slowness 0:c03cffe402df 1324
slowness 0:c03cffe402df 1325 \param [in] IRQn Interrupt number.
slowness 0:c03cffe402df 1326 \param [in] priority Priority to set.
slowness 0:c03cffe402df 1327 */
slowness 0:c03cffe402df 1328 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
slowness 0:c03cffe402df 1329 {
slowness 0:c03cffe402df 1330 if(IRQn < 0) {
slowness 0:c03cffe402df 1331 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
slowness 0:c03cffe402df 1332 else {
slowness 0:c03cffe402df 1333 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
slowness 0:c03cffe402df 1334 }
slowness 0:c03cffe402df 1335
slowness 0:c03cffe402df 1336
slowness 0:c03cffe402df 1337 /** \brief Get Interrupt Priority
slowness 0:c03cffe402df 1338
slowness 0:c03cffe402df 1339 The function reads the priority of an interrupt. The interrupt
slowness 0:c03cffe402df 1340 number can be positive to specify an external (device specific)
slowness 0:c03cffe402df 1341 interrupt, or negative to specify an internal (core) interrupt.
slowness 0:c03cffe402df 1342
slowness 0:c03cffe402df 1343
slowness 0:c03cffe402df 1344 \param [in] IRQn Interrupt number.
slowness 0:c03cffe402df 1345 \return Interrupt Priority. Value is aligned automatically to the implemented
slowness 0:c03cffe402df 1346 priority bits of the microcontroller.
slowness 0:c03cffe402df 1347 */
slowness 0:c03cffe402df 1348 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
slowness 0:c03cffe402df 1349 {
slowness 0:c03cffe402df 1350
slowness 0:c03cffe402df 1351 if(IRQn < 0) {
slowness 0:c03cffe402df 1352 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
slowness 0:c03cffe402df 1353 else {
slowness 0:c03cffe402df 1354 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
slowness 0:c03cffe402df 1355 }
slowness 0:c03cffe402df 1356
slowness 0:c03cffe402df 1357
slowness 0:c03cffe402df 1358 /** \brief Encode Priority
slowness 0:c03cffe402df 1359
slowness 0:c03cffe402df 1360 The function encodes the priority for an interrupt with the given priority group,
slowness 0:c03cffe402df 1361 preemptive priority value, and subpriority value.
slowness 0:c03cffe402df 1362 In case of a conflict between priority grouping and available
slowness 0:c03cffe402df 1363 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
slowness 0:c03cffe402df 1364
slowness 0:c03cffe402df 1365 \param [in] PriorityGroup Used priority group.
slowness 0:c03cffe402df 1366 \param [in] PreemptPriority Preemptive priority value (starting from 0).
slowness 0:c03cffe402df 1367 \param [in] SubPriority Subpriority value (starting from 0).
slowness 0:c03cffe402df 1368 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
slowness 0:c03cffe402df 1369 */
slowness 0:c03cffe402df 1370 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
slowness 0:c03cffe402df 1371 {
slowness 0:c03cffe402df 1372 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
slowness 0:c03cffe402df 1373 uint32_t PreemptPriorityBits;
slowness 0:c03cffe402df 1374 uint32_t SubPriorityBits;
slowness 0:c03cffe402df 1375
slowness 0:c03cffe402df 1376 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
slowness 0:c03cffe402df 1377 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
slowness 0:c03cffe402df 1378
slowness 0:c03cffe402df 1379 return (
slowness 0:c03cffe402df 1380 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
slowness 0:c03cffe402df 1381 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
slowness 0:c03cffe402df 1382 );
slowness 0:c03cffe402df 1383 }
slowness 0:c03cffe402df 1384
slowness 0:c03cffe402df 1385
slowness 0:c03cffe402df 1386 /** \brief Decode Priority
slowness 0:c03cffe402df 1387
slowness 0:c03cffe402df 1388 The function decodes an interrupt priority value with a given priority group to
slowness 0:c03cffe402df 1389 preemptive priority value and subpriority value.
slowness 0:c03cffe402df 1390 In case of a conflict between priority grouping and available
slowness 0:c03cffe402df 1391 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
slowness 0:c03cffe402df 1392
slowness 0:c03cffe402df 1393 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
slowness 0:c03cffe402df 1394 \param [in] PriorityGroup Used priority group.
slowness 0:c03cffe402df 1395 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
slowness 0:c03cffe402df 1396 \param [out] pSubPriority Subpriority value (starting from 0).
slowness 0:c03cffe402df 1397 */
slowness 0:c03cffe402df 1398 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
slowness 0:c03cffe402df 1399 {
slowness 0:c03cffe402df 1400 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
slowness 0:c03cffe402df 1401 uint32_t PreemptPriorityBits;
slowness 0:c03cffe402df 1402 uint32_t SubPriorityBits;
slowness 0:c03cffe402df 1403
slowness 0:c03cffe402df 1404 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
slowness 0:c03cffe402df 1405 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
slowness 0:c03cffe402df 1406
slowness 0:c03cffe402df 1407 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
slowness 0:c03cffe402df 1408 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
slowness 0:c03cffe402df 1409 }
slowness 0:c03cffe402df 1410
slowness 0:c03cffe402df 1411
slowness 0:c03cffe402df 1412 /** \brief System Reset
slowness 0:c03cffe402df 1413
slowness 0:c03cffe402df 1414 The function initiates a system reset request to reset the MCU.
slowness 0:c03cffe402df 1415 */
slowness 0:c03cffe402df 1416 __STATIC_INLINE void NVIC_SystemReset(void)
slowness 0:c03cffe402df 1417 {
slowness 0:c03cffe402df 1418 __DSB(); /* Ensure all outstanding memory accesses included
slowness 0:c03cffe402df 1419 buffered write are completed before reset */
slowness 0:c03cffe402df 1420 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
slowness 0:c03cffe402df 1421 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
slowness 0:c03cffe402df 1422 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
slowness 0:c03cffe402df 1423 __DSB(); /* Ensure completion of memory access */
slowness 0:c03cffe402df 1424 while(1); /* wait until reset */
slowness 0:c03cffe402df 1425 }
slowness 0:c03cffe402df 1426
slowness 0:c03cffe402df 1427 /*@} end of CMSIS_Core_NVICFunctions */
slowness 0:c03cffe402df 1428
slowness 0:c03cffe402df 1429
slowness 0:c03cffe402df 1430
slowness 0:c03cffe402df 1431 /* ################################## SysTick function ############################################ */
slowness 0:c03cffe402df 1432 /** \ingroup CMSIS_Core_FunctionInterface
slowness 0:c03cffe402df 1433 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
slowness 0:c03cffe402df 1434 \brief Functions that configure the System.
slowness 0:c03cffe402df 1435 @{
slowness 0:c03cffe402df 1436 */
slowness 0:c03cffe402df 1437
slowness 0:c03cffe402df 1438 #if (__Vendor_SysTickConfig == 0)
slowness 0:c03cffe402df 1439
slowness 0:c03cffe402df 1440 /** \brief System Tick Configuration
slowness 0:c03cffe402df 1441
slowness 0:c03cffe402df 1442 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
slowness 0:c03cffe402df 1443 Counter is in free running mode to generate periodic interrupts.
slowness 0:c03cffe402df 1444
slowness 0:c03cffe402df 1445 \param [in] ticks Number of ticks between two interrupts.
slowness 0:c03cffe402df 1446
slowness 0:c03cffe402df 1447 \return 0 Function succeeded.
slowness 0:c03cffe402df 1448 \return 1 Function failed.
slowness 0:c03cffe402df 1449
slowness 0:c03cffe402df 1450 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
slowness 0:c03cffe402df 1451 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
slowness 0:c03cffe402df 1452 must contain a vendor-specific implementation of this function.
slowness 0:c03cffe402df 1453
slowness 0:c03cffe402df 1454 */
slowness 0:c03cffe402df 1455 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
slowness 0:c03cffe402df 1456 {
slowness 0:c03cffe402df 1457 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
slowness 0:c03cffe402df 1458
slowness 0:c03cffe402df 1459 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
slowness 0:c03cffe402df 1460 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
slowness 0:c03cffe402df 1461 SysTick->VAL = 0; /* Load the SysTick Counter Value */
slowness 0:c03cffe402df 1462 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
slowness 0:c03cffe402df 1463 SysTick_CTRL_TICKINT_Msk |
slowness 0:c03cffe402df 1464 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
slowness 0:c03cffe402df 1465 return (0); /* Function successful */
slowness 0:c03cffe402df 1466 }
slowness 0:c03cffe402df 1467
slowness 0:c03cffe402df 1468 #endif
slowness 0:c03cffe402df 1469
slowness 0:c03cffe402df 1470 /*@} end of CMSIS_Core_SysTickFunctions */
slowness 0:c03cffe402df 1471
slowness 0:c03cffe402df 1472
slowness 0:c03cffe402df 1473
slowness 0:c03cffe402df 1474 /* ##################################### Debug In/Output function ########################################### */
slowness 0:c03cffe402df 1475 /** \ingroup CMSIS_Core_FunctionInterface
slowness 0:c03cffe402df 1476 \defgroup CMSIS_core_DebugFunctions ITM Functions
slowness 0:c03cffe402df 1477 \brief Functions that access the ITM debug interface.
slowness 0:c03cffe402df 1478 @{
slowness 0:c03cffe402df 1479 */
slowness 0:c03cffe402df 1480
slowness 0:c03cffe402df 1481 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
slowness 0:c03cffe402df 1482 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
slowness 0:c03cffe402df 1483
slowness 0:c03cffe402df 1484
slowness 0:c03cffe402df 1485 /** \brief ITM Send Character
slowness 0:c03cffe402df 1486
slowness 0:c03cffe402df 1487 The function transmits a character via the ITM channel 0, and
slowness 0:c03cffe402df 1488 \li Just returns when no debugger is connected that has booked the output.
slowness 0:c03cffe402df 1489 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
slowness 0:c03cffe402df 1490
slowness 0:c03cffe402df 1491 \param [in] ch Character to transmit.
slowness 0:c03cffe402df 1492
slowness 0:c03cffe402df 1493 \returns Character to transmit.
slowness 0:c03cffe402df 1494 */
slowness 0:c03cffe402df 1495 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
slowness 0:c03cffe402df 1496 {
slowness 0:c03cffe402df 1497 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
slowness 0:c03cffe402df 1498 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
slowness 0:c03cffe402df 1499 {
slowness 0:c03cffe402df 1500 while (ITM->PORT[0].u32 == 0);
slowness 0:c03cffe402df 1501 ITM->PORT[0].u8 = (uint8_t) ch;
slowness 0:c03cffe402df 1502 }
slowness 0:c03cffe402df 1503 return (ch);
slowness 0:c03cffe402df 1504 }
slowness 0:c03cffe402df 1505
slowness 0:c03cffe402df 1506
slowness 0:c03cffe402df 1507 /** \brief ITM Receive Character
slowness 0:c03cffe402df 1508
slowness 0:c03cffe402df 1509 The function inputs a character via the external variable \ref ITM_RxBuffer.
slowness 0:c03cffe402df 1510
slowness 0:c03cffe402df 1511 \return Received character.
slowness 0:c03cffe402df 1512 \return -1 No character pending.
slowness 0:c03cffe402df 1513 */
slowness 0:c03cffe402df 1514 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
slowness 0:c03cffe402df 1515 int32_t ch = -1; /* no character available */
slowness 0:c03cffe402df 1516
slowness 0:c03cffe402df 1517 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
slowness 0:c03cffe402df 1518 ch = ITM_RxBuffer;
slowness 0:c03cffe402df 1519 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
slowness 0:c03cffe402df 1520 }
slowness 0:c03cffe402df 1521
slowness 0:c03cffe402df 1522 return (ch);
slowness 0:c03cffe402df 1523 }
slowness 0:c03cffe402df 1524
slowness 0:c03cffe402df 1525
slowness 0:c03cffe402df 1526 /** \brief ITM Check Character
slowness 0:c03cffe402df 1527
slowness 0:c03cffe402df 1528 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
slowness 0:c03cffe402df 1529
slowness 0:c03cffe402df 1530 \return 0 No character available.
slowness 0:c03cffe402df 1531 \return 1 Character available.
slowness 0:c03cffe402df 1532 */
slowness 0:c03cffe402df 1533 __STATIC_INLINE int32_t ITM_CheckChar (void) {
slowness 0:c03cffe402df 1534
slowness 0:c03cffe402df 1535 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
slowness 0:c03cffe402df 1536 return (0); /* no character available */
slowness 0:c03cffe402df 1537 } else {
slowness 0:c03cffe402df 1538 return (1); /* character available */
slowness 0:c03cffe402df 1539 }
slowness 0:c03cffe402df 1540 }
slowness 0:c03cffe402df 1541
slowness 0:c03cffe402df 1542 /*@} end of CMSIS_core_DebugFunctions */
slowness 0:c03cffe402df 1543
slowness 0:c03cffe402df 1544 #endif /* __CORE_CM3_H_DEPENDANT */
slowness 0:c03cffe402df 1545
slowness 0:c03cffe402df 1546 #endif /* __CMSIS_GENERIC */
slowness 0:c03cffe402df 1547
slowness 0:c03cffe402df 1548 #ifdef __cplusplus
slowness 0:c03cffe402df 1549 }
slowness 0:c03cffe402df 1550 #endif