clement lignie / configure_ax12_test_bras_module

config AX12

Fork of configure_ax12_test_bras_module by CRAC Team

mbed/LPC1768/LPC17xx.h@2:91b6646ea994, 2017-02-01 (annotated)

Committer:
clementlignie
Date:
Wed Feb 01 13:42:30 2017 +0000
Revision:
2:91b6646ea994
Parent:
0:c03cffe402df 
config AX12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
slowness 0:c03cffe402df 1 /**************************************************************************//**
slowness 0:c03cffe402df 2 * @file LPC17xx.h
slowness 0:c03cffe402df 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
slowness 0:c03cffe402df 4 * NXP LPC17xx Device Series
slowness 0:c03cffe402df 5 * @version: V1.09
slowness 0:c03cffe402df 6 * @date: 17. March 2010
slowness 0:c03cffe402df 7
slowness 0:c03cffe402df 8 *
slowness 0:c03cffe402df 9 * @note
slowness 0:c03cffe402df 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
slowness 0:c03cffe402df 11 *
slowness 0:c03cffe402df 12 * @par
slowness 0:c03cffe402df 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
slowness 0:c03cffe402df 14 * processor based microcontrollers. This file can be freely distributed
slowness 0:c03cffe402df 15 * within development tools that are supporting such ARM based processors.
slowness 0:c03cffe402df 16 *
slowness 0:c03cffe402df 17 * @par
slowness 0:c03cffe402df 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
slowness 0:c03cffe402df 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
slowness 0:c03cffe402df 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
slowness 0:c03cffe402df 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
slowness 0:c03cffe402df 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
slowness 0:c03cffe402df 23 *
slowness 0:c03cffe402df 24 ******************************************************************************/
slowness 0:c03cffe402df 25
slowness 0:c03cffe402df 26
slowness 0:c03cffe402df 27 #ifndef __LPC17xx_H__
slowness 0:c03cffe402df 28 #define __LPC17xx_H__
slowness 0:c03cffe402df 29
slowness 0:c03cffe402df 30 /*
slowness 0:c03cffe402df 31 * ==========================================================================
slowness 0:c03cffe402df 32 * ---------- Interrupt Number Definition -----------------------------------
slowness 0:c03cffe402df 33 * ==========================================================================
slowness 0:c03cffe402df 34 */
slowness 0:c03cffe402df 35
slowness 0:c03cffe402df 36 typedef enum IRQn
slowness 0:c03cffe402df 37 {
slowness 0:c03cffe402df 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
slowness 0:c03cffe402df 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
slowness 0:c03cffe402df 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
slowness 0:c03cffe402df 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
slowness 0:c03cffe402df 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
slowness 0:c03cffe402df 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
slowness 0:c03cffe402df 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
slowness 0:c03cffe402df 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
slowness 0:c03cffe402df 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
slowness 0:c03cffe402df 47
slowness 0:c03cffe402df 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
slowness 0:c03cffe402df 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
slowness 0:c03cffe402df 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
slowness 0:c03cffe402df 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
slowness 0:c03cffe402df 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
slowness 0:c03cffe402df 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
slowness 0:c03cffe402df 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
slowness 0:c03cffe402df 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
slowness 0:c03cffe402df 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
slowness 0:c03cffe402df 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
slowness 0:c03cffe402df 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
slowness 0:c03cffe402df 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
slowness 0:c03cffe402df 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
slowness 0:c03cffe402df 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
slowness 0:c03cffe402df 62 SPI_IRQn = 13, /*!< SPI Interrupt */
slowness 0:c03cffe402df 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
slowness 0:c03cffe402df 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
slowness 0:c03cffe402df 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
slowness 0:c03cffe402df 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
slowness 0:c03cffe402df 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
slowness 0:c03cffe402df 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
slowness 0:c03cffe402df 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
slowness 0:c03cffe402df 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
slowness 0:c03cffe402df 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
slowness 0:c03cffe402df 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
slowness 0:c03cffe402df 73 USB_IRQn = 24, /*!< USB Interrupt */
slowness 0:c03cffe402df 74 CAN_IRQn = 25, /*!< CAN Interrupt */
slowness 0:c03cffe402df 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
slowness 0:c03cffe402df 76 I2S_IRQn = 27, /*!< I2S Interrupt */
slowness 0:c03cffe402df 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
slowness 0:c03cffe402df 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
slowness 0:c03cffe402df 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
slowness 0:c03cffe402df 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
slowness 0:c03cffe402df 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
slowness 0:c03cffe402df 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
slowness 0:c03cffe402df 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
slowness 0:c03cffe402df 84 } IRQn_Type;
slowness 0:c03cffe402df 85
slowness 0:c03cffe402df 86
slowness 0:c03cffe402df 87 /*
slowness 0:c03cffe402df 88 * ==========================================================================
slowness 0:c03cffe402df 89 * ----------- Processor and Core Peripheral Section ------------------------
slowness 0:c03cffe402df 90 * ==========================================================================
slowness 0:c03cffe402df 91 */
slowness 0:c03cffe402df 92
slowness 0:c03cffe402df 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
slowness 0:c03cffe402df 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
slowness 0:c03cffe402df 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
slowness 0:c03cffe402df 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
slowness 0:c03cffe402df 97
slowness 0:c03cffe402df 98
slowness 0:c03cffe402df 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
slowness 0:c03cffe402df 100 #include "system_LPC17xx.h" /* System Header */
slowness 0:c03cffe402df 101
slowness 0:c03cffe402df 102
slowness 0:c03cffe402df 103 /******************************************************************************/
slowness 0:c03cffe402df 104 /* Device Specific Peripheral registers structures */
slowness 0:c03cffe402df 105 /******************************************************************************/
slowness 0:c03cffe402df 106
slowness 0:c03cffe402df 107 #if defined ( __CC_ARM )
slowness 0:c03cffe402df 108 #pragma anon_unions
slowness 0:c03cffe402df 109 #endif
slowness 0:c03cffe402df 110
slowness 0:c03cffe402df 111 /*------------- System Control (SC) ------------------------------------------*/
slowness 0:c03cffe402df 112 typedef struct
slowness 0:c03cffe402df 113 {
slowness 0:c03cffe402df 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
slowness 0:c03cffe402df 115 uint32_t RESERVED0[31];
slowness 0:c03cffe402df 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
slowness 0:c03cffe402df 117 __IO uint32_t PLL0CFG;
slowness 0:c03cffe402df 118 __I uint32_t PLL0STAT;
slowness 0:c03cffe402df 119 __O uint32_t PLL0FEED;
slowness 0:c03cffe402df 120 uint32_t RESERVED1[4];
slowness 0:c03cffe402df 121 __IO uint32_t PLL1CON;
slowness 0:c03cffe402df 122 __IO uint32_t PLL1CFG;
slowness 0:c03cffe402df 123 __I uint32_t PLL1STAT;
slowness 0:c03cffe402df 124 __O uint32_t PLL1FEED;
slowness 0:c03cffe402df 125 uint32_t RESERVED2[4];
slowness 0:c03cffe402df 126 __IO uint32_t PCON;
slowness 0:c03cffe402df 127 __IO uint32_t PCONP;
slowness 0:c03cffe402df 128 uint32_t RESERVED3[15];
slowness 0:c03cffe402df 129 __IO uint32_t CCLKCFG;
slowness 0:c03cffe402df 130 __IO uint32_t USBCLKCFG;
slowness 0:c03cffe402df 131 __IO uint32_t CLKSRCSEL;
slowness 0:c03cffe402df 132 __IO uint32_t CANSLEEPCLR;
slowness 0:c03cffe402df 133 __IO uint32_t CANWAKEFLAGS;
slowness 0:c03cffe402df 134 uint32_t RESERVED4[10];
slowness 0:c03cffe402df 135 __IO uint32_t EXTINT; /* External Interrupts */
slowness 0:c03cffe402df 136 uint32_t RESERVED5;
slowness 0:c03cffe402df 137 __IO uint32_t EXTMODE;
slowness 0:c03cffe402df 138 __IO uint32_t EXTPOLAR;
slowness 0:c03cffe402df 139 uint32_t RESERVED6[12];
slowness 0:c03cffe402df 140 __IO uint32_t RSID; /* Reset */
slowness 0:c03cffe402df 141 uint32_t RESERVED7[7];
slowness 0:c03cffe402df 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
slowness 0:c03cffe402df 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
slowness 0:c03cffe402df 144 __IO uint32_t PCLKSEL0;
slowness 0:c03cffe402df 145 __IO uint32_t PCLKSEL1;
slowness 0:c03cffe402df 146 uint32_t RESERVED8[4];
slowness 0:c03cffe402df 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
slowness 0:c03cffe402df 148 __IO uint32_t DMAREQSEL;
slowness 0:c03cffe402df 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
slowness 0:c03cffe402df 150 } LPC_SC_TypeDef;
slowness 0:c03cffe402df 151
slowness 0:c03cffe402df 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
slowness 0:c03cffe402df 153 typedef struct
slowness 0:c03cffe402df 154 {
slowness 0:c03cffe402df 155 __IO uint32_t PINSEL0;
slowness 0:c03cffe402df 156 __IO uint32_t PINSEL1;
slowness 0:c03cffe402df 157 __IO uint32_t PINSEL2;
slowness 0:c03cffe402df 158 __IO uint32_t PINSEL3;
slowness 0:c03cffe402df 159 __IO uint32_t PINSEL4;
slowness 0:c03cffe402df 160 __IO uint32_t PINSEL5;
slowness 0:c03cffe402df 161 __IO uint32_t PINSEL6;
slowness 0:c03cffe402df 162 __IO uint32_t PINSEL7;
slowness 0:c03cffe402df 163 __IO uint32_t PINSEL8;
slowness 0:c03cffe402df 164 __IO uint32_t PINSEL9;
slowness 0:c03cffe402df 165 __IO uint32_t PINSEL10;
slowness 0:c03cffe402df 166 uint32_t RESERVED0[5];
slowness 0:c03cffe402df 167 __IO uint32_t PINMODE0;
slowness 0:c03cffe402df 168 __IO uint32_t PINMODE1;
slowness 0:c03cffe402df 169 __IO uint32_t PINMODE2;
slowness 0:c03cffe402df 170 __IO uint32_t PINMODE3;
slowness 0:c03cffe402df 171 __IO uint32_t PINMODE4;
slowness 0:c03cffe402df 172 __IO uint32_t PINMODE5;
slowness 0:c03cffe402df 173 __IO uint32_t PINMODE6;
slowness 0:c03cffe402df 174 __IO uint32_t PINMODE7;
slowness 0:c03cffe402df 175 __IO uint32_t PINMODE8;
slowness 0:c03cffe402df 176 __IO uint32_t PINMODE9;
slowness 0:c03cffe402df 177 __IO uint32_t PINMODE_OD0;
slowness 0:c03cffe402df 178 __IO uint32_t PINMODE_OD1;
slowness 0:c03cffe402df 179 __IO uint32_t PINMODE_OD2;
slowness 0:c03cffe402df 180 __IO uint32_t PINMODE_OD3;
slowness 0:c03cffe402df 181 __IO uint32_t PINMODE_OD4;
slowness 0:c03cffe402df 182 __IO uint32_t I2CPADCFG;
slowness 0:c03cffe402df 183 } LPC_PINCON_TypeDef;
slowness 0:c03cffe402df 184
slowness 0:c03cffe402df 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
slowness 0:c03cffe402df 186 typedef struct
slowness 0:c03cffe402df 187 {
slowness 0:c03cffe402df 188 union {
slowness 0:c03cffe402df 189 __IO uint32_t FIODIR;
slowness 0:c03cffe402df 190 struct {
slowness 0:c03cffe402df 191 __IO uint16_t FIODIRL;
slowness 0:c03cffe402df 192 __IO uint16_t FIODIRH;
slowness 0:c03cffe402df 193 };
slowness 0:c03cffe402df 194 struct {
slowness 0:c03cffe402df 195 __IO uint8_t FIODIR0;
slowness 0:c03cffe402df 196 __IO uint8_t FIODIR1;
slowness 0:c03cffe402df 197 __IO uint8_t FIODIR2;
slowness 0:c03cffe402df 198 __IO uint8_t FIODIR3;
slowness 0:c03cffe402df 199 };
slowness 0:c03cffe402df 200 };
slowness 0:c03cffe402df 201 uint32_t RESERVED0[3];
slowness 0:c03cffe402df 202 union {
slowness 0:c03cffe402df 203 __IO uint32_t FIOMASK;
slowness 0:c03cffe402df 204 struct {
slowness 0:c03cffe402df 205 __IO uint16_t FIOMASKL;
slowness 0:c03cffe402df 206 __IO uint16_t FIOMASKH;
slowness 0:c03cffe402df 207 };
slowness 0:c03cffe402df 208 struct {
slowness 0:c03cffe402df 209 __IO uint8_t FIOMASK0;
slowness 0:c03cffe402df 210 __IO uint8_t FIOMASK1;
slowness 0:c03cffe402df 211 __IO uint8_t FIOMASK2;
slowness 0:c03cffe402df 212 __IO uint8_t FIOMASK3;
slowness 0:c03cffe402df 213 };
slowness 0:c03cffe402df 214 };
slowness 0:c03cffe402df 215 union {
slowness 0:c03cffe402df 216 __IO uint32_t FIOPIN;
slowness 0:c03cffe402df 217 struct {
slowness 0:c03cffe402df 218 __IO uint16_t FIOPINL;
slowness 0:c03cffe402df 219 __IO uint16_t FIOPINH;
slowness 0:c03cffe402df 220 };
slowness 0:c03cffe402df 221 struct {
slowness 0:c03cffe402df 222 __IO uint8_t FIOPIN0;
slowness 0:c03cffe402df 223 __IO uint8_t FIOPIN1;
slowness 0:c03cffe402df 224 __IO uint8_t FIOPIN2;
slowness 0:c03cffe402df 225 __IO uint8_t FIOPIN3;
slowness 0:c03cffe402df 226 };
slowness 0:c03cffe402df 227 };
slowness 0:c03cffe402df 228 union {
slowness 0:c03cffe402df 229 __IO uint32_t FIOSET;
slowness 0:c03cffe402df 230 struct {
slowness 0:c03cffe402df 231 __IO uint16_t FIOSETL;
slowness 0:c03cffe402df 232 __IO uint16_t FIOSETH;
slowness 0:c03cffe402df 233 };
slowness 0:c03cffe402df 234 struct {
slowness 0:c03cffe402df 235 __IO uint8_t FIOSET0;
slowness 0:c03cffe402df 236 __IO uint8_t FIOSET1;
slowness 0:c03cffe402df 237 __IO uint8_t FIOSET2;
slowness 0:c03cffe402df 238 __IO uint8_t FIOSET3;
slowness 0:c03cffe402df 239 };
slowness 0:c03cffe402df 240 };
slowness 0:c03cffe402df 241 union {
slowness 0:c03cffe402df 242 __O uint32_t FIOCLR;
slowness 0:c03cffe402df 243 struct {
slowness 0:c03cffe402df 244 __O uint16_t FIOCLRL;
slowness 0:c03cffe402df 245 __O uint16_t FIOCLRH;
slowness 0:c03cffe402df 246 };
slowness 0:c03cffe402df 247 struct {
slowness 0:c03cffe402df 248 __O uint8_t FIOCLR0;
slowness 0:c03cffe402df 249 __O uint8_t FIOCLR1;
slowness 0:c03cffe402df 250 __O uint8_t FIOCLR2;
slowness 0:c03cffe402df 251 __O uint8_t FIOCLR3;
slowness 0:c03cffe402df 252 };
slowness 0:c03cffe402df 253 };
slowness 0:c03cffe402df 254 } LPC_GPIO_TypeDef;
slowness 0:c03cffe402df 255
slowness 0:c03cffe402df 256 typedef struct
slowness 0:c03cffe402df 257 {
slowness 0:c03cffe402df 258 __I uint32_t IntStatus;
slowness 0:c03cffe402df 259 __I uint32_t IO0IntStatR;
slowness 0:c03cffe402df 260 __I uint32_t IO0IntStatF;
slowness 0:c03cffe402df 261 __O uint32_t IO0IntClr;
slowness 0:c03cffe402df 262 __IO uint32_t IO0IntEnR;
slowness 0:c03cffe402df 263 __IO uint32_t IO0IntEnF;
slowness 0:c03cffe402df 264 uint32_t RESERVED0[3];
slowness 0:c03cffe402df 265 __I uint32_t IO2IntStatR;
slowness 0:c03cffe402df 266 __I uint32_t IO2IntStatF;
slowness 0:c03cffe402df 267 __O uint32_t IO2IntClr;
slowness 0:c03cffe402df 268 __IO uint32_t IO2IntEnR;
slowness 0:c03cffe402df 269 __IO uint32_t IO2IntEnF;
slowness 0:c03cffe402df 270 } LPC_GPIOINT_TypeDef;
slowness 0:c03cffe402df 271
slowness 0:c03cffe402df 272 /*------------- Timer (TIM) --------------------------------------------------*/
slowness 0:c03cffe402df 273 typedef struct
slowness 0:c03cffe402df 274 {
slowness 0:c03cffe402df 275 __IO uint32_t IR;
slowness 0:c03cffe402df 276 __IO uint32_t TCR;
slowness 0:c03cffe402df 277 __IO uint32_t TC;
slowness 0:c03cffe402df 278 __IO uint32_t PR;
slowness 0:c03cffe402df 279 __IO uint32_t PC;
slowness 0:c03cffe402df 280 __IO uint32_t MCR;
slowness 0:c03cffe402df 281 __IO uint32_t MR0;
slowness 0:c03cffe402df 282 __IO uint32_t MR1;
slowness 0:c03cffe402df 283 __IO uint32_t MR2;
slowness 0:c03cffe402df 284 __IO uint32_t MR3;
slowness 0:c03cffe402df 285 __IO uint32_t CCR;
slowness 0:c03cffe402df 286 __I uint32_t CR0;
slowness 0:c03cffe402df 287 __I uint32_t CR1;
slowness 0:c03cffe402df 288 uint32_t RESERVED0[2];
slowness 0:c03cffe402df 289 __IO uint32_t EMR;
slowness 0:c03cffe402df 290 uint32_t RESERVED1[12];
slowness 0:c03cffe402df 291 __IO uint32_t CTCR;
slowness 0:c03cffe402df 292 } LPC_TIM_TypeDef;
slowness 0:c03cffe402df 293
slowness 0:c03cffe402df 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
slowness 0:c03cffe402df 295 typedef struct
slowness 0:c03cffe402df 296 {
slowness 0:c03cffe402df 297 __IO uint32_t IR;
slowness 0:c03cffe402df 298 __IO uint32_t TCR;
slowness 0:c03cffe402df 299 __IO uint32_t TC;
slowness 0:c03cffe402df 300 __IO uint32_t PR;
slowness 0:c03cffe402df 301 __IO uint32_t PC;
slowness 0:c03cffe402df 302 __IO uint32_t MCR;
slowness 0:c03cffe402df 303 __IO uint32_t MR0;
slowness 0:c03cffe402df 304 __IO uint32_t MR1;
slowness 0:c03cffe402df 305 __IO uint32_t MR2;
slowness 0:c03cffe402df 306 __IO uint32_t MR3;
slowness 0:c03cffe402df 307 __IO uint32_t CCR;
slowness 0:c03cffe402df 308 __I uint32_t CR0;
slowness 0:c03cffe402df 309 __I uint32_t CR1;
slowness 0:c03cffe402df 310 __I uint32_t CR2;
slowness 0:c03cffe402df 311 __I uint32_t CR3;
slowness 0:c03cffe402df 312 uint32_t RESERVED0;
slowness 0:c03cffe402df 313 __IO uint32_t MR4;
slowness 0:c03cffe402df 314 __IO uint32_t MR5;
slowness 0:c03cffe402df 315 __IO uint32_t MR6;
slowness 0:c03cffe402df 316 __IO uint32_t PCR;
slowness 0:c03cffe402df 317 __IO uint32_t LER;
slowness 0:c03cffe402df 318 uint32_t RESERVED1[7];
slowness 0:c03cffe402df 319 __IO uint32_t CTCR;
slowness 0:c03cffe402df 320 } LPC_PWM_TypeDef;
slowness 0:c03cffe402df 321
slowness 0:c03cffe402df 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
slowness 0:c03cffe402df 323 typedef struct
slowness 0:c03cffe402df 324 {
slowness 0:c03cffe402df 325 union {
slowness 0:c03cffe402df 326 __I uint8_t RBR;
slowness 0:c03cffe402df 327 __O uint8_t THR;
slowness 0:c03cffe402df 328 __IO uint8_t DLL;
slowness 0:c03cffe402df 329 uint32_t RESERVED0;
slowness 0:c03cffe402df 330 };
slowness 0:c03cffe402df 331 union {
slowness 0:c03cffe402df 332 __IO uint8_t DLM;
slowness 0:c03cffe402df 333 __IO uint32_t IER;
slowness 0:c03cffe402df 334 };
slowness 0:c03cffe402df 335 union {
slowness 0:c03cffe402df 336 __I uint32_t IIR;
slowness 0:c03cffe402df 337 __O uint8_t FCR;
slowness 0:c03cffe402df 338 };
slowness 0:c03cffe402df 339 __IO uint8_t LCR;
slowness 0:c03cffe402df 340 uint8_t RESERVED1[7];
slowness 0:c03cffe402df 341 __I uint8_t LSR;
slowness 0:c03cffe402df 342 uint8_t RESERVED2[7];
slowness 0:c03cffe402df 343 __IO uint8_t SCR;
slowness 0:c03cffe402df 344 uint8_t RESERVED3[3];
slowness 0:c03cffe402df 345 __IO uint32_t ACR;
slowness 0:c03cffe402df 346 __IO uint8_t ICR;
slowness 0:c03cffe402df 347 uint8_t RESERVED4[3];
slowness 0:c03cffe402df 348 __IO uint8_t FDR;
slowness 0:c03cffe402df 349 uint8_t RESERVED5[7];
slowness 0:c03cffe402df 350 __IO uint8_t TER;
slowness 0:c03cffe402df 351 uint8_t RESERVED6[39];
slowness 0:c03cffe402df 352 __IO uint32_t FIFOLVL;
slowness 0:c03cffe402df 353 } LPC_UART_TypeDef;
slowness 0:c03cffe402df 354
slowness 0:c03cffe402df 355 typedef struct
slowness 0:c03cffe402df 356 {
slowness 0:c03cffe402df 357 union {
slowness 0:c03cffe402df 358 __I uint8_t RBR;
slowness 0:c03cffe402df 359 __O uint8_t THR;
slowness 0:c03cffe402df 360 __IO uint8_t DLL;
slowness 0:c03cffe402df 361 uint32_t RESERVED0;
slowness 0:c03cffe402df 362 };
slowness 0:c03cffe402df 363 union {
slowness 0:c03cffe402df 364 __IO uint8_t DLM;
slowness 0:c03cffe402df 365 __IO uint32_t IER;
slowness 0:c03cffe402df 366 };
slowness 0:c03cffe402df 367 union {
slowness 0:c03cffe402df 368 __I uint32_t IIR;
slowness 0:c03cffe402df 369 __O uint8_t FCR;
slowness 0:c03cffe402df 370 };
slowness 0:c03cffe402df 371 __IO uint8_t LCR;
slowness 0:c03cffe402df 372 uint8_t RESERVED1[7];
slowness 0:c03cffe402df 373 __I uint8_t LSR;
slowness 0:c03cffe402df 374 uint8_t RESERVED2[7];
slowness 0:c03cffe402df 375 __IO uint8_t SCR;
slowness 0:c03cffe402df 376 uint8_t RESERVED3[3];
slowness 0:c03cffe402df 377 __IO uint32_t ACR;
slowness 0:c03cffe402df 378 __IO uint8_t ICR;
slowness 0:c03cffe402df 379 uint8_t RESERVED4[3];
slowness 0:c03cffe402df 380 __IO uint8_t FDR;
slowness 0:c03cffe402df 381 uint8_t RESERVED5[7];
slowness 0:c03cffe402df 382 __IO uint8_t TER;
slowness 0:c03cffe402df 383 uint8_t RESERVED6[39];
slowness 0:c03cffe402df 384 __IO uint32_t FIFOLVL;
slowness 0:c03cffe402df 385 } LPC_UART0_TypeDef;
slowness 0:c03cffe402df 386
slowness 0:c03cffe402df 387 typedef struct
slowness 0:c03cffe402df 388 {
slowness 0:c03cffe402df 389 union {
slowness 0:c03cffe402df 390 __I uint8_t RBR;
slowness 0:c03cffe402df 391 __O uint8_t THR;
slowness 0:c03cffe402df 392 __IO uint8_t DLL;
slowness 0:c03cffe402df 393 uint32_t RESERVED0;
slowness 0:c03cffe402df 394 };
slowness 0:c03cffe402df 395 union {
slowness 0:c03cffe402df 396 __IO uint8_t DLM;
slowness 0:c03cffe402df 397 __IO uint32_t IER;
slowness 0:c03cffe402df 398 };
slowness 0:c03cffe402df 399 union {
slowness 0:c03cffe402df 400 __I uint32_t IIR;
slowness 0:c03cffe402df 401 __O uint8_t FCR;
slowness 0:c03cffe402df 402 };
slowness 0:c03cffe402df 403 __IO uint8_t LCR;
slowness 0:c03cffe402df 404 uint8_t RESERVED1[3];
slowness 0:c03cffe402df 405 __IO uint8_t MCR;
slowness 0:c03cffe402df 406 uint8_t RESERVED2[3];
slowness 0:c03cffe402df 407 __I uint8_t LSR;
slowness 0:c03cffe402df 408 uint8_t RESERVED3[3];
slowness 0:c03cffe402df 409 __I uint8_t MSR;
slowness 0:c03cffe402df 410 uint8_t RESERVED4[3];
slowness 0:c03cffe402df 411 __IO uint8_t SCR;
slowness 0:c03cffe402df 412 uint8_t RESERVED5[3];
slowness 0:c03cffe402df 413 __IO uint32_t ACR;
slowness 0:c03cffe402df 414 uint32_t RESERVED6;
slowness 0:c03cffe402df 415 __IO uint32_t FDR;
slowness 0:c03cffe402df 416 uint32_t RESERVED7;
slowness 0:c03cffe402df 417 __IO uint8_t TER;
slowness 0:c03cffe402df 418 uint8_t RESERVED8[27];
slowness 0:c03cffe402df 419 __IO uint8_t RS485CTRL;
slowness 0:c03cffe402df 420 uint8_t RESERVED9[3];
slowness 0:c03cffe402df 421 __IO uint8_t ADRMATCH;
slowness 0:c03cffe402df 422 uint8_t RESERVED10[3];
slowness 0:c03cffe402df 423 __IO uint8_t RS485DLY;
slowness 0:c03cffe402df 424 uint8_t RESERVED11[3];
slowness 0:c03cffe402df 425 __IO uint32_t FIFOLVL;
slowness 0:c03cffe402df 426 } LPC_UART1_TypeDef;
slowness 0:c03cffe402df 427
slowness 0:c03cffe402df 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
slowness 0:c03cffe402df 429 typedef struct
slowness 0:c03cffe402df 430 {
slowness 0:c03cffe402df 431 __IO uint32_t SPCR;
slowness 0:c03cffe402df 432 __I uint32_t SPSR;
slowness 0:c03cffe402df 433 __IO uint32_t SPDR;
slowness 0:c03cffe402df 434 __IO uint32_t SPCCR;
slowness 0:c03cffe402df 435 uint32_t RESERVED0[3];
slowness 0:c03cffe402df 436 __IO uint32_t SPINT;
slowness 0:c03cffe402df 437 } LPC_SPI_TypeDef;
slowness 0:c03cffe402df 438
slowness 0:c03cffe402df 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
slowness 0:c03cffe402df 440 typedef struct
slowness 0:c03cffe402df 441 {
slowness 0:c03cffe402df 442 __IO uint32_t CR0;
slowness 0:c03cffe402df 443 __IO uint32_t CR1;
slowness 0:c03cffe402df 444 __IO uint32_t DR;
slowness 0:c03cffe402df 445 __I uint32_t SR;
slowness 0:c03cffe402df 446 __IO uint32_t CPSR;
slowness 0:c03cffe402df 447 __IO uint32_t IMSC;
slowness 0:c03cffe402df 448 __IO uint32_t RIS;
slowness 0:c03cffe402df 449 __IO uint32_t MIS;
slowness 0:c03cffe402df 450 __IO uint32_t ICR;
slowness 0:c03cffe402df 451 __IO uint32_t DMACR;
slowness 0:c03cffe402df 452 } LPC_SSP_TypeDef;
slowness 0:c03cffe402df 453
slowness 0:c03cffe402df 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
slowness 0:c03cffe402df 455 typedef struct
slowness 0:c03cffe402df 456 {
slowness 0:c03cffe402df 457 __IO uint32_t I2CONSET;
slowness 0:c03cffe402df 458 __I uint32_t I2STAT;
slowness 0:c03cffe402df 459 __IO uint32_t I2DAT;
slowness 0:c03cffe402df 460 __IO uint32_t I2ADR0;
slowness 0:c03cffe402df 461 __IO uint32_t I2SCLH;
slowness 0:c03cffe402df 462 __IO uint32_t I2SCLL;
slowness 0:c03cffe402df 463 __O uint32_t I2CONCLR;
slowness 0:c03cffe402df 464 __IO uint32_t MMCTRL;
slowness 0:c03cffe402df 465 __IO uint32_t I2ADR1;
slowness 0:c03cffe402df 466 __IO uint32_t I2ADR2;
slowness 0:c03cffe402df 467 __IO uint32_t I2ADR3;
slowness 0:c03cffe402df 468 __I uint32_t I2DATA_BUFFER;
slowness 0:c03cffe402df 469 __IO uint32_t I2MASK0;
slowness 0:c03cffe402df 470 __IO uint32_t I2MASK1;
slowness 0:c03cffe402df 471 __IO uint32_t I2MASK2;
slowness 0:c03cffe402df 472 __IO uint32_t I2MASK3;
slowness 0:c03cffe402df 473 } LPC_I2C_TypeDef;
slowness 0:c03cffe402df 474
slowness 0:c03cffe402df 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
slowness 0:c03cffe402df 476 typedef struct
slowness 0:c03cffe402df 477 {
slowness 0:c03cffe402df 478 __IO uint32_t I2SDAO;
slowness 0:c03cffe402df 479 __IO uint32_t I2SDAI;
slowness 0:c03cffe402df 480 __O uint32_t I2STXFIFO;
slowness 0:c03cffe402df 481 __I uint32_t I2SRXFIFO;
slowness 0:c03cffe402df 482 __I uint32_t I2SSTATE;
slowness 0:c03cffe402df 483 __IO uint32_t I2SDMA1;
slowness 0:c03cffe402df 484 __IO uint32_t I2SDMA2;
slowness 0:c03cffe402df 485 __IO uint32_t I2SIRQ;
slowness 0:c03cffe402df 486 __IO uint32_t I2STXRATE;
slowness 0:c03cffe402df 487 __IO uint32_t I2SRXRATE;
slowness 0:c03cffe402df 488 __IO uint32_t I2STXBITRATE;
slowness 0:c03cffe402df 489 __IO uint32_t I2SRXBITRATE;
slowness 0:c03cffe402df 490 __IO uint32_t I2STXMODE;
slowness 0:c03cffe402df 491 __IO uint32_t I2SRXMODE;
slowness 0:c03cffe402df 492 } LPC_I2S_TypeDef;
slowness 0:c03cffe402df 493
slowness 0:c03cffe402df 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
slowness 0:c03cffe402df 495 typedef struct
slowness 0:c03cffe402df 496 {
slowness 0:c03cffe402df 497 __IO uint32_t RICOMPVAL;
slowness 0:c03cffe402df 498 __IO uint32_t RIMASK;
slowness 0:c03cffe402df 499 __IO uint8_t RICTRL;
slowness 0:c03cffe402df 500 uint8_t RESERVED0[3];
slowness 0:c03cffe402df 501 __IO uint32_t RICOUNTER;
slowness 0:c03cffe402df 502 } LPC_RIT_TypeDef;
slowness 0:c03cffe402df 503
slowness 0:c03cffe402df 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
slowness 0:c03cffe402df 505 typedef struct
slowness 0:c03cffe402df 506 {
slowness 0:c03cffe402df 507 __IO uint8_t ILR;
slowness 0:c03cffe402df 508 uint8_t RESERVED0[7];
slowness 0:c03cffe402df 509 __IO uint8_t CCR;
slowness 0:c03cffe402df 510 uint8_t RESERVED1[3];
slowness 0:c03cffe402df 511 __IO uint8_t CIIR;
slowness 0:c03cffe402df 512 uint8_t RESERVED2[3];
slowness 0:c03cffe402df 513 __IO uint8_t AMR;
slowness 0:c03cffe402df 514 uint8_t RESERVED3[3];
slowness 0:c03cffe402df 515 __I uint32_t CTIME0;
slowness 0:c03cffe402df 516 __I uint32_t CTIME1;
slowness 0:c03cffe402df 517 __I uint32_t CTIME2;
slowness 0:c03cffe402df 518 __IO uint8_t SEC;
slowness 0:c03cffe402df 519 uint8_t RESERVED4[3];
slowness 0:c03cffe402df 520 __IO uint8_t MIN;
slowness 0:c03cffe402df 521 uint8_t RESERVED5[3];
slowness 0:c03cffe402df 522 __IO uint8_t HOUR;
slowness 0:c03cffe402df 523 uint8_t RESERVED6[3];
slowness 0:c03cffe402df 524 __IO uint8_t DOM;
slowness 0:c03cffe402df 525 uint8_t RESERVED7[3];
slowness 0:c03cffe402df 526 __IO uint8_t DOW;
slowness 0:c03cffe402df 527 uint8_t RESERVED8[3];
slowness 0:c03cffe402df 528 __IO uint16_t DOY;
slowness 0:c03cffe402df 529 uint16_t RESERVED9;
slowness 0:c03cffe402df 530 __IO uint8_t MONTH;
slowness 0:c03cffe402df 531 uint8_t RESERVED10[3];
slowness 0:c03cffe402df 532 __IO uint16_t YEAR;
slowness 0:c03cffe402df 533 uint16_t RESERVED11;
slowness 0:c03cffe402df 534 __IO uint32_t CALIBRATION;
slowness 0:c03cffe402df 535 __IO uint32_t GPREG0;
slowness 0:c03cffe402df 536 __IO uint32_t GPREG1;
slowness 0:c03cffe402df 537 __IO uint32_t GPREG2;
slowness 0:c03cffe402df 538 __IO uint32_t GPREG3;
slowness 0:c03cffe402df 539 __IO uint32_t GPREG4;
slowness 0:c03cffe402df 540 __IO uint8_t RTC_AUXEN;
slowness 0:c03cffe402df 541 uint8_t RESERVED12[3];
slowness 0:c03cffe402df 542 __IO uint8_t RTC_AUX;
slowness 0:c03cffe402df 543 uint8_t RESERVED13[3];
slowness 0:c03cffe402df 544 __IO uint8_t ALSEC;
slowness 0:c03cffe402df 545 uint8_t RESERVED14[3];
slowness 0:c03cffe402df 546 __IO uint8_t ALMIN;
slowness 0:c03cffe402df 547 uint8_t RESERVED15[3];
slowness 0:c03cffe402df 548 __IO uint8_t ALHOUR;
slowness 0:c03cffe402df 549 uint8_t RESERVED16[3];
slowness 0:c03cffe402df 550 __IO uint8_t ALDOM;
slowness 0:c03cffe402df 551 uint8_t RESERVED17[3];
slowness 0:c03cffe402df 552 __IO uint8_t ALDOW;
slowness 0:c03cffe402df 553 uint8_t RESERVED18[3];
slowness 0:c03cffe402df 554 __IO uint16_t ALDOY;
slowness 0:c03cffe402df 555 uint16_t RESERVED19;
slowness 0:c03cffe402df 556 __IO uint8_t ALMON;
slowness 0:c03cffe402df 557 uint8_t RESERVED20[3];
slowness 0:c03cffe402df 558 __IO uint16_t ALYEAR;
slowness 0:c03cffe402df 559 uint16_t RESERVED21;
slowness 0:c03cffe402df 560 } LPC_RTC_TypeDef;
slowness 0:c03cffe402df 561
slowness 0:c03cffe402df 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
slowness 0:c03cffe402df 563 typedef struct
slowness 0:c03cffe402df 564 {
slowness 0:c03cffe402df 565 __IO uint8_t WDMOD;
slowness 0:c03cffe402df 566 uint8_t RESERVED0[3];
slowness 0:c03cffe402df 567 __IO uint32_t WDTC;
slowness 0:c03cffe402df 568 __O uint8_t WDFEED;
slowness 0:c03cffe402df 569 uint8_t RESERVED1[3];
slowness 0:c03cffe402df 570 __I uint32_t WDTV;
slowness 0:c03cffe402df 571 __IO uint32_t WDCLKSEL;
slowness 0:c03cffe402df 572 } LPC_WDT_TypeDef;
slowness 0:c03cffe402df 573
slowness 0:c03cffe402df 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
slowness 0:c03cffe402df 575 typedef struct
slowness 0:c03cffe402df 576 {
slowness 0:c03cffe402df 577 __IO uint32_t ADCR;
slowness 0:c03cffe402df 578 __IO uint32_t ADGDR;
slowness 0:c03cffe402df 579 uint32_t RESERVED0;
slowness 0:c03cffe402df 580 __IO uint32_t ADINTEN;
slowness 0:c03cffe402df 581 __I uint32_t ADDR0;
slowness 0:c03cffe402df 582 __I uint32_t ADDR1;
slowness 0:c03cffe402df 583 __I uint32_t ADDR2;
slowness 0:c03cffe402df 584 __I uint32_t ADDR3;
slowness 0:c03cffe402df 585 __I uint32_t ADDR4;
slowness 0:c03cffe402df 586 __I uint32_t ADDR5;
slowness 0:c03cffe402df 587 __I uint32_t ADDR6;
slowness 0:c03cffe402df 588 __I uint32_t ADDR7;
slowness 0:c03cffe402df 589 __I uint32_t ADSTAT;
slowness 0:c03cffe402df 590 __IO uint32_t ADTRM;
slowness 0:c03cffe402df 591 } LPC_ADC_TypeDef;
slowness 0:c03cffe402df 592
slowness 0:c03cffe402df 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
slowness 0:c03cffe402df 594 typedef struct
slowness 0:c03cffe402df 595 {
slowness 0:c03cffe402df 596 __IO uint32_t DACR;
slowness 0:c03cffe402df 597 __IO uint32_t DACCTRL;
slowness 0:c03cffe402df 598 __IO uint16_t DACCNTVAL;
slowness 0:c03cffe402df 599 } LPC_DAC_TypeDef;
slowness 0:c03cffe402df 600
slowness 0:c03cffe402df 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
slowness 0:c03cffe402df 602 typedef struct
slowness 0:c03cffe402df 603 {
slowness 0:c03cffe402df 604 __I uint32_t MCCON;
slowness 0:c03cffe402df 605 __O uint32_t MCCON_SET;
slowness 0:c03cffe402df 606 __O uint32_t MCCON_CLR;
slowness 0:c03cffe402df 607 __I uint32_t MCCAPCON;
slowness 0:c03cffe402df 608 __O uint32_t MCCAPCON_SET;
slowness 0:c03cffe402df 609 __O uint32_t MCCAPCON_CLR;
slowness 0:c03cffe402df 610 __IO uint32_t MCTIM0;
slowness 0:c03cffe402df 611 __IO uint32_t MCTIM1;
slowness 0:c03cffe402df 612 __IO uint32_t MCTIM2;
slowness 0:c03cffe402df 613 __IO uint32_t MCPER0;
slowness 0:c03cffe402df 614 __IO uint32_t MCPER1;
slowness 0:c03cffe402df 615 __IO uint32_t MCPER2;
slowness 0:c03cffe402df 616 __IO uint32_t MCPW0;
slowness 0:c03cffe402df 617 __IO uint32_t MCPW1;
slowness 0:c03cffe402df 618 __IO uint32_t MCPW2;
slowness 0:c03cffe402df 619 __IO uint32_t MCDEADTIME;
slowness 0:c03cffe402df 620 __IO uint32_t MCCCP;
slowness 0:c03cffe402df 621 __IO uint32_t MCCR0;
slowness 0:c03cffe402df 622 __IO uint32_t MCCR1;
slowness 0:c03cffe402df 623 __IO uint32_t MCCR2;
slowness 0:c03cffe402df 624 __I uint32_t MCINTEN;
slowness 0:c03cffe402df 625 __O uint32_t MCINTEN_SET;
slowness 0:c03cffe402df 626 __O uint32_t MCINTEN_CLR;
slowness 0:c03cffe402df 627 __I uint32_t MCCNTCON;
slowness 0:c03cffe402df 628 __O uint32_t MCCNTCON_SET;
slowness 0:c03cffe402df 629 __O uint32_t MCCNTCON_CLR;
slowness 0:c03cffe402df 630 __I uint32_t MCINTFLAG;
slowness 0:c03cffe402df 631 __O uint32_t MCINTFLAG_SET;
slowness 0:c03cffe402df 632 __O uint32_t MCINTFLAG_CLR;
slowness 0:c03cffe402df 633 __O uint32_t MCCAP_CLR;
slowness 0:c03cffe402df 634 } LPC_MCPWM_TypeDef;
slowness 0:c03cffe402df 635
slowness 0:c03cffe402df 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
slowness 0:c03cffe402df 637 typedef struct
slowness 0:c03cffe402df 638 {
slowness 0:c03cffe402df 639 __O uint32_t QEICON;
slowness 0:c03cffe402df 640 __I uint32_t QEISTAT;
slowness 0:c03cffe402df 641 __IO uint32_t QEICONF;
slowness 0:c03cffe402df 642 __I uint32_t QEIPOS;
slowness 0:c03cffe402df 643 __IO uint32_t QEIMAXPOS;
slowness 0:c03cffe402df 644 __IO uint32_t CMPOS0;
slowness 0:c03cffe402df 645 __IO uint32_t CMPOS1;
slowness 0:c03cffe402df 646 __IO uint32_t CMPOS2;
slowness 0:c03cffe402df 647 __I uint32_t INXCNT;
slowness 0:c03cffe402df 648 __IO uint32_t INXCMP;
slowness 0:c03cffe402df 649 __IO uint32_t QEILOAD;
slowness 0:c03cffe402df 650 __I uint32_t QEITIME;
slowness 0:c03cffe402df 651 __I uint32_t QEIVEL;
slowness 0:c03cffe402df 652 __I uint32_t QEICAP;
slowness 0:c03cffe402df 653 __IO uint32_t VELCOMP;
slowness 0:c03cffe402df 654 __IO uint32_t FILTER;
slowness 0:c03cffe402df 655 uint32_t RESERVED0[998];
slowness 0:c03cffe402df 656 __O uint32_t QEIIEC;
slowness 0:c03cffe402df 657 __O uint32_t QEIIES;
slowness 0:c03cffe402df 658 __I uint32_t QEIINTSTAT;
slowness 0:c03cffe402df 659 __I uint32_t QEIIE;
slowness 0:c03cffe402df 660 __O uint32_t QEICLR;
slowness 0:c03cffe402df 661 __O uint32_t QEISET;
slowness 0:c03cffe402df 662 } LPC_QEI_TypeDef;
slowness 0:c03cffe402df 663
slowness 0:c03cffe402df 664 /*------------- Controller Area Network (CAN) --------------------------------*/
slowness 0:c03cffe402df 665 typedef struct
slowness 0:c03cffe402df 666 {
slowness 0:c03cffe402df 667 __IO uint32_t mask[512]; /* ID Masks */
slowness 0:c03cffe402df 668 } LPC_CANAF_RAM_TypeDef;
slowness 0:c03cffe402df 669
slowness 0:c03cffe402df 670 typedef struct /* Acceptance Filter Registers */
slowness 0:c03cffe402df 671 {
slowness 0:c03cffe402df 672 __IO uint32_t AFMR;
slowness 0:c03cffe402df 673 __IO uint32_t SFF_sa;
slowness 0:c03cffe402df 674 __IO uint32_t SFF_GRP_sa;
slowness 0:c03cffe402df 675 __IO uint32_t EFF_sa;
slowness 0:c03cffe402df 676 __IO uint32_t EFF_GRP_sa;
slowness 0:c03cffe402df 677 __IO uint32_t ENDofTable;
slowness 0:c03cffe402df 678 __I uint32_t LUTerrAd;
slowness 0:c03cffe402df 679 __I uint32_t LUTerr;
slowness 0:c03cffe402df 680 __IO uint32_t FCANIE;
slowness 0:c03cffe402df 681 __IO uint32_t FCANIC0;
slowness 0:c03cffe402df 682 __IO uint32_t FCANIC1;
slowness 0:c03cffe402df 683 } LPC_CANAF_TypeDef;
slowness 0:c03cffe402df 684
slowness 0:c03cffe402df 685 typedef struct /* Central Registers */
slowness 0:c03cffe402df 686 {
slowness 0:c03cffe402df 687 __I uint32_t CANTxSR;
slowness 0:c03cffe402df 688 __I uint32_t CANRxSR;
slowness 0:c03cffe402df 689 __I uint32_t CANMSR;
slowness 0:c03cffe402df 690 } LPC_CANCR_TypeDef;
slowness 0:c03cffe402df 691
slowness 0:c03cffe402df 692 typedef struct /* Controller Registers */
slowness 0:c03cffe402df 693 {
slowness 0:c03cffe402df 694 __IO uint32_t MOD;
slowness 0:c03cffe402df 695 __O uint32_t CMR;
slowness 0:c03cffe402df 696 __IO uint32_t GSR;
slowness 0:c03cffe402df 697 __I uint32_t ICR;
slowness 0:c03cffe402df 698 __IO uint32_t IER;
slowness 0:c03cffe402df 699 __IO uint32_t BTR;
slowness 0:c03cffe402df 700 __IO uint32_t EWL;
slowness 0:c03cffe402df 701 __I uint32_t SR;
slowness 0:c03cffe402df 702 __IO uint32_t RFS;
slowness 0:c03cffe402df 703 __IO uint32_t RID;
slowness 0:c03cffe402df 704 __IO uint32_t RDA;
slowness 0:c03cffe402df 705 __IO uint32_t RDB;
slowness 0:c03cffe402df 706 __IO uint32_t TFI1;
slowness 0:c03cffe402df 707 __IO uint32_t TID1;
slowness 0:c03cffe402df 708 __IO uint32_t TDA1;
slowness 0:c03cffe402df 709 __IO uint32_t TDB1;
slowness 0:c03cffe402df 710 __IO uint32_t TFI2;
slowness 0:c03cffe402df 711 __IO uint32_t TID2;
slowness 0:c03cffe402df 712 __IO uint32_t TDA2;
slowness 0:c03cffe402df 713 __IO uint32_t TDB2;
slowness 0:c03cffe402df 714 __IO uint32_t TFI3;
slowness 0:c03cffe402df 715 __IO uint32_t TID3;
slowness 0:c03cffe402df 716 __IO uint32_t TDA3;
slowness 0:c03cffe402df 717 __IO uint32_t TDB3;
slowness 0:c03cffe402df 718 } LPC_CAN_TypeDef;
slowness 0:c03cffe402df 719
slowness 0:c03cffe402df 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
slowness 0:c03cffe402df 721 typedef struct /* Common Registers */
slowness 0:c03cffe402df 722 {
slowness 0:c03cffe402df 723 __I uint32_t DMACIntStat;
slowness 0:c03cffe402df 724 __I uint32_t DMACIntTCStat;
slowness 0:c03cffe402df 725 __O uint32_t DMACIntTCClear;
slowness 0:c03cffe402df 726 __I uint32_t DMACIntErrStat;
slowness 0:c03cffe402df 727 __O uint32_t DMACIntErrClr;
slowness 0:c03cffe402df 728 __I uint32_t DMACRawIntTCStat;
slowness 0:c03cffe402df 729 __I uint32_t DMACRawIntErrStat;
slowness 0:c03cffe402df 730 __I uint32_t DMACEnbldChns;
slowness 0:c03cffe402df 731 __IO uint32_t DMACSoftBReq;
slowness 0:c03cffe402df 732 __IO uint32_t DMACSoftSReq;
slowness 0:c03cffe402df 733 __IO uint32_t DMACSoftLBReq;
slowness 0:c03cffe402df 734 __IO uint32_t DMACSoftLSReq;
slowness 0:c03cffe402df 735 __IO uint32_t DMACConfig;
slowness 0:c03cffe402df 736 __IO uint32_t DMACSync;
slowness 0:c03cffe402df 737 } LPC_GPDMA_TypeDef;
slowness 0:c03cffe402df 738
slowness 0:c03cffe402df 739 typedef struct /* Channel Registers */
slowness 0:c03cffe402df 740 {
slowness 0:c03cffe402df 741 __IO uint32_t DMACCSrcAddr;
slowness 0:c03cffe402df 742 __IO uint32_t DMACCDestAddr;
slowness 0:c03cffe402df 743 __IO uint32_t DMACCLLI;
slowness 0:c03cffe402df 744 __IO uint32_t DMACCControl;
slowness 0:c03cffe402df 745 __IO uint32_t DMACCConfig;
slowness 0:c03cffe402df 746 } LPC_GPDMACH_TypeDef;
slowness 0:c03cffe402df 747
slowness 0:c03cffe402df 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
slowness 0:c03cffe402df 749 typedef struct
slowness 0:c03cffe402df 750 {
slowness 0:c03cffe402df 751 __I uint32_t HcRevision; /* USB Host Registers */
slowness 0:c03cffe402df 752 __IO uint32_t HcControl;
slowness 0:c03cffe402df 753 __IO uint32_t HcCommandStatus;
slowness 0:c03cffe402df 754 __IO uint32_t HcInterruptStatus;
slowness 0:c03cffe402df 755 __IO uint32_t HcInterruptEnable;
slowness 0:c03cffe402df 756 __IO uint32_t HcInterruptDisable;
slowness 0:c03cffe402df 757 __IO uint32_t HcHCCA;
slowness 0:c03cffe402df 758 __I uint32_t HcPeriodCurrentED;
slowness 0:c03cffe402df 759 __IO uint32_t HcControlHeadED;
slowness 0:c03cffe402df 760 __IO uint32_t HcControlCurrentED;
slowness 0:c03cffe402df 761 __IO uint32_t HcBulkHeadED;
slowness 0:c03cffe402df 762 __IO uint32_t HcBulkCurrentED;
slowness 0:c03cffe402df 763 __I uint32_t HcDoneHead;
slowness 0:c03cffe402df 764 __IO uint32_t HcFmInterval;
slowness 0:c03cffe402df 765 __I uint32_t HcFmRemaining;
slowness 0:c03cffe402df 766 __I uint32_t HcFmNumber;
slowness 0:c03cffe402df 767 __IO uint32_t HcPeriodicStart;
slowness 0:c03cffe402df 768 __IO uint32_t HcLSTreshold;
slowness 0:c03cffe402df 769 __IO uint32_t HcRhDescriptorA;
slowness 0:c03cffe402df 770 __IO uint32_t HcRhDescriptorB;
slowness 0:c03cffe402df 771 __IO uint32_t HcRhStatus;
slowness 0:c03cffe402df 772 __IO uint32_t HcRhPortStatus1;
slowness 0:c03cffe402df 773 __IO uint32_t HcRhPortStatus2;
slowness 0:c03cffe402df 774 uint32_t RESERVED0[40];
slowness 0:c03cffe402df 775 __I uint32_t Module_ID;
slowness 0:c03cffe402df 776
slowness 0:c03cffe402df 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
slowness 0:c03cffe402df 778 __IO uint32_t OTGIntEn;
slowness 0:c03cffe402df 779 __O uint32_t OTGIntSet;
slowness 0:c03cffe402df 780 __O uint32_t OTGIntClr;
slowness 0:c03cffe402df 781 __IO uint32_t OTGStCtrl;
slowness 0:c03cffe402df 782 __IO uint32_t OTGTmr;
slowness 0:c03cffe402df 783 uint32_t RESERVED1[58];
slowness 0:c03cffe402df 784
slowness 0:c03cffe402df 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
slowness 0:c03cffe402df 786 __IO uint32_t USBDevIntEn;
slowness 0:c03cffe402df 787 __O uint32_t USBDevIntClr;
slowness 0:c03cffe402df 788 __O uint32_t USBDevIntSet;
slowness 0:c03cffe402df 789
slowness 0:c03cffe402df 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
slowness 0:c03cffe402df 791 __I uint32_t USBCmdData;
slowness 0:c03cffe402df 792
slowness 0:c03cffe402df 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
slowness 0:c03cffe402df 794 __O uint32_t USBTxData;
slowness 0:c03cffe402df 795 __I uint32_t USBRxPLen;
slowness 0:c03cffe402df 796 __O uint32_t USBTxPLen;
slowness 0:c03cffe402df 797 __IO uint32_t USBCtrl;
slowness 0:c03cffe402df 798 __O uint32_t USBDevIntPri;
slowness 0:c03cffe402df 799
slowness 0:c03cffe402df 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
slowness 0:c03cffe402df 801 __IO uint32_t USBEpIntEn;
slowness 0:c03cffe402df 802 __O uint32_t USBEpIntClr;
slowness 0:c03cffe402df 803 __O uint32_t USBEpIntSet;
slowness 0:c03cffe402df 804 __O uint32_t USBEpIntPri;
slowness 0:c03cffe402df 805
slowness 0:c03cffe402df 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
slowness 0:c03cffe402df 807 __O uint32_t USBEpInd;
slowness 0:c03cffe402df 808 __IO uint32_t USBMaxPSize;
slowness 0:c03cffe402df 809
slowness 0:c03cffe402df 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
slowness 0:c03cffe402df 811 __O uint32_t USBDMARClr;
slowness 0:c03cffe402df 812 __O uint32_t USBDMARSet;
slowness 0:c03cffe402df 813 uint32_t RESERVED2[9];
slowness 0:c03cffe402df 814 __IO uint32_t USBUDCAH;
slowness 0:c03cffe402df 815 __I uint32_t USBEpDMASt;
slowness 0:c03cffe402df 816 __O uint32_t USBEpDMAEn;
slowness 0:c03cffe402df 817 __O uint32_t USBEpDMADis;
slowness 0:c03cffe402df 818 __I uint32_t USBDMAIntSt;
slowness 0:c03cffe402df 819 __IO uint32_t USBDMAIntEn;
slowness 0:c03cffe402df 820 uint32_t RESERVED3[2];
slowness 0:c03cffe402df 821 __I uint32_t USBEoTIntSt;
slowness 0:c03cffe402df 822 __O uint32_t USBEoTIntClr;
slowness 0:c03cffe402df 823 __O uint32_t USBEoTIntSet;
slowness 0:c03cffe402df 824 __I uint32_t USBNDDRIntSt;
slowness 0:c03cffe402df 825 __O uint32_t USBNDDRIntClr;
slowness 0:c03cffe402df 826 __O uint32_t USBNDDRIntSet;
slowness 0:c03cffe402df 827 __I uint32_t USBSysErrIntSt;
slowness 0:c03cffe402df 828 __O uint32_t USBSysErrIntClr;
slowness 0:c03cffe402df 829 __O uint32_t USBSysErrIntSet;
slowness 0:c03cffe402df 830 uint32_t RESERVED4[15];
slowness 0:c03cffe402df 831
slowness 0:c03cffe402df 832 union {
slowness 0:c03cffe402df 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
slowness 0:c03cffe402df 834 __O uint32_t I2C_TX;
slowness 0:c03cffe402df 835 };
slowness 0:c03cffe402df 836 __I uint32_t I2C_STS;
slowness 0:c03cffe402df 837 __IO uint32_t I2C_CTL;
slowness 0:c03cffe402df 838 __IO uint32_t I2C_CLKHI;
slowness 0:c03cffe402df 839 __O uint32_t I2C_CLKLO;
slowness 0:c03cffe402df 840 uint32_t RESERVED5[824];
slowness 0:c03cffe402df 841
slowness 0:c03cffe402df 842 union {
slowness 0:c03cffe402df 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
slowness 0:c03cffe402df 844 __IO uint32_t OTGClkCtrl;
slowness 0:c03cffe402df 845 };
slowness 0:c03cffe402df 846 union {
slowness 0:c03cffe402df 847 __I uint32_t USBClkSt;
slowness 0:c03cffe402df 848 __I uint32_t OTGClkSt;
slowness 0:c03cffe402df 849 };
slowness 0:c03cffe402df 850 } LPC_USB_TypeDef;
slowness 0:c03cffe402df 851
slowness 0:c03cffe402df 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
slowness 0:c03cffe402df 853 typedef struct
slowness 0:c03cffe402df 854 {
slowness 0:c03cffe402df 855 __IO uint32_t MAC1; /* MAC Registers */
slowness 0:c03cffe402df 856 __IO uint32_t MAC2;
slowness 0:c03cffe402df 857 __IO uint32_t IPGT;
slowness 0:c03cffe402df 858 __IO uint32_t IPGR;
slowness 0:c03cffe402df 859 __IO uint32_t CLRT;
slowness 0:c03cffe402df 860 __IO uint32_t MAXF;
slowness 0:c03cffe402df 861 __IO uint32_t SUPP;
slowness 0:c03cffe402df 862 __IO uint32_t TEST;
slowness 0:c03cffe402df 863 __IO uint32_t MCFG;
slowness 0:c03cffe402df 864 __IO uint32_t MCMD;
slowness 0:c03cffe402df 865 __IO uint32_t MADR;
slowness 0:c03cffe402df 866 __O uint32_t MWTD;
slowness 0:c03cffe402df 867 __I uint32_t MRDD;
slowness 0:c03cffe402df 868 __I uint32_t MIND;
slowness 0:c03cffe402df 869 uint32_t RESERVED0[2];
slowness 0:c03cffe402df 870 __IO uint32_t SA0;
slowness 0:c03cffe402df 871 __IO uint32_t SA1;
slowness 0:c03cffe402df 872 __IO uint32_t SA2;
slowness 0:c03cffe402df 873 uint32_t RESERVED1[45];
slowness 0:c03cffe402df 874 __IO uint32_t Command; /* Control Registers */
slowness 0:c03cffe402df 875 __I uint32_t Status;
slowness 0:c03cffe402df 876 __IO uint32_t RxDescriptor;
slowness 0:c03cffe402df 877 __IO uint32_t RxStatus;
slowness 0:c03cffe402df 878 __IO uint32_t RxDescriptorNumber;
slowness 0:c03cffe402df 879 __I uint32_t RxProduceIndex;
slowness 0:c03cffe402df 880 __IO uint32_t RxConsumeIndex;
slowness 0:c03cffe402df 881 __IO uint32_t TxDescriptor;
slowness 0:c03cffe402df 882 __IO uint32_t TxStatus;
slowness 0:c03cffe402df 883 __IO uint32_t TxDescriptorNumber;
slowness 0:c03cffe402df 884 __IO uint32_t TxProduceIndex;
slowness 0:c03cffe402df 885 __I uint32_t TxConsumeIndex;
slowness 0:c03cffe402df 886 uint32_t RESERVED2[10];
slowness 0:c03cffe402df 887 __I uint32_t TSV0;
slowness 0:c03cffe402df 888 __I uint32_t TSV1;
slowness 0:c03cffe402df 889 __I uint32_t RSV;
slowness 0:c03cffe402df 890 uint32_t RESERVED3[3];
slowness 0:c03cffe402df 891 __IO uint32_t FlowControlCounter;
slowness 0:c03cffe402df 892 __I uint32_t FlowControlStatus;
slowness 0:c03cffe402df 893 uint32_t RESERVED4[34];
slowness 0:c03cffe402df 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
slowness 0:c03cffe402df 895 __IO uint32_t RxFilterWoLStatus;
slowness 0:c03cffe402df 896 __IO uint32_t RxFilterWoLClear;
slowness 0:c03cffe402df 897 uint32_t RESERVED5;
slowness 0:c03cffe402df 898 __IO uint32_t HashFilterL;
slowness 0:c03cffe402df 899 __IO uint32_t HashFilterH;
slowness 0:c03cffe402df 900 uint32_t RESERVED6[882];
slowness 0:c03cffe402df 901 __I uint32_t IntStatus; /* Module Control Registers */
slowness 0:c03cffe402df 902 __IO uint32_t IntEnable;
slowness 0:c03cffe402df 903 __O uint32_t IntClear;
slowness 0:c03cffe402df 904 __O uint32_t IntSet;
slowness 0:c03cffe402df 905 uint32_t RESERVED7;
slowness 0:c03cffe402df 906 __IO uint32_t PowerDown;
slowness 0:c03cffe402df 907 uint32_t RESERVED8;
slowness 0:c03cffe402df 908 __IO uint32_t Module_ID;
slowness 0:c03cffe402df 909 } LPC_EMAC_TypeDef;
slowness 0:c03cffe402df 910
slowness 0:c03cffe402df 911 #if defined ( __CC_ARM )
slowness 0:c03cffe402df 912 #pragma no_anon_unions
slowness 0:c03cffe402df 913 #endif
slowness 0:c03cffe402df 914
slowness 0:c03cffe402df 915
slowness 0:c03cffe402df 916 /******************************************************************************/
slowness 0:c03cffe402df 917 /* Peripheral memory map */
slowness 0:c03cffe402df 918 /******************************************************************************/
slowness 0:c03cffe402df 919 /* Base addresses */
slowness 0:c03cffe402df 920 #define LPC_FLASH_BASE (0x00000000UL)
slowness 0:c03cffe402df 921 #define LPC_RAM_BASE (0x10000000UL)
slowness 0:c03cffe402df 922 #define LPC_GPIO_BASE (0x2009C000UL)
slowness 0:c03cffe402df 923 #define LPC_APB0_BASE (0x40000000UL)
slowness 0:c03cffe402df 924 #define LPC_APB1_BASE (0x40080000UL)
slowness 0:c03cffe402df 925 #define LPC_AHB_BASE (0x50000000UL)
slowness 0:c03cffe402df 926 #define LPC_CM3_BASE (0xE0000000UL)
slowness 0:c03cffe402df 927
slowness 0:c03cffe402df 928 /* APB0 peripherals */
slowness 0:c03cffe402df 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
slowness 0:c03cffe402df 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
slowness 0:c03cffe402df 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
slowness 0:c03cffe402df 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
slowness 0:c03cffe402df 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
slowness 0:c03cffe402df 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
slowness 0:c03cffe402df 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
slowness 0:c03cffe402df 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
slowness 0:c03cffe402df 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
slowness 0:c03cffe402df 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
slowness 0:c03cffe402df 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
slowness 0:c03cffe402df 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
slowness 0:c03cffe402df 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
slowness 0:c03cffe402df 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
slowness 0:c03cffe402df 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
slowness 0:c03cffe402df 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
slowness 0:c03cffe402df 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
slowness 0:c03cffe402df 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
slowness 0:c03cffe402df 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
slowness 0:c03cffe402df 948
slowness 0:c03cffe402df 949 /* APB1 peripherals */
slowness 0:c03cffe402df 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
slowness 0:c03cffe402df 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
slowness 0:c03cffe402df 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
slowness 0:c03cffe402df 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
slowness 0:c03cffe402df 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
slowness 0:c03cffe402df 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
slowness 0:c03cffe402df 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
slowness 0:c03cffe402df 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
slowness 0:c03cffe402df 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
slowness 0:c03cffe402df 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
slowness 0:c03cffe402df 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
slowness 0:c03cffe402df 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
slowness 0:c03cffe402df 962
slowness 0:c03cffe402df 963 /* AHB peripherals */
slowness 0:c03cffe402df 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
slowness 0:c03cffe402df 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
slowness 0:c03cffe402df 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
slowness 0:c03cffe402df 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
slowness 0:c03cffe402df 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
slowness 0:c03cffe402df 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
slowness 0:c03cffe402df 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
slowness 0:c03cffe402df 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
slowness 0:c03cffe402df 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
slowness 0:c03cffe402df 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
slowness 0:c03cffe402df 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
slowness 0:c03cffe402df 975
slowness 0:c03cffe402df 976 /* GPIOs */
slowness 0:c03cffe402df 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
slowness 0:c03cffe402df 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
slowness 0:c03cffe402df 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
slowness 0:c03cffe402df 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
slowness 0:c03cffe402df 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
slowness 0:c03cffe402df 982
slowness 0:c03cffe402df 983
slowness 0:c03cffe402df 984 /******************************************************************************/
slowness 0:c03cffe402df 985 /* Peripheral declaration */
slowness 0:c03cffe402df 986 /******************************************************************************/
slowness 0:c03cffe402df 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
slowness 0:c03cffe402df 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
slowness 0:c03cffe402df 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
slowness 0:c03cffe402df 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
slowness 0:c03cffe402df 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
slowness 0:c03cffe402df 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
slowness 0:c03cffe402df 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
slowness 0:c03cffe402df 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
slowness 0:c03cffe402df 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
slowness 0:c03cffe402df 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
slowness 0:c03cffe402df 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
slowness 0:c03cffe402df 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
slowness 0:c03cffe402df 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
slowness 0:c03cffe402df 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
slowness 0:c03cffe402df 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
slowness 0:c03cffe402df 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
slowness 0:c03cffe402df 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
slowness 0:c03cffe402df 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
slowness 0:c03cffe402df 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
slowness 0:c03cffe402df 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
slowness 0:c03cffe402df 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
slowness 0:c03cffe402df 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
slowness 0:c03cffe402df 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
slowness 0:c03cffe402df 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
slowness 0:c03cffe402df 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
slowness 0:c03cffe402df 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
slowness 0:c03cffe402df 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
slowness 0:c03cffe402df 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
slowness 0:c03cffe402df 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
slowness 0:c03cffe402df 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
slowness 0:c03cffe402df 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
slowness 0:c03cffe402df 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
slowness 0:c03cffe402df 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
slowness 0:c03cffe402df 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
slowness 0:c03cffe402df 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
slowness 0:c03cffe402df 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
slowness 0:c03cffe402df 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
slowness 0:c03cffe402df 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
slowness 0:c03cffe402df 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
slowness 0:c03cffe402df 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
slowness 0:c03cffe402df 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
slowness 0:c03cffe402df 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
slowness 0:c03cffe402df 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
slowness 0:c03cffe402df 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
slowness 0:c03cffe402df 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
slowness 0:c03cffe402df 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
slowness 0:c03cffe402df 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
slowness 0:c03cffe402df 1034
slowness 0:c03cffe402df 1035 #endif // __LPC17xx_H__