MSCUsbHost - This is Igors USB Host Mass Storage Class example…

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This is Igors USB Host Mass Storage Class example with main.cpp removed. Import this as files, add your own main.cpp and have all the USB MSC fun you can!

Dependents: mbedDemoDisplay mbedDemoDisplay MMEx_Challenge

USBHostLite/usbhost_lpc17xx.c@0:cfb58054ab28, 2010-02-20 (annotated)

Committer:: chris
Date:: Sat Feb 20 08:06:12 2010 +0000
Revision:: 0:cfb58054ab28

Who changed what in which revision?

User	Revision	Line number	New contents of line
chris	0:cfb58054ab28	1	/*
chris	0:cfb58054ab28	2	**************************************************************************************************************
chris	0:cfb58054ab28	3	* NXP USB Host Stack
chris	0:cfb58054ab28	4	*
chris	0:cfb58054ab28	5	* (c) Copyright 2008, NXP SemiConductors
chris	0:cfb58054ab28	6	* (c) Copyright 2008, OnChip Technologies LLC
chris	0:cfb58054ab28	7	* All Rights Reserved
chris	0:cfb58054ab28	8	*
chris	0:cfb58054ab28	9	* www.nxp.com
chris	0:cfb58054ab28	10	* www.onchiptech.com
chris	0:cfb58054ab28	11	*
chris	0:cfb58054ab28	12	* File : usbhost_lpc17xx.c
chris	0:cfb58054ab28	13	* Programmer(s) : Ravikanth.P
chris	0:cfb58054ab28	14	* Version :
chris	0:cfb58054ab28	15	*
chris	0:cfb58054ab28	16	**************************************************************************************************************
chris	0:cfb58054ab28	17	*/
chris	0:cfb58054ab28	18
chris	0:cfb58054ab28	19	/*
chris	0:cfb58054ab28	20	**************************************************************************************************************
chris	0:cfb58054ab28	21	* INCLUDE HEADER FILES
chris	0:cfb58054ab28	22	**************************************************************************************************************
chris	0:cfb58054ab28	23	*/
chris	0:cfb58054ab28	24
chris	0:cfb58054ab28	25	#include "usbhost_lpc17xx.h"
chris	0:cfb58054ab28	26
chris	0:cfb58054ab28	27	/*
chris	0:cfb58054ab28	28	**************************************************************************************************************
chris	0:cfb58054ab28	29	* GLOBAL VARIABLES
chris	0:cfb58054ab28	30	**************************************************************************************************************
chris	0:cfb58054ab28	31	*/
chris	0:cfb58054ab28	32	int gUSBConnected;
chris	0:cfb58054ab28	33
chris	0:cfb58054ab28	34	volatile USB_INT32U HOST_RhscIntr = 0; /* Root Hub Status Change interrupt */
chris	0:cfb58054ab28	35	volatile USB_INT32U HOST_WdhIntr = 0; /* Semaphore to wait until the TD is submitted */
chris	0:cfb58054ab28	36	volatile USB_INT08U HOST_TDControlStatus = 0;
chris	0:cfb58054ab28	37	volatile HCED EDCtrl; / Control endpoint descriptor structure */
chris	0:cfb58054ab28	38	volatile HCED EDBulkIn; / BulkIn endpoint descriptor structure */
chris	0:cfb58054ab28	39	volatile HCED EDBulkOut; / BulkOut endpoint descriptor structure */
chris	0:cfb58054ab28	40	volatile HCTD TDHead; / Head transfer descriptor structure */
chris	0:cfb58054ab28	41	volatile HCTD TDTail; / Tail transfer descriptor structure */
chris	0:cfb58054ab28	42	volatile HCCA Hcca; / Host Controller Communications Area structure */
chris	0:cfb58054ab28	43	USB_INT16U TDBufNonVol; / Identical to TDBuffer just to reduce compiler warnings */
chris	0:cfb58054ab28	44	volatile USB_INT08U TDBuffer; / Current Buffer Pointer of transfer descriptor */
chris	0:cfb58054ab28	45
chris	0:cfb58054ab28	46	// USB host structures
chris	0:cfb58054ab28	47	// AHB SRAM block 1
chris	0:cfb58054ab28	48	#define HOSTBASEADDR 0x2007C000
chris	0:cfb58054ab28	49	// reserve memory for the linker
chris	0:cfb58054ab28	50	static USB_INT08U HostBuf[0x200] __attribute__((at(HOSTBASEADDR)));
chris	0:cfb58054ab28	51	/*
chris	0:cfb58054ab28	52	**************************************************************************************************************
chris	0:cfb58054ab28	53	* DELAY IN MILLI SECONDS
chris	0:cfb58054ab28	54	*
chris	0:cfb58054ab28	55	* Description: This function provides a delay in milli seconds
chris	0:cfb58054ab28	56	*
chris	0:cfb58054ab28	57	* Arguments : delay The delay required
chris	0:cfb58054ab28	58	*
chris	0:cfb58054ab28	59	* Returns : None
chris	0:cfb58054ab28	60	*
chris	0:cfb58054ab28	61	**************************************************************************************************************
chris	0:cfb58054ab28	62	*/
chris	0:cfb58054ab28	63
chris	0:cfb58054ab28	64	void Host_DelayMS (USB_INT32U delay)
chris	0:cfb58054ab28	65	{
chris	0:cfb58054ab28	66	volatile USB_INT32U i;
chris	0:cfb58054ab28	67
chris	0:cfb58054ab28	68
chris	0:cfb58054ab28	69	for (i = 0; i < delay; i++) {
chris	0:cfb58054ab28	70	Host_DelayUS(1000);
chris	0:cfb58054ab28	71	}
chris	0:cfb58054ab28	72	}
chris	0:cfb58054ab28	73
chris	0:cfb58054ab28	74	/*
chris	0:cfb58054ab28	75	**************************************************************************************************************
chris	0:cfb58054ab28	76	* DELAY IN MICRO SECONDS
chris	0:cfb58054ab28	77	*
chris	0:cfb58054ab28	78	* Description: This function provides a delay in micro seconds
chris	0:cfb58054ab28	79	*
chris	0:cfb58054ab28	80	* Arguments : delay The delay required
chris	0:cfb58054ab28	81	*
chris	0:cfb58054ab28	82	* Returns : None
chris	0:cfb58054ab28	83	*
chris	0:cfb58054ab28	84	**************************************************************************************************************
chris	0:cfb58054ab28	85	*/
chris	0:cfb58054ab28	86
chris	0:cfb58054ab28	87	void Host_DelayUS (USB_INT32U delay)
chris	0:cfb58054ab28	88	{
chris	0:cfb58054ab28	89	volatile USB_INT32U i;
chris	0:cfb58054ab28	90
chris	0:cfb58054ab28	91
chris	0:cfb58054ab28	92	for (i = 0; i < (4 * delay); i++) { /* This logic was tested. It gives app. 1 micro sec delay */
chris	0:cfb58054ab28	93	;
chris	0:cfb58054ab28	94	}
chris	0:cfb58054ab28	95	}
chris	0:cfb58054ab28	96
chris	0:cfb58054ab28	97	// bits of the USB/OTG clock control register
chris	0:cfb58054ab28	98	#define HOST_CLK_EN (1<<0)
chris	0:cfb58054ab28	99	#define DEV_CLK_EN (1<<1)
chris	0:cfb58054ab28	100	#define PORTSEL_CLK_EN (1<<3)
chris	0:cfb58054ab28	101	#define AHB_CLK_EN (1<<4)
chris	0:cfb58054ab28	102
chris	0:cfb58054ab28	103	// bits of the USB/OTG clock status register
chris	0:cfb58054ab28	104	#define HOST_CLK_ON (1<<0)
chris	0:cfb58054ab28	105	#define DEV_CLK_ON (1<<1)
chris	0:cfb58054ab28	106	#define PORTSEL_CLK_ON (1<<3)
chris	0:cfb58054ab28	107	#define AHB_CLK_ON (1<<4)
chris	0:cfb58054ab28	108
chris	0:cfb58054ab28	109	// we need host clock, OTG/portsel clock and AHB clock
chris	0:cfb58054ab28	110	#define CLOCK_MASK (HOST_CLK_EN \| PORTSEL_CLK_EN \| AHB_CLK_EN)
chris	0:cfb58054ab28	111
chris	0:cfb58054ab28	112	/*
chris	0:cfb58054ab28	113	**************************************************************************************************************
chris	0:cfb58054ab28	114	* INITIALIZE THE HOST CONTROLLER
chris	0:cfb58054ab28	115	*
chris	0:cfb58054ab28	116	* Description: This function initializes lpc17xx host controller
chris	0:cfb58054ab28	117	*
chris	0:cfb58054ab28	118	* Arguments : None
chris	0:cfb58054ab28	119	*
chris	0:cfb58054ab28	120	* Returns :
chris	0:cfb58054ab28	121	*
chris	0:cfb58054ab28	122	**************************************************************************************************************
chris	0:cfb58054ab28	123	*/
chris	0:cfb58054ab28	124	void Host_Init (void)
chris	0:cfb58054ab28	125	{
chris	0:cfb58054ab28	126	PRINT_Log("In Host_Init\n");
chris	0:cfb58054ab28	127	NVIC_DisableIRQ(USB_IRQn); /* Disable the USB interrupt source */
chris	0:cfb58054ab28	128
chris	0:cfb58054ab28	129	// turn on power for USB
chris	0:cfb58054ab28	130	LPC_SC->PCONP \|= (1UL<<31);
chris	0:cfb58054ab28	131	// Enable USB host clock, port selection and AHB clock
chris	0:cfb58054ab28	132	LPC_USB->USBClkCtrl \|= CLOCK_MASK;
chris	0:cfb58054ab28	133	// Wait for clocks to become available
chris	0:cfb58054ab28	134	while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK)
chris	0:cfb58054ab28	135	;
chris	0:cfb58054ab28	136
chris	0:cfb58054ab28	137	// it seems the bits[0:1] mean the following
chris	0:cfb58054ab28	138	// 0: U1=device, U2=host
chris	0:cfb58054ab28	139	// 1: U1=host, U2=host
chris	0:cfb58054ab28	140	// 2: reserved
chris	0:cfb58054ab28	141	// 3: U1=host, U2=device
chris	0:cfb58054ab28	142	// NB: this register is only available if OTG clock (aka "port select") is enabled!!
chris	0:cfb58054ab28	143	// since we don't care about port 2, set just bit 0 to 1 (U1=host)
chris	0:cfb58054ab28	144	LPC_USB->OTGStCtrl \|= 1;
chris	0:cfb58054ab28	145
chris	0:cfb58054ab28	146	// now that we've configured the ports, we can turn off the portsel clock
chris	0:cfb58054ab28	147	LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
chris	0:cfb58054ab28	148
chris	0:cfb58054ab28	149	// power pins are not connected on mbed, so we can skip them
chris	0:cfb58054ab28	150	/* P1[18] = USB_UP_LED, 01 */
chris	0:cfb58054ab28	151	/* P1[19] = /USB_PPWR, 10 */
chris	0:cfb58054ab28	152	/* P1[22] = USB_PWRD, 10 */
chris	0:cfb58054ab28	153	/* P1[27] = /USB_OVRCR, 10 */
chris	0:cfb58054ab28	154	/*LPC_PINCON->PINSEL3 &= ~((3<<4) \| (3<<6) \| (3<<12) \| (3<<22));
chris	0:cfb58054ab28	155	LPC_PINCON->PINSEL3 \|= ((1<<4)\|(2<<6) \| (2<<12) \| (2<<22)); // 0x00802080
chris	0:cfb58054ab28	156	*/
chris	0:cfb58054ab28	157
chris	0:cfb58054ab28	158	// configure USB D+/D- pins
chris	0:cfb58054ab28	159	/* P0[29] = USB_D+, 01 */
chris	0:cfb58054ab28	160	/* P0[30] = USB_D-, 01 */
chris	0:cfb58054ab28	161	LPC_PINCON->PINSEL1 &= ~((3<<26) \| (3<<28));
chris	0:cfb58054ab28	162	LPC_PINCON->PINSEL1 \|= ((1<<26)\|(1<<28)); // 0x14000000
chris	0:cfb58054ab28	163
chris	0:cfb58054ab28	164	PRINT_Log("Initializing Host Stack\n");
chris	0:cfb58054ab28	165
chris	0:cfb58054ab28	166	Hcca = (volatile HCCA *)(HostBuf+0x000);
chris	0:cfb58054ab28	167	TDHead = (volatile HCTD *)(HostBuf+0x100);
chris	0:cfb58054ab28	168	TDTail = (volatile HCTD *)(HostBuf+0x110);
chris	0:cfb58054ab28	169	EDCtrl = (volatile HCED *)(HostBuf+0x120);
chris	0:cfb58054ab28	170	EDBulkIn = (volatile HCED *)(HostBuf+0x130);
chris	0:cfb58054ab28	171	EDBulkOut = (volatile HCED *)(HostBuf+0x140);
chris	0:cfb58054ab28	172	TDBuffer = (volatile USB_INT08U *)(HostBuf+0x150);
chris	0:cfb58054ab28	173
chris	0:cfb58054ab28	174	/* Initialize all the TDs, EDs and HCCA to 0 */
chris	0:cfb58054ab28	175	Host_EDInit(EDCtrl);
chris	0:cfb58054ab28	176	Host_EDInit(EDBulkIn);
chris	0:cfb58054ab28	177	Host_EDInit(EDBulkOut);
chris	0:cfb58054ab28	178	Host_TDInit(TDHead);
chris	0:cfb58054ab28	179	Host_TDInit(TDTail);
chris	0:cfb58054ab28	180	Host_HCCAInit(Hcca);
chris	0:cfb58054ab28	181
chris	0:cfb58054ab28	182	Host_DelayMS(50); /* Wait 50 ms before apply reset */
chris	0:cfb58054ab28	183	LPC_USB->HcControl = 0; /* HARDWARE RESET */
chris	0:cfb58054ab28	184	LPC_USB->HcControlHeadED = 0; /* Initialize Control list head to Zero */
chris	0:cfb58054ab28	185	LPC_USB->HcBulkHeadED = 0; /* Initialize Bulk list head to Zero */
chris	0:cfb58054ab28	186
chris	0:cfb58054ab28	187	/* SOFTWARE RESET */
chris	0:cfb58054ab28	188	LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
chris	0:cfb58054ab28	189	LPC_USB->HcFmInterval = DEFAULT_FMINTERVAL; /* Write Fm Interval and Largest Data Packet Counter */
chris	0:cfb58054ab28	190
chris	0:cfb58054ab28	191	/* Put HC in operational state */
chris	0:cfb58054ab28	192	LPC_USB->HcControl = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) \| OR_CONTROL_HC_OPER;
chris	0:cfb58054ab28	193	LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC; /* Set Global Power */
chris	0:cfb58054ab28	194
chris	0:cfb58054ab28	195	LPC_USB->HcHCCA = (USB_INT32U)Hcca;
chris	0:cfb58054ab28	196	LPC_USB->HcInterruptStatus \|= LPC_USB->HcInterruptStatus; /* Clear Interrrupt Status */
chris	0:cfb58054ab28	197
chris	0:cfb58054ab28	198
chris	0:cfb58054ab28	199	LPC_USB->HcInterruptEnable = OR_INTR_ENABLE_MIE \|
chris	0:cfb58054ab28	200	OR_INTR_ENABLE_WDH \|
chris	0:cfb58054ab28	201	OR_INTR_ENABLE_RHSC;
chris	0:cfb58054ab28	202
chris	0:cfb58054ab28	203	NVIC_SetPriority(USB_IRQn, 0); /* highest priority */
chris	0:cfb58054ab28	204	/* Enable the USB Interrupt */
chris	0:cfb58054ab28	205	NVIC_EnableIRQ(USB_IRQn);
chris	0:cfb58054ab28	206	PRINT_Log("Host Initialized\n");
chris	0:cfb58054ab28	207	}
chris	0:cfb58054ab28	208
chris	0:cfb58054ab28	209	/*
chris	0:cfb58054ab28	210	**************************************************************************************************************
chris	0:cfb58054ab28	211	* INTERRUPT SERVICE ROUTINE
chris	0:cfb58054ab28	212	*
chris	0:cfb58054ab28	213	* Description: This function services the interrupt caused by host controller
chris	0:cfb58054ab28	214	*
chris	0:cfb58054ab28	215	* Arguments : None
chris	0:cfb58054ab28	216	*
chris	0:cfb58054ab28	217	* Returns : None
chris	0:cfb58054ab28	218	*
chris	0:cfb58054ab28	219	**************************************************************************************************************
chris	0:cfb58054ab28	220	*/
chris	0:cfb58054ab28	221
chris	0:cfb58054ab28	222	void USB_IRQHandler (void) __irq
chris	0:cfb58054ab28	223	{
chris	0:cfb58054ab28	224	USB_INT32U int_status;
chris	0:cfb58054ab28	225	USB_INT32U ie_status;
chris	0:cfb58054ab28	226
chris	0:cfb58054ab28	227	int_status = LPC_USB->HcInterruptStatus; /* Read Interrupt Status */
chris	0:cfb58054ab28	228	ie_status = LPC_USB->HcInterruptEnable; /* Read Interrupt enable status */
chris	0:cfb58054ab28	229
chris	0:cfb58054ab28	230	if (!(int_status & ie_status)) {
chris	0:cfb58054ab28	231	return;
chris	0:cfb58054ab28	232	} else {
chris	0:cfb58054ab28	233
chris	0:cfb58054ab28	234	int_status = int_status & ie_status;
chris	0:cfb58054ab28	235	if (int_status & OR_INTR_STATUS_RHSC) { /* Root hub status change interrupt */
chris	0:cfb58054ab28	236	if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
chris	0:cfb58054ab28	237	if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
chris	0:cfb58054ab28	238	/*
chris	0:cfb58054ab28	239	* When DRWE is on, Connect Status Change
chris	0:cfb58054ab28	240	* means a remote wakeup event.
chris	0:cfb58054ab28	241	*/
chris	0:cfb58054ab28	242	HOST_RhscIntr = 1;// JUST SOMETHING FOR A BREAKPOINT
chris	0:cfb58054ab28	243	}
chris	0:cfb58054ab28	244	else {
chris	0:cfb58054ab28	245	/*
chris	0:cfb58054ab28	246	* When DRWE is off, Connect Status Change
chris	0:cfb58054ab28	247	* is NOT a remote wakeup event
chris	0:cfb58054ab28	248	*/
chris	0:cfb58054ab28	249	if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
chris	0:cfb58054ab28	250	if (!gUSBConnected) {
chris	0:cfb58054ab28	251	HOST_TDControlStatus = 0;
chris	0:cfb58054ab28	252	HOST_WdhIntr = 0;
chris	0:cfb58054ab28	253	HOST_RhscIntr = 1;
chris	0:cfb58054ab28	254	gUSBConnected = 1;
chris	0:cfb58054ab28	255	}
chris	0:cfb58054ab28	256	else
chris	0:cfb58054ab28	257	PRINT_Log("Spurious status change (connected)?\n");
chris	0:cfb58054ab28	258	} else {
chris	0:cfb58054ab28	259	if (gUSBConnected) {
chris	0:cfb58054ab28	260	LPC_USB->HcInterruptEnable = 0; // why do we get multiple disc. rupts???
chris	0:cfb58054ab28	261	HOST_RhscIntr = 0;
chris	0:cfb58054ab28	262	gUSBConnected = 0;
chris	0:cfb58054ab28	263	}
chris	0:cfb58054ab28	264	else
chris	0:cfb58054ab28	265	PRINT_Log("Spurious status change (disconnected)?\n");
chris	0:cfb58054ab28	266	}
chris	0:cfb58054ab28	267	}
chris	0:cfb58054ab28	268	LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
chris	0:cfb58054ab28	269	}
chris	0:cfb58054ab28	270	if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
chris	0:cfb58054ab28	271	LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
chris	0:cfb58054ab28	272	}
chris	0:cfb58054ab28	273	}
chris	0:cfb58054ab28	274	if (int_status & OR_INTR_STATUS_WDH) { /* Writeback Done Head interrupt */
chris	0:cfb58054ab28	275	HOST_WdhIntr = 1;
chris	0:cfb58054ab28	276	HOST_TDControlStatus = (TDHead->Control >> 28) & 0xf;
chris	0:cfb58054ab28	277	}
chris	0:cfb58054ab28	278	LPC_USB->HcInterruptStatus = int_status; /* Clear interrupt status register */
chris	0:cfb58054ab28	279	}
chris	0:cfb58054ab28	280	return;
chris	0:cfb58054ab28	281	}
chris	0:cfb58054ab28	282
chris	0:cfb58054ab28	283	/*
chris	0:cfb58054ab28	284	**************************************************************************************************************
chris	0:cfb58054ab28	285	* PROCESS TRANSFER DESCRIPTOR
chris	0:cfb58054ab28	286	*
chris	0:cfb58054ab28	287	* Description: This function processes the transfer descriptor
chris	0:cfb58054ab28	288	*
chris	0:cfb58054ab28	289	* Arguments : ed Endpoint descriptor that contains this transfer descriptor
chris	0:cfb58054ab28	290	* token SETUP, IN, OUT
chris	0:cfb58054ab28	291	* buffer Current Buffer Pointer of the transfer descriptor
chris	0:cfb58054ab28	292	* buffer_len Length of the buffer
chris	0:cfb58054ab28	293	*
chris	0:cfb58054ab28	294	* Returns : OK if TD submission is successful
chris	0:cfb58054ab28	295	* ERROR if TD submission fails
chris	0:cfb58054ab28	296	*
chris	0:cfb58054ab28	297	**************************************************************************************************************
chris	0:cfb58054ab28	298	*/
chris	0:cfb58054ab28	299
chris	0:cfb58054ab28	300	USB_INT32S Host_ProcessTD (volatile HCED *ed,
chris	0:cfb58054ab28	301	volatile USB_INT32U token,
chris	0:cfb58054ab28	302	volatile USB_INT08U *buffer,
chris	0:cfb58054ab28	303	USB_INT32U buffer_len)
chris	0:cfb58054ab28	304	{
chris	0:cfb58054ab28	305	volatile USB_INT32U td_toggle;
chris	0:cfb58054ab28	306
chris	0:cfb58054ab28	307
chris	0:cfb58054ab28	308	if (ed == EDCtrl) {
chris	0:cfb58054ab28	309	if (token == TD_SETUP) {
chris	0:cfb58054ab28	310	td_toggle = TD_TOGGLE_0;
chris	0:cfb58054ab28	311	} else {
chris	0:cfb58054ab28	312	td_toggle = TD_TOGGLE_1;
chris	0:cfb58054ab28	313	}
chris	0:cfb58054ab28	314	} else {
chris	0:cfb58054ab28	315	td_toggle = 0;
chris	0:cfb58054ab28	316	}
chris	0:cfb58054ab28	317	TDHead->Control = (TD_ROUNDING \|
chris	0:cfb58054ab28	318	token \|
chris	0:cfb58054ab28	319	TD_DELAY_INT(0) \|
chris	0:cfb58054ab28	320	td_toggle \|
chris	0:cfb58054ab28	321	TD_CC);
chris	0:cfb58054ab28	322	TDTail->Control = 0;
chris	0:cfb58054ab28	323	TDHead->CurrBufPtr = (USB_INT32U) buffer;
chris	0:cfb58054ab28	324	TDTail->CurrBufPtr = 0;
chris	0:cfb58054ab28	325	TDHead->Next = (USB_INT32U) TDTail;
chris	0:cfb58054ab28	326	TDTail->Next = 0;
chris	0:cfb58054ab28	327	TDHead->BufEnd = (USB_INT32U)(buffer + (buffer_len - 1));
chris	0:cfb58054ab28	328	TDTail->BufEnd = 0;
chris	0:cfb58054ab28	329
chris	0:cfb58054ab28	330	ed->HeadTd = (USB_INT32U)TDHead \| ((ed->HeadTd) & 0x00000002);
chris	0:cfb58054ab28	331	ed->TailTd = (USB_INT32U)TDTail;
chris	0:cfb58054ab28	332	ed->Next = 0;
chris	0:cfb58054ab28	333
chris	0:cfb58054ab28	334	if (ed == EDCtrl) {
chris	0:cfb58054ab28	335	LPC_USB->HcControlHeadED = (USB_INT32U)ed;
chris	0:cfb58054ab28	336	LPC_USB->HcCommandStatus = LPC_USB->HcCommandStatus \| OR_CMD_STATUS_CLF;
chris	0:cfb58054ab28	337	LPC_USB->HcControl = LPC_USB->HcControl \| OR_CONTROL_CLE;
chris	0:cfb58054ab28	338	} else {
chris	0:cfb58054ab28	339	LPC_USB->HcBulkHeadED = (USB_INT32U)ed;
chris	0:cfb58054ab28	340	LPC_USB->HcCommandStatus = LPC_USB->HcCommandStatus \| OR_CMD_STATUS_BLF;
chris	0:cfb58054ab28	341	LPC_USB->HcControl = LPC_USB->HcControl \| OR_CONTROL_BLE;
chris	0:cfb58054ab28	342	}
chris	0:cfb58054ab28	343
chris	0:cfb58054ab28	344	Host_WDHWait();
chris	0:cfb58054ab28	345
chris	0:cfb58054ab28	346	// if (!(TDHead->Control & 0xF0000000)) {
chris	0:cfb58054ab28	347	if (!HOST_TDControlStatus) {
chris	0:cfb58054ab28	348	return (OK);
chris	0:cfb58054ab28	349	} else {
chris	0:cfb58054ab28	350	return (ERR_TD_FAIL);
chris	0:cfb58054ab28	351	}
chris	0:cfb58054ab28	352	}
chris	0:cfb58054ab28	353
chris	0:cfb58054ab28	354	/*
chris	0:cfb58054ab28	355	**************************************************************************************************************
chris	0:cfb58054ab28	356	* ENUMERATE THE DEVICE
chris	0:cfb58054ab28	357	*
chris	0:cfb58054ab28	358	* Description: This function is used to enumerate the device connected
chris	0:cfb58054ab28	359	*
chris	0:cfb58054ab28	360	* Arguments : None
chris	0:cfb58054ab28	361	*
chris	0:cfb58054ab28	362	* Returns : None
chris	0:cfb58054ab28	363	*
chris	0:cfb58054ab28	364	**************************************************************************************************************
chris	0:cfb58054ab28	365	*/
chris	0:cfb58054ab28	366
chris	0:cfb58054ab28	367	USB_INT32S Host_EnumDev (void)
chris	0:cfb58054ab28	368	{
chris	0:cfb58054ab28	369	USB_INT32S rc;
chris	0:cfb58054ab28	370
chris	0:cfb58054ab28	371	PRINT_Log("Connect a Mass Storage device\n");
chris	0:cfb58054ab28	372	while (!HOST_RhscIntr)
chris	0:cfb58054ab28	373	__WFI();
chris	0:cfb58054ab28	374	Host_DelayMS(100); /* USB 2.0 spec says atleast 50ms delay beore port reset */
chris	0:cfb58054ab28	375	LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS; // Initiate port reset
chris	0:cfb58054ab28	376	while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS)
chris	0:cfb58054ab28	377	__WFI(); // Wait for port reset to complete...
chris	0:cfb58054ab28	378	LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC; // ...and clear port reset signal
chris	0:cfb58054ab28	379	Host_DelayMS(200); /* Wait for 100 MS after port reset */
chris	0:cfb58054ab28	380
chris	0:cfb58054ab28	381	EDCtrl->Control = 8 << 16; /* Put max pkt size = 8 */
chris	0:cfb58054ab28	382	/* Read first 8 bytes of device desc */
chris	0:cfb58054ab28	383	rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_DEVICE, 0, TDBuffer, 8);
chris	0:cfb58054ab28	384	if (rc != OK) {
chris	0:cfb58054ab28	385	PRINT_Err(rc);
chris	0:cfb58054ab28	386	return (rc);
chris	0:cfb58054ab28	387	}
chris	0:cfb58054ab28	388	EDCtrl->Control = TDBuffer[7] << 16; /* Get max pkt size of endpoint 0 */
chris	0:cfb58054ab28	389	rc = HOST_SET_ADDRESS(1); /* Set the device address to 1 */
chris	0:cfb58054ab28	390	if (rc != OK) {
chris	0:cfb58054ab28	391	PRINT_Err(rc);
chris	0:cfb58054ab28	392	return (rc);
chris	0:cfb58054ab28	393	}
chris	0:cfb58054ab28	394	Host_DelayMS(2);
chris	0:cfb58054ab28	395	EDCtrl->Control = (EDCtrl->Control) \| 1; /* Modify control pipe with address 1 */
chris	0:cfb58054ab28	396	/* Get the configuration descriptor */
chris	0:cfb58054ab28	397	rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_CONFIGURATION, 0, TDBuffer, 9);
chris	0:cfb58054ab28	398	if (rc != OK) {
chris	0:cfb58054ab28	399	PRINT_Err(rc);
chris	0:cfb58054ab28	400	return (rc);
chris	0:cfb58054ab28	401	}
chris	0:cfb58054ab28	402	/* Get the first configuration data */
chris	0:cfb58054ab28	403	rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_CONFIGURATION, 0, TDBuffer, ReadLE16U(&TDBuffer[2]));
chris	0:cfb58054ab28	404	if (rc != OK) {
chris	0:cfb58054ab28	405	PRINT_Err(rc);
chris	0:cfb58054ab28	406	return (rc);
chris	0:cfb58054ab28	407	}
chris	0:cfb58054ab28	408	rc = MS_ParseConfiguration(); /* Parse the configuration */
chris	0:cfb58054ab28	409	if (rc != OK) {
chris	0:cfb58054ab28	410	PRINT_Err(rc);
chris	0:cfb58054ab28	411	return (rc);
chris	0:cfb58054ab28	412	}
chris	0:cfb58054ab28	413	rc = USBH_SET_CONFIGURATION(1); /* Select device configuration 1 */
chris	0:cfb58054ab28	414	if (rc != OK) {
chris	0:cfb58054ab28	415	PRINT_Err(rc);
chris	0:cfb58054ab28	416	}
chris	0:cfb58054ab28	417	Host_DelayMS(100); /* Some devices may require this delay */
chris	0:cfb58054ab28	418	return (rc);
chris	0:cfb58054ab28	419	}
chris	0:cfb58054ab28	420
chris	0:cfb58054ab28	421	/*
chris	0:cfb58054ab28	422	**************************************************************************************************************
chris	0:cfb58054ab28	423	* RECEIVE THE CONTROL INFORMATION
chris	0:cfb58054ab28	424	*
chris	0:cfb58054ab28	425	* Description: This function is used to receive the control information
chris	0:cfb58054ab28	426	*
chris	0:cfb58054ab28	427	* Arguments : bm_request_type
chris	0:cfb58054ab28	428	* b_request
chris	0:cfb58054ab28	429	* w_value
chris	0:cfb58054ab28	430	* w_index
chris	0:cfb58054ab28	431	* w_length
chris	0:cfb58054ab28	432	* buffer
chris	0:cfb58054ab28	433	*
chris	0:cfb58054ab28	434	* Returns : OK if Success
chris	0:cfb58054ab28	435	* ERROR if Failed
chris	0:cfb58054ab28	436	*
chris	0:cfb58054ab28	437	**************************************************************************************************************
chris	0:cfb58054ab28	438	*/
chris	0:cfb58054ab28	439
chris	0:cfb58054ab28	440	USB_INT32S Host_CtrlRecv ( USB_INT08U bm_request_type,
chris	0:cfb58054ab28	441	USB_INT08U b_request,
chris	0:cfb58054ab28	442	USB_INT16U w_value,
chris	0:cfb58054ab28	443	USB_INT16U w_index,
chris	0:cfb58054ab28	444	USB_INT16U w_length,
chris	0:cfb58054ab28	445	volatile USB_INT08U *buffer)
chris	0:cfb58054ab28	446	{
chris	0:cfb58054ab28	447	USB_INT32S rc;
chris	0:cfb58054ab28	448
chris	0:cfb58054ab28	449
chris	0:cfb58054ab28	450	Host_FillSetup(bm_request_type, b_request, w_value, w_index, w_length);
chris	0:cfb58054ab28	451	rc = Host_ProcessTD(EDCtrl, TD_SETUP, TDBuffer, 8);
chris	0:cfb58054ab28	452	if (rc == OK) {
chris	0:cfb58054ab28	453	if (w_length) {
chris	0:cfb58054ab28	454	rc = Host_ProcessTD(EDCtrl, TD_IN, TDBuffer, w_length);
chris	0:cfb58054ab28	455	}
chris	0:cfb58054ab28	456	if (rc == OK) {
chris	0:cfb58054ab28	457	rc = Host_ProcessTD(EDCtrl, TD_OUT, NULL, 0);
chris	0:cfb58054ab28	458	}
chris	0:cfb58054ab28	459	}
chris	0:cfb58054ab28	460	return (rc);
chris	0:cfb58054ab28	461	}
chris	0:cfb58054ab28	462
chris	0:cfb58054ab28	463	/*
chris	0:cfb58054ab28	464	**************************************************************************************************************
chris	0:cfb58054ab28	465	* SEND THE CONTROL INFORMATION
chris	0:cfb58054ab28	466	*
chris	0:cfb58054ab28	467	* Description: This function is used to send the control information
chris	0:cfb58054ab28	468	*
chris	0:cfb58054ab28	469	* Arguments : None
chris	0:cfb58054ab28	470	*
chris	0:cfb58054ab28	471	* Returns : OK if Success
chris	0:cfb58054ab28	472	* ERR_INVALID_BOOTSIG if Failed
chris	0:cfb58054ab28	473	*
chris	0:cfb58054ab28	474	**************************************************************************************************************
chris	0:cfb58054ab28	475	*/
chris	0:cfb58054ab28	476
chris	0:cfb58054ab28	477	USB_INT32S Host_CtrlSend ( USB_INT08U bm_request_type,
chris	0:cfb58054ab28	478	USB_INT08U b_request,
chris	0:cfb58054ab28	479	USB_INT16U w_value,
chris	0:cfb58054ab28	480	USB_INT16U w_index,
chris	0:cfb58054ab28	481	USB_INT16U w_length,
chris	0:cfb58054ab28	482	volatile USB_INT08U *buffer)
chris	0:cfb58054ab28	483	{
chris	0:cfb58054ab28	484	USB_INT32S rc;
chris	0:cfb58054ab28	485
chris	0:cfb58054ab28	486
chris	0:cfb58054ab28	487	Host_FillSetup(bm_request_type, b_request, w_value, w_index, w_length);
chris	0:cfb58054ab28	488
chris	0:cfb58054ab28	489	rc = Host_ProcessTD(EDCtrl, TD_SETUP, TDBuffer, 8);
chris	0:cfb58054ab28	490	if (rc == OK) {
chris	0:cfb58054ab28	491	if (w_length) {
chris	0:cfb58054ab28	492	rc = Host_ProcessTD(EDCtrl, TD_OUT, TDBuffer, w_length);
chris	0:cfb58054ab28	493	}
chris	0:cfb58054ab28	494	if (rc == OK) {
chris	0:cfb58054ab28	495	rc = Host_ProcessTD(EDCtrl, TD_IN, NULL, 0);
chris	0:cfb58054ab28	496	}
chris	0:cfb58054ab28	497	}
chris	0:cfb58054ab28	498	return (rc);
chris	0:cfb58054ab28	499	}
chris	0:cfb58054ab28	500
chris	0:cfb58054ab28	501	/*
chris	0:cfb58054ab28	502	**************************************************************************************************************
chris	0:cfb58054ab28	503	* FILL SETUP PACKET
chris	0:cfb58054ab28	504	*
chris	0:cfb58054ab28	505	* Description: This function is used to fill the setup packet
chris	0:cfb58054ab28	506	*
chris	0:cfb58054ab28	507	* Arguments : None
chris	0:cfb58054ab28	508	*
chris	0:cfb58054ab28	509	* Returns : OK if Success
chris	0:cfb58054ab28	510	* ERR_INVALID_BOOTSIG if Failed
chris	0:cfb58054ab28	511	*
chris	0:cfb58054ab28	512	**************************************************************************************************************
chris	0:cfb58054ab28	513	*/
chris	0:cfb58054ab28	514
chris	0:cfb58054ab28	515	void Host_FillSetup (USB_INT08U bm_request_type,
chris	0:cfb58054ab28	516	USB_INT08U b_request,
chris	0:cfb58054ab28	517	USB_INT16U w_value,
chris	0:cfb58054ab28	518	USB_INT16U w_index,
chris	0:cfb58054ab28	519	USB_INT16U w_length)
chris	0:cfb58054ab28	520	{
chris	0:cfb58054ab28	521	int i;
chris	0:cfb58054ab28	522	for (i=0;i<w_length;i++)
chris	0:cfb58054ab28	523	TDBuffer[i] = 0;
chris	0:cfb58054ab28	524
chris	0:cfb58054ab28	525	TDBuffer[0] = bm_request_type;
chris	0:cfb58054ab28	526	TDBuffer[1] = b_request;
chris	0:cfb58054ab28	527	WriteLE16U(&TDBuffer[2], w_value);
chris	0:cfb58054ab28	528	WriteLE16U(&TDBuffer[4], w_index);
chris	0:cfb58054ab28	529	WriteLE16U(&TDBuffer[6], w_length);
chris	0:cfb58054ab28	530	}
chris	0:cfb58054ab28	531
chris	0:cfb58054ab28	532
chris	0:cfb58054ab28	533
chris	0:cfb58054ab28	534	/*
chris	0:cfb58054ab28	535	**************************************************************************************************************
chris	0:cfb58054ab28	536	* INITIALIZE THE TRANSFER DESCRIPTOR
chris	0:cfb58054ab28	537	*
chris	0:cfb58054ab28	538	* Description: This function initializes transfer descriptor
chris	0:cfb58054ab28	539	*
chris	0:cfb58054ab28	540	* Arguments : Pointer to TD structure
chris	0:cfb58054ab28	541	*
chris	0:cfb58054ab28	542	* Returns : None
chris	0:cfb58054ab28	543	*
chris	0:cfb58054ab28	544	**************************************************************************************************************
chris	0:cfb58054ab28	545	*/
chris	0:cfb58054ab28	546
chris	0:cfb58054ab28	547	void Host_TDInit (volatile HCTD *td)
chris	0:cfb58054ab28	548	{
chris	0:cfb58054ab28	549
chris	0:cfb58054ab28	550	td->Control = 0;
chris	0:cfb58054ab28	551	td->CurrBufPtr = 0;
chris	0:cfb58054ab28	552	td->Next = 0;
chris	0:cfb58054ab28	553	td->BufEnd = 0;
chris	0:cfb58054ab28	554	}
chris	0:cfb58054ab28	555
chris	0:cfb58054ab28	556	/*
chris	0:cfb58054ab28	557	**************************************************************************************************************
chris	0:cfb58054ab28	558	* INITIALIZE THE ENDPOINT DESCRIPTOR
chris	0:cfb58054ab28	559	*
chris	0:cfb58054ab28	560	* Description: This function initializes endpoint descriptor
chris	0:cfb58054ab28	561	*
chris	0:cfb58054ab28	562	* Arguments : Pointer to ED strcuture
chris	0:cfb58054ab28	563	*
chris	0:cfb58054ab28	564	* Returns : None
chris	0:cfb58054ab28	565	*
chris	0:cfb58054ab28	566	**************************************************************************************************************
chris	0:cfb58054ab28	567	*/
chris	0:cfb58054ab28	568
chris	0:cfb58054ab28	569	void Host_EDInit (volatile HCED *ed)
chris	0:cfb58054ab28	570	{
chris	0:cfb58054ab28	571
chris	0:cfb58054ab28	572	ed->Control = 0;
chris	0:cfb58054ab28	573	ed->TailTd = 0;
chris	0:cfb58054ab28	574	ed->HeadTd = 0;
chris	0:cfb58054ab28	575	ed->Next = 0;
chris	0:cfb58054ab28	576	}
chris	0:cfb58054ab28	577
chris	0:cfb58054ab28	578	/*
chris	0:cfb58054ab28	579	**************************************************************************************************************
chris	0:cfb58054ab28	580	* INITIALIZE HOST CONTROLLER COMMUNICATIONS AREA
chris	0:cfb58054ab28	581	*
chris	0:cfb58054ab28	582	* Description: This function initializes host controller communications area
chris	0:cfb58054ab28	583	*
chris	0:cfb58054ab28	584	* Arguments : Pointer to HCCA
chris	0:cfb58054ab28	585	*
chris	0:cfb58054ab28	586	* Returns :
chris	0:cfb58054ab28	587	*
chris	0:cfb58054ab28	588	**************************************************************************************************************
chris	0:cfb58054ab28	589	*/
chris	0:cfb58054ab28	590
chris	0:cfb58054ab28	591	void Host_HCCAInit (volatile HCCA *hcca)
chris	0:cfb58054ab28	592	{
chris	0:cfb58054ab28	593	USB_INT32U i;
chris	0:cfb58054ab28	594
chris	0:cfb58054ab28	595
chris	0:cfb58054ab28	596	for (i = 0; i < 32; i++) {
chris	0:cfb58054ab28	597
chris	0:cfb58054ab28	598	hcca->IntTable[i] = 0;
chris	0:cfb58054ab28	599	hcca->FrameNumber = 0;
chris	0:cfb58054ab28	600	hcca->DoneHead = 0;
chris	0:cfb58054ab28	601	}
chris	0:cfb58054ab28	602
chris	0:cfb58054ab28	603	}
chris	0:cfb58054ab28	604
chris	0:cfb58054ab28	605	/*
chris	0:cfb58054ab28	606	**************************************************************************************************************
chris	0:cfb58054ab28	607	* WAIT FOR WDH INTERRUPT
chris	0:cfb58054ab28	608	*
chris	0:cfb58054ab28	609	* Description: This function is infinite loop which breaks when ever a WDH interrupt rises
chris	0:cfb58054ab28	610	*
chris	0:cfb58054ab28	611	* Arguments : None
chris	0:cfb58054ab28	612	*
chris	0:cfb58054ab28	613	* Returns : None
chris	0:cfb58054ab28	614	*
chris	0:cfb58054ab28	615	**************************************************************************************************************
chris	0:cfb58054ab28	616	*/
chris	0:cfb58054ab28	617
chris	0:cfb58054ab28	618	void Host_WDHWait (void)
chris	0:cfb58054ab28	619	{
chris	0:cfb58054ab28	620	while (!HOST_WdhIntr)
chris	0:cfb58054ab28	621	__WFI();
chris	0:cfb58054ab28	622
chris	0:cfb58054ab28	623	HOST_WdhIntr = 0;
chris	0:cfb58054ab28	624	}
chris	0:cfb58054ab28	625
chris	0:cfb58054ab28	626	/*
chris	0:cfb58054ab28	627	**************************************************************************************************************
chris	0:cfb58054ab28	628	* READ LE 32U
chris	0:cfb58054ab28	629	*
chris	0:cfb58054ab28	630	* Description: This function is used to read an unsigned integer from a character buffer in the platform
chris	0:cfb58054ab28	631	* containing little endian processor
chris	0:cfb58054ab28	632	*
chris	0:cfb58054ab28	633	* Arguments : pmem Pointer to the character buffer
chris	0:cfb58054ab28	634	*
chris	0:cfb58054ab28	635	* Returns : val Unsigned integer
chris	0:cfb58054ab28	636	*
chris	0:cfb58054ab28	637	**************************************************************************************************************
chris	0:cfb58054ab28	638	*/
chris	0:cfb58054ab28	639
chris	0:cfb58054ab28	640	USB_INT32U ReadLE32U (volatile USB_INT08U *pmem)
chris	0:cfb58054ab28	641	{
chris	0:cfb58054ab28	642	USB_INT32U val = (USB_INT32U)pmem;
chris	0:cfb58054ab28	643	#ifdef __BIG_ENDIAN
chris	0:cfb58054ab28	644	return __REV(val);
chris	0:cfb58054ab28	645	#else
chris	0:cfb58054ab28	646	return val;
chris	0:cfb58054ab28	647	#endif
chris	0:cfb58054ab28	648	}
chris	0:cfb58054ab28	649
chris	0:cfb58054ab28	650	/*
chris	0:cfb58054ab28	651	**************************************************************************************************************
chris	0:cfb58054ab28	652	* WRITE LE 32U
chris	0:cfb58054ab28	653	*
chris	0:cfb58054ab28	654	* Description: This function is used to write an unsigned integer into a charecter buffer in the platform
chris	0:cfb58054ab28	655	* containing little endian processor.
chris	0:cfb58054ab28	656	*
chris	0:cfb58054ab28	657	* Arguments : pmem Pointer to the charecter buffer
chris	0:cfb58054ab28	658	* val Integer value to be placed in the charecter buffer
chris	0:cfb58054ab28	659	*
chris	0:cfb58054ab28	660	* Returns : None
chris	0:cfb58054ab28	661	*
chris	0:cfb58054ab28	662	**************************************************************************************************************
chris	0:cfb58054ab28	663	*/
chris	0:cfb58054ab28	664
chris	0:cfb58054ab28	665	void WriteLE32U (volatile USB_INT08U *pmem,
chris	0:cfb58054ab28	666	USB_INT32U val)
chris	0:cfb58054ab28	667	{
chris	0:cfb58054ab28	668	#ifdef __BIG_ENDIAN
chris	0:cfb58054ab28	669	(USB_INT32U)pmem = __REV(val);
chris	0:cfb58054ab28	670	#else
chris	0:cfb58054ab28	671	(USB_INT32U)pmem = val;
chris	0:cfb58054ab28	672	#endif
chris	0:cfb58054ab28	673	}
chris	0:cfb58054ab28	674
chris	0:cfb58054ab28	675	/*
chris	0:cfb58054ab28	676	**************************************************************************************************************
chris	0:cfb58054ab28	677	* READ LE 16U
chris	0:cfb58054ab28	678	*
chris	0:cfb58054ab28	679	* Description: This function is used to read an unsigned short integer from a charecter buffer in the platform
chris	0:cfb58054ab28	680	* containing little endian processor
chris	0:cfb58054ab28	681	*
chris	0:cfb58054ab28	682	* Arguments : pmem Pointer to the charecter buffer
chris	0:cfb58054ab28	683	*
chris	0:cfb58054ab28	684	* Returns : val Unsigned short integer
chris	0:cfb58054ab28	685	*
chris	0:cfb58054ab28	686	**************************************************************************************************************
chris	0:cfb58054ab28	687	*/
chris	0:cfb58054ab28	688
chris	0:cfb58054ab28	689	USB_INT16U ReadLE16U (volatile USB_INT08U *pmem)
chris	0:cfb58054ab28	690	{
chris	0:cfb58054ab28	691	USB_INT16U val = (USB_INT16U)pmem;
chris	0:cfb58054ab28	692	#ifdef __BIG_ENDIAN
chris	0:cfb58054ab28	693	return __REV16(val);
chris	0:cfb58054ab28	694	#else
chris	0:cfb58054ab28	695	return val;
chris	0:cfb58054ab28	696	#endif
chris	0:cfb58054ab28	697	}
chris	0:cfb58054ab28	698
chris	0:cfb58054ab28	699	/*
chris	0:cfb58054ab28	700	**************************************************************************************************************
chris	0:cfb58054ab28	701	* WRITE LE 16U
chris	0:cfb58054ab28	702	*
chris	0:cfb58054ab28	703	* Description: This function is used to write an unsigned short integer into a charecter buffer in the
chris	0:cfb58054ab28	704	* platform containing little endian processor
chris	0:cfb58054ab28	705	*
chris	0:cfb58054ab28	706	* Arguments : pmem Pointer to the charecter buffer
chris	0:cfb58054ab28	707	* val Value to be placed in the charecter buffer
chris	0:cfb58054ab28	708	*
chris	0:cfb58054ab28	709	* Returns : None
chris	0:cfb58054ab28	710	*
chris	0:cfb58054ab28	711	**************************************************************************************************************
chris	0:cfb58054ab28	712	*/
chris	0:cfb58054ab28	713
chris	0:cfb58054ab28	714	void WriteLE16U (volatile USB_INT08U *pmem,
chris	0:cfb58054ab28	715	USB_INT16U val)
chris	0:cfb58054ab28	716	{
chris	0:cfb58054ab28	717	#ifdef __BIG_ENDIAN
chris	0:cfb58054ab28	718	(USB_INT16U)pmem = (__REV16(val) & 0xFFFF);
chris	0:cfb58054ab28	719	#else
chris	0:cfb58054ab28	720	(USB_INT16U)pmem = val;
chris	0:cfb58054ab28	721	#endif
chris	0:cfb58054ab28	722	}
chris	0:cfb58054ab28	723
chris	0:cfb58054ab28	724	/*
chris	0:cfb58054ab28	725	**************************************************************************************************************
chris	0:cfb58054ab28	726	* READ BE 32U
chris	0:cfb58054ab28	727	*
chris	0:cfb58054ab28	728	* Description: This function is used to read an unsigned integer from a charecter buffer in the platform
chris	0:cfb58054ab28	729	* containing big endian processor
chris	0:cfb58054ab28	730	*
chris	0:cfb58054ab28	731	* Arguments : pmem Pointer to the charecter buffer
chris	0:cfb58054ab28	732	*
chris	0:cfb58054ab28	733	* Returns : val Unsigned integer
chris	0:cfb58054ab28	734	*
chris	0:cfb58054ab28	735	**************************************************************************************************************
chris	0:cfb58054ab28	736	*/
chris	0:cfb58054ab28	737
chris	0:cfb58054ab28	738	USB_INT32U ReadBE32U (volatile USB_INT08U *pmem)
chris	0:cfb58054ab28	739	{
chris	0:cfb58054ab28	740	USB_INT32U val = (USB_INT32U)pmem;
chris	0:cfb58054ab28	741	#ifdef __BIG_ENDIAN
chris	0:cfb58054ab28	742	return val;
chris	0:cfb58054ab28	743	#else
chris	0:cfb58054ab28	744	return __REV(val);
chris	0:cfb58054ab28	745	#endif
chris	0:cfb58054ab28	746	}
chris	0:cfb58054ab28	747
chris	0:cfb58054ab28	748	/*
chris	0:cfb58054ab28	749	**************************************************************************************************************
chris	0:cfb58054ab28	750	* WRITE BE 32U
chris	0:cfb58054ab28	751	*
chris	0:cfb58054ab28	752	* Description: This function is used to write an unsigned integer into a charecter buffer in the platform
chris	0:cfb58054ab28	753	* containing big endian processor
chris	0:cfb58054ab28	754	*
chris	0:cfb58054ab28	755	* Arguments : pmem Pointer to the charecter buffer
chris	0:cfb58054ab28	756	* val Value to be placed in the charecter buffer
chris	0:cfb58054ab28	757	*
chris	0:cfb58054ab28	758	* Returns : None
chris	0:cfb58054ab28	759	*
chris	0:cfb58054ab28	760	**************************************************************************************************************
chris	0:cfb58054ab28	761	*/
chris	0:cfb58054ab28	762
chris	0:cfb58054ab28	763	void WriteBE32U (volatile USB_INT08U *pmem,
chris	0:cfb58054ab28	764	USB_INT32U val)
chris	0:cfb58054ab28	765	{
chris	0:cfb58054ab28	766	#ifdef __BIG_ENDIAN
chris	0:cfb58054ab28	767	(USB_INT32U)pmem = val;
chris	0:cfb58054ab28	768	#else
chris	0:cfb58054ab28	769	(USB_INT32U)pmem = __REV(val);
chris	0:cfb58054ab28	770	#endif
chris	0:cfb58054ab28	771	}
chris	0:cfb58054ab28	772
chris	0:cfb58054ab28	773	/*
chris	0:cfb58054ab28	774	**************************************************************************************************************
chris	0:cfb58054ab28	775	* READ BE 16U
chris	0:cfb58054ab28	776	*
chris	0:cfb58054ab28	777	* Description: This function is used to read an unsigned short integer from a charecter buffer in the platform
chris	0:cfb58054ab28	778	* containing big endian processor
chris	0:cfb58054ab28	779	*
chris	0:cfb58054ab28	780	* Arguments : pmem Pointer to the charecter buffer
chris	0:cfb58054ab28	781	*
chris	0:cfb58054ab28	782	* Returns : val Unsigned short integer
chris	0:cfb58054ab28	783	*
chris	0:cfb58054ab28	784	**************************************************************************************************************
chris	0:cfb58054ab28	785	*/
chris	0:cfb58054ab28	786
chris	0:cfb58054ab28	787	USB_INT16U ReadBE16U (volatile USB_INT08U *pmem)
chris	0:cfb58054ab28	788	{
chris	0:cfb58054ab28	789	USB_INT16U val = (USB_INT16U)pmem;
chris	0:cfb58054ab28	790	#ifdef __BIG_ENDIAN
chris	0:cfb58054ab28	791	return val;
chris	0:cfb58054ab28	792	#else
chris	0:cfb58054ab28	793	return __REV16(val);
chris	0:cfb58054ab28	794	#endif
chris	0:cfb58054ab28	795	}
chris	0:cfb58054ab28	796
chris	0:cfb58054ab28	797	/*
chris	0:cfb58054ab28	798	**************************************************************************************************************
chris	0:cfb58054ab28	799	* WRITE BE 16U
chris	0:cfb58054ab28	800	*
chris	0:cfb58054ab28	801	* Description: This function is used to write an unsigned short integer into the charecter buffer in the
chris	0:cfb58054ab28	802	* platform containing big endian processor
chris	0:cfb58054ab28	803	*
chris	0:cfb58054ab28	804	* Arguments : pmem Pointer to the charecter buffer
chris	0:cfb58054ab28	805	* val Value to be placed in the charecter buffer
chris	0:cfb58054ab28	806	*
chris	0:cfb58054ab28	807	* Returns : None
chris	0:cfb58054ab28	808	*
chris	0:cfb58054ab28	809	**************************************************************************************************************
chris	0:cfb58054ab28	810	*/
chris	0:cfb58054ab28	811
chris	0:cfb58054ab28	812	void WriteBE16U (volatile USB_INT08U *pmem,
chris	0:cfb58054ab28	813	USB_INT16U val)
chris	0:cfb58054ab28	814	{
chris	0:cfb58054ab28	815	#ifdef __BIG_ENDIAN
chris	0:cfb58054ab28	816	(USB_INT16U)pmem = val;
chris	0:cfb58054ab28	817	#else
chris	0:cfb58054ab28	818	(USB_INT16U)pmem = (__REV16(val) & 0xFFFF);
chris	0:cfb58054ab28	819	#endif
chris	0:cfb58054ab28	820	}

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Type:	Program
Created:	20 Feb 2010
Imports:	246
Forks:	0
Commits:	1
Dependents:	3
Dependencies:	0
Followers:	8

USBHostLite/usbhost_lpc17xx.c@0:cfb58054ab28, 2010-02-20 (annotated)

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