Diff: scmRTOS/CortexM3/device.h

Revision:

0:331db0b44b67

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/scmRTOS/CortexM3/device.h	Tue Sep 21 19:48:05 2010 +0000
@@ -0,0 +1,60 @@
+//******************************************************************************
+//*
+//*     FULLNAME:  Single-Chip Microcontroller Real-Time Operating System
+//*
+//*     NICKNAME:  scmRTOS
+//*
+//*     PROCESSOR: ARM Cortex-M3 
+//*
+//*     TOOLKIT:   EWARM (IAR Systems)
+//*
+//*     PURPOSE:   Device Definitions
+//*
+//*     Version: 3.10
+//*
+//*     $Revision: 196 $
+//*     $Date:: 2008-06-19 #$
+//*
+//*     Copyright (c) 2003-2010, Harry E. Zhurov
+//*
+//*     Permission is hereby granted, free of charge, to any person 
+//*     obtaining  a copy of this software and associated documentation 
+//*     files (the "Software"), to deal in the Software without restriction, 
+//*     including without limitation the rights to use, copy, modify, merge, 
+//*     publish, distribute, sublicense, and/or sell copies of the Software, 
+//*     and to permit persons to whom the Software is furnished to do so, 
+//*     subject to the following conditions:
+//*
+//*     The above copyright notice and this permission notice shall be included 
+//*     in all copies or substantial portions of the Software.
+//*
+//*     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
+//*     EXPRESS  OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
+//*     MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
+//*     IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
+//*     CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//*     TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH 
+//*     THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+//*
+//*     =================================================================
+//*     See http://scmrtos.sourceforge.net for documentation, latest
+//*     information, license and contact details.
+//*     =================================================================
+//*
+//******************************************************************************
+//*     Ported by Andrey Chuikin, Copyright (c) 2008-2010
+
+#ifndef DEVICE_H
+#define DEVICE_H
+
+#include <commdefs.h>
+
+//------------------------------------------------------------------------------
+// Definitions for some processor registers in order to not include specific
+// header file for various Cortex-M3 processor derivatives.
+#define CPU_ICSR            ( ( sfr_dword *) 0xE000ED04 )   // Interrupt Control State Register
+#define CPU_SYSTICKCSR      ( ( sfr_dword *) 0xE000E010 )   // SysTick Control and Status Register
+#define CPU_SYSTICKCSR_EINT 0x02                            // Bit for enable/disable SysTick interrupt
+
+
+#endif  /* DEVICE_H */