Hiroh Satoh / mbed-dev

mbed library sources. Supersedes mbed-src.

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Fork of mbed-dev by mbed official

targets/cmsis/core_cm4.h@19:112740acecfa, 2015-11-10 (annotated)

Committer:
mbed_official
Date:
Tue Nov 10 09:30:11 2015 +0000
Revision:
19:112740acecfa
Parent:
0:9b334a45a8ff 
Synchronized with git revision 7218418919aeaf775fb8d386ea7ee0dfc0c80ff9



Full URL: https://github.com/mbedmicro/mbed/commit/7218418919aeaf775fb8d386ea7ee0dfc0c80ff9/



DISCO_F469NI - add disco F469NI support

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file core_cm4.h
bogdanm 0:9b334a45a8ff 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
mbed_official 19:112740acecfa 4 * @version V4.10
mbed_official 19:112740acecfa 5 * @date 18. March 2015
bogdanm 0:9b334a45a8ff 6 *
bogdanm 0:9b334a45a8ff 7 * @note
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 ******************************************************************************/
mbed_official 19:112740acecfa 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
bogdanm 0:9b334a45a8ff 11
bogdanm 0:9b334a45a8ff 12 All rights reserved.
bogdanm 0:9b334a45a8ff 13 Redistribution and use in source and binary forms, with or without
bogdanm 0:9b334a45a8ff 14 modification, are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 15 - Redistributions of source code must retain the above copyright
bogdanm 0:9b334a45a8ff 16 notice, this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 0:9b334a45a8ff 18 notice, this list of conditions and the following disclaimer in the
bogdanm 0:9b334a45a8ff 19 documentation and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 0:9b334a45a8ff 21 to endorse or promote products derived from this software without
bogdanm 0:9b334a45a8ff 22 specific prior written permission.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 0:9b334a45a8ff 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 0:9b334a45a8ff 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 0:9b334a45a8ff 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 0:9b334a45a8ff 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 0:9b334a45a8ff 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 0:9b334a45a8ff 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 0:9b334a45a8ff 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 0:9b334a45a8ff 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 35 ---------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 #if defined ( __ICCARM__ )
bogdanm 0:9b334a45a8ff 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 0:9b334a45a8ff 40 #endif
bogdanm 0:9b334a45a8ff 41
mbed_official 19:112740acecfa 42 #ifndef __CORE_CM4_H_GENERIC
mbed_official 19:112740acecfa 43 #define __CORE_CM4_H_GENERIC
mbed_official 19:112740acecfa 44
bogdanm 0:9b334a45a8ff 45 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 46 extern "C" {
bogdanm 0:9b334a45a8ff 47 #endif
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 0:9b334a45a8ff 50 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 0:9b334a45a8ff 53 Function definitions in header files are used to allow 'inlining'.
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 0:9b334a45a8ff 56 Unions are used for effective representation of core registers.
bogdanm 0:9b334a45a8ff 57
bogdanm 0:9b334a45a8ff 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 0:9b334a45a8ff 59 Function-like macros are used to allow more efficient code.
bogdanm 0:9b334a45a8ff 60 */
bogdanm 0:9b334a45a8ff 61
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 /*******************************************************************************
bogdanm 0:9b334a45a8ff 64 * CMSIS definitions
bogdanm 0:9b334a45a8ff 65 ******************************************************************************/
bogdanm 0:9b334a45a8ff 66 /** \ingroup Cortex_M4
bogdanm 0:9b334a45a8ff 67 @{
bogdanm 0:9b334a45a8ff 68 */
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 /* CMSIS CM4 definitions */
mbed_official 19:112740acecfa 71 #define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
mbed_official 19:112740acecfa 72 #define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
bogdanm 0:9b334a45a8ff 73 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
bogdanm 0:9b334a45a8ff 74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76 #define __CORTEX_M (0x04) /*!< Cortex-M Core */
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78
bogdanm 0:9b334a45a8ff 79 #if defined ( __CC_ARM )
bogdanm 0:9b334a45a8ff 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 0:9b334a45a8ff 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 0:9b334a45a8ff 82 #define __STATIC_INLINE static __inline
bogdanm 0:9b334a45a8ff 83
mbed_official 19:112740acecfa 84 #elif defined ( __GNUC__ )
mbed_official 19:112740acecfa 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
mbed_official 19:112740acecfa 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
mbed_official 19:112740acecfa 87 #define __STATIC_INLINE static inline
mbed_official 19:112740acecfa 88
bogdanm 0:9b334a45a8ff 89 #elif defined ( __ICCARM__ )
bogdanm 0:9b334a45a8ff 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 0:9b334a45a8ff 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 0:9b334a45a8ff 92 #define __STATIC_INLINE static inline
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 #elif defined ( __TMS470__ )
bogdanm 0:9b334a45a8ff 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
bogdanm 0:9b334a45a8ff 96 #define __STATIC_INLINE static inline
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 #elif defined ( __TASKING__ )
bogdanm 0:9b334a45a8ff 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 0:9b334a45a8ff 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 0:9b334a45a8ff 101 #define __STATIC_INLINE static inline
bogdanm 0:9b334a45a8ff 102
mbed_official 19:112740acecfa 103 #elif defined ( __CSMC__ )
mbed_official 19:112740acecfa 104 #define __packed
mbed_official 19:112740acecfa 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
mbed_official 19:112740acecfa 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
mbed_official 19:112740acecfa 107 #define __STATIC_INLINE static inline
mbed_official 19:112740acecfa 108
bogdanm 0:9b334a45a8ff 109 #endif
bogdanm 0:9b334a45a8ff 110
mbed_official 19:112740acecfa 111 /** __FPU_USED indicates whether an FPU is used or not.
mbed_official 19:112740acecfa 112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
bogdanm 0:9b334a45a8ff 113 */
bogdanm 0:9b334a45a8ff 114 #if defined ( __CC_ARM )
bogdanm 0:9b334a45a8ff 115 #if defined __TARGET_FPU_VFP
bogdanm 0:9b334a45a8ff 116 #if (__FPU_PRESENT == 1)
bogdanm 0:9b334a45a8ff 117 #define __FPU_USED 1
bogdanm 0:9b334a45a8ff 118 #else
bogdanm 0:9b334a45a8ff 119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 0:9b334a45a8ff 120 #define __FPU_USED 0
bogdanm 0:9b334a45a8ff 121 #endif
bogdanm 0:9b334a45a8ff 122 #else
bogdanm 0:9b334a45a8ff 123 #define __FPU_USED 0
bogdanm 0:9b334a45a8ff 124 #endif
bogdanm 0:9b334a45a8ff 125
mbed_official 19:112740acecfa 126 #elif defined ( __GNUC__ )
mbed_official 19:112740acecfa 127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mbed_official 19:112740acecfa 128 #if (__FPU_PRESENT == 1)
mbed_official 19:112740acecfa 129 #define __FPU_USED 1
mbed_official 19:112740acecfa 130 #else
mbed_official 19:112740acecfa 131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 19:112740acecfa 132 #define __FPU_USED 0
mbed_official 19:112740acecfa 133 #endif
mbed_official 19:112740acecfa 134 #else
mbed_official 19:112740acecfa 135 #define __FPU_USED 0
mbed_official 19:112740acecfa 136 #endif
mbed_official 19:112740acecfa 137
bogdanm 0:9b334a45a8ff 138 #elif defined ( __ICCARM__ )
bogdanm 0:9b334a45a8ff 139 #if defined __ARMVFP__
bogdanm 0:9b334a45a8ff 140 #if (__FPU_PRESENT == 1)
bogdanm 0:9b334a45a8ff 141 #define __FPU_USED 1
bogdanm 0:9b334a45a8ff 142 #else
bogdanm 0:9b334a45a8ff 143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 0:9b334a45a8ff 144 #define __FPU_USED 0
bogdanm 0:9b334a45a8ff 145 #endif
bogdanm 0:9b334a45a8ff 146 #else
bogdanm 0:9b334a45a8ff 147 #define __FPU_USED 0
bogdanm 0:9b334a45a8ff 148 #endif
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 #elif defined ( __TMS470__ )
bogdanm 0:9b334a45a8ff 151 #if defined __TI_VFP_SUPPORT__
bogdanm 0:9b334a45a8ff 152 #if (__FPU_PRESENT == 1)
bogdanm 0:9b334a45a8ff 153 #define __FPU_USED 1
bogdanm 0:9b334a45a8ff 154 #else
bogdanm 0:9b334a45a8ff 155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 0:9b334a45a8ff 156 #define __FPU_USED 0
bogdanm 0:9b334a45a8ff 157 #endif
bogdanm 0:9b334a45a8ff 158 #else
bogdanm 0:9b334a45a8ff 159 #define __FPU_USED 0
bogdanm 0:9b334a45a8ff 160 #endif
bogdanm 0:9b334a45a8ff 161
mbed_official 19:112740acecfa 162 #elif defined ( __TASKING__ )
mbed_official 19:112740acecfa 163 #if defined __FPU_VFP__
bogdanm 0:9b334a45a8ff 164 #if (__FPU_PRESENT == 1)
bogdanm 0:9b334a45a8ff 165 #define __FPU_USED 1
bogdanm 0:9b334a45a8ff 166 #else
mbed_official 19:112740acecfa 167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 0:9b334a45a8ff 168 #define __FPU_USED 0
bogdanm 0:9b334a45a8ff 169 #endif
bogdanm 0:9b334a45a8ff 170 #else
bogdanm 0:9b334a45a8ff 171 #define __FPU_USED 0
bogdanm 0:9b334a45a8ff 172 #endif
bogdanm 0:9b334a45a8ff 173
mbed_official 19:112740acecfa 174 #elif defined ( __CSMC__ ) /* Cosmic */
mbed_official 19:112740acecfa 175 #if ( __CSMC__ & 0x400) // FPU present for parser
bogdanm 0:9b334a45a8ff 176 #if (__FPU_PRESENT == 1)
bogdanm 0:9b334a45a8ff 177 #define __FPU_USED 1
bogdanm 0:9b334a45a8ff 178 #else
bogdanm 0:9b334a45a8ff 179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 0:9b334a45a8ff 180 #define __FPU_USED 0
bogdanm 0:9b334a45a8ff 181 #endif
bogdanm 0:9b334a45a8ff 182 #else
bogdanm 0:9b334a45a8ff 183 #define __FPU_USED 0
bogdanm 0:9b334a45a8ff 184 #endif
bogdanm 0:9b334a45a8ff 185 #endif
bogdanm 0:9b334a45a8ff 186
bogdanm 0:9b334a45a8ff 187 #include <stdint.h> /* standard types definitions */
bogdanm 0:9b334a45a8ff 188 #include <core_cmInstr.h> /* Core Instruction Access */
bogdanm 0:9b334a45a8ff 189 #include <core_cmFunc.h> /* Core Function Access */
mbed_official 19:112740acecfa 190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
mbed_official 19:112740acecfa 191
mbed_official 19:112740acecfa 192 #ifdef __cplusplus
mbed_official 19:112740acecfa 193 }
mbed_official 19:112740acecfa 194 #endif
bogdanm 0:9b334a45a8ff 195
bogdanm 0:9b334a45a8ff 196 #endif /* __CORE_CM4_H_GENERIC */
bogdanm 0:9b334a45a8ff 197
bogdanm 0:9b334a45a8ff 198 #ifndef __CMSIS_GENERIC
bogdanm 0:9b334a45a8ff 199
bogdanm 0:9b334a45a8ff 200 #ifndef __CORE_CM4_H_DEPENDANT
bogdanm 0:9b334a45a8ff 201 #define __CORE_CM4_H_DEPENDANT
bogdanm 0:9b334a45a8ff 202
mbed_official 19:112740acecfa 203 #ifdef __cplusplus
mbed_official 19:112740acecfa 204 extern "C" {
mbed_official 19:112740acecfa 205 #endif
mbed_official 19:112740acecfa 206
bogdanm 0:9b334a45a8ff 207 /* check device defines and use defaults */
bogdanm 0:9b334a45a8ff 208 #if defined __CHECK_DEVICE_DEFINES
bogdanm 0:9b334a45a8ff 209 #ifndef __CM4_REV
bogdanm 0:9b334a45a8ff 210 #define __CM4_REV 0x0000
bogdanm 0:9b334a45a8ff 211 #warning "__CM4_REV not defined in device header file; using default!"
bogdanm 0:9b334a45a8ff 212 #endif
bogdanm 0:9b334a45a8ff 213
bogdanm 0:9b334a45a8ff 214 #ifndef __FPU_PRESENT
bogdanm 0:9b334a45a8ff 215 #define __FPU_PRESENT 0
bogdanm 0:9b334a45a8ff 216 #warning "__FPU_PRESENT not defined in device header file; using default!"
bogdanm 0:9b334a45a8ff 217 #endif
bogdanm 0:9b334a45a8ff 218
bogdanm 0:9b334a45a8ff 219 #ifndef __MPU_PRESENT
bogdanm 0:9b334a45a8ff 220 #define __MPU_PRESENT 0
bogdanm 0:9b334a45a8ff 221 #warning "__MPU_PRESENT not defined in device header file; using default!"
bogdanm 0:9b334a45a8ff 222 #endif
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 #ifndef __NVIC_PRIO_BITS
bogdanm 0:9b334a45a8ff 225 #define __NVIC_PRIO_BITS 4
bogdanm 0:9b334a45a8ff 226 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 0:9b334a45a8ff 227 #endif
bogdanm 0:9b334a45a8ff 228
bogdanm 0:9b334a45a8ff 229 #ifndef __Vendor_SysTickConfig
bogdanm 0:9b334a45a8ff 230 #define __Vendor_SysTickConfig 0
bogdanm 0:9b334a45a8ff 231 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 0:9b334a45a8ff 232 #endif
bogdanm 0:9b334a45a8ff 233 #endif
bogdanm 0:9b334a45a8ff 234
bogdanm 0:9b334a45a8ff 235 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 0:9b334a45a8ff 236 /**
bogdanm 0:9b334a45a8ff 237 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 0:9b334a45a8ff 238
bogdanm 0:9b334a45a8ff 239 <strong>IO Type Qualifiers</strong> are used
bogdanm 0:9b334a45a8ff 240 \li to specify the access to peripheral variables.
bogdanm 0:9b334a45a8ff 241 \li for automatic generation of peripheral register debug information.
bogdanm 0:9b334a45a8ff 242 */
bogdanm 0:9b334a45a8ff 243 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 244 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 0:9b334a45a8ff 245 #else
bogdanm 0:9b334a45a8ff 246 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 0:9b334a45a8ff 247 #endif
bogdanm 0:9b334a45a8ff 248 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 0:9b334a45a8ff 249 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 0:9b334a45a8ff 250
bogdanm 0:9b334a45a8ff 251 /*@} end of group Cortex_M4 */
bogdanm 0:9b334a45a8ff 252
bogdanm 0:9b334a45a8ff 253
bogdanm 0:9b334a45a8ff 254
bogdanm 0:9b334a45a8ff 255 /*******************************************************************************
bogdanm 0:9b334a45a8ff 256 * Register Abstraction
bogdanm 0:9b334a45a8ff 257 Core Register contain:
bogdanm 0:9b334a45a8ff 258 - Core Register
bogdanm 0:9b334a45a8ff 259 - Core NVIC Register
bogdanm 0:9b334a45a8ff 260 - Core SCB Register
bogdanm 0:9b334a45a8ff 261 - Core SysTick Register
bogdanm 0:9b334a45a8ff 262 - Core Debug Register
bogdanm 0:9b334a45a8ff 263 - Core MPU Register
bogdanm 0:9b334a45a8ff 264 - Core FPU Register
bogdanm 0:9b334a45a8ff 265 ******************************************************************************/
bogdanm 0:9b334a45a8ff 266 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 0:9b334a45a8ff 267 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 0:9b334a45a8ff 268 */
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 271 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 0:9b334a45a8ff 272 \brief Core Register type definitions.
bogdanm 0:9b334a45a8ff 273 @{
bogdanm 0:9b334a45a8ff 274 */
bogdanm 0:9b334a45a8ff 275
bogdanm 0:9b334a45a8ff 276 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 0:9b334a45a8ff 277 */
bogdanm 0:9b334a45a8ff 278 typedef union
bogdanm 0:9b334a45a8ff 279 {
bogdanm 0:9b334a45a8ff 280 struct
bogdanm 0:9b334a45a8ff 281 {
bogdanm 0:9b334a45a8ff 282 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
bogdanm 0:9b334a45a8ff 283 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 0:9b334a45a8ff 284 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
bogdanm 0:9b334a45a8ff 285 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 0:9b334a45a8ff 286 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 0:9b334a45a8ff 287 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 0:9b334a45a8ff 288 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 0:9b334a45a8ff 289 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 0:9b334a45a8ff 290 } b; /*!< Structure used for bit access */
bogdanm 0:9b334a45a8ff 291 uint32_t w; /*!< Type used for word access */
bogdanm 0:9b334a45a8ff 292 } APSR_Type;
bogdanm 0:9b334a45a8ff 293
mbed_official 19:112740acecfa 294 /* APSR Register Definitions */
mbed_official 19:112740acecfa 295 #define APSR_N_Pos 31 /*!< APSR: N Position */
mbed_official 19:112740acecfa 296 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
mbed_official 19:112740acecfa 297
mbed_official 19:112740acecfa 298 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
mbed_official 19:112740acecfa 299 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
mbed_official 19:112740acecfa 300
mbed_official 19:112740acecfa 301 #define APSR_C_Pos 29 /*!< APSR: C Position */
mbed_official 19:112740acecfa 302 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
mbed_official 19:112740acecfa 303
mbed_official 19:112740acecfa 304 #define APSR_V_Pos 28 /*!< APSR: V Position */
mbed_official 19:112740acecfa 305 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
mbed_official 19:112740acecfa 306
mbed_official 19:112740acecfa 307 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
mbed_official 19:112740acecfa 308 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
mbed_official 19:112740acecfa 309
mbed_official 19:112740acecfa 310 #define APSR_GE_Pos 16 /*!< APSR: GE Position */
mbed_official 19:112740acecfa 311 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
mbed_official 19:112740acecfa 312
bogdanm 0:9b334a45a8ff 313
bogdanm 0:9b334a45a8ff 314 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 0:9b334a45a8ff 315 */
bogdanm 0:9b334a45a8ff 316 typedef union
bogdanm 0:9b334a45a8ff 317 {
bogdanm 0:9b334a45a8ff 318 struct
bogdanm 0:9b334a45a8ff 319 {
bogdanm 0:9b334a45a8ff 320 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 0:9b334a45a8ff 321 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
bogdanm 0:9b334a45a8ff 322 } b; /*!< Structure used for bit access */
bogdanm 0:9b334a45a8ff 323 uint32_t w; /*!< Type used for word access */
bogdanm 0:9b334a45a8ff 324 } IPSR_Type;
bogdanm 0:9b334a45a8ff 325
mbed_official 19:112740acecfa 326 /* IPSR Register Definitions */
mbed_official 19:112740acecfa 327 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
mbed_official 19:112740acecfa 328 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
mbed_official 19:112740acecfa 329
bogdanm 0:9b334a45a8ff 330
bogdanm 0:9b334a45a8ff 331 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 0:9b334a45a8ff 332 */
bogdanm 0:9b334a45a8ff 333 typedef union
bogdanm 0:9b334a45a8ff 334 {
bogdanm 0:9b334a45a8ff 335 struct
bogdanm 0:9b334a45a8ff 336 {
bogdanm 0:9b334a45a8ff 337 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 0:9b334a45a8ff 338 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
bogdanm 0:9b334a45a8ff 339 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 0:9b334a45a8ff 340 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
bogdanm 0:9b334a45a8ff 341 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
bogdanm 0:9b334a45a8ff 342 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
bogdanm 0:9b334a45a8ff 343 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 0:9b334a45a8ff 344 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 0:9b334a45a8ff 345 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 0:9b334a45a8ff 346 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 0:9b334a45a8ff 347 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 0:9b334a45a8ff 348 } b; /*!< Structure used for bit access */
bogdanm 0:9b334a45a8ff 349 uint32_t w; /*!< Type used for word access */
bogdanm 0:9b334a45a8ff 350 } xPSR_Type;
bogdanm 0:9b334a45a8ff 351
mbed_official 19:112740acecfa 352 /* xPSR Register Definitions */
mbed_official 19:112740acecfa 353 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
mbed_official 19:112740acecfa 354 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
mbed_official 19:112740acecfa 355
mbed_official 19:112740acecfa 356 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
mbed_official 19:112740acecfa 357 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
mbed_official 19:112740acecfa 358
mbed_official 19:112740acecfa 359 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
mbed_official 19:112740acecfa 360 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
mbed_official 19:112740acecfa 361
mbed_official 19:112740acecfa 362 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
mbed_official 19:112740acecfa 363 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
mbed_official 19:112740acecfa 364
mbed_official 19:112740acecfa 365 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
mbed_official 19:112740acecfa 366 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
mbed_official 19:112740acecfa 367
mbed_official 19:112740acecfa 368 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
mbed_official 19:112740acecfa 369 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
mbed_official 19:112740acecfa 370
mbed_official 19:112740acecfa 371 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
mbed_official 19:112740acecfa 372 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
mbed_official 19:112740acecfa 373
mbed_official 19:112740acecfa 374 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
mbed_official 19:112740acecfa 375 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
mbed_official 19:112740acecfa 376
mbed_official 19:112740acecfa 377 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
mbed_official 19:112740acecfa 378 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
mbed_official 19:112740acecfa 379
bogdanm 0:9b334a45a8ff 380
bogdanm 0:9b334a45a8ff 381 /** \brief Union type to access the Control Registers (CONTROL).
bogdanm 0:9b334a45a8ff 382 */
bogdanm 0:9b334a45a8ff 383 typedef union
bogdanm 0:9b334a45a8ff 384 {
bogdanm 0:9b334a45a8ff 385 struct
bogdanm 0:9b334a45a8ff 386 {
bogdanm 0:9b334a45a8ff 387 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
bogdanm 0:9b334a45a8ff 388 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
bogdanm 0:9b334a45a8ff 389 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
bogdanm 0:9b334a45a8ff 390 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
bogdanm 0:9b334a45a8ff 391 } b; /*!< Structure used for bit access */
bogdanm 0:9b334a45a8ff 392 uint32_t w; /*!< Type used for word access */
bogdanm 0:9b334a45a8ff 393 } CONTROL_Type;
bogdanm 0:9b334a45a8ff 394
mbed_official 19:112740acecfa 395 /* CONTROL Register Definitions */
mbed_official 19:112740acecfa 396 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
mbed_official 19:112740acecfa 397 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
mbed_official 19:112740acecfa 398
mbed_official 19:112740acecfa 399 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
mbed_official 19:112740acecfa 400 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
mbed_official 19:112740acecfa 401
mbed_official 19:112740acecfa 402 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
mbed_official 19:112740acecfa 403 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
mbed_official 19:112740acecfa 404
bogdanm 0:9b334a45a8ff 405 /*@} end of group CMSIS_CORE */
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407
bogdanm 0:9b334a45a8ff 408 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 409 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm 0:9b334a45a8ff 410 \brief Type definitions for the NVIC Registers
bogdanm 0:9b334a45a8ff 411 @{
bogdanm 0:9b334a45a8ff 412 */
bogdanm 0:9b334a45a8ff 413
bogdanm 0:9b334a45a8ff 414 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 0:9b334a45a8ff 415 */
bogdanm 0:9b334a45a8ff 416 typedef struct
bogdanm 0:9b334a45a8ff 417 {
bogdanm 0:9b334a45a8ff 418 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
bogdanm 0:9b334a45a8ff 419 uint32_t RESERVED0[24];
bogdanm 0:9b334a45a8ff 420 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
bogdanm 0:9b334a45a8ff 421 uint32_t RSERVED1[24];
bogdanm 0:9b334a45a8ff 422 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
bogdanm 0:9b334a45a8ff 423 uint32_t RESERVED2[24];
bogdanm 0:9b334a45a8ff 424 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
bogdanm 0:9b334a45a8ff 425 uint32_t RESERVED3[24];
bogdanm 0:9b334a45a8ff 426 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
bogdanm 0:9b334a45a8ff 427 uint32_t RESERVED4[56];
bogdanm 0:9b334a45a8ff 428 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
bogdanm 0:9b334a45a8ff 429 uint32_t RESERVED5[644];
bogdanm 0:9b334a45a8ff 430 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
bogdanm 0:9b334a45a8ff 431 } NVIC_Type;
bogdanm 0:9b334a45a8ff 432
bogdanm 0:9b334a45a8ff 433 /* Software Triggered Interrupt Register Definitions */
bogdanm 0:9b334a45a8ff 434 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
mbed_official 19:112740acecfa 435 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
bogdanm 0:9b334a45a8ff 436
bogdanm 0:9b334a45a8ff 437 /*@} end of group CMSIS_NVIC */
bogdanm 0:9b334a45a8ff 438
bogdanm 0:9b334a45a8ff 439
bogdanm 0:9b334a45a8ff 440 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 441 \defgroup CMSIS_SCB System Control Block (SCB)
bogdanm 0:9b334a45a8ff 442 \brief Type definitions for the System Control Block Registers
bogdanm 0:9b334a45a8ff 443 @{
bogdanm 0:9b334a45a8ff 444 */
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 /** \brief Structure type to access the System Control Block (SCB).
bogdanm 0:9b334a45a8ff 447 */
bogdanm 0:9b334a45a8ff 448 typedef struct
bogdanm 0:9b334a45a8ff 449 {
bogdanm 0:9b334a45a8ff 450 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
bogdanm 0:9b334a45a8ff 451 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
bogdanm 0:9b334a45a8ff 452 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
bogdanm 0:9b334a45a8ff 453 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
bogdanm 0:9b334a45a8ff 454 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
bogdanm 0:9b334a45a8ff 455 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
bogdanm 0:9b334a45a8ff 456 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
bogdanm 0:9b334a45a8ff 457 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
bogdanm 0:9b334a45a8ff 458 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
bogdanm 0:9b334a45a8ff 459 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
bogdanm 0:9b334a45a8ff 460 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
bogdanm 0:9b334a45a8ff 461 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
bogdanm 0:9b334a45a8ff 462 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
bogdanm 0:9b334a45a8ff 463 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
bogdanm 0:9b334a45a8ff 464 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
bogdanm 0:9b334a45a8ff 465 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
bogdanm 0:9b334a45a8ff 466 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
bogdanm 0:9b334a45a8ff 467 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
bogdanm 0:9b334a45a8ff 468 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
bogdanm 0:9b334a45a8ff 469 uint32_t RESERVED0[5];
bogdanm 0:9b334a45a8ff 470 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
bogdanm 0:9b334a45a8ff 471 } SCB_Type;
bogdanm 0:9b334a45a8ff 472
bogdanm 0:9b334a45a8ff 473 /* SCB CPUID Register Definitions */
bogdanm 0:9b334a45a8ff 474 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 0:9b334a45a8ff 475 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 0:9b334a45a8ff 476
bogdanm 0:9b334a45a8ff 477 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
bogdanm 0:9b334a45a8ff 478 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 0:9b334a45a8ff 479
bogdanm 0:9b334a45a8ff 480 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 0:9b334a45a8ff 481 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 0:9b334a45a8ff 482
bogdanm 0:9b334a45a8ff 483 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
bogdanm 0:9b334a45a8ff 484 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 0:9b334a45a8ff 485
bogdanm 0:9b334a45a8ff 486 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
mbed_official 19:112740acecfa 487 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
bogdanm 0:9b334a45a8ff 488
bogdanm 0:9b334a45a8ff 489 /* SCB Interrupt Control State Register Definitions */
bogdanm 0:9b334a45a8ff 490 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 0:9b334a45a8ff 491 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 0:9b334a45a8ff 492
bogdanm 0:9b334a45a8ff 493 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
bogdanm 0:9b334a45a8ff 494 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 0:9b334a45a8ff 495
bogdanm 0:9b334a45a8ff 496 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 0:9b334a45a8ff 497 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 0:9b334a45a8ff 498
bogdanm 0:9b334a45a8ff 499 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
bogdanm 0:9b334a45a8ff 500 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 0:9b334a45a8ff 501
bogdanm 0:9b334a45a8ff 502 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 0:9b334a45a8ff 503 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 0:9b334a45a8ff 504
bogdanm 0:9b334a45a8ff 505 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 0:9b334a45a8ff 506 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 0:9b334a45a8ff 507
bogdanm 0:9b334a45a8ff 508 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
bogdanm 0:9b334a45a8ff 509 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 0:9b334a45a8ff 510
bogdanm 0:9b334a45a8ff 511 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
bogdanm 0:9b334a45a8ff 512 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 0:9b334a45a8ff 513
bogdanm 0:9b334a45a8ff 514 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
bogdanm 0:9b334a45a8ff 515 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
bogdanm 0:9b334a45a8ff 516
bogdanm 0:9b334a45a8ff 517 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
mbed_official 19:112740acecfa 518 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 0:9b334a45a8ff 519
bogdanm 0:9b334a45a8ff 520 /* SCB Vector Table Offset Register Definitions */
bogdanm 0:9b334a45a8ff 521 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
bogdanm 0:9b334a45a8ff 522 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
bogdanm 0:9b334a45a8ff 523
bogdanm 0:9b334a45a8ff 524 /* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm 0:9b334a45a8ff 525 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
bogdanm 0:9b334a45a8ff 526 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 0:9b334a45a8ff 527
bogdanm 0:9b334a45a8ff 528 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 0:9b334a45a8ff 529 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 0:9b334a45a8ff 530
bogdanm 0:9b334a45a8ff 531 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 0:9b334a45a8ff 532 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 0:9b334a45a8ff 533
bogdanm 0:9b334a45a8ff 534 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
bogdanm 0:9b334a45a8ff 535 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
bogdanm 0:9b334a45a8ff 536
bogdanm 0:9b334a45a8ff 537 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 0:9b334a45a8ff 538 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 0:9b334a45a8ff 539
bogdanm 0:9b334a45a8ff 540 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 0:9b334a45a8ff 541 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 0:9b334a45a8ff 542
bogdanm 0:9b334a45a8ff 543 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
mbed_official 19:112740acecfa 544 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
bogdanm 0:9b334a45a8ff 545
bogdanm 0:9b334a45a8ff 546 /* SCB System Control Register Definitions */
bogdanm 0:9b334a45a8ff 547 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
bogdanm 0:9b334a45a8ff 548 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 0:9b334a45a8ff 549
bogdanm 0:9b334a45a8ff 550 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 0:9b334a45a8ff 551 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 0:9b334a45a8ff 552
bogdanm 0:9b334a45a8ff 553 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 0:9b334a45a8ff 554 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 0:9b334a45a8ff 555
bogdanm 0:9b334a45a8ff 556 /* SCB Configuration Control Register Definitions */
bogdanm 0:9b334a45a8ff 557 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
bogdanm 0:9b334a45a8ff 558 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 0:9b334a45a8ff 559
bogdanm 0:9b334a45a8ff 560 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
bogdanm 0:9b334a45a8ff 561 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
bogdanm 0:9b334a45a8ff 562
bogdanm 0:9b334a45a8ff 563 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
bogdanm 0:9b334a45a8ff 564 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
bogdanm 0:9b334a45a8ff 565
bogdanm 0:9b334a45a8ff 566 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 0:9b334a45a8ff 567 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 0:9b334a45a8ff 568
bogdanm 0:9b334a45a8ff 569 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
bogdanm 0:9b334a45a8ff 570 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
bogdanm 0:9b334a45a8ff 571
bogdanm 0:9b334a45a8ff 572 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
mbed_official 19:112740acecfa 573 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
bogdanm 0:9b334a45a8ff 574
bogdanm 0:9b334a45a8ff 575 /* SCB System Handler Control and State Register Definitions */
bogdanm 0:9b334a45a8ff 576 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
bogdanm 0:9b334a45a8ff 577 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
bogdanm 0:9b334a45a8ff 578
bogdanm 0:9b334a45a8ff 579 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
bogdanm 0:9b334a45a8ff 580 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
bogdanm 0:9b334a45a8ff 581
bogdanm 0:9b334a45a8ff 582 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
bogdanm 0:9b334a45a8ff 583 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
bogdanm 0:9b334a45a8ff 584
bogdanm 0:9b334a45a8ff 585 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 0:9b334a45a8ff 586 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 0:9b334a45a8ff 587
bogdanm 0:9b334a45a8ff 588 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
bogdanm 0:9b334a45a8ff 589 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
bogdanm 0:9b334a45a8ff 590
bogdanm 0:9b334a45a8ff 591 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
bogdanm 0:9b334a45a8ff 592 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
bogdanm 0:9b334a45a8ff 593
bogdanm 0:9b334a45a8ff 594 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
bogdanm 0:9b334a45a8ff 595 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
bogdanm 0:9b334a45a8ff 596
bogdanm 0:9b334a45a8ff 597 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
bogdanm 0:9b334a45a8ff 598 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
bogdanm 0:9b334a45a8ff 599
bogdanm 0:9b334a45a8ff 600 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
bogdanm 0:9b334a45a8ff 601 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
bogdanm 0:9b334a45a8ff 602
bogdanm 0:9b334a45a8ff 603 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
bogdanm 0:9b334a45a8ff 604 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
bogdanm 0:9b334a45a8ff 605
bogdanm 0:9b334a45a8ff 606 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
bogdanm 0:9b334a45a8ff 607 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
bogdanm 0:9b334a45a8ff 608
bogdanm 0:9b334a45a8ff 609 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
bogdanm 0:9b334a45a8ff 610 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
bogdanm 0:9b334a45a8ff 611
bogdanm 0:9b334a45a8ff 612 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
bogdanm 0:9b334a45a8ff 613 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
bogdanm 0:9b334a45a8ff 614
bogdanm 0:9b334a45a8ff 615 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
mbed_official 19:112740acecfa 616 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
bogdanm 0:9b334a45a8ff 617
bogdanm 0:9b334a45a8ff 618 /* SCB Configurable Fault Status Registers Definitions */
bogdanm 0:9b334a45a8ff 619 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
bogdanm 0:9b334a45a8ff 620 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
bogdanm 0:9b334a45a8ff 621
bogdanm 0:9b334a45a8ff 622 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
bogdanm 0:9b334a45a8ff 623 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
bogdanm 0:9b334a45a8ff 624
bogdanm 0:9b334a45a8ff 625 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
mbed_official 19:112740acecfa 626 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
bogdanm 0:9b334a45a8ff 627
bogdanm 0:9b334a45a8ff 628 /* SCB Hard Fault Status Registers Definitions */
bogdanm 0:9b334a45a8ff 629 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
bogdanm 0:9b334a45a8ff 630 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
bogdanm 0:9b334a45a8ff 631
bogdanm 0:9b334a45a8ff 632 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
bogdanm 0:9b334a45a8ff 633 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
bogdanm 0:9b334a45a8ff 634
bogdanm 0:9b334a45a8ff 635 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
bogdanm 0:9b334a45a8ff 636 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
bogdanm 0:9b334a45a8ff 637
bogdanm 0:9b334a45a8ff 638 /* SCB Debug Fault Status Register Definitions */
bogdanm 0:9b334a45a8ff 639 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
bogdanm 0:9b334a45a8ff 640 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
bogdanm 0:9b334a45a8ff 641
bogdanm 0:9b334a45a8ff 642 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
bogdanm 0:9b334a45a8ff 643 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
bogdanm 0:9b334a45a8ff 644
bogdanm 0:9b334a45a8ff 645 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
bogdanm 0:9b334a45a8ff 646 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
bogdanm 0:9b334a45a8ff 647
bogdanm 0:9b334a45a8ff 648 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
bogdanm 0:9b334a45a8ff 649 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
bogdanm 0:9b334a45a8ff 650
bogdanm 0:9b334a45a8ff 651 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
mbed_official 19:112740acecfa 652 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
bogdanm 0:9b334a45a8ff 653
bogdanm 0:9b334a45a8ff 654 /*@} end of group CMSIS_SCB */
bogdanm 0:9b334a45a8ff 655
bogdanm 0:9b334a45a8ff 656
bogdanm 0:9b334a45a8ff 657 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 658 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
bogdanm 0:9b334a45a8ff 659 \brief Type definitions for the System Control and ID Register not in the SCB
bogdanm 0:9b334a45a8ff 660 @{
bogdanm 0:9b334a45a8ff 661 */
bogdanm 0:9b334a45a8ff 662
bogdanm 0:9b334a45a8ff 663 /** \brief Structure type to access the System Control and ID Register not in the SCB.
bogdanm 0:9b334a45a8ff 664 */
bogdanm 0:9b334a45a8ff 665 typedef struct
bogdanm 0:9b334a45a8ff 666 {
bogdanm 0:9b334a45a8ff 667 uint32_t RESERVED0[1];
bogdanm 0:9b334a45a8ff 668 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
bogdanm 0:9b334a45a8ff 669 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
bogdanm 0:9b334a45a8ff 670 } SCnSCB_Type;
bogdanm 0:9b334a45a8ff 671
bogdanm 0:9b334a45a8ff 672 /* Interrupt Controller Type Register Definitions */
bogdanm 0:9b334a45a8ff 673 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
mbed_official 19:112740acecfa 674 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
bogdanm 0:9b334a45a8ff 675
bogdanm 0:9b334a45a8ff 676 /* Auxiliary Control Register Definitions */
bogdanm 0:9b334a45a8ff 677 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
bogdanm 0:9b334a45a8ff 678 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
bogdanm 0:9b334a45a8ff 679
bogdanm 0:9b334a45a8ff 680 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
bogdanm 0:9b334a45a8ff 681 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
bogdanm 0:9b334a45a8ff 682
bogdanm 0:9b334a45a8ff 683 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
bogdanm 0:9b334a45a8ff 684 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
bogdanm 0:9b334a45a8ff 685
bogdanm 0:9b334a45a8ff 686 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
bogdanm 0:9b334a45a8ff 687 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
bogdanm 0:9b334a45a8ff 688
bogdanm 0:9b334a45a8ff 689 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
mbed_official 19:112740acecfa 690 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
bogdanm 0:9b334a45a8ff 691
bogdanm 0:9b334a45a8ff 692 /*@} end of group CMSIS_SCnotSCB */
bogdanm 0:9b334a45a8ff 693
bogdanm 0:9b334a45a8ff 694
bogdanm 0:9b334a45a8ff 695 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 696 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm 0:9b334a45a8ff 697 \brief Type definitions for the System Timer Registers.
bogdanm 0:9b334a45a8ff 698 @{
bogdanm 0:9b334a45a8ff 699 */
bogdanm 0:9b334a45a8ff 700
bogdanm 0:9b334a45a8ff 701 /** \brief Structure type to access the System Timer (SysTick).
bogdanm 0:9b334a45a8ff 702 */
bogdanm 0:9b334a45a8ff 703 typedef struct
bogdanm 0:9b334a45a8ff 704 {
bogdanm 0:9b334a45a8ff 705 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
bogdanm 0:9b334a45a8ff 706 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
bogdanm 0:9b334a45a8ff 707 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
bogdanm 0:9b334a45a8ff 708 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 0:9b334a45a8ff 709 } SysTick_Type;
bogdanm 0:9b334a45a8ff 710
bogdanm 0:9b334a45a8ff 711 /* SysTick Control / Status Register Definitions */
bogdanm 0:9b334a45a8ff 712 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 0:9b334a45a8ff 713 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 0:9b334a45a8ff 714
bogdanm 0:9b334a45a8ff 715 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 0:9b334a45a8ff 716 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 0:9b334a45a8ff 717
bogdanm 0:9b334a45a8ff 718 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
bogdanm 0:9b334a45a8ff 719 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 0:9b334a45a8ff 720
bogdanm 0:9b334a45a8ff 721 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
mbed_official 19:112740acecfa 722 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 0:9b334a45a8ff 723
bogdanm 0:9b334a45a8ff 724 /* SysTick Reload Register Definitions */
bogdanm 0:9b334a45a8ff 725 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
mbed_official 19:112740acecfa 726 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 0:9b334a45a8ff 727
bogdanm 0:9b334a45a8ff 728 /* SysTick Current Register Definitions */
bogdanm 0:9b334a45a8ff 729 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
mbed_official 19:112740acecfa 730 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
bogdanm 0:9b334a45a8ff 731
bogdanm 0:9b334a45a8ff 732 /* SysTick Calibration Register Definitions */
bogdanm 0:9b334a45a8ff 733 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
bogdanm 0:9b334a45a8ff 734 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 0:9b334a45a8ff 735
bogdanm 0:9b334a45a8ff 736 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
bogdanm 0:9b334a45a8ff 737 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 0:9b334a45a8ff 738
bogdanm 0:9b334a45a8ff 739 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
mbed_official 19:112740acecfa 740 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
bogdanm 0:9b334a45a8ff 741
bogdanm 0:9b334a45a8ff 742 /*@} end of group CMSIS_SysTick */
bogdanm 0:9b334a45a8ff 743
bogdanm 0:9b334a45a8ff 744
bogdanm 0:9b334a45a8ff 745 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 746 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
bogdanm 0:9b334a45a8ff 747 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
bogdanm 0:9b334a45a8ff 748 @{
bogdanm 0:9b334a45a8ff 749 */
bogdanm 0:9b334a45a8ff 750
bogdanm 0:9b334a45a8ff 751 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
bogdanm 0:9b334a45a8ff 752 */
bogdanm 0:9b334a45a8ff 753 typedef struct
bogdanm 0:9b334a45a8ff 754 {
bogdanm 0:9b334a45a8ff 755 __O union
bogdanm 0:9b334a45a8ff 756 {
bogdanm 0:9b334a45a8ff 757 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
bogdanm 0:9b334a45a8ff 758 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
bogdanm 0:9b334a45a8ff 759 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
bogdanm 0:9b334a45a8ff 760 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
bogdanm 0:9b334a45a8ff 761 uint32_t RESERVED0[864];
bogdanm 0:9b334a45a8ff 762 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
bogdanm 0:9b334a45a8ff 763 uint32_t RESERVED1[15];
bogdanm 0:9b334a45a8ff 764 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
bogdanm 0:9b334a45a8ff 765 uint32_t RESERVED2[15];
bogdanm 0:9b334a45a8ff 766 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
bogdanm 0:9b334a45a8ff 767 uint32_t RESERVED3[29];
bogdanm 0:9b334a45a8ff 768 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
bogdanm 0:9b334a45a8ff 769 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
bogdanm 0:9b334a45a8ff 770 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
bogdanm 0:9b334a45a8ff 771 uint32_t RESERVED4[43];
bogdanm 0:9b334a45a8ff 772 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
bogdanm 0:9b334a45a8ff 773 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
bogdanm 0:9b334a45a8ff 774 uint32_t RESERVED5[6];
bogdanm 0:9b334a45a8ff 775 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
bogdanm 0:9b334a45a8ff 776 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
bogdanm 0:9b334a45a8ff 777 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
bogdanm 0:9b334a45a8ff 778 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
bogdanm 0:9b334a45a8ff 779 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
bogdanm 0:9b334a45a8ff 780 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
bogdanm 0:9b334a45a8ff 781 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
bogdanm 0:9b334a45a8ff 782 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
bogdanm 0:9b334a45a8ff 783 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
bogdanm 0:9b334a45a8ff 784 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
bogdanm 0:9b334a45a8ff 785 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
bogdanm 0:9b334a45a8ff 786 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
bogdanm 0:9b334a45a8ff 787 } ITM_Type;
bogdanm 0:9b334a45a8ff 788
bogdanm 0:9b334a45a8ff 789 /* ITM Trace Privilege Register Definitions */
bogdanm 0:9b334a45a8ff 790 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
mbed_official 19:112740acecfa 791 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
bogdanm 0:9b334a45a8ff 792
bogdanm 0:9b334a45a8ff 793 /* ITM Trace Control Register Definitions */
bogdanm 0:9b334a45a8ff 794 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
bogdanm 0:9b334a45a8ff 795 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
bogdanm 0:9b334a45a8ff 796
bogdanm 0:9b334a45a8ff 797 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
bogdanm 0:9b334a45a8ff 798 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
bogdanm 0:9b334a45a8ff 799
bogdanm 0:9b334a45a8ff 800 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
bogdanm 0:9b334a45a8ff 801 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
bogdanm 0:9b334a45a8ff 802
bogdanm 0:9b334a45a8ff 803 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
bogdanm 0:9b334a45a8ff 804 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
bogdanm 0:9b334a45a8ff 805
bogdanm 0:9b334a45a8ff 806 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
bogdanm 0:9b334a45a8ff 807 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
bogdanm 0:9b334a45a8ff 808
bogdanm 0:9b334a45a8ff 809 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
bogdanm 0:9b334a45a8ff 810 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
bogdanm 0:9b334a45a8ff 811
bogdanm 0:9b334a45a8ff 812 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
bogdanm 0:9b334a45a8ff 813 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
bogdanm 0:9b334a45a8ff 814
bogdanm 0:9b334a45a8ff 815 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
bogdanm 0:9b334a45a8ff 816 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
bogdanm 0:9b334a45a8ff 817
bogdanm 0:9b334a45a8ff 818 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
mbed_official 19:112740acecfa 819 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
bogdanm 0:9b334a45a8ff 820
bogdanm 0:9b334a45a8ff 821 /* ITM Integration Write Register Definitions */
bogdanm 0:9b334a45a8ff 822 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
mbed_official 19:112740acecfa 823 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
bogdanm 0:9b334a45a8ff 824
bogdanm 0:9b334a45a8ff 825 /* ITM Integration Read Register Definitions */
bogdanm 0:9b334a45a8ff 826 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
mbed_official 19:112740acecfa 827 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
bogdanm 0:9b334a45a8ff 828
bogdanm 0:9b334a45a8ff 829 /* ITM Integration Mode Control Register Definitions */
bogdanm 0:9b334a45a8ff 830 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
mbed_official 19:112740acecfa 831 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
bogdanm 0:9b334a45a8ff 832
bogdanm 0:9b334a45a8ff 833 /* ITM Lock Status Register Definitions */
bogdanm 0:9b334a45a8ff 834 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
bogdanm 0:9b334a45a8ff 835 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
bogdanm 0:9b334a45a8ff 836
bogdanm 0:9b334a45a8ff 837 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
bogdanm 0:9b334a45a8ff 838 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
bogdanm 0:9b334a45a8ff 839
bogdanm 0:9b334a45a8ff 840 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
mbed_official 19:112740acecfa 841 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
bogdanm 0:9b334a45a8ff 842
bogdanm 0:9b334a45a8ff 843 /*@}*/ /* end of group CMSIS_ITM */
bogdanm 0:9b334a45a8ff 844
bogdanm 0:9b334a45a8ff 845
bogdanm 0:9b334a45a8ff 846 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 847 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
bogdanm 0:9b334a45a8ff 848 \brief Type definitions for the Data Watchpoint and Trace (DWT)
bogdanm 0:9b334a45a8ff 849 @{
bogdanm 0:9b334a45a8ff 850 */
bogdanm 0:9b334a45a8ff 851
bogdanm 0:9b334a45a8ff 852 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
bogdanm 0:9b334a45a8ff 853 */
bogdanm 0:9b334a45a8ff 854 typedef struct
bogdanm 0:9b334a45a8ff 855 {
bogdanm 0:9b334a45a8ff 856 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
bogdanm 0:9b334a45a8ff 857 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
bogdanm 0:9b334a45a8ff 858 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
bogdanm 0:9b334a45a8ff 859 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
bogdanm 0:9b334a45a8ff 860 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
bogdanm 0:9b334a45a8ff 861 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
bogdanm 0:9b334a45a8ff 862 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
bogdanm 0:9b334a45a8ff 863 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
bogdanm 0:9b334a45a8ff 864 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
bogdanm 0:9b334a45a8ff 865 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
bogdanm 0:9b334a45a8ff 866 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
bogdanm 0:9b334a45a8ff 867 uint32_t RESERVED0[1];
bogdanm 0:9b334a45a8ff 868 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
bogdanm 0:9b334a45a8ff 869 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
bogdanm 0:9b334a45a8ff 870 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
bogdanm 0:9b334a45a8ff 871 uint32_t RESERVED1[1];
bogdanm 0:9b334a45a8ff 872 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
bogdanm 0:9b334a45a8ff 873 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
bogdanm 0:9b334a45a8ff 874 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
bogdanm 0:9b334a45a8ff 875 uint32_t RESERVED2[1];
bogdanm 0:9b334a45a8ff 876 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
bogdanm 0:9b334a45a8ff 877 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
bogdanm 0:9b334a45a8ff 878 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
bogdanm 0:9b334a45a8ff 879 } DWT_Type;
bogdanm 0:9b334a45a8ff 880
bogdanm 0:9b334a45a8ff 881 /* DWT Control Register Definitions */
bogdanm 0:9b334a45a8ff 882 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
bogdanm 0:9b334a45a8ff 883 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
bogdanm 0:9b334a45a8ff 884
bogdanm 0:9b334a45a8ff 885 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
bogdanm 0:9b334a45a8ff 886 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
bogdanm 0:9b334a45a8ff 887
bogdanm 0:9b334a45a8ff 888 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
bogdanm 0:9b334a45a8ff 889 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
bogdanm 0:9b334a45a8ff 890
bogdanm 0:9b334a45a8ff 891 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
bogdanm 0:9b334a45a8ff 892 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
bogdanm 0:9b334a45a8ff 893
bogdanm 0:9b334a45a8ff 894 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
bogdanm 0:9b334a45a8ff 895 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
bogdanm 0:9b334a45a8ff 896
bogdanm 0:9b334a45a8ff 897 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
bogdanm 0:9b334a45a8ff 898 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
bogdanm 0:9b334a45a8ff 899
bogdanm 0:9b334a45a8ff 900 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
bogdanm 0:9b334a45a8ff 901 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
bogdanm 0:9b334a45a8ff 902
bogdanm 0:9b334a45a8ff 903 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
bogdanm 0:9b334a45a8ff 904 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
bogdanm 0:9b334a45a8ff 905
bogdanm 0:9b334a45a8ff 906 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
bogdanm 0:9b334a45a8ff 907 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
bogdanm 0:9b334a45a8ff 908
bogdanm 0:9b334a45a8ff 909 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
bogdanm 0:9b334a45a8ff 910 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
bogdanm 0:9b334a45a8ff 911
bogdanm 0:9b334a45a8ff 912 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
bogdanm 0:9b334a45a8ff 913 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
bogdanm 0:9b334a45a8ff 914
bogdanm 0:9b334a45a8ff 915 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
bogdanm 0:9b334a45a8ff 916 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
bogdanm 0:9b334a45a8ff 917
bogdanm 0:9b334a45a8ff 918 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
bogdanm 0:9b334a45a8ff 919 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
bogdanm 0:9b334a45a8ff 920
bogdanm 0:9b334a45a8ff 921 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
bogdanm 0:9b334a45a8ff 922 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
bogdanm 0:9b334a45a8ff 923
bogdanm 0:9b334a45a8ff 924 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
bogdanm 0:9b334a45a8ff 925 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
bogdanm 0:9b334a45a8ff 926
bogdanm 0:9b334a45a8ff 927 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
bogdanm 0:9b334a45a8ff 928 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
bogdanm 0:9b334a45a8ff 929
bogdanm 0:9b334a45a8ff 930 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
bogdanm 0:9b334a45a8ff 931 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
bogdanm 0:9b334a45a8ff 932
bogdanm 0:9b334a45a8ff 933 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
mbed_official 19:112740acecfa 934 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
bogdanm 0:9b334a45a8ff 935
bogdanm 0:9b334a45a8ff 936 /* DWT CPI Count Register Definitions */
bogdanm 0:9b334a45a8ff 937 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
mbed_official 19:112740acecfa 938 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
bogdanm 0:9b334a45a8ff 939
bogdanm 0:9b334a45a8ff 940 /* DWT Exception Overhead Count Register Definitions */
bogdanm 0:9b334a45a8ff 941 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
mbed_official 19:112740acecfa 942 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
bogdanm 0:9b334a45a8ff 943
bogdanm 0:9b334a45a8ff 944 /* DWT Sleep Count Register Definitions */
bogdanm 0:9b334a45a8ff 945 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
mbed_official 19:112740acecfa 946 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
bogdanm 0:9b334a45a8ff 947
bogdanm 0:9b334a45a8ff 948 /* DWT LSU Count Register Definitions */
bogdanm 0:9b334a45a8ff 949 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
mbed_official 19:112740acecfa 950 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
bogdanm 0:9b334a45a8ff 951
bogdanm 0:9b334a45a8ff 952 /* DWT Folded-instruction Count Register Definitions */
bogdanm 0:9b334a45a8ff 953 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
mbed_official 19:112740acecfa 954 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
bogdanm 0:9b334a45a8ff 955
bogdanm 0:9b334a45a8ff 956 /* DWT Comparator Mask Register Definitions */
bogdanm 0:9b334a45a8ff 957 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
mbed_official 19:112740acecfa 958 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
bogdanm 0:9b334a45a8ff 959
bogdanm 0:9b334a45a8ff 960 /* DWT Comparator Function Register Definitions */
bogdanm 0:9b334a45a8ff 961 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
bogdanm 0:9b334a45a8ff 962 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
bogdanm 0:9b334a45a8ff 963
bogdanm 0:9b334a45a8ff 964 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
bogdanm 0:9b334a45a8ff 965 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
bogdanm 0:9b334a45a8ff 966
bogdanm 0:9b334a45a8ff 967 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
bogdanm 0:9b334a45a8ff 968 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
bogdanm 0:9b334a45a8ff 969
bogdanm 0:9b334a45a8ff 970 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
bogdanm 0:9b334a45a8ff 971 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
bogdanm 0:9b334a45a8ff 972
bogdanm 0:9b334a45a8ff 973 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
bogdanm 0:9b334a45a8ff 974 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
bogdanm 0:9b334a45a8ff 975
bogdanm 0:9b334a45a8ff 976 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
bogdanm 0:9b334a45a8ff 977 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
bogdanm 0:9b334a45a8ff 978
bogdanm 0:9b334a45a8ff 979 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
bogdanm 0:9b334a45a8ff 980 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
bogdanm 0:9b334a45a8ff 981
bogdanm 0:9b334a45a8ff 982 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
bogdanm 0:9b334a45a8ff 983 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
bogdanm 0:9b334a45a8ff 984
bogdanm 0:9b334a45a8ff 985 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
mbed_official 19:112740acecfa 986 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
bogdanm 0:9b334a45a8ff 987
bogdanm 0:9b334a45a8ff 988 /*@}*/ /* end of group CMSIS_DWT */
bogdanm 0:9b334a45a8ff 989
bogdanm 0:9b334a45a8ff 990
bogdanm 0:9b334a45a8ff 991 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 992 \defgroup CMSIS_TPI Trace Port Interface (TPI)
bogdanm 0:9b334a45a8ff 993 \brief Type definitions for the Trace Port Interface (TPI)
bogdanm 0:9b334a45a8ff 994 @{
bogdanm 0:9b334a45a8ff 995 */
bogdanm 0:9b334a45a8ff 996
bogdanm 0:9b334a45a8ff 997 /** \brief Structure type to access the Trace Port Interface Register (TPI).
bogdanm 0:9b334a45a8ff 998 */
bogdanm 0:9b334a45a8ff 999 typedef struct
bogdanm 0:9b334a45a8ff 1000 {
bogdanm 0:9b334a45a8ff 1001 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
bogdanm 0:9b334a45a8ff 1002 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
bogdanm 0:9b334a45a8ff 1003 uint32_t RESERVED0[2];
bogdanm 0:9b334a45a8ff 1004 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
bogdanm 0:9b334a45a8ff 1005 uint32_t RESERVED1[55];
bogdanm 0:9b334a45a8ff 1006 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
bogdanm 0:9b334a45a8ff 1007 uint32_t RESERVED2[131];
bogdanm 0:9b334a45a8ff 1008 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
bogdanm 0:9b334a45a8ff 1009 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
bogdanm 0:9b334a45a8ff 1010 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
bogdanm 0:9b334a45a8ff 1011 uint32_t RESERVED3[759];
bogdanm 0:9b334a45a8ff 1012 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
bogdanm 0:9b334a45a8ff 1013 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
bogdanm 0:9b334a45a8ff 1014 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
bogdanm 0:9b334a45a8ff 1015 uint32_t RESERVED4[1];
bogdanm 0:9b334a45a8ff 1016 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
bogdanm 0:9b334a45a8ff 1017 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
bogdanm 0:9b334a45a8ff 1018 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
bogdanm 0:9b334a45a8ff 1019 uint32_t RESERVED5[39];
bogdanm 0:9b334a45a8ff 1020 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
bogdanm 0:9b334a45a8ff 1021 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
bogdanm 0:9b334a45a8ff 1022 uint32_t RESERVED7[8];
bogdanm 0:9b334a45a8ff 1023 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
bogdanm 0:9b334a45a8ff 1024 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
bogdanm 0:9b334a45a8ff 1025 } TPI_Type;
bogdanm 0:9b334a45a8ff 1026
bogdanm 0:9b334a45a8ff 1027 /* TPI Asynchronous Clock Prescaler Register Definitions */
bogdanm 0:9b334a45a8ff 1028 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
mbed_official 19:112740acecfa 1029 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
bogdanm 0:9b334a45a8ff 1030
bogdanm 0:9b334a45a8ff 1031 /* TPI Selected Pin Protocol Register Definitions */
bogdanm 0:9b334a45a8ff 1032 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
mbed_official 19:112740acecfa 1033 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
bogdanm 0:9b334a45a8ff 1034
bogdanm 0:9b334a45a8ff 1035 /* TPI Formatter and Flush Status Register Definitions */
bogdanm 0:9b334a45a8ff 1036 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
bogdanm 0:9b334a45a8ff 1037 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
bogdanm 0:9b334a45a8ff 1038
bogdanm 0:9b334a45a8ff 1039 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
bogdanm 0:9b334a45a8ff 1040 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
bogdanm 0:9b334a45a8ff 1041
bogdanm 0:9b334a45a8ff 1042 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
bogdanm 0:9b334a45a8ff 1043 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
bogdanm 0:9b334a45a8ff 1044
bogdanm 0:9b334a45a8ff 1045 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
mbed_official 19:112740acecfa 1046 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
bogdanm 0:9b334a45a8ff 1047
bogdanm 0:9b334a45a8ff 1048 /* TPI Formatter and Flush Control Register Definitions */
bogdanm 0:9b334a45a8ff 1049 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
bogdanm 0:9b334a45a8ff 1050 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
bogdanm 0:9b334a45a8ff 1051
bogdanm 0:9b334a45a8ff 1052 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
bogdanm 0:9b334a45a8ff 1053 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
bogdanm 0:9b334a45a8ff 1054
bogdanm 0:9b334a45a8ff 1055 /* TPI TRIGGER Register Definitions */
bogdanm 0:9b334a45a8ff 1056 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
mbed_official 19:112740acecfa 1057 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
bogdanm 0:9b334a45a8ff 1058
bogdanm 0:9b334a45a8ff 1059 /* TPI Integration ETM Data Register Definitions (FIFO0) */
bogdanm 0:9b334a45a8ff 1060 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
bogdanm 0:9b334a45a8ff 1061 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
bogdanm 0:9b334a45a8ff 1062
bogdanm 0:9b334a45a8ff 1063 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
bogdanm 0:9b334a45a8ff 1064 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
bogdanm 0:9b334a45a8ff 1065
bogdanm 0:9b334a45a8ff 1066 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
bogdanm 0:9b334a45a8ff 1067 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
bogdanm 0:9b334a45a8ff 1068
bogdanm 0:9b334a45a8ff 1069 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
bogdanm 0:9b334a45a8ff 1070 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
bogdanm 0:9b334a45a8ff 1071
bogdanm 0:9b334a45a8ff 1072 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
bogdanm 0:9b334a45a8ff 1073 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
bogdanm 0:9b334a45a8ff 1074
bogdanm 0:9b334a45a8ff 1075 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
bogdanm 0:9b334a45a8ff 1076 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
bogdanm 0:9b334a45a8ff 1077
bogdanm 0:9b334a45a8ff 1078 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
mbed_official 19:112740acecfa 1079 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
bogdanm 0:9b334a45a8ff 1080
bogdanm 0:9b334a45a8ff 1081 /* TPI ITATBCTR2 Register Definitions */
bogdanm 0:9b334a45a8ff 1082 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
mbed_official 19:112740acecfa 1083 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
bogdanm 0:9b334a45a8ff 1084
bogdanm 0:9b334a45a8ff 1085 /* TPI Integration ITM Data Register Definitions (FIFO1) */
bogdanm 0:9b334a45a8ff 1086 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
bogdanm 0:9b334a45a8ff 1087 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
bogdanm 0:9b334a45a8ff 1088
bogdanm 0:9b334a45a8ff 1089 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
bogdanm 0:9b334a45a8ff 1090 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
bogdanm 0:9b334a45a8ff 1091
bogdanm 0:9b334a45a8ff 1092 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
bogdanm 0:9b334a45a8ff 1093 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
bogdanm 0:9b334a45a8ff 1094
bogdanm 0:9b334a45a8ff 1095 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
bogdanm 0:9b334a45a8ff 1096 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
bogdanm 0:9b334a45a8ff 1097
bogdanm 0:9b334a45a8ff 1098 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
bogdanm 0:9b334a45a8ff 1099 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
bogdanm 0:9b334a45a8ff 1100
bogdanm 0:9b334a45a8ff 1101 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
bogdanm 0:9b334a45a8ff 1102 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
bogdanm 0:9b334a45a8ff 1103
bogdanm 0:9b334a45a8ff 1104 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
mbed_official 19:112740acecfa 1105 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
bogdanm 0:9b334a45a8ff 1106
bogdanm 0:9b334a45a8ff 1107 /* TPI ITATBCTR0 Register Definitions */
bogdanm 0:9b334a45a8ff 1108 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
mbed_official 19:112740acecfa 1109 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
bogdanm 0:9b334a45a8ff 1110
bogdanm 0:9b334a45a8ff 1111 /* TPI Integration Mode Control Register Definitions */
bogdanm 0:9b334a45a8ff 1112 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
mbed_official 19:112740acecfa 1113 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
bogdanm 0:9b334a45a8ff 1114
bogdanm 0:9b334a45a8ff 1115 /* TPI DEVID Register Definitions */
bogdanm 0:9b334a45a8ff 1116 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
bogdanm 0:9b334a45a8ff 1117 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
bogdanm 0:9b334a45a8ff 1118
bogdanm 0:9b334a45a8ff 1119 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
bogdanm 0:9b334a45a8ff 1120 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
bogdanm 0:9b334a45a8ff 1121
bogdanm 0:9b334a45a8ff 1122 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
bogdanm 0:9b334a45a8ff 1123 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
bogdanm 0:9b334a45a8ff 1124
bogdanm 0:9b334a45a8ff 1125 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
bogdanm 0:9b334a45a8ff 1126 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
bogdanm 0:9b334a45a8ff 1127
bogdanm 0:9b334a45a8ff 1128 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
bogdanm 0:9b334a45a8ff 1129 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
bogdanm 0:9b334a45a8ff 1130
bogdanm 0:9b334a45a8ff 1131 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
mbed_official 19:112740acecfa 1132 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
bogdanm 0:9b334a45a8ff 1133
bogdanm 0:9b334a45a8ff 1134 /* TPI DEVTYPE Register Definitions */
bogdanm 0:9b334a45a8ff 1135 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
bogdanm 0:9b334a45a8ff 1136 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
bogdanm 0:9b334a45a8ff 1137
mbed_official 19:112740acecfa 1138 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
mbed_official 19:112740acecfa 1139 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
mbed_official 19:112740acecfa 1140
bogdanm 0:9b334a45a8ff 1141 /*@}*/ /* end of group CMSIS_TPI */
bogdanm 0:9b334a45a8ff 1142
bogdanm 0:9b334a45a8ff 1143
bogdanm 0:9b334a45a8ff 1144 #if (__MPU_PRESENT == 1)
bogdanm 0:9b334a45a8ff 1145 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 1146 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
bogdanm 0:9b334a45a8ff 1147 \brief Type definitions for the Memory Protection Unit (MPU)
bogdanm 0:9b334a45a8ff 1148 @{
bogdanm 0:9b334a45a8ff 1149 */
bogdanm 0:9b334a45a8ff 1150
bogdanm 0:9b334a45a8ff 1151 /** \brief Structure type to access the Memory Protection Unit (MPU).
bogdanm 0:9b334a45a8ff 1152 */
bogdanm 0:9b334a45a8ff 1153 typedef struct
bogdanm 0:9b334a45a8ff 1154 {
bogdanm 0:9b334a45a8ff 1155 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
bogdanm 0:9b334a45a8ff 1156 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
bogdanm 0:9b334a45a8ff 1157 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
bogdanm 0:9b334a45a8ff 1158 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
bogdanm 0:9b334a45a8ff 1159 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
bogdanm 0:9b334a45a8ff 1160 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
bogdanm 0:9b334a45a8ff 1161 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
bogdanm 0:9b334a45a8ff 1162 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
bogdanm 0:9b334a45a8ff 1163 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
bogdanm 0:9b334a45a8ff 1164 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
bogdanm 0:9b334a45a8ff 1165 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
bogdanm 0:9b334a45a8ff 1166 } MPU_Type;
bogdanm 0:9b334a45a8ff 1167
bogdanm 0:9b334a45a8ff 1168 /* MPU Type Register */
bogdanm 0:9b334a45a8ff 1169 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
bogdanm 0:9b334a45a8ff 1170 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
bogdanm 0:9b334a45a8ff 1171
bogdanm 0:9b334a45a8ff 1172 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
bogdanm 0:9b334a45a8ff 1173 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
bogdanm 0:9b334a45a8ff 1174
bogdanm 0:9b334a45a8ff 1175 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
mbed_official 19:112740acecfa 1176 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
bogdanm 0:9b334a45a8ff 1177
bogdanm 0:9b334a45a8ff 1178 /* MPU Control Register */
bogdanm 0:9b334a45a8ff 1179 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
bogdanm 0:9b334a45a8ff 1180 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
bogdanm 0:9b334a45a8ff 1181
bogdanm 0:9b334a45a8ff 1182 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
bogdanm 0:9b334a45a8ff 1183 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
bogdanm 0:9b334a45a8ff 1184
bogdanm 0:9b334a45a8ff 1185 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
mbed_official 19:112740acecfa 1186 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
bogdanm 0:9b334a45a8ff 1187
bogdanm 0:9b334a45a8ff 1188 /* MPU Region Number Register */
bogdanm 0:9b334a45a8ff 1189 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
mbed_official 19:112740acecfa 1190 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
bogdanm 0:9b334a45a8ff 1191
bogdanm 0:9b334a45a8ff 1192 /* MPU Region Base Address Register */
bogdanm 0:9b334a45a8ff 1193 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
bogdanm 0:9b334a45a8ff 1194 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
bogdanm 0:9b334a45a8ff 1195
bogdanm 0:9b334a45a8ff 1196 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
bogdanm 0:9b334a45a8ff 1197 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
bogdanm 0:9b334a45a8ff 1198
bogdanm 0:9b334a45a8ff 1199 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
mbed_official 19:112740acecfa 1200 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
bogdanm 0:9b334a45a8ff 1201
bogdanm 0:9b334a45a8ff 1202 /* MPU Region Attribute and Size Register */
bogdanm 0:9b334a45a8ff 1203 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
bogdanm 0:9b334a45a8ff 1204 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
bogdanm 0:9b334a45a8ff 1205
bogdanm 0:9b334a45a8ff 1206 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
bogdanm 0:9b334a45a8ff 1207 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
bogdanm 0:9b334a45a8ff 1208
bogdanm 0:9b334a45a8ff 1209 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
bogdanm 0:9b334a45a8ff 1210 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
bogdanm 0:9b334a45a8ff 1211
bogdanm 0:9b334a45a8ff 1212 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
bogdanm 0:9b334a45a8ff 1213 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
bogdanm 0:9b334a45a8ff 1214
bogdanm 0:9b334a45a8ff 1215 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
bogdanm 0:9b334a45a8ff 1216 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
bogdanm 0:9b334a45a8ff 1217
bogdanm 0:9b334a45a8ff 1218 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
bogdanm 0:9b334a45a8ff 1219 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
bogdanm 0:9b334a45a8ff 1220
bogdanm 0:9b334a45a8ff 1221 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
bogdanm 0:9b334a45a8ff 1222 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
bogdanm 0:9b334a45a8ff 1223
bogdanm 0:9b334a45a8ff 1224 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
bogdanm 0:9b334a45a8ff 1225 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
bogdanm 0:9b334a45a8ff 1226
bogdanm 0:9b334a45a8ff 1227 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
bogdanm 0:9b334a45a8ff 1228 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
bogdanm 0:9b334a45a8ff 1229
bogdanm 0:9b334a45a8ff 1230 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
mbed_official 19:112740acecfa 1231 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
bogdanm 0:9b334a45a8ff 1232
bogdanm 0:9b334a45a8ff 1233 /*@} end of group CMSIS_MPU */
bogdanm 0:9b334a45a8ff 1234 #endif
bogdanm 0:9b334a45a8ff 1235
bogdanm 0:9b334a45a8ff 1236
bogdanm 0:9b334a45a8ff 1237 #if (__FPU_PRESENT == 1)
bogdanm 0:9b334a45a8ff 1238 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 1239 \defgroup CMSIS_FPU Floating Point Unit (FPU)
bogdanm 0:9b334a45a8ff 1240 \brief Type definitions for the Floating Point Unit (FPU)
bogdanm 0:9b334a45a8ff 1241 @{
bogdanm 0:9b334a45a8ff 1242 */
bogdanm 0:9b334a45a8ff 1243
bogdanm 0:9b334a45a8ff 1244 /** \brief Structure type to access the Floating Point Unit (FPU).
bogdanm 0:9b334a45a8ff 1245 */
bogdanm 0:9b334a45a8ff 1246 typedef struct
bogdanm 0:9b334a45a8ff 1247 {
bogdanm 0:9b334a45a8ff 1248 uint32_t RESERVED0[1];
bogdanm 0:9b334a45a8ff 1249 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
bogdanm 0:9b334a45a8ff 1250 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
bogdanm 0:9b334a45a8ff 1251 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
bogdanm 0:9b334a45a8ff 1252 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
bogdanm 0:9b334a45a8ff 1253 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
bogdanm 0:9b334a45a8ff 1254 } FPU_Type;
bogdanm 0:9b334a45a8ff 1255
bogdanm 0:9b334a45a8ff 1256 /* Floating-Point Context Control Register */
bogdanm 0:9b334a45a8ff 1257 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
bogdanm 0:9b334a45a8ff 1258 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
bogdanm 0:9b334a45a8ff 1259
bogdanm 0:9b334a45a8ff 1260 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
bogdanm 0:9b334a45a8ff 1261 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
bogdanm 0:9b334a45a8ff 1262
bogdanm 0:9b334a45a8ff 1263 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
bogdanm 0:9b334a45a8ff 1264 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
bogdanm 0:9b334a45a8ff 1265
bogdanm 0:9b334a45a8ff 1266 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
bogdanm 0:9b334a45a8ff 1267 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
bogdanm 0:9b334a45a8ff 1268
bogdanm 0:9b334a45a8ff 1269 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
bogdanm 0:9b334a45a8ff 1270 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
bogdanm 0:9b334a45a8ff 1271
bogdanm 0:9b334a45a8ff 1272 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
bogdanm 0:9b334a45a8ff 1273 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
bogdanm 0:9b334a45a8ff 1274
bogdanm 0:9b334a45a8ff 1275 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
bogdanm 0:9b334a45a8ff 1276 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
bogdanm 0:9b334a45a8ff 1277
bogdanm 0:9b334a45a8ff 1278 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
bogdanm 0:9b334a45a8ff 1279 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
bogdanm 0:9b334a45a8ff 1280
bogdanm 0:9b334a45a8ff 1281 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
mbed_official 19:112740acecfa 1282 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
bogdanm 0:9b334a45a8ff 1283
bogdanm 0:9b334a45a8ff 1284 /* Floating-Point Context Address Register */
bogdanm 0:9b334a45a8ff 1285 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
bogdanm 0:9b334a45a8ff 1286 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
bogdanm 0:9b334a45a8ff 1287
bogdanm 0:9b334a45a8ff 1288 /* Floating-Point Default Status Control Register */
bogdanm 0:9b334a45a8ff 1289 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
bogdanm 0:9b334a45a8ff 1290 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
bogdanm 0:9b334a45a8ff 1291
bogdanm 0:9b334a45a8ff 1292 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
bogdanm 0:9b334a45a8ff 1293 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
bogdanm 0:9b334a45a8ff 1294
bogdanm 0:9b334a45a8ff 1295 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
bogdanm 0:9b334a45a8ff 1296 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
bogdanm 0:9b334a45a8ff 1297
bogdanm 0:9b334a45a8ff 1298 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
bogdanm 0:9b334a45a8ff 1299 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
bogdanm 0:9b334a45a8ff 1300
bogdanm 0:9b334a45a8ff 1301 /* Media and FP Feature Register 0 */
bogdanm 0:9b334a45a8ff 1302 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
bogdanm 0:9b334a45a8ff 1303 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
bogdanm 0:9b334a45a8ff 1304
bogdanm 0:9b334a45a8ff 1305 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
bogdanm 0:9b334a45a8ff 1306 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
bogdanm 0:9b334a45a8ff 1307
bogdanm 0:9b334a45a8ff 1308 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
bogdanm 0:9b334a45a8ff 1309 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
bogdanm 0:9b334a45a8ff 1310
bogdanm 0:9b334a45a8ff 1311 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
bogdanm 0:9b334a45a8ff 1312 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
bogdanm 0:9b334a45a8ff 1313
bogdanm 0:9b334a45a8ff 1314 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
bogdanm 0:9b334a45a8ff 1315 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
bogdanm 0:9b334a45a8ff 1316
bogdanm 0:9b334a45a8ff 1317 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
bogdanm 0:9b334a45a8ff 1318 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
bogdanm 0:9b334a45a8ff 1319
bogdanm 0:9b334a45a8ff 1320 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
bogdanm 0:9b334a45a8ff 1321 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
bogdanm 0:9b334a45a8ff 1322
bogdanm 0:9b334a45a8ff 1323 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
mbed_official 19:112740acecfa 1324 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
bogdanm 0:9b334a45a8ff 1325
bogdanm 0:9b334a45a8ff 1326 /* Media and FP Feature Register 1 */
bogdanm 0:9b334a45a8ff 1327 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
bogdanm 0:9b334a45a8ff 1328 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
bogdanm 0:9b334a45a8ff 1329
bogdanm 0:9b334a45a8ff 1330 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
bogdanm 0:9b334a45a8ff 1331 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
bogdanm 0:9b334a45a8ff 1332
bogdanm 0:9b334a45a8ff 1333 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
bogdanm 0:9b334a45a8ff 1334 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
bogdanm 0:9b334a45a8ff 1335
bogdanm 0:9b334a45a8ff 1336 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
mbed_official 19:112740acecfa 1337 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
bogdanm 0:9b334a45a8ff 1338
bogdanm 0:9b334a45a8ff 1339 /*@} end of group CMSIS_FPU */
bogdanm 0:9b334a45a8ff 1340 #endif
bogdanm 0:9b334a45a8ff 1341
bogdanm 0:9b334a45a8ff 1342
bogdanm 0:9b334a45a8ff 1343 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 1344 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm 0:9b334a45a8ff 1345 \brief Type definitions for the Core Debug Registers
bogdanm 0:9b334a45a8ff 1346 @{
bogdanm 0:9b334a45a8ff 1347 */
bogdanm 0:9b334a45a8ff 1348
bogdanm 0:9b334a45a8ff 1349 /** \brief Structure type to access the Core Debug Register (CoreDebug).
bogdanm 0:9b334a45a8ff 1350 */
bogdanm 0:9b334a45a8ff 1351 typedef struct
bogdanm 0:9b334a45a8ff 1352 {
bogdanm 0:9b334a45a8ff 1353 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
bogdanm 0:9b334a45a8ff 1354 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
bogdanm 0:9b334a45a8ff 1355 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
bogdanm 0:9b334a45a8ff 1356 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
bogdanm 0:9b334a45a8ff 1357 } CoreDebug_Type;
bogdanm 0:9b334a45a8ff 1358
bogdanm 0:9b334a45a8ff 1359 /* Debug Halting Control and Status Register */
bogdanm 0:9b334a45a8ff 1360 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
bogdanm 0:9b334a45a8ff 1361 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
bogdanm 0:9b334a45a8ff 1362
bogdanm 0:9b334a45a8ff 1363 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
bogdanm 0:9b334a45a8ff 1364 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
bogdanm 0:9b334a45a8ff 1365
bogdanm 0:9b334a45a8ff 1366 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
bogdanm 0:9b334a45a8ff 1367 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
bogdanm 0:9b334a45a8ff 1368
bogdanm 0:9b334a45a8ff 1369 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
bogdanm 0:9b334a45a8ff 1370 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
bogdanm 0:9b334a45a8ff 1371
bogdanm 0:9b334a45a8ff 1372 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
bogdanm 0:9b334a45a8ff 1373 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
bogdanm 0:9b334a45a8ff 1374
bogdanm 0:9b334a45a8ff 1375 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
bogdanm 0:9b334a45a8ff 1376 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
bogdanm 0:9b334a45a8ff 1377
bogdanm 0:9b334a45a8ff 1378 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
bogdanm 0:9b334a45a8ff 1379 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
bogdanm 0:9b334a45a8ff 1380
bogdanm 0:9b334a45a8ff 1381 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
bogdanm 0:9b334a45a8ff 1382 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
bogdanm 0:9b334a45a8ff 1383
bogdanm 0:9b334a45a8ff 1384 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
bogdanm 0:9b334a45a8ff 1385 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
bogdanm 0:9b334a45a8ff 1386
bogdanm 0:9b334a45a8ff 1387 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
bogdanm 0:9b334a45a8ff 1388 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
bogdanm 0:9b334a45a8ff 1389
bogdanm 0:9b334a45a8ff 1390 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
bogdanm 0:9b334a45a8ff 1391 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
bogdanm 0:9b334a45a8ff 1392
bogdanm 0:9b334a45a8ff 1393 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
mbed_official 19:112740acecfa 1394 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
bogdanm 0:9b334a45a8ff 1395
bogdanm 0:9b334a45a8ff 1396 /* Debug Core Register Selector Register */
bogdanm 0:9b334a45a8ff 1397 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
bogdanm 0:9b334a45a8ff 1398 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
bogdanm 0:9b334a45a8ff 1399
bogdanm 0:9b334a45a8ff 1400 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
mbed_official 19:112740acecfa 1401 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
bogdanm 0:9b334a45a8ff 1402
bogdanm 0:9b334a45a8ff 1403 /* Debug Exception and Monitor Control Register */
bogdanm 0:9b334a45a8ff 1404 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
bogdanm 0:9b334a45a8ff 1405 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
bogdanm 0:9b334a45a8ff 1406
bogdanm 0:9b334a45a8ff 1407 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
bogdanm 0:9b334a45a8ff 1408 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
bogdanm 0:9b334a45a8ff 1409
bogdanm 0:9b334a45a8ff 1410 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
bogdanm 0:9b334a45a8ff 1411 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
bogdanm 0:9b334a45a8ff 1412
bogdanm 0:9b334a45a8ff 1413 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
bogdanm 0:9b334a45a8ff 1414 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
bogdanm 0:9b334a45a8ff 1415
bogdanm 0:9b334a45a8ff 1416 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
bogdanm 0:9b334a45a8ff 1417 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
bogdanm 0:9b334a45a8ff 1418
bogdanm 0:9b334a45a8ff 1419 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
bogdanm 0:9b334a45a8ff 1420 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
bogdanm 0:9b334a45a8ff 1421
bogdanm 0:9b334a45a8ff 1422 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
bogdanm 0:9b334a45a8ff 1423 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
bogdanm 0:9b334a45a8ff 1424
bogdanm 0:9b334a45a8ff 1425 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
bogdanm 0:9b334a45a8ff 1426 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
bogdanm 0:9b334a45a8ff 1427
bogdanm 0:9b334a45a8ff 1428 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
bogdanm 0:9b334a45a8ff 1429 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
bogdanm 0:9b334a45a8ff 1430
bogdanm 0:9b334a45a8ff 1431 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
bogdanm 0:9b334a45a8ff 1432 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
bogdanm 0:9b334a45a8ff 1433
bogdanm 0:9b334a45a8ff 1434 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
bogdanm 0:9b334a45a8ff 1435 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
bogdanm 0:9b334a45a8ff 1436
bogdanm 0:9b334a45a8ff 1437 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
bogdanm 0:9b334a45a8ff 1438 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
bogdanm 0:9b334a45a8ff 1439
bogdanm 0:9b334a45a8ff 1440 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
mbed_official 19:112740acecfa 1441 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
bogdanm 0:9b334a45a8ff 1442
bogdanm 0:9b334a45a8ff 1443 /*@} end of group CMSIS_CoreDebug */
bogdanm 0:9b334a45a8ff 1444
bogdanm 0:9b334a45a8ff 1445
bogdanm 0:9b334a45a8ff 1446 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 1447 \defgroup CMSIS_core_base Core Definitions
bogdanm 0:9b334a45a8ff 1448 \brief Definitions for base addresses, unions, and structures.
bogdanm 0:9b334a45a8ff 1449 @{
bogdanm 0:9b334a45a8ff 1450 */
bogdanm 0:9b334a45a8ff 1451
bogdanm 0:9b334a45a8ff 1452 /* Memory mapping of Cortex-M4 Hardware */
bogdanm 0:9b334a45a8ff 1453 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
bogdanm 0:9b334a45a8ff 1454 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
bogdanm 0:9b334a45a8ff 1455 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
bogdanm 0:9b334a45a8ff 1456 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
bogdanm 0:9b334a45a8ff 1457 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
bogdanm 0:9b334a45a8ff 1458 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
bogdanm 0:9b334a45a8ff 1459 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
bogdanm 0:9b334a45a8ff 1460 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 0:9b334a45a8ff 1461
bogdanm 0:9b334a45a8ff 1462 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
bogdanm 0:9b334a45a8ff 1463 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
bogdanm 0:9b334a45a8ff 1464 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
bogdanm 0:9b334a45a8ff 1465 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
bogdanm 0:9b334a45a8ff 1466 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
bogdanm 0:9b334a45a8ff 1467 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
bogdanm 0:9b334a45a8ff 1468 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
bogdanm 0:9b334a45a8ff 1469 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
bogdanm 0:9b334a45a8ff 1470
bogdanm 0:9b334a45a8ff 1471 #if (__MPU_PRESENT == 1)
bogdanm 0:9b334a45a8ff 1472 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
bogdanm 0:9b334a45a8ff 1473 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
bogdanm 0:9b334a45a8ff 1474 #endif
bogdanm 0:9b334a45a8ff 1475
bogdanm 0:9b334a45a8ff 1476 #if (__FPU_PRESENT == 1)
bogdanm 0:9b334a45a8ff 1477 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
bogdanm 0:9b334a45a8ff 1478 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
bogdanm 0:9b334a45a8ff 1479 #endif
bogdanm 0:9b334a45a8ff 1480
bogdanm 0:9b334a45a8ff 1481 /*@} */
bogdanm 0:9b334a45a8ff 1482
bogdanm 0:9b334a45a8ff 1483
bogdanm 0:9b334a45a8ff 1484
bogdanm 0:9b334a45a8ff 1485 /*******************************************************************************
bogdanm 0:9b334a45a8ff 1486 * Hardware Abstraction Layer
bogdanm 0:9b334a45a8ff 1487 Core Function Interface contains:
bogdanm 0:9b334a45a8ff 1488 - Core NVIC Functions
bogdanm 0:9b334a45a8ff 1489 - Core SysTick Functions
bogdanm 0:9b334a45a8ff 1490 - Core Debug Functions
bogdanm 0:9b334a45a8ff 1491 - Core Register Access Functions
bogdanm 0:9b334a45a8ff 1492 ******************************************************************************/
bogdanm 0:9b334a45a8ff 1493 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 0:9b334a45a8ff 1494 */
bogdanm 0:9b334a45a8ff 1495
bogdanm 0:9b334a45a8ff 1496
bogdanm 0:9b334a45a8ff 1497
bogdanm 0:9b334a45a8ff 1498 /* ########################## NVIC functions #################################### */
bogdanm 0:9b334a45a8ff 1499 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 0:9b334a45a8ff 1500 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm 0:9b334a45a8ff 1501 \brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm 0:9b334a45a8ff 1502 @{
bogdanm 0:9b334a45a8ff 1503 */
bogdanm 0:9b334a45a8ff 1504
bogdanm 0:9b334a45a8ff 1505 /** \brief Set Priority Grouping
bogdanm 0:9b334a45a8ff 1506
bogdanm 0:9b334a45a8ff 1507 The function sets the priority grouping field using the required unlock sequence.
bogdanm 0:9b334a45a8ff 1508 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
bogdanm 0:9b334a45a8ff 1509 Only values from 0..7 are used.
bogdanm 0:9b334a45a8ff 1510 In case of a conflict between priority grouping and available
bogdanm 0:9b334a45a8ff 1511 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
bogdanm 0:9b334a45a8ff 1512
bogdanm 0:9b334a45a8ff 1513 \param [in] PriorityGroup Priority grouping field.
bogdanm 0:9b334a45a8ff 1514 */
bogdanm 0:9b334a45a8ff 1515 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
bogdanm 0:9b334a45a8ff 1516 {
bogdanm 0:9b334a45a8ff 1517 uint32_t reg_value;
mbed_official 19:112740acecfa 1518 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
bogdanm 0:9b334a45a8ff 1519
bogdanm 0:9b334a45a8ff 1520 reg_value = SCB->AIRCR; /* read old register configuration */
mbed_official 19:112740acecfa 1521 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
mbed_official 19:112740acecfa 1522 reg_value = (reg_value |
mbed_official 19:112740acecfa 1523 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
mbed_official 19:112740acecfa 1524 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
bogdanm 0:9b334a45a8ff 1525 SCB->AIRCR = reg_value;
bogdanm 0:9b334a45a8ff 1526 }
bogdanm 0:9b334a45a8ff 1527
bogdanm 0:9b334a45a8ff 1528
bogdanm 0:9b334a45a8ff 1529 /** \brief Get Priority Grouping
bogdanm 0:9b334a45a8ff 1530
bogdanm 0:9b334a45a8ff 1531 The function reads the priority grouping field from the NVIC Interrupt Controller.
bogdanm 0:9b334a45a8ff 1532
bogdanm 0:9b334a45a8ff 1533 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
bogdanm 0:9b334a45a8ff 1534 */
bogdanm 0:9b334a45a8ff 1535 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
bogdanm 0:9b334a45a8ff 1536 {
mbed_official 19:112740acecfa 1537 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
bogdanm 0:9b334a45a8ff 1538 }
bogdanm 0:9b334a45a8ff 1539
bogdanm 0:9b334a45a8ff 1540
bogdanm 0:9b334a45a8ff 1541 /** \brief Enable External Interrupt
bogdanm 0:9b334a45a8ff 1542
bogdanm 0:9b334a45a8ff 1543 The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 0:9b334a45a8ff 1544
bogdanm 0:9b334a45a8ff 1545 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 0:9b334a45a8ff 1546 */
bogdanm 0:9b334a45a8ff 1547 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 1548 {
mbed_official 19:112740acecfa 1549 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 0:9b334a45a8ff 1550 }
bogdanm 0:9b334a45a8ff 1551
bogdanm 0:9b334a45a8ff 1552
bogdanm 0:9b334a45a8ff 1553 /** \brief Disable External Interrupt
bogdanm 0:9b334a45a8ff 1554
bogdanm 0:9b334a45a8ff 1555 The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 0:9b334a45a8ff 1556
bogdanm 0:9b334a45a8ff 1557 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 0:9b334a45a8ff 1558 */
bogdanm 0:9b334a45a8ff 1559 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 1560 {
mbed_official 19:112740acecfa 1561 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 0:9b334a45a8ff 1562 }
bogdanm 0:9b334a45a8ff 1563
bogdanm 0:9b334a45a8ff 1564
bogdanm 0:9b334a45a8ff 1565 /** \brief Get Pending Interrupt
bogdanm 0:9b334a45a8ff 1566
bogdanm 0:9b334a45a8ff 1567 The function reads the pending register in the NVIC and returns the pending bit
bogdanm 0:9b334a45a8ff 1568 for the specified interrupt.
bogdanm 0:9b334a45a8ff 1569
bogdanm 0:9b334a45a8ff 1570 \param [in] IRQn Interrupt number.
bogdanm 0:9b334a45a8ff 1571
bogdanm 0:9b334a45a8ff 1572 \return 0 Interrupt status is not pending.
bogdanm 0:9b334a45a8ff 1573 \return 1 Interrupt status is pending.
bogdanm 0:9b334a45a8ff 1574 */
bogdanm 0:9b334a45a8ff 1575 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 1576 {
mbed_official 19:112740acecfa 1577 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
bogdanm 0:9b334a45a8ff 1578 }
bogdanm 0:9b334a45a8ff 1579
bogdanm 0:9b334a45a8ff 1580
bogdanm 0:9b334a45a8ff 1581 /** \brief Set Pending Interrupt
bogdanm 0:9b334a45a8ff 1582
bogdanm 0:9b334a45a8ff 1583 The function sets the pending bit of an external interrupt.
bogdanm 0:9b334a45a8ff 1584
bogdanm 0:9b334a45a8ff 1585 \param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm 0:9b334a45a8ff 1586 */
bogdanm 0:9b334a45a8ff 1587 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 1588 {
mbed_official 19:112740acecfa 1589 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 0:9b334a45a8ff 1590 }
bogdanm 0:9b334a45a8ff 1591
bogdanm 0:9b334a45a8ff 1592
bogdanm 0:9b334a45a8ff 1593 /** \brief Clear Pending Interrupt
bogdanm 0:9b334a45a8ff 1594
bogdanm 0:9b334a45a8ff 1595 The function clears the pending bit of an external interrupt.
bogdanm 0:9b334a45a8ff 1596
bogdanm 0:9b334a45a8ff 1597 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 0:9b334a45a8ff 1598 */
bogdanm 0:9b334a45a8ff 1599 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 1600 {
mbed_official 19:112740acecfa 1601 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 0:9b334a45a8ff 1602 }
bogdanm 0:9b334a45a8ff 1603
bogdanm 0:9b334a45a8ff 1604
bogdanm 0:9b334a45a8ff 1605 /** \brief Get Active Interrupt
bogdanm 0:9b334a45a8ff 1606
bogdanm 0:9b334a45a8ff 1607 The function reads the active register in NVIC and returns the active bit.
bogdanm 0:9b334a45a8ff 1608
bogdanm 0:9b334a45a8ff 1609 \param [in] IRQn Interrupt number.
bogdanm 0:9b334a45a8ff 1610
bogdanm 0:9b334a45a8ff 1611 \return 0 Interrupt status is not active.
bogdanm 0:9b334a45a8ff 1612 \return 1 Interrupt status is active.
bogdanm 0:9b334a45a8ff 1613 */
bogdanm 0:9b334a45a8ff 1614 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 1615 {
mbed_official 19:112740acecfa 1616 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
bogdanm 0:9b334a45a8ff 1617 }
bogdanm 0:9b334a45a8ff 1618
bogdanm 0:9b334a45a8ff 1619
bogdanm 0:9b334a45a8ff 1620 /** \brief Set Interrupt Priority
bogdanm 0:9b334a45a8ff 1621
bogdanm 0:9b334a45a8ff 1622 The function sets the priority of an interrupt.
bogdanm 0:9b334a45a8ff 1623
bogdanm 0:9b334a45a8ff 1624 \note The priority cannot be set for every core interrupt.
bogdanm 0:9b334a45a8ff 1625
bogdanm 0:9b334a45a8ff 1626 \param [in] IRQn Interrupt number.
bogdanm 0:9b334a45a8ff 1627 \param [in] priority Priority to set.
bogdanm 0:9b334a45a8ff 1628 */
bogdanm 0:9b334a45a8ff 1629 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm 0:9b334a45a8ff 1630 {
mbed_official 19:112740acecfa 1631 if((int32_t)IRQn < 0) {
mbed_official 19:112740acecfa 1632 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
mbed_official 19:112740acecfa 1633 }
bogdanm 0:9b334a45a8ff 1634 else {
mbed_official 19:112740acecfa 1635 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
mbed_official 19:112740acecfa 1636 }
bogdanm 0:9b334a45a8ff 1637 }
bogdanm 0:9b334a45a8ff 1638
bogdanm 0:9b334a45a8ff 1639
bogdanm 0:9b334a45a8ff 1640 /** \brief Get Interrupt Priority
bogdanm 0:9b334a45a8ff 1641
bogdanm 0:9b334a45a8ff 1642 The function reads the priority of an interrupt. The interrupt
bogdanm 0:9b334a45a8ff 1643 number can be positive to specify an external (device specific)
bogdanm 0:9b334a45a8ff 1644 interrupt, or negative to specify an internal (core) interrupt.
bogdanm 0:9b334a45a8ff 1645
bogdanm 0:9b334a45a8ff 1646
bogdanm 0:9b334a45a8ff 1647 \param [in] IRQn Interrupt number.
bogdanm 0:9b334a45a8ff 1648 \return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm 0:9b334a45a8ff 1649 priority bits of the microcontroller.
bogdanm 0:9b334a45a8ff 1650 */
bogdanm 0:9b334a45a8ff 1651 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 1652 {
bogdanm 0:9b334a45a8ff 1653
mbed_official 19:112740acecfa 1654 if((int32_t)IRQn < 0) {
mbed_official 19:112740acecfa 1655 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
mbed_official 19:112740acecfa 1656 }
bogdanm 0:9b334a45a8ff 1657 else {
mbed_official 19:112740acecfa 1658 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
mbed_official 19:112740acecfa 1659 }
bogdanm 0:9b334a45a8ff 1660 }
bogdanm 0:9b334a45a8ff 1661
bogdanm 0:9b334a45a8ff 1662
bogdanm 0:9b334a45a8ff 1663 /** \brief Encode Priority
bogdanm 0:9b334a45a8ff 1664
bogdanm 0:9b334a45a8ff 1665 The function encodes the priority for an interrupt with the given priority group,
bogdanm 0:9b334a45a8ff 1666 preemptive priority value, and subpriority value.
bogdanm 0:9b334a45a8ff 1667 In case of a conflict between priority grouping and available
mbed_official 19:112740acecfa 1668 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
bogdanm 0:9b334a45a8ff 1669
bogdanm 0:9b334a45a8ff 1670 \param [in] PriorityGroup Used priority group.
bogdanm 0:9b334a45a8ff 1671 \param [in] PreemptPriority Preemptive priority value (starting from 0).
bogdanm 0:9b334a45a8ff 1672 \param [in] SubPriority Subpriority value (starting from 0).
bogdanm 0:9b334a45a8ff 1673 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
bogdanm 0:9b334a45a8ff 1674 */
bogdanm 0:9b334a45a8ff 1675 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
bogdanm 0:9b334a45a8ff 1676 {
mbed_official 19:112740acecfa 1677 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
bogdanm 0:9b334a45a8ff 1678 uint32_t PreemptPriorityBits;
bogdanm 0:9b334a45a8ff 1679 uint32_t SubPriorityBits;
bogdanm 0:9b334a45a8ff 1680
mbed_official 19:112740acecfa 1681 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
mbed_official 19:112740acecfa 1682 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
bogdanm 0:9b334a45a8ff 1683
bogdanm 0:9b334a45a8ff 1684 return (
mbed_official 19:112740acecfa 1685 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
mbed_official 19:112740acecfa 1686 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
bogdanm 0:9b334a45a8ff 1687 );
bogdanm 0:9b334a45a8ff 1688 }
bogdanm 0:9b334a45a8ff 1689
bogdanm 0:9b334a45a8ff 1690
bogdanm 0:9b334a45a8ff 1691 /** \brief Decode Priority
bogdanm 0:9b334a45a8ff 1692
bogdanm 0:9b334a45a8ff 1693 The function decodes an interrupt priority value with a given priority group to
bogdanm 0:9b334a45a8ff 1694 preemptive priority value and subpriority value.
bogdanm 0:9b334a45a8ff 1695 In case of a conflict between priority grouping and available
mbed_official 19:112740acecfa 1696 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
bogdanm 0:9b334a45a8ff 1697
bogdanm 0:9b334a45a8ff 1698 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
bogdanm 0:9b334a45a8ff 1699 \param [in] PriorityGroup Used priority group.
bogdanm 0:9b334a45a8ff 1700 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
bogdanm 0:9b334a45a8ff 1701 \param [out] pSubPriority Subpriority value (starting from 0).
bogdanm 0:9b334a45a8ff 1702 */
bogdanm 0:9b334a45a8ff 1703 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
bogdanm 0:9b334a45a8ff 1704 {
mbed_official 19:112740acecfa 1705 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
bogdanm 0:9b334a45a8ff 1706 uint32_t PreemptPriorityBits;
bogdanm 0:9b334a45a8ff 1707 uint32_t SubPriorityBits;
bogdanm 0:9b334a45a8ff 1708
mbed_official 19:112740acecfa 1709 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
mbed_official 19:112740acecfa 1710 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
bogdanm 0:9b334a45a8ff 1711
mbed_official 19:112740acecfa 1712 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
mbed_official 19:112740acecfa 1713 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
bogdanm 0:9b334a45a8ff 1714 }
bogdanm 0:9b334a45a8ff 1715
bogdanm 0:9b334a45a8ff 1716
bogdanm 0:9b334a45a8ff 1717 /** \brief System Reset
bogdanm 0:9b334a45a8ff 1718
bogdanm 0:9b334a45a8ff 1719 The function initiates a system reset request to reset the MCU.
bogdanm 0:9b334a45a8ff 1720 */
bogdanm 0:9b334a45a8ff 1721 __STATIC_INLINE void NVIC_SystemReset(void)
bogdanm 0:9b334a45a8ff 1722 {
mbed_official 19:112740acecfa 1723 __DSB(); /* Ensure all outstanding memory accesses included
mbed_official 19:112740acecfa 1724 buffered write are completed before reset */
mbed_official 19:112740acecfa 1725 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
mbed_official 19:112740acecfa 1726 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
mbed_official 19:112740acecfa 1727 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
mbed_official 19:112740acecfa 1728 __DSB(); /* Ensure completion of memory access */
mbed_official 19:112740acecfa 1729 while(1) { __NOP(); } /* wait until reset */
bogdanm 0:9b334a45a8ff 1730 }
bogdanm 0:9b334a45a8ff 1731
bogdanm 0:9b334a45a8ff 1732 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 0:9b334a45a8ff 1733
bogdanm 0:9b334a45a8ff 1734
bogdanm 0:9b334a45a8ff 1735
bogdanm 0:9b334a45a8ff 1736 /* ################################## SysTick function ############################################ */
bogdanm 0:9b334a45a8ff 1737 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 0:9b334a45a8ff 1738 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm 0:9b334a45a8ff 1739 \brief Functions that configure the System.
bogdanm 0:9b334a45a8ff 1740 @{
bogdanm 0:9b334a45a8ff 1741 */
bogdanm 0:9b334a45a8ff 1742
bogdanm 0:9b334a45a8ff 1743 #if (__Vendor_SysTickConfig == 0)
bogdanm 0:9b334a45a8ff 1744
bogdanm 0:9b334a45a8ff 1745 /** \brief System Tick Configuration
bogdanm 0:9b334a45a8ff 1746
bogdanm 0:9b334a45a8ff 1747 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 0:9b334a45a8ff 1748 Counter is in free running mode to generate periodic interrupts.
bogdanm 0:9b334a45a8ff 1749
bogdanm 0:9b334a45a8ff 1750 \param [in] ticks Number of ticks between two interrupts.
bogdanm 0:9b334a45a8ff 1751
bogdanm 0:9b334a45a8ff 1752 \return 0 Function succeeded.
bogdanm 0:9b334a45a8ff 1753 \return 1 Function failed.
bogdanm 0:9b334a45a8ff 1754
bogdanm 0:9b334a45a8ff 1755 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm 0:9b334a45a8ff 1756 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm 0:9b334a45a8ff 1757 must contain a vendor-specific implementation of this function.
bogdanm 0:9b334a45a8ff 1758
bogdanm 0:9b334a45a8ff 1759 */
bogdanm 0:9b334a45a8ff 1760 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 0:9b334a45a8ff 1761 {
mbed_official 19:112740acecfa 1762 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
bogdanm 0:9b334a45a8ff 1763
mbed_official 19:112740acecfa 1764 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
mbed_official 19:112740acecfa 1765 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
mbed_official 19:112740acecfa 1766 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
bogdanm 0:9b334a45a8ff 1767 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 0:9b334a45a8ff 1768 SysTick_CTRL_TICKINT_Msk |
mbed_official 19:112740acecfa 1769 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mbed_official 19:112740acecfa 1770 return (0UL); /* Function successful */
bogdanm 0:9b334a45a8ff 1771 }
bogdanm 0:9b334a45a8ff 1772
bogdanm 0:9b334a45a8ff 1773 #endif
bogdanm 0:9b334a45a8ff 1774
bogdanm 0:9b334a45a8ff 1775 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 0:9b334a45a8ff 1776
bogdanm 0:9b334a45a8ff 1777
bogdanm 0:9b334a45a8ff 1778
bogdanm 0:9b334a45a8ff 1779 /* ##################################### Debug In/Output function ########################################### */
bogdanm 0:9b334a45a8ff 1780 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 0:9b334a45a8ff 1781 \defgroup CMSIS_core_DebugFunctions ITM Functions
bogdanm 0:9b334a45a8ff 1782 \brief Functions that access the ITM debug interface.
bogdanm 0:9b334a45a8ff 1783 @{
bogdanm 0:9b334a45a8ff 1784 */
bogdanm 0:9b334a45a8ff 1785
bogdanm 0:9b334a45a8ff 1786 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
bogdanm 0:9b334a45a8ff 1787 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
bogdanm 0:9b334a45a8ff 1788
bogdanm 0:9b334a45a8ff 1789
bogdanm 0:9b334a45a8ff 1790 /** \brief ITM Send Character
bogdanm 0:9b334a45a8ff 1791
bogdanm 0:9b334a45a8ff 1792 The function transmits a character via the ITM channel 0, and
bogdanm 0:9b334a45a8ff 1793 \li Just returns when no debugger is connected that has booked the output.
bogdanm 0:9b334a45a8ff 1794 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
bogdanm 0:9b334a45a8ff 1795
bogdanm 0:9b334a45a8ff 1796 \param [in] ch Character to transmit.
bogdanm 0:9b334a45a8ff 1797
bogdanm 0:9b334a45a8ff 1798 \returns Character to transmit.
bogdanm 0:9b334a45a8ff 1799 */
bogdanm 0:9b334a45a8ff 1800 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
bogdanm 0:9b334a45a8ff 1801 {
mbed_official 19:112740acecfa 1802 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
mbed_official 19:112740acecfa 1803 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
bogdanm 0:9b334a45a8ff 1804 {
mbed_official 19:112740acecfa 1805 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
mbed_official 19:112740acecfa 1806 ITM->PORT[0].u8 = (uint8_t)ch;
bogdanm 0:9b334a45a8ff 1807 }
bogdanm 0:9b334a45a8ff 1808 return (ch);
bogdanm 0:9b334a45a8ff 1809 }
bogdanm 0:9b334a45a8ff 1810
bogdanm 0:9b334a45a8ff 1811
bogdanm 0:9b334a45a8ff 1812 /** \brief ITM Receive Character
bogdanm 0:9b334a45a8ff 1813
bogdanm 0:9b334a45a8ff 1814 The function inputs a character via the external variable \ref ITM_RxBuffer.
bogdanm 0:9b334a45a8ff 1815
bogdanm 0:9b334a45a8ff 1816 \return Received character.
bogdanm 0:9b334a45a8ff 1817 \return -1 No character pending.
bogdanm 0:9b334a45a8ff 1818 */
bogdanm 0:9b334a45a8ff 1819 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
bogdanm 0:9b334a45a8ff 1820 int32_t ch = -1; /* no character available */
bogdanm 0:9b334a45a8ff 1821
bogdanm 0:9b334a45a8ff 1822 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
bogdanm 0:9b334a45a8ff 1823 ch = ITM_RxBuffer;
bogdanm 0:9b334a45a8ff 1824 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
bogdanm 0:9b334a45a8ff 1825 }
bogdanm 0:9b334a45a8ff 1826
bogdanm 0:9b334a45a8ff 1827 return (ch);
bogdanm 0:9b334a45a8ff 1828 }
bogdanm 0:9b334a45a8ff 1829
bogdanm 0:9b334a45a8ff 1830
bogdanm 0:9b334a45a8ff 1831 /** \brief ITM Check Character
bogdanm 0:9b334a45a8ff 1832
bogdanm 0:9b334a45a8ff 1833 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
bogdanm 0:9b334a45a8ff 1834
bogdanm 0:9b334a45a8ff 1835 \return 0 No character available.
bogdanm 0:9b334a45a8ff 1836 \return 1 Character available.
bogdanm 0:9b334a45a8ff 1837 */
bogdanm 0:9b334a45a8ff 1838 __STATIC_INLINE int32_t ITM_CheckChar (void) {
bogdanm 0:9b334a45a8ff 1839
bogdanm 0:9b334a45a8ff 1840 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
bogdanm 0:9b334a45a8ff 1841 return (0); /* no character available */
bogdanm 0:9b334a45a8ff 1842 } else {
bogdanm 0:9b334a45a8ff 1843 return (1); /* character available */
bogdanm 0:9b334a45a8ff 1844 }
bogdanm 0:9b334a45a8ff 1845 }
bogdanm 0:9b334a45a8ff 1846
bogdanm 0:9b334a45a8ff 1847 /*@} end of CMSIS_core_DebugFunctions */
bogdanm 0:9b334a45a8ff 1848
bogdanm 0:9b334a45a8ff 1849
mbed_official 19:112740acecfa 1850
bogdanm 0:9b334a45a8ff 1851
bogdanm 0:9b334a45a8ff 1852 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 1853 }
bogdanm 0:9b334a45a8ff 1854 #endif
mbed_official 19:112740acecfa 1855
mbed_official 19:112740acecfa 1856 #endif /* __CORE_CM4_H_DEPENDANT */
mbed_official 19:112740acecfa 1857
mbed_official 19:112740acecfa 1858 #endif /* __CMSIS_GENERIC */