Yu Jiaqi / Mbed OS FTHR_USB_serial

V1.1 For EVIC

Dependencies:   SDFileSystem max32630fthr USBDevice

DUT_RegConfig.cpp@1:7530b7eb757a, 2020-05-28 (annotated)

Committer:
china_sn0w
Date:
Thu May 28 02:30:39 2020 +0000
Revision:
1:7530b7eb757a
Child:
3:35b05d91568d
V1.1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
china_sn0w 1:7530b7eb757a 1 #include "mbed.h"
china_sn0w 1:7530b7eb757a 2 #include "cmsis_os.h"
china_sn0w 1:7530b7eb757a 3 #include "max32630fthr.h"
china_sn0w 1:7530b7eb757a 4 #include "USBSerial.h"
china_sn0w 1:7530b7eb757a 5 #include "CmdHandler.h"
china_sn0w 1:7530b7eb757a 6 #include "DUT_RegConfig.h"
china_sn0w 1:7530b7eb757a 7 #include "ServoRun.h"
china_sn0w 1:7530b7eb757a 8 #include "SDFileSystem.h"
china_sn0w 1:7530b7eb757a 9 #include "Firmware.h"
china_sn0w 1:7530b7eb757a 10 #include "RegTable.h"
china_sn0w 1:7530b7eb757a 11 #include "CmdHandler.h"
china_sn0w 1:7530b7eb757a 12
china_sn0w 1:7530b7eb757a 13 DUTREG dut_reg[DUT_REG_NUM];
china_sn0w 1:7530b7eb757a 14 uint8_t Firmware[8192];
china_sn0w 1:7530b7eb757a 15 uint8_t histogram[10][1024];
china_sn0w 1:7530b7eb757a 16 uint8_t dcr_matrix[17][9*2];
china_sn0w 1:7530b7eb757a 17
china_sn0w 1:7530b7eb757a 18 uint8_t int_mark = 0;
china_sn0w 1:7530b7eb757a 19 uint8_t int_enable = 1;
china_sn0w 1:7530b7eb757a 20 uint8_t histogram_mode = 0;
china_sn0w 1:7530b7eb757a 21 uint8_t histogram_tdc = 0;
china_sn0w 1:7530b7eb757a 22
china_sn0w 1:7530b7eb757a 23 Semaphore chip_int_semph(1);
china_sn0w 1:7530b7eb757a 24 extern DigitalOut xSHUT;
china_sn0w 1:7530b7eb757a 25 extern I2C i2c_v;
china_sn0w 1:7530b7eb757a 26
china_sn0w 1:7530b7eb757a 27 uint16_t histogram_pos_num = 0;
china_sn0w 1:7530b7eb757a 28 uint16_t histogram_per_pos = 0;
china_sn0w 1:7530b7eb757a 29
china_sn0w 1:7530b7eb757a 30 extern const uint8_t reg_table[];
china_sn0w 1:7530b7eb757a 31 extern const uint8_t Firmware_Ranging[];
china_sn0w 1:7530b7eb757a 32 extern uint8_t _uart_send_pbuff[CMD_BUF_LEN] ;
china_sn0w 1:7530b7eb757a 33
china_sn0w 1:7530b7eb757a 34 void ChipInitReset(void)
china_sn0w 1:7530b7eb757a 35 {
china_sn0w 1:7530b7eb757a 36 xSHUT = 0;
china_sn0w 1:7530b7eb757a 37 wait_ms(30);
china_sn0w 1:7530b7eb757a 38 xSHUT = 1;
china_sn0w 1:7530b7eb757a 39 }
china_sn0w 1:7530b7eb757a 40
china_sn0w 1:7530b7eb757a 41 void DUT_RegInit(void)
china_sn0w 1:7530b7eb757a 42 {
china_sn0w 1:7530b7eb757a 43 LoadRegTable();
china_sn0w 1:7530b7eb757a 44 for(uint16_t i = 0; i < 256; i++) {
china_sn0w 1:7530b7eb757a 45 //WriteOneReg(dut_reg[i].addr, dut_reg[i].value);
china_sn0w 1:7530b7eb757a 46 dut_reg[i].addr = i;
china_sn0w 1:7530b7eb757a 47 dut_reg[i].value = 0x00;
china_sn0w 1:7530b7eb757a 48 }
china_sn0w 1:7530b7eb757a 49 }
china_sn0w 1:7530b7eb757a 50
china_sn0w 1:7530b7eb757a 51
china_sn0w 1:7530b7eb757a 52 void DUT_FirmwareInit(void)
china_sn0w 1:7530b7eb757a 53 {
china_sn0w 1:7530b7eb757a 54 WriteFW(LoadFirmware());
china_sn0w 1:7530b7eb757a 55 }
china_sn0w 1:7530b7eb757a 56
china_sn0w 1:7530b7eb757a 57 void Enable_DUT_Interrupt(void)
china_sn0w 1:7530b7eb757a 58 {
china_sn0w 1:7530b7eb757a 59 int_enable = 1;
china_sn0w 1:7530b7eb757a 60 }
china_sn0w 1:7530b7eb757a 61
china_sn0w 1:7530b7eb757a 62 void Disable_DUT_Interrupt(void)
china_sn0w 1:7530b7eb757a 63 {
china_sn0w 1:7530b7eb757a 64 int_enable = 0;
china_sn0w 1:7530b7eb757a 65 }
china_sn0w 1:7530b7eb757a 66
china_sn0w 1:7530b7eb757a 67 void InterruptHandle(void)
china_sn0w 1:7530b7eb757a 68 {
china_sn0w 1:7530b7eb757a 69 if(int_enable == 0)
china_sn0w 1:7530b7eb757a 70 return;
china_sn0w 1:7530b7eb757a 71
china_sn0w 1:7530b7eb757a 72 if(int_mark == 1) {
china_sn0w 1:7530b7eb757a 73 int_mark = 0;
china_sn0w 1:7530b7eb757a 74 } else if(int_mark == 2) {
china_sn0w 1:7530b7eb757a 75 chip_int_semph.release();
china_sn0w 1:7530b7eb757a 76 //发送信号量
china_sn0w 1:7530b7eb757a 77 }
china_sn0w 1:7530b7eb757a 78 }
china_sn0w 1:7530b7eb757a 79
china_sn0w 1:7530b7eb757a 80 void HistogramReport()
china_sn0w 1:7530b7eb757a 81 {
china_sn0w 1:7530b7eb757a 82 uint8_t ret = 0;
china_sn0w 1:7530b7eb757a 83 uint16_t lsb, mili;
china_sn0w 1:7530b7eb757a 84
china_sn0w 1:7530b7eb757a 85
china_sn0w 1:7530b7eb757a 86 uint16_t histogram_pos = 0;
china_sn0w 1:7530b7eb757a 87 uint16_t histogram_num = 0;
china_sn0w 1:7530b7eb757a 88 while(1) {
china_sn0w 1:7530b7eb757a 89 if(histogram_mode == 1) {
china_sn0w 1:7530b7eb757a 90 //ReadOneReg(REG_SYS_CFG, &sys_cfg_save);
china_sn0w 1:7530b7eb757a 91 //WriteOneReg(REG_SYS_CFG, 0x00);
china_sn0w 1:7530b7eb757a 92 ret = OneTimeMeasure(&lsb, &mili);
china_sn0w 1:7530b7eb757a 93 if(ret != 0) {
china_sn0w 1:7530b7eb757a 94 histogram_mode = 0;
china_sn0w 1:7530b7eb757a 95 } else {
china_sn0w 1:7530b7eb757a 96 ret = vangogh_ram_rd(histogram_tdc);
china_sn0w 1:7530b7eb757a 97 if(ret != 0) {
china_sn0w 1:7530b7eb757a 98 histogram_mode = 0;
china_sn0w 1:7530b7eb757a 99 } else {
china_sn0w 1:7530b7eb757a 100 HandleReadHistogram(histogram_tdc);
china_sn0w 1:7530b7eb757a 101 }
china_sn0w 1:7530b7eb757a 102 }
china_sn0w 1:7530b7eb757a 103 //WriteOneReg(REG_SYS_CFG, sys_cfg_save);
china_sn0w 1:7530b7eb757a 104 } else if(histogram_mode == 2) {
china_sn0w 1:7530b7eb757a 105 //ReadOneReg(REG_SYS_CFG, &sys_cfg_save);
china_sn0w 1:7530b7eb757a 106 //WriteOneReg(REG_SYS_CFG, 0x00);
china_sn0w 1:7530b7eb757a 107 ret = OneTimeMeasure(&lsb, &mili);
china_sn0w 1:7530b7eb757a 108 if(ret != 0) {
china_sn0w 1:7530b7eb757a 109 histogram_mode = 0;
china_sn0w 1:7530b7eb757a 110 } else {
china_sn0w 1:7530b7eb757a 111 for(uint8_t i = 0; i < 10; i++) {
china_sn0w 1:7530b7eb757a 112 ret = vangogh_ram_rd(i);
china_sn0w 1:7530b7eb757a 113 if(ret != 0) {
china_sn0w 1:7530b7eb757a 114 histogram_mode = 0;
china_sn0w 1:7530b7eb757a 115 break;
china_sn0w 1:7530b7eb757a 116 } else {
china_sn0w 1:7530b7eb757a 117 HandleReadHistogram(i);
china_sn0w 1:7530b7eb757a 118 wait_ms(1);
china_sn0w 1:7530b7eb757a 119 }
china_sn0w 1:7530b7eb757a 120 }
china_sn0w 1:7530b7eb757a 121 }
china_sn0w 1:7530b7eb757a 122 //WriteOneReg(REG_SYS_CFG, sys_cfg_save);
china_sn0w 1:7530b7eb757a 123 } else if(histogram_mode == 3) {
china_sn0w 1:7530b7eb757a 124
china_sn0w 1:7530b7eb757a 125
china_sn0w 1:7530b7eb757a 126 if(histogram_num >= histogram_per_pos) {
china_sn0w 1:7530b7eb757a 127 histogram_num = 0;
china_sn0w 1:7530b7eb757a 128 histogram_pos++;
china_sn0w 1:7530b7eb757a 129 if(histogram_pos >= histogram_pos_num) {
china_sn0w 1:7530b7eb757a 130 histogram_mode = 0;
china_sn0w 1:7530b7eb757a 131 }
china_sn0w 1:7530b7eb757a 132 ServoRun(1, 10);
china_sn0w 1:7530b7eb757a 133 while(CheckUntil()) wait_ms(100);
china_sn0w 1:7530b7eb757a 134 }
china_sn0w 1:7530b7eb757a 135 //ReadOneReg(REG_SYS_CFG, &sys_cfg_save);
china_sn0w 1:7530b7eb757a 136 //WriteOneReg(REG_SYS_CFG, 0x00);
china_sn0w 1:7530b7eb757a 137 ret = OneTimeMeasure(&lsb, &mili);
china_sn0w 1:7530b7eb757a 138 if(ret != 0) {
china_sn0w 1:7530b7eb757a 139 histogram_mode = 0;
china_sn0w 1:7530b7eb757a 140 } else {
china_sn0w 1:7530b7eb757a 141 for(uint8_t i = 0; i < 10; i++) {
china_sn0w 1:7530b7eb757a 142 ret = vangogh_ram_rd(i);
china_sn0w 1:7530b7eb757a 143 if(ret != 0) {
china_sn0w 1:7530b7eb757a 144 histogram_mode = 0;
china_sn0w 1:7530b7eb757a 145 break;
china_sn0w 1:7530b7eb757a 146 } else {
china_sn0w 1:7530b7eb757a 147 StoreHistogram(histogram_pos, histogram_num, i);
china_sn0w 1:7530b7eb757a 148 wait_ms(100);
china_sn0w 1:7530b7eb757a 149 }
china_sn0w 1:7530b7eb757a 150 }
china_sn0w 1:7530b7eb757a 151 }
china_sn0w 1:7530b7eb757a 152 //WriteOneReg(REG_SYS_CFG, sys_cfg_save);
china_sn0w 1:7530b7eb757a 153 histogram_num++;
china_sn0w 1:7530b7eb757a 154 } else if(histogram_mode == 4) {
china_sn0w 1:7530b7eb757a 155 //ReadOneReg(REG_SYS_CFG, &sys_cfg_save);
china_sn0w 1:7530b7eb757a 156 //WriteOneReg(REG_SYS_CFG, 0x00);
china_sn0w 1:7530b7eb757a 157 ret = OneTimeMeasure(&lsb, &mili);
china_sn0w 1:7530b7eb757a 158 if(ret != 0) {
china_sn0w 1:7530b7eb757a 159 histogram_mode = 0;
china_sn0w 1:7530b7eb757a 160 } else {
china_sn0w 1:7530b7eb757a 161 for(uint8_t i = 0; i < 9; i++) {
china_sn0w 1:7530b7eb757a 162 ret = vangogh_ram_rd(i);
china_sn0w 1:7530b7eb757a 163 if(ret != 0) {
china_sn0w 1:7530b7eb757a 164 histogram_mode = 0;
china_sn0w 1:7530b7eb757a 165 break;
china_sn0w 1:7530b7eb757a 166 } else {
china_sn0w 1:7530b7eb757a 167 HandleReadHistogram(i);
china_sn0w 1:7530b7eb757a 168 wait_ms(1);
china_sn0w 1:7530b7eb757a 169 }
china_sn0w 1:7530b7eb757a 170 }
china_sn0w 1:7530b7eb757a 171 }
china_sn0w 1:7530b7eb757a 172 //WriteOneReg(REG_SYS_CFG, sys_cfg_save);
china_sn0w 1:7530b7eb757a 173 }else {
china_sn0w 1:7530b7eb757a 174 histogram_num = 0;
china_sn0w 1:7530b7eb757a 175 histogram_pos = 0;
china_sn0w 1:7530b7eb757a 176 histogram_pos_num = 0;
china_sn0w 1:7530b7eb757a 177 histogram_per_pos = 0;
china_sn0w 1:7530b7eb757a 178 }
china_sn0w 1:7530b7eb757a 179 wait(1);
china_sn0w 1:7530b7eb757a 180 }
china_sn0w 1:7530b7eb757a 181 }
china_sn0w 1:7530b7eb757a 182
china_sn0w 1:7530b7eb757a 183 void ContinuousMeasureReport()
china_sn0w 1:7530b7eb757a 184 {
china_sn0w 1:7530b7eb757a 185 uint16_t lsb, milimeter;
china_sn0w 1:7530b7eb757a 186 uint8_t int_flag = 0;
china_sn0w 1:7530b7eb757a 187 uint16_t time_out = 0;
china_sn0w 1:7530b7eb757a 188
china_sn0w 1:7530b7eb757a 189 while(1) {
china_sn0w 1:7530b7eb757a 190
china_sn0w 1:7530b7eb757a 191 chip_int_semph.wait();
china_sn0w 1:7530b7eb757a 192
china_sn0w 1:7530b7eb757a 193 if(RaadContinuousMeasure(&lsb, &milimeter) == 0) {
china_sn0w 1:7530b7eb757a 194 HandleContinuousMeasureReport(lsb, milimeter);
china_sn0w 1:7530b7eb757a 195 }
china_sn0w 1:7530b7eb757a 196
china_sn0w 1:7530b7eb757a 197 }
china_sn0w 1:7530b7eb757a 198 }
china_sn0w 1:7530b7eb757a 199
china_sn0w 1:7530b7eb757a 200 uint8_t WriteOneReg(uint8_t addr, uint8_t data)
china_sn0w 1:7530b7eb757a 201 {
china_sn0w 1:7530b7eb757a 202 uint8_t buf[2];
china_sn0w 1:7530b7eb757a 203 buf[0] = addr;
china_sn0w 1:7530b7eb757a 204 buf[1] = data;
china_sn0w 1:7530b7eb757a 205
china_sn0w 1:7530b7eb757a 206 i2c_v.write(DUT_DEV_ADDR, (char*)buf, 2);
china_sn0w 1:7530b7eb757a 207
china_sn0w 1:7530b7eb757a 208 return 0;
china_sn0w 1:7530b7eb757a 209 }
china_sn0w 1:7530b7eb757a 210
china_sn0w 1:7530b7eb757a 211 uint8_t ReadOneReg(uint8_t addr, uint8_t *data)
china_sn0w 1:7530b7eb757a 212 {
china_sn0w 1:7530b7eb757a 213 uint8_t buf[2];
china_sn0w 1:7530b7eb757a 214 buf[0] = addr;
china_sn0w 1:7530b7eb757a 215
china_sn0w 1:7530b7eb757a 216 i2c_v.write(DUT_DEV_ADDR, (char*)buf, 1);
china_sn0w 1:7530b7eb757a 217 i2c_v.read (DUT_DEV_ADDR, (char*)data, 1);
china_sn0w 1:7530b7eb757a 218
china_sn0w 1:7530b7eb757a 219 return 0;
china_sn0w 1:7530b7eb757a 220 }
china_sn0w 1:7530b7eb757a 221
china_sn0w 1:7530b7eb757a 222
china_sn0w 1:7530b7eb757a 223 uint8_t ReadAllRegToTable(void)
china_sn0w 1:7530b7eb757a 224 {
china_sn0w 1:7530b7eb757a 225 for(uint16_t i = 0; i < DUT_REG_NUM; i++) {
china_sn0w 1:7530b7eb757a 226 ReadOneReg(dut_reg[i].addr, &(dut_reg[i].value));
china_sn0w 1:7530b7eb757a 227 }
china_sn0w 1:7530b7eb757a 228
china_sn0w 1:7530b7eb757a 229 return 0;
china_sn0w 1:7530b7eb757a 230 }
china_sn0w 1:7530b7eb757a 231
china_sn0w 1:7530b7eb757a 232 uint8_t WriteFW(uint16_t size)
china_sn0w 1:7530b7eb757a 233 {
china_sn0w 1:7530b7eb757a 234 uint8_t ret = 0;
china_sn0w 1:7530b7eb757a 235 uint8_t i;
china_sn0w 1:7530b7eb757a 236 uint8_t reg_sys_cfg;
china_sn0w 1:7530b7eb757a 237 uint8_t uart_rx_data;
china_sn0w 1:7530b7eb757a 238 uint16_t fw_size = size;
china_sn0w 1:7530b7eb757a 239 uint16_t fw_send = 0;
china_sn0w 1:7530b7eb757a 240
china_sn0w 1:7530b7eb757a 241 ret = WriteOneReg(REG_PW_CTRL, 0x08);
china_sn0w 1:7530b7eb757a 242 ret = WriteOneReg(REG_PW_CTRL, 0x0a);
china_sn0w 1:7530b7eb757a 243 ret = WriteOneReg(REG_MCU_CFG, 0x02);
china_sn0w 1:7530b7eb757a 244 ret = ReadOneReg (REG_SYS_CFG, &reg_sys_cfg);
china_sn0w 1:7530b7eb757a 245 ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg | (0x01<<0));
china_sn0w 1:7530b7eb757a 246 ret = WriteOneReg(REG_CMD, 0x01);
china_sn0w 1:7530b7eb757a 247 ret = WriteOneReg(REG_SIZE, 0x02);
china_sn0w 1:7530b7eb757a 248 ret = WriteOneReg(REG_SCRATCH_PAD_BASE+0x00, 0x00);
china_sn0w 1:7530b7eb757a 249 ret = WriteOneReg(REG_SCRATCH_PAD_BASE+0x01, 0x00);
china_sn0w 1:7530b7eb757a 250
china_sn0w 1:7530b7eb757a 251 while(fw_size >= 32) {
china_sn0w 1:7530b7eb757a 252 ret = WriteOneReg(REG_CMD,0x03);
china_sn0w 1:7530b7eb757a 253 ret = WriteOneReg(REG_SIZE,0x20);
china_sn0w 1:7530b7eb757a 254 for(i=0; i<32; i++) {
china_sn0w 1:7530b7eb757a 255 uart_rx_data = Firmware[fw_send++];
china_sn0w 1:7530b7eb757a 256 ret = WriteOneReg(REG_SCRATCH_PAD_BASE+i, uart_rx_data);
china_sn0w 1:7530b7eb757a 257 wait_us(5);
china_sn0w 1:7530b7eb757a 258 }
china_sn0w 1:7530b7eb757a 259 fw_size -= 32;
china_sn0w 1:7530b7eb757a 260 }
china_sn0w 1:7530b7eb757a 261 if(fw_size > 0) {
china_sn0w 1:7530b7eb757a 262 ret = WriteOneReg(REG_CMD,0x03);
china_sn0w 1:7530b7eb757a 263 ret = WriteOneReg(REG_SIZE,(uint8_t)fw_size);
china_sn0w 1:7530b7eb757a 264 for(i=0; i<fw_size; i++) {
china_sn0w 1:7530b7eb757a 265 uart_rx_data = Firmware[fw_send++];
china_sn0w 1:7530b7eb757a 266 ret = WriteOneReg(REG_SCRATCH_PAD_BASE+i, uart_rx_data);
china_sn0w 1:7530b7eb757a 267 wait_us(5);
china_sn0w 1:7530b7eb757a 268 }
china_sn0w 1:7530b7eb757a 269 }
china_sn0w 1:7530b7eb757a 270 ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg & ~(0x01<<0));
china_sn0w 1:7530b7eb757a 271 ret = WriteOneReg(REG_MCU_CFG, 0x03);
china_sn0w 1:7530b7eb757a 272 ret = WriteOneReg(REG_PW_CTRL, 0x02); //reset r_otp_ld_done, is a must
china_sn0w 1:7530b7eb757a 273 ret = WriteOneReg(REG_PW_CTRL, 0x00); //reset r_otp_ld_done, exit low power mode
china_sn0w 1:7530b7eb757a 274
china_sn0w 1:7530b7eb757a 275 return ret;
china_sn0w 1:7530b7eb757a 276 }
china_sn0w 1:7530b7eb757a 277
china_sn0w 1:7530b7eb757a 278 uint8_t vangogh_ram_rd(uint8_t tdc) //UART CMD foramt: CMD-1-byte|TDC-index-1-byte
china_sn0w 1:7530b7eb757a 279 {
china_sn0w 1:7530b7eb757a 280 uint8_t ret = 0;
china_sn0w 1:7530b7eb757a 281 uint8_t i;
china_sn0w 1:7530b7eb757a 282 uint8_t j;
china_sn0w 1:7530b7eb757a 283 uint8_t reg_pw_ctrl;
china_sn0w 1:7530b7eb757a 284 uint8_t reg_sys_cfg;
china_sn0w 1:7530b7eb757a 285 uint8_t tdc_index = tdc;
china_sn0w 1:7530b7eb757a 286 uint16_t ram_addr_base = 0x1000 + 0x0400 * tdc_index;
china_sn0w 1:7530b7eb757a 287
china_sn0w 1:7530b7eb757a 288 ret = ReadOneReg (REG_SYS_CFG, &reg_sys_cfg );
china_sn0w 1:7530b7eb757a 289 ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg | (0x01<<0));
china_sn0w 1:7530b7eb757a 290 ret = ReadOneReg (REG_PW_CTRL, &reg_pw_ctrl);
china_sn0w 1:7530b7eb757a 291 ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl | (0x01<<3)); //set otp_ld_done
china_sn0w 1:7530b7eb757a 292 ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl | (0x01<<3) | (0x01<<1)); //set otp_ld_done, pw_ctrl_lp
china_sn0w 1:7530b7eb757a 293 ret = WriteOneReg(REG_CMD, 0x01);
china_sn0w 1:7530b7eb757a 294 ret = WriteOneReg(REG_SIZE, 0x02);
china_sn0w 1:7530b7eb757a 295 ret = WriteOneReg(REG_SCRATCH_PAD_BASE+0x00, *((uint8_t*)(&ram_addr_base) ));
china_sn0w 1:7530b7eb757a 296 ret = WriteOneReg(REG_SCRATCH_PAD_BASE+0x01, *((uint8_t*)(&ram_addr_base)+1));
china_sn0w 1:7530b7eb757a 297 wait_us(100);
china_sn0w 1:7530b7eb757a 298 for(j=0; j<32; j++) {
china_sn0w 1:7530b7eb757a 299 ret = WriteOneReg(REG_CMD,0x05); //Issue RAM read command
china_sn0w 1:7530b7eb757a 300 ret = WriteOneReg(REG_SIZE,0x20); //Issue RAM read command
china_sn0w 1:7530b7eb757a 301 wait_us(100);
china_sn0w 1:7530b7eb757a 302 for(i=0; i<32; i++) {
china_sn0w 1:7530b7eb757a 303 ret = ReadOneReg(0x0c+i, &histogram[tdc_index][32*j + i]);
china_sn0w 1:7530b7eb757a 304 }
china_sn0w 1:7530b7eb757a 305 }
china_sn0w 1:7530b7eb757a 306 ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg & ~(0x01<<0)); //clear sc_en
china_sn0w 1:7530b7eb757a 307 ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl | (0x01<<1)); //restore power control register
china_sn0w 1:7530b7eb757a 308 ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl & ~(0x01<<1)); //clear pw_ctrl_lp
china_sn0w 1:7530b7eb757a 309
china_sn0w 1:7530b7eb757a 310 return ret;
china_sn0w 1:7530b7eb757a 311 }
china_sn0w 1:7530b7eb757a 312
china_sn0w 1:7530b7eb757a 313 uint8_t OneTimeMeasure(uint16_t *lsb, uint16_t *milimeter)
china_sn0w 1:7530b7eb757a 314 {
china_sn0w 1:7530b7eb757a 315 uint8_t ret = 0;
china_sn0w 1:7530b7eb757a 316 uint8_t reg_pw_ctrl;
china_sn0w 1:7530b7eb757a 317 uint8_t reg_sys_cfg;
china_sn0w 1:7530b7eb757a 318 uint32_t timeout = 0;
china_sn0w 1:7530b7eb757a 319
china_sn0w 1:7530b7eb757a 320 int_mark = 1;//One Time Measure
china_sn0w 1:7530b7eb757a 321
china_sn0w 1:7530b7eb757a 322 //ret = ReadOneReg (REG_SYS_CFG, &reg_sys_cfg );
china_sn0w 1:7530b7eb757a 323 //ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg | (0x01<<0));
china_sn0w 1:7530b7eb757a 324 //ret = ReadOneReg (REG_PW_CTRL, &reg_pw_ctrl);
china_sn0w 1:7530b7eb757a 325 //ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl | (0x01<<3)); //set otp_ld_done
china_sn0w 1:7530b7eb757a 326 //ret = WriteOneReg(REG_PW_CTRL, (reg_pw_ctrl | (0x01<<3)) & ~(0x01<<1)); //set otp_ld_done, clear pw_ctrl_lp
china_sn0w 1:7530b7eb757a 327 ret = WriteOneReg(REG_CMD, 0x0E);
china_sn0w 1:7530b7eb757a 328 //ret = WriteOneReg(REG_SIZE, 0x00);
china_sn0w 1:7530b7eb757a 329
china_sn0w 1:7530b7eb757a 330 timeout = 1000;
china_sn0w 1:7530b7eb757a 331 while(int_mark == 1 && timeout != 0) {
china_sn0w 1:7530b7eb757a 332 timeout--;
china_sn0w 1:7530b7eb757a 333 wait_ms(5);
china_sn0w 1:7530b7eb757a 334 }
china_sn0w 1:7530b7eb757a 335
china_sn0w 1:7530b7eb757a 336 if(timeout == 0) {
china_sn0w 1:7530b7eb757a 337 return 1;
china_sn0w 1:7530b7eb757a 338
china_sn0w 1:7530b7eb757a 339 } else {
china_sn0w 1:7530b7eb757a 340
china_sn0w 1:7530b7eb757a 341 ret = ReadOneReg(0x0d, (uint8_t*)lsb);
china_sn0w 1:7530b7eb757a 342 ret = ReadOneReg(0x0e, (uint8_t*)lsb + 1);
china_sn0w 1:7530b7eb757a 343
china_sn0w 1:7530b7eb757a 344 ret = ReadOneReg(0x18, (uint8_t*)milimeter);
china_sn0w 1:7530b7eb757a 345 ret = ReadOneReg(0x19, (uint8_t*)milimeter + 1);
china_sn0w 1:7530b7eb757a 346
china_sn0w 1:7530b7eb757a 347 }
china_sn0w 1:7530b7eb757a 348
china_sn0w 1:7530b7eb757a 349 //ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg & ~(0x01<<0)); //clear sc_en
china_sn0w 1:7530b7eb757a 350 //ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl | (0x01<<1)); //restore power control register
china_sn0w 1:7530b7eb757a 351 //ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl & ~(0x01<<1)); //clear pw_ctrl_lp
china_sn0w 1:7530b7eb757a 352
china_sn0w 1:7530b7eb757a 353 return ret;
china_sn0w 1:7530b7eb757a 354 }
china_sn0w 1:7530b7eb757a 355
china_sn0w 1:7530b7eb757a 356 uint8_t ContinuousMeasure(void)
china_sn0w 1:7530b7eb757a 357 {
china_sn0w 1:7530b7eb757a 358 uint8_t ret = 0;
china_sn0w 1:7530b7eb757a 359 uint8_t reg_pw_ctrl;
china_sn0w 1:7530b7eb757a 360 uint8_t reg_sys_cfg;
china_sn0w 1:7530b7eb757a 361
china_sn0w 1:7530b7eb757a 362 int_mark = 2;//Continuous Time Measure
china_sn0w 1:7530b7eb757a 363
china_sn0w 1:7530b7eb757a 364 //ret = ReadOneReg (REG_SYS_CFG, &reg_sys_cfg );
china_sn0w 1:7530b7eb757a 365 //ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg | (0x01<<0));
china_sn0w 1:7530b7eb757a 366 //ret = ReadOneReg (REG_PW_CTRL, &reg_pw_ctrl);
china_sn0w 1:7530b7eb757a 367 //ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl | (0x01<<3)); //set otp_ld_done
china_sn0w 1:7530b7eb757a 368 //ret = WriteOneReg(REG_PW_CTRL, (reg_pw_ctrl | (0x01<<3)) & ~(0x01<<1)); //set otp_ld_done, clear pw_ctrl_lp
china_sn0w 1:7530b7eb757a 369 ret = WriteOneReg(REG_CMD, 0x0F);
china_sn0w 1:7530b7eb757a 370 //ret = WriteOneReg(REG_SIZE, 0x00);
china_sn0w 1:7530b7eb757a 371
china_sn0w 1:7530b7eb757a 372 //ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg & ~(0x01<<0)); //clear sc_en
china_sn0w 1:7530b7eb757a 373
china_sn0w 1:7530b7eb757a 374 return ret;
china_sn0w 1:7530b7eb757a 375 }
china_sn0w 1:7530b7eb757a 376
china_sn0w 1:7530b7eb757a 377 uint8_t RaadContinuousMeasure(uint16_t *lsb, uint16_t *milimeter)
china_sn0w 1:7530b7eb757a 378 {
china_sn0w 1:7530b7eb757a 379 uint8_t ret = 0;
china_sn0w 1:7530b7eb757a 380 uint8_t reg_pw_ctrl;
china_sn0w 1:7530b7eb757a 381 uint8_t reg_sys_cfg;
china_sn0w 1:7530b7eb757a 382
china_sn0w 1:7530b7eb757a 383 int_mark = 2;//Continuous Time Measure
china_sn0w 1:7530b7eb757a 384
china_sn0w 1:7530b7eb757a 385 //ret = ReadOneReg (REG_SYS_CFG, &reg_sys_cfg );
china_sn0w 1:7530b7eb757a 386 //ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg | (0x01<<0));
china_sn0w 1:7530b7eb757a 387 //ret = ReadOneReg (REG_PW_CTRL, &reg_pw_ctrl);
china_sn0w 1:7530b7eb757a 388 //ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl | (0x01<<3)); //set otp_ld_done
china_sn0w 1:7530b7eb757a 389 //ret = WriteOneReg(REG_PW_CTRL, (reg_pw_ctrl | (0x01<<3)) & ~(0x01<<1)); //set otp_ld_done, clear pw_ctrl_lp
china_sn0w 1:7530b7eb757a 390
china_sn0w 1:7530b7eb757a 391 ret = ReadOneReg(0x0d, (uint8_t*)lsb);
china_sn0w 1:7530b7eb757a 392 ret = ReadOneReg(0x0e, (uint8_t*)lsb + 1);
china_sn0w 1:7530b7eb757a 393
china_sn0w 1:7530b7eb757a 394 ret = ReadOneReg(0x18, (uint8_t*)milimeter);
china_sn0w 1:7530b7eb757a 395 ret = ReadOneReg(0x19, (uint8_t*)milimeter + 1);
china_sn0w 1:7530b7eb757a 396
china_sn0w 1:7530b7eb757a 397 //ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg & ~(0x01<<0)); //clear sc_en
china_sn0w 1:7530b7eb757a 398
china_sn0w 1:7530b7eb757a 399 return ret;
china_sn0w 1:7530b7eb757a 400 }
china_sn0w 1:7530b7eb757a 401
china_sn0w 1:7530b7eb757a 402 uint8_t StopContinuousMeasure()
china_sn0w 1:7530b7eb757a 403 {
china_sn0w 1:7530b7eb757a 404 uint8_t ret = 0;
china_sn0w 1:7530b7eb757a 405 uint8_t reg_pw_ctrl;
china_sn0w 1:7530b7eb757a 406 uint8_t reg_sys_cfg;
china_sn0w 1:7530b7eb757a 407
china_sn0w 1:7530b7eb757a 408 int_mark = 0;//Continuous Time Measure
china_sn0w 1:7530b7eb757a 409
china_sn0w 1:7530b7eb757a 410 //ret = ReadOneReg (REG_SYS_CFG, &reg_sys_cfg );
china_sn0w 1:7530b7eb757a 411 //ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg | (0x01<<0));
china_sn0w 1:7530b7eb757a 412 //ret = ReadOneReg (REG_PW_CTRL, &reg_pw_ctrl);
china_sn0w 1:7530b7eb757a 413 //ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl | (0x01<<3)); //set otp_ld_done
china_sn0w 1:7530b7eb757a 414 //ret = WriteOneReg(REG_PW_CTRL, (reg_pw_ctrl | (0x01<<3)) & ~(0x01<<1)); //set otp_ld_done, clear pw_ctrl_lp
china_sn0w 1:7530b7eb757a 415 ret = WriteOneReg(REG_CMD, 0x00);
china_sn0w 1:7530b7eb757a 416 ret = WriteOneReg(REG_SIZE, 0x00);
china_sn0w 1:7530b7eb757a 417
china_sn0w 1:7530b7eb757a 418 //ret = WriteOneReg(REG_SYS_CFG, reg_sys_cfg & ~(0x01<<0)); //clear sc_en
china_sn0w 1:7530b7eb757a 419 //ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl | (0x01<<1)); //restore power control register
china_sn0w 1:7530b7eb757a 420 //ret = WriteOneReg(REG_PW_CTRL, reg_pw_ctrl & ~(0x01<<1)); //clear pw_ctrl_lp
china_sn0w 1:7530b7eb757a 421
china_sn0w 1:7530b7eb757a 422 return ret;
china_sn0w 1:7530b7eb757a 423 }
china_sn0w 1:7530b7eb757a 424
china_sn0w 1:7530b7eb757a 425 void StoreHistogram(uint16_t histogram_pos, uint16_t histogram_num, uint8_t tdc)
china_sn0w 1:7530b7eb757a 426 {
china_sn0w 1:7530b7eb757a 427 /*
china_sn0w 1:7530b7eb757a 428 char file_name[20];
china_sn0w 1:7530b7eb757a 429
china_sn0w 1:7530b7eb757a 430 //sprintf(file_name, "/sd/hist_%d_%d_tdc%d", histogram_pos, histogram_num, tdc);
china_sn0w 1:7530b7eb757a 431 sprintf(file_name, "/sd/hello.txt");
china_sn0w 1:7530b7eb757a 432
china_sn0w 1:7530b7eb757a 433 FILE *fp = fopen(file_name, "w");
china_sn0w 1:7530b7eb757a 434 //for(uint32_t i = 0; i < 1024; i++) {
china_sn0w 1:7530b7eb757a 435 // fseek(fp,0,SEEK_END);
china_sn0w 1:7530b7eb757a 436 // fprintf(fp, "%02X ", histogram[tdc][i]);
china_sn0w 1:7530b7eb757a 437 //}
china_sn0w 1:7530b7eb757a 438 fprintf(fp, "hello ");
china_sn0w 1:7530b7eb757a 439
china_sn0w 1:7530b7eb757a 440 fflush(fp);
china_sn0w 1:7530b7eb757a 441 fclose(fp);
china_sn0w 1:7530b7eb757a 442 */
china_sn0w 1:7530b7eb757a 443
china_sn0w 1:7530b7eb757a 444 _uart_send_pbuff[0] = histogram_pos;
china_sn0w 1:7530b7eb757a 445 _uart_send_pbuff[1] = histogram_pos >> 8;
china_sn0w 1:7530b7eb757a 446
china_sn0w 1:7530b7eb757a 447 _uart_send_pbuff[2] = tdc;
china_sn0w 1:7530b7eb757a 448
china_sn0w 1:7530b7eb757a 449 _uart_send_pbuff[3] = histogram_num;
china_sn0w 1:7530b7eb757a 450 _uart_send_pbuff[4] = histogram_num >> 8;
china_sn0w 1:7530b7eb757a 451
china_sn0w 1:7530b7eb757a 452 memcpy(&_uart_send_pbuff[5], histogram[tdc], 1024);
china_sn0w 1:7530b7eb757a 453
china_sn0w 1:7530b7eb757a 454 UART_CmdAckSend(READ_CMD | 0x80, VAN_STEP_HISTOGRAM_CMD, _uart_send_pbuff, 1024 + 1 + 2 + 2);
china_sn0w 1:7530b7eb757a 455 //return 0;
china_sn0w 1:7530b7eb757a 456 }
china_sn0w 1:7530b7eb757a 457
china_sn0w 1:7530b7eb757a 458 uint8_t DCRTest(uint8_t vspad, uint8_t test_time)
china_sn0w 1:7530b7eb757a 459 {
china_sn0w 1:7530b7eb757a 460 uint8_t ret = 0;
china_sn0w 1:7530b7eb757a 461 uint32_t timeout = 0;
china_sn0w 1:7530b7eb757a 462 memset(dcr_matrix, 0x00, 17*9*2);
china_sn0w 1:7530b7eb757a 463 WriteOneReg(0x50, 0x01);
china_sn0w 1:7530b7eb757a 464 WriteOneReg(0xBD, 0x01);
china_sn0w 1:7530b7eb757a 465 wait_ms(100);
china_sn0w 1:7530b7eb757a 466 WriteOneReg(0xD8, 0xF0);
china_sn0w 1:7530b7eb757a 467
china_sn0w 1:7530b7eb757a 468 for(uint8_t group = 0; group < 9; group++) {
china_sn0w 1:7530b7eb757a 469 WriteOneReg(0x0C, group);
china_sn0w 1:7530b7eb757a 470 wait_ms(1);
china_sn0w 1:7530b7eb757a 471 WriteOneReg(0x0D, test_time);
china_sn0w 1:7530b7eb757a 472 wait_ms(1);
china_sn0w 1:7530b7eb757a 473
china_sn0w 1:7530b7eb757a 474 timeout = 25;
china_sn0w 1:7530b7eb757a 475 int_mark = 1;
china_sn0w 1:7530b7eb757a 476 WriteOneReg(0x0A, 0x0C);
china_sn0w 1:7530b7eb757a 477 while(int_mark == 1 && timeout != 0) {
china_sn0w 1:7530b7eb757a 478 timeout--;
china_sn0w 1:7530b7eb757a 479 wait_ms(100);
china_sn0w 1:7530b7eb757a 480 }
china_sn0w 1:7530b7eb757a 481 //osDelay(80);
china_sn0w 1:7530b7eb757a 482 for(uint8_t pix = 0; pix < 17; pix++) {
china_sn0w 1:7530b7eb757a 483 ret = ReadOneReg(0x82 + pix*2, &dcr_matrix[pix][group*2 + 1]);
china_sn0w 1:7530b7eb757a 484 ret = ReadOneReg(0x82 + pix*2 + 1, &dcr_matrix[pix][group*2]);
china_sn0w 1:7530b7eb757a 485 //osDelay(1);
china_sn0w 1:7530b7eb757a 486 if(ret != 0)
china_sn0w 1:7530b7eb757a 487 return ret;
china_sn0w 1:7530b7eb757a 488 }
china_sn0w 1:7530b7eb757a 489
china_sn0w 1:7530b7eb757a 490 }
china_sn0w 1:7530b7eb757a 491
china_sn0w 1:7530b7eb757a 492 return 0;
china_sn0w 1:7530b7eb757a 493 }
china_sn0w 1:7530b7eb757a 494
china_sn0w 1:7530b7eb757a 495 uint8_t DelayLineTest(uint8_t phase, uint8_t* buf)
china_sn0w 1:7530b7eb757a 496 {
china_sn0w 1:7530b7eb757a 497 uint8_t ret = 0;
china_sn0w 1:7530b7eb757a 498 uint32_t timeout = 0;
china_sn0w 1:7530b7eb757a 499
china_sn0w 1:7530b7eb757a 500 WriteOneReg(0xE4, phase);
china_sn0w 1:7530b7eb757a 501 wait_ms(10);
china_sn0w 1:7530b7eb757a 502
china_sn0w 1:7530b7eb757a 503 for(uint8_t step = 0; step < 8; step++) {
china_sn0w 1:7530b7eb757a 504 WriteOneReg(0xE1, 0x61 | (step << 1));
china_sn0w 1:7530b7eb757a 505 wait_ms(10);
china_sn0w 1:7530b7eb757a 506
china_sn0w 1:7530b7eb757a 507 timeout = 50;
china_sn0w 1:7530b7eb757a 508 int_mark = 1;
china_sn0w 1:7530b7eb757a 509 WriteOneReg(0x0A, 0x0B);
china_sn0w 1:7530b7eb757a 510 wait_ms(10);
china_sn0w 1:7530b7eb757a 511 while(int_mark == 1 && timeout != 0) {
china_sn0w 1:7530b7eb757a 512 timeout--;
china_sn0w 1:7530b7eb757a 513 wait_ms(100);
china_sn0w 1:7530b7eb757a 514 }
china_sn0w 1:7530b7eb757a 515 for(uint8_t tdc = 0; tdc < 9; tdc++) {
china_sn0w 1:7530b7eb757a 516 ret = ReadOneReg(0x0c + tdc*2, buf + step*18 + tdc*2 + 1);
china_sn0w 1:7530b7eb757a 517 wait_ms(1);
china_sn0w 1:7530b7eb757a 518 ret = ReadOneReg(0x0c + tdc*2 + 1, buf + step*18 + tdc*2);
china_sn0w 1:7530b7eb757a 519 wait_ms(1);
china_sn0w 1:7530b7eb757a 520 }
china_sn0w 1:7530b7eb757a 521
china_sn0w 1:7530b7eb757a 522 }
china_sn0w 1:7530b7eb757a 523
china_sn0w 1:7530b7eb757a 524 return 0;
china_sn0w 1:7530b7eb757a 525 }
china_sn0w 1:7530b7eb757a 526
china_sn0w 1:7530b7eb757a 527 uint8_t GetTdcPhase(uint8_t* buf)
china_sn0w 1:7530b7eb757a 528 {
china_sn0w 1:7530b7eb757a 529 uint8_t ret = 0;
china_sn0w 1:7530b7eb757a 530 uint32_t timeout = 0;
china_sn0w 1:7530b7eb757a 531 memset(buf, 0x00, 10);
china_sn0w 1:7530b7eb757a 532
china_sn0w 1:7530b7eb757a 533 WriteOneReg(0x0C, 0x0C);
china_sn0w 1:7530b7eb757a 534 WriteOneReg(0x0A, 0x0A);
china_sn0w 1:7530b7eb757a 535 wait_ms(1);
china_sn0w 1:7530b7eb757a 536
china_sn0w 1:7530b7eb757a 537 timeout = 10;
china_sn0w 1:7530b7eb757a 538 int_mark = 1;
china_sn0w 1:7530b7eb757a 539 WriteOneReg(0x0A, 0x0B);
china_sn0w 1:7530b7eb757a 540 while(int_mark == 1 && timeout != 0) {
china_sn0w 1:7530b7eb757a 541 timeout--;
china_sn0w 1:7530b7eb757a 542 wait_ms(100);
china_sn0w 1:7530b7eb757a 543 }
china_sn0w 1:7530b7eb757a 544 //osDelay(80);
china_sn0w 1:7530b7eb757a 545
china_sn0w 1:7530b7eb757a 546 ret = ReadOneReg(0x0D, buf);
china_sn0w 1:7530b7eb757a 547 ret = ReadOneReg(0xE4, buf + 1);
china_sn0w 1:7530b7eb757a 548
china_sn0w 1:7530b7eb757a 549 if(ret != 0)
china_sn0w 1:7530b7eb757a 550 return ret;
china_sn0w 1:7530b7eb757a 551
china_sn0w 1:7530b7eb757a 552 return 0;
china_sn0w 1:7530b7eb757a 553 }
china_sn0w 1:7530b7eb757a 554
china_sn0w 1:7530b7eb757a 555