nikos chalikias
mbed-HDK used 'as is' for n-U35 board. Just flash the lpc11u35_lpc1768_if_mbed.bin file to LPC11U35. It is in the LPC1768 directory, inside NXP directory
Diff: mbed-HDK.lbr
- Revision:
- 2:9aa761c69da4
- Child:
- 3:6bd3dd3819ff
diff -r 6f64b7ee2718 -r 9aa761c69da4 mbed-HDK.lbr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-HDK.lbr Fri Sep 13 17:15:41 2013 +0100 @@ -0,0 +1,15998 @@ +<?xml version="1.0" encoding="utf-8"?> +<!DOCTYPE eagle SYSTEM "eagle.dtd"> +<eagle version="6.2"> +<drawing> +<settings> +<setting alwaysvectorfont="no"/> +<setting verticaltext="up"/> +</settings> +<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/> +<layers> +<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/> +<layer number="2" name="Route2" color="1" fill="3" visible="no" active="yes"/> +<layer number="3" name="Route3" color="4" fill="3" visible="no" active="yes"/> +<layer number="4" name="Route4" color="1" fill="4" visible="no" active="yes"/> +<layer number="5" name="Route5" color="4" fill="4" visible="no" active="yes"/> +<layer number="6" name="Route6" color="1" fill="8" visible="no" active="yes"/> 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x2="17.78" y2="2.54" width="0.254" layer="94"/> +<wire x1="17.78" y1="2.54" x2="-17.78" y2="2.54" width="0.254" layer="94"/> +<wire x1="-17.78" y1="2.54" x2="-17.78" y2="-58.42" width="0.254" layer="94"/> +<pin name="IF_NRESET" x="-22.86" y="-5.08" length="middle"/> +<pin name="LED_HID" x="22.86" y="-7.62" length="middle" rot="R180"/> +<pin name="LED_MSD" x="22.86" y="-5.08" length="middle" rot="R180"/> +<pin name="LED_UART" x="22.86" y="-10.16" length="middle" rot="R180"/> +<pin name="NC2" x="-10.16" y="-63.5" length="middle" rot="R90"/> +<pin name="NC3" x="-7.62" y="-63.5" length="middle" rot="R90"/> +<pin name="NC4" x="-5.08" y="-63.5" length="middle" rot="R90"/> +<pin name="NC5" x="-2.54" y="-63.5" length="middle" rot="R90"/> +<pin name="NC6" x="0" y="-63.5" length="middle" rot="R90"/> +<pin name="NC7" x="2.54" y="-63.5" length="middle" rot="R90"/> +<pin name="NC8" x="5.08" y="-63.5" length="middle" rot="R90"/> +<pin name="NC9" x="7.62" y="-63.5" length="middle" rot="R90"/> +<pin name="NC10" x="10.16" y="-63.5" length="middle" rot="R90"/> +<pin name="NC11" x="12.7" y="-63.5" length="middle" rot="R90"/> +<pin name="NRESET_FB_BL" x="-22.86" y="-10.16" length="middle"/> +<pin name="NRESET_FB_ISP" x="-22.86" y="-12.7" length="middle"/> +<pin name="SLEEP_NREQ" x="22.86" y="-33.02" length="middle" rot="R180"/> +<pin name="TGT_NRESET" x="22.86" y="-25.4" length="middle" rot="R180"/> +<pin name="TGT_RX" x="22.86" y="-43.18" length="middle" rot="R180"/> +<pin name="TGT_SWCLK" x="22.86" y="-15.24" length="middle" rot="R180"/> +<pin name="TGT_SWDIO" x="22.86" y="-17.78" length="middle" rot="R180"/> +<pin name="TGT_SWO" x="22.86" y="-20.32" length="middle" rot="R180"/> +<pin name="TGT_TX" x="22.86" y="-40.64" length="middle" rot="R180"/> +<pin name="USB_D+" x="-22.86" y="-17.78" length="middle"/> +<pin name="USB_D-" x="-22.86" y="-20.32" length="middle"/> +<pin name="USB_SCON" x="-22.86" y="-25.4" length="middle"/> +<pin name="USB_VBUS" x="-22.86" y="-22.86" length="middle"/> +<pin name="VDD1" x="-22.86" y="-30.48" length="middle"/> +<pin name="VDD2" x="-22.86" y="-33.02" length="middle"/> +<pin name="VSS" x="-22.86" y="-40.64" length="middle"/> +<pin name="WAKE_NREQ" x="22.86" y="-30.48" length="middle" rot="R180"/> +<pin name="XTALIN" x="-22.86" y="-45.72" length="middle"/> +<pin name="XTALOUT" x="-22.86" y="-48.26" length="middle"/> +<text x="-17.78" y="5.08" size="1.016" layer="95" font="vector">>NAME</text> +<text x="-10.16" y="5.08" size="1.016" layer="96" font="vector">>VALUE</text> +<text x="-13.97" y="-1.27" size="1.778" layer="94" font="vector">LPC11U35FHI33/501</text> +</symbol> +</symbols> +<devicesets> +<deviceset name="SWD-10" prefix="CON"> +<gates> +<gate name="G$1" symbol="SWD-10" x="-5.08" y="0"/> +</gates> +<devices> +<device name="_TC" package="SWD-10-TAGCONNECT"> +<connects> +<connect gate="G$1" pin="P$1" pad="P$1"/> +<connect gate="G$1" pin="P$10" pad="P$10"/> +<connect gate="G$1" pin="P$2" pad="P$2"/> +<connect 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+<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$10" pad="10"/> +<connect gate="G$1" pin="P$2" pad="2"/> +<connect gate="G$1" pin="P$3" pad="3"/> +<connect gate="G$1" pin="P$4" pad="4"/> +<connect gate="G$1" pin="P$5" pad="5"/> +<connect gate="G$1" pin="P$6" pad="6"/> +<connect gate="G$1" pin="P$7" pad="7"/> +<connect gate="G$1" pin="P$8" pad="8"/> +<connect gate="G$1" pin="P$9" pad="9"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="BAT60A" prefix="D"> +<description><b>Schottky Diode</b><p></description> +<gates> +<gate name="G$1" symbol="BAT60A" x="0" y="0"/> +</gates> +<devices> +<device name="" package="BAT60A"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="K" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="BSS84" prefix="T"> +<description><b>P-CHANNEL MOS FET</b></description> +<gates> +<gate name="G$1" symbol="P-MOS" x="0" y="0"/> +</gates> +<devices> +<device name="" package="SOT23"> +<connects> +<connect gate="G$1" pin="D" pad="3"/> +<connect gate="G$1" pin="G" pad="1"/> +<connect gate="G$1" pin="S" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="MBED_HDK"> +<gates> +<gate name="G$1" symbol="MBED_HDK" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="MBED-ENABLED-LOGO" prefix="SS"> +<gates> +<gate name="G$1" symbol="MBED-ENABLED-LOGO" x="2.54" y="2.54"/> +</gates> +<devices> +<device name="SMALL" package="MBED-ENABLED-LOGO-250X250-MIL"> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="MEDIUM" package="MBED-ENABLED-LOGO-500X500-MIL"> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="LARGE" package="MBED-ENABLED-LOGO-1000X1000-MIL"> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="CE-MARK" prefix="SS"> +<gates> +<gate name="G$1" symbol="CE-MARK" x="0" y="0"/> +</gates> +<devices> +<device name="" package="CE-MARK-0.2"> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="PB-MARK" prefix="SS"> +<gates> +<gate name="G$1" symbol="PB-FREE" x="-6.35" y="1.27"/> +</gates> +<devices> +<device name="" package="PB-MARK-0.2"> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="LD1117S33" prefix="IC"> +<description>VOLTAGE REGULATOR SMD 3,3V</description> +<gates> +<gate name="G$1" symbol="LD1117S33" x="-2.54" y="0"/> +</gates> +<devices> +<device name="" package="SOT223"> +<connects> +<connect gate="G$1" pin="GND" pad="1"/> +<connect gate="G$1" pin="IN" pad="3"/> +<connect gate="G$1" pin="K" pad="4"/> +<connect gate="G$1" pin="OUT" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="LPC11U24" prefix="IC"> +<description>NXP Cortex-M0 Micrcontroller</description> +<gates> +<gate name="G$1" symbol="LPC11U24" x="0" y="0"/> +</gates> +<devices> +<device name="" package="MBED-ICS_LQFP64"> +<connects> +<connect gate="G$1" pin="NTRST/PIO0.14/AD3/CT32B1M1" pad="46"/> +<connect gate="G$1" pin="PIO0.0/NRESET" pad="4"/> +<connect gate="G$1" pin="PIO0.1/CLKOUT/CT32B0M2/USB_FTOG" pad="5"/> +<connect gate="G$1" pin="PIO0.16/AD5/CT32B1M3/WAKEUP" pad="53"/> +<connect gate="G$1" pin="PIO0.17/RTS/CT32B0C0/SCLK" pad="60"/> +<connect gate="G$1" pin="PIO0.18/RXD/CT32B0M0" pad="61"/> +<connect gate="G$1" pin="PIO0.19/TXD/CT32B0M1" pad="62"/> +<connect gate="G$1" pin="PIO0.2/SSEL0/CT16B0C0" pad="13"/> +<connect gate="G$1" pin="PIO0.20/CT16B1C0" pad="11"/> +<connect gate="G$1" pin="PIO0.21/CT16B1M0/MOSI1" pad="22"/> +<connect gate="G$1" pin="PIO0.22/AD6/CT16B1M1/MISO1" pad="40"/> +<connect gate="G$1" pin="PIO0.23/AD7" pad="56"/> +<connect gate="G$1" pin="PIO0.3/USB_VBUS" pad="19"/> +<connect gate="G$1" pin="PIO0.4/SCL(OD)" pad="20"/> +<connect gate="G$1" pin="PIO0.5/SDA(OD)" pad="21"/> +<connect gate="G$1" pin="PIO0.6/USB_CON/SCK0" pad="29"/> +<connect gate="G$1" pin="PIO0.7/CTS" pad="30"/> +<connect gate="G$1" pin="PIO0.8/MISO0/CT16B0M0" pad="36"/> +<connect gate="G$1" pin="PIO0.9/MOSI0/CT16B0M1" pad="37"/> +<connect gate="G$1" pin="PIO1.0/CT32B1M0" pad="1"/> +<connect gate="G$1" pin="PIO1.1/CT32B1M1" pad="17"/> +<connect gate="G$1" pin="PIO1.10" pad="12"/> +<connect gate="G$1" pin="PIO1.11" pad="43"/> +<connect gate="G$1" pin="PIO1.12" pad="59"/> +<connect gate="G$1" pin="PIO1.13/DTR/CT16B0M1/TXD" pad="47"/> +<connect gate="G$1" pin="PIO1.14/DSR/CT16B0M1/RXD" pad="49"/> +<connect gate="G$1" pin="PIO1.15/DCD/CT16B0M2/SCK1" pad="57"/> +<connect gate="G$1" pin="PIO1.16/RI/CT16B0C0" pad="63"/> +<connect gate="G$1" pin="PIO1.17/CT16B0C1/RXD" pad="23"/> +<connect gate="G$1" pin="PIO1.18/CT16B1C1/TXD" pad="28"/> +<connect gate="G$1" pin="PIO1.19/DTR/SSEL1" pad="3"/> +<connect gate="G$1" pin="PIO1.2/CT32B1M2" pad="34"/> +<connect gate="G$1" pin="PIO1.20/DSR/SCK1" pad="18"/> +<connect gate="G$1" pin="PIO1.21/DCD/MISO1" pad="35"/> +<connect gate="G$1" pin="PIO1.22/RI/MOSI1" pad="51"/> +<connect gate="G$1" pin="PIO1.23/CT16B1M1/SSEL1" pad="24"/> +<connect gate="G$1" pin="PIO1.24/CT32B0M0" pad="27"/> +<connect gate="G$1" pin="PIO1.25/CT32B0M1" pad="2"/> +<connect gate="G$1" pin="PIO1.26/CT32B0M2/RXD" pad="14"/> +<connect gate="G$1" pin="PIO1.27/CT32B0M3/TXD" pad="15"/> +<connect gate="G$1" pin="PIO1.28/CT32B0C0/SCLK" pad="31"/> +<connect gate="G$1" pin="PIO1.29/SCK0/CT32B0C1" pad="41"/> +<connect gate="G$1" pin="PIO1.3/CT32B1M3" pad="50"/> +<connect gate="G$1" pin="PIO1.4/CT32B1C0" pad="16"/> +<connect gate="G$1" pin="PIO1.5/CT32B1C1" pad="32"/> +<connect gate="G$1" pin="PIO1.6" pad="64"/> +<connect gate="G$1" pin="PIO1.7" pad="6"/> +<connect gate="G$1" pin="PIO1.8" pad="39"/> +<connect gate="G$1" pin="PIO1.9" pad="55"/> +<connect gate="G$1" pin="SWCLK/PIO0.10/SCK0/CT16B0M2" pad="38"/> +<connect gate="G$1" pin="SWDIO/PIO0.15/AD4/CT32B1M2" pad="52"/> +<connect gate="G$1" pin="TDI/PIO0.11/AD0/CT32B0M3" pad="42"/> +<connect gate="G$1" pin="TDO/PIO0.13/AD2/CB32B1M0" pad="45"/> +<connect gate="G$1" pin="TMS/PIO0.12/AD1/CT32B1M0" pad="44"/> +<connect gate="G$1" pin="USB_D+" pad="26"/> +<connect gate="G$1" pin="USB_D-" pad="25"/> +<connect gate="G$1" pin="VDD@10" pad="10"/> +<connect gate="G$1" pin="VDD@33" pad="33"/> +<connect gate="G$1" pin="VDD@48" pad="48"/> +<connect gate="G$1" pin="VDD@58" pad="58"/> +<connect gate="G$1" pin="VSS@54" pad="54"/> +<connect gate="G$1" pin="VSS@7" pad="7"/> +<connect gate="G$1" pin="XTALIN" pad="8"/> +<connect gate="G$1" pin="XTALOUT" pad="9"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="LPC1768" prefix="IC"> +<gates> +<gate name="G$1" symbol="LPC1768" x="-2.54" y="0"/> +</gates> +<devices> +<device name="" package="LQFP100"> +<connects> +<connect gate="G$1" pin="NC" pad="13"/> +<connect gate="G$1" pin="NRESET" pad="17"/> +<connect gate="G$1" pin="P0.0/CAN_RX1/TXD3/SDA1" pad="46"/> +<connect gate="G$1" pin="P0.1/CAN_TX1/RXD3/SCL1" pad="47"/> +<connect gate="G$1" pin="P0.10/TXD2/SDA2/MAT3.0" pad="48"/> +<connect gate="G$1" pin="P0.11/RXD2/SCL2/MAT3.1" pad="49"/> +<connect gate="G$1" pin="P0.15/TXD1/SCK0/SCK" pad="62"/> +<connect gate="G$1" pin="P0.16/RXD1/SSEL0/SSEL" pad="63"/> +<connect gate="G$1" pin="P0.17/CTS1/MISO0/MISO" pad="61"/> +<connect gate="G$1" pin="P0.18/DCD1/MOSI0/MOSI1" pad="60"/> +<connect gate="G$1" pin="P0.19/DSR1/MCICLK/SDA1" pad="59"/> +<connect gate="G$1" pin="P0.2/TXD0/AD0.7" pad="98"/> +<connect gate="G$1" pin="P0.20/DTR1/SCL1" pad="58"/> +<connect gate="G$1" pin="P0.21/RI1/CAN_RX1" pad="57"/> +<connect gate="G$1" pin="P0.22/RTS1/CAN_TX1" pad="56"/> +<connect gate="G$1" pin="P0.23/AD0.0/I2SRX_CLK/CAP3.0" pad="9"/> +<connect gate="G$1" pin="P0.24/AD0.1/I2SRX_WS/CAP3.1" pad="8"/> +<connect gate="G$1" pin="P0.25/AD0.2/I2SRX_SDA/TXD3" pad="7"/> +<connect gate="G$1" pin="P0.26/AD0.3/AOUT/RXD3" pad="6"/> +<connect gate="G$1" pin="P0.27/SDA0/USB_SDA" pad="25"/> +<connect gate="G$1" pin="P0.28/SCL0/USB_SCL" pad="24"/> +<connect gate="G$1" pin="P0.29/USB_D+" pad="29"/> +<connect gate="G$1" pin="P0.3/RXD0/AD0.6" pad="99"/> +<connect gate="G$1" pin="P0.30/USB_D-" pad="30"/> +<connect gate="G$1" pin="P0.4/I2SRX_CLK/CAN_RX2/CAP2.0" pad="81"/> +<connect gate="G$1" pin="P0.5/I2SRX_WS/CAN_TX2/CAP2.1" pad="80"/> +<connect gate="G$1" pin="P0.6/I2SRX_SDA/SSEL1/MAT2.0" pad="79"/> +<connect gate="G$1" pin="P0.7/I2STX_CLK/SCK1/MAT2.1" pad="78"/> +<connect gate="G$1" pin="P0.8/I2STX_WS/MISO1/MAT2.2" pad="77"/> +<connect gate="G$1" pin="P0.9/I2STX_SDA/MOSI1/MAT2.3" pad="76"/> +<connect gate="G$1" pin="P1.0/ENET-TXD0" pad="95"/> +<connect gate="G$1" pin="P1.1/ENET-TXD1" pad="94"/> +<connect gate="G$1" pin="P1.10/ENET_RXD1" pad="90"/> +<connect gate="G$1" pin="P1.14/ENET-RX_ER" pad="89"/> +<connect gate="G$1" pin="P1.15/ENET-RX_CLK" pad="88"/> +<connect gate="G$1" pin="P1.16/ENET-MDC" pad="87"/> +<connect gate="G$1" pin="P1.17/ENET-MDIO" pad="86"/> +<connect gate="G$1" pin="P1.18/USB_UP/PWM1.1/CAP1.0" pad="32"/> +<connect gate="G$1" pin="P1.19/MC0A/USB_PPWR/CAP1.1" pad="33"/> +<connect gate="G$1" pin="P1.20/MCFB0/PWM1.2/SCK0" pad="34"/> +<connect gate="G$1" pin="P1.21/MCABORT/PWM1.3/SSEL0" pad="35"/> +<connect gate="G$1" pin="P1.22/MC0B/USB_PWRD/MAT1.0" pad="36"/> +<connect gate="G$1" pin="P1.23/MCFB1/PWM1.4/MISO0" pad="37"/> +<connect gate="G$1" pin="P1.24/MCFB2/PWM1.5/MOSI0" pad="38"/> +<connect gate="G$1" pin="P1.25/MC1A/MAT1.1" pad="39"/> +<connect gate="G$1" pin="P1.26/MC1B/PWM1.6/CAP0.0" pad="40"/> +<connect gate="G$1" pin="P1.27/CLKOUT/USB_OVRCR/CAP0.1" pad="43"/> +<connect gate="G$1" pin="P1.28/MC2A/PCAP1.0/MAT0.0" pad="44"/> +<connect gate="G$1" pin="P1.29/MC2B/PCAP1.1/MAT0.1" pad="45"/> +<connect gate="G$1" pin="P1.30/VBUS/AD0.4" pad="21"/> +<connect gate="G$1" pin="P1.31/SCK1/AD0.5" pad="20"/> +<connect gate="G$1" pin="P1.4/ENET-TX_EN" pad="93"/> +<connect gate="G$1" pin="P1.8/ENET_CRS" pad="92"/> +<connect gate="G$1" pin="P1.9/ENET_RXD0" pad="91"/> +<connect gate="G$1" pin="P2.0/PWM1.1/TXD1/TRACECLK" pad="75"/> +<connect gate="G$1" pin="P2.1/PWM1.2/RXD1" pad="74"/> +<connect gate="G$1" pin="P2.10/EINT0N/NMI" pad="53"/> +<connect gate="G$1" pin="P2.11/EINT1N/I2STX_CLK" pad="52"/> +<connect gate="G$1" pin="P2.12/EINT2N/I2STX_WS" pad="51"/> +<connect gate="G$1" pin="P2.13/EINT3N/I2STX_SDA" pad="50"/> +<connect gate="G$1" pin="P2.2/PWM1.3/CTS1/TRACEDATA3" pad="73"/> +<connect gate="G$1" pin="P2.3/PWM1.4/DCD1/TRACEDATA2" pad="70"/> +<connect gate="G$1" pin="P2.4/PWM1.5/DSR1/TRACEDATA1" pad="69"/> +<connect gate="G$1" pin="P2.5/PWM1.6/DTR1/TRACEDATA0" pad="68"/> +<connect gate="G$1" pin="P2.6/PCAP1.0/RI1/TRACECLK" pad="67"/> +<connect gate="G$1" pin="P2.7/CAN_RX2/RTS1" pad="66"/> +<connect gate="G$1" pin="P2.8/CAN_TX2/TXD2" pad="65"/> +<connect gate="G$1" pin="P2.9/USB_CONNECT/RXD2" pad="64"/> +<connect gate="G$1" pin="P3.25/MAT0.0/PWM1.2" pad="27"/> +<connect gate="G$1" pin="P3.26/STCLK/MAT0.1/PWM1.3" pad="26"/> +<connect gate="G$1" pin="P4.28/RX_MCLK/MAT2.0/TXD3" pad="82"/> +<connect gate="G$1" pin="P4.29/TX_MCLK/MAT2.1/RXD3" pad="85"/> +<connect gate="G$1" pin="RSTOUTN" pad="14"/> +<connect gate="G$1" pin="RTCK" pad="100"/> +<connect gate="G$1" pin="RTCX1" pad="16"/> +<connect gate="G$1" pin="RTCX2" pad="18"/> +<connect gate="G$1" pin="TCK/SWDCLK" pad="5"/> +<connect gate="G$1" pin="TDI" pad="2"/> +<connect gate="G$1" pin="TDO/SWO" pad="1"/> +<connect gate="G$1" pin="TMS/SWDIO" pad="3"/> +<connect gate="G$1" pin="TRST_N" pad="4"/> +<connect gate="G$1" pin="VBAT" pad="19"/> +<connect gate="G$1" pin="VDD3.3V@1" pad="96"/> +<connect gate="G$1" pin="VDD3.3V@2" pad="71"/> +<connect gate="G$1" pin="VDD3.3V@3" pad="54"/> +<connect gate="G$1" pin="VDD3.3V@4" pad="28"/> +<connect gate="G$1" pin="VDDA" pad="10"/> +<connect gate="G$1" pin="VDDREG3.3V@1" pad="42"/> +<connect gate="G$1" pin="VDDREG3.3V@2" pad="84"/> +<connect gate="G$1" pin="VREFN" pad="15"/> +<connect gate="G$1" pin="VREFP" pad="12"/> +<connect gate="G$1" pin="VSS@1" pad="83"/> +<connect gate="G$1" pin="VSS@2" pad="41"/> +<connect gate="G$1" pin="VSS@3" pad="97"/> +<connect gate="G$1" pin="VSS@4" pad="72"/> +<connect gate="G$1" pin="VSS@5" pad="55"/> +<connect gate="G$1" pin="VSS@6" pad="31"/> +<connect gate="G$1" pin="VSSA" pad="11"/> +<connect gate="G$1" pin="X1" pad="22"/> +<connect gate="G$1" pin="X2" pad="23"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="C" prefix="C" uservalue="yes"> +<description><b>Capacitor</b><p></description> +<gates> +<gate name="G$1" symbol="C" x="0" y="0"/> +</gates> +<devices> +<device name="0402" package="0402"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0603" package="0603"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0805" package="0805"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="1206" package="C1206"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="1210" package="C1210"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="1812" package="C1812"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="R" prefix="R" uservalue="yes"> +<gates> +<gate name="G$1" symbol="R" x="0" y="0"/> +</gates> +<devices> +<device name="0402" package="0402"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0603" package="0603"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0805" package="0805"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="1206" package="C1206"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="1210" package="C1210"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="1812" package="C1812"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="Q" prefix="Q" uservalue="yes"> +<gates> +<gate name="G$1" symbol="Q" x="0" y="0"/> +</gates> +<devices> +<device name="_FC135" package="FC135"> +<connects> +<connect gate="G$1" pin="1" pad="X1"/> +<connect gate="G$1" pin="2" pad="X2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_HC49UP" package="HC49UP"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_TC38" package="TC38"> +<connects> +<connect gate="G$1" pin="1" pad="+"/> +<connect gate="G$1" pin="2" pad="-"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_3.2X2.5" package="3.2X.2.5"> +<connects> +<connect gate="G$1" pin="1" pad="P$1"/> +<connect gate="G$1" pin="2" pad="P$3"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="OSCILLATOR" prefix="OSC" uservalue="yes"> +<gates> +<gate name="G$1" symbol="OSCILLATOR" x="0" y="0"/> +</gates> +<devices> +<device name="" package="3.2X.2.5"> +<connects> +<connect gate="G$1" pin="CLK" pad="P$3"/> +<connect gate="G$1" pin="EN" pad="P$1"/> +<connect gate="G$1" pin="GND" pad="P$2"/> +<connect gate="G$1" pin="VCC" pad="P$4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="SPST" prefix="SW"> +<gates> +<gate name="G$1" symbol="TS" x="0" y="0"/> +</gates> +<devices> +<device name="" package="DTSM-32S-B"> +<connects> +<connect gate="G$1" pin="P" pad="P$1"/> +<connect gate="G$1" pin="S" pad="P$2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_SKRKAWW010" package="SKRKAEE010"> +<connects> +<connect gate="G$1" pin="P" pad="P$1"/> +<connect gate="G$1" pin="S" pad="P$2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="LED" prefix="LED"> +<description><b>SMD LED</b><p></description> +<gates> +<gate name="G$1" symbol="LED" x="0" y="0"/> +</gates> +<devices> +<device name="0603" package="CHIPLED_0603"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0805" package="CHIPLED_0805"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="1206" package="CHIPLED_1206"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="IF-MK20DX128" prefix="IC"> +<description><b>CMSIS-DAP Interface (MK20DX128)</b></description> +<gates> +<gate name="G$1" symbol="MK20DX128VFM5" x="0" y="2.54"/> +</gates> +<devices> +<device name="" package="HVQFN33"> +<connects> +<connect gate="G$1" pin="EPAD" pad="EXP"/> +<connect gate="G$1" pin="IF_NRESET" pad="19"/> +<connect gate="G$1" pin="LED_HID" pad="30"/> +<connect gate="G$1" pin="LED_MSD" pad="29"/> +<connect gate="G$1" pin="LED_UART" pad="31"/> +<connect gate="G$1" pin="NC1" pad="9"/> +<connect gate="G$1" pin="NC2" pad="10"/> +<connect gate="G$1" pin="NC3" pad="11"/> +<connect gate="G$1" pin="NC4" pad="12"/> +<connect gate="G$1" pin="NC5" pad="13"/> +<connect gate="G$1" pin="NC6" pad="14"/> +<connect gate="G$1" pin="NC7" pad="15"/> +<connect gate="G$1" pin="NRESET_FB_BL" pad="16"/> +<connect gate="G$1" pin="NRESET_FB_ISP" pad="21"/> +<connect gate="G$1" pin="SLEEP_NREQ" pad="20"/> +<connect gate="G$1" pin="TGT_NRESET" pad="22"/> +<connect gate="G$1" pin="TGT_RX" pad="25"/> +<connect gate="G$1" pin="TGT_SWCLK" pad="26"/> +<connect gate="G$1" pin="TGT_SWDIO" pad="27"/> +<connect gate="G$1" pin="TGT_SWO" pad="28"/> +<connect gate="G$1" pin="TGT_TX" pad="24"/> +<connect gate="G$1" pin="USB_D+" pad="3"/> +<connect gate="G$1" pin="USB_D-" pad="4"/> +<connect gate="G$1" pin="USB_VBUS" pad="32"/> +<connect gate="G$1" pin="VDD" pad="1"/> +<connect gate="G$1" pin="VDDA" pad="7"/> +<connect gate="G$1" pin="VOUT33" pad="5"/> +<connect gate="G$1" pin="VREGIN" pad="6"/> +<connect gate="G$1" pin="VSS" pad="2"/> +<connect gate="G$1" pin="VSSA" pad="8"/> +<connect gate="G$1" pin="WAKE_NREQ" pad="23"/> +<connect gate="G$1" pin="XTALIN" pad="17"/> +<connect gate="G$1" pin="XTALOUT" pad="18"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="MKL25Z128VLK4" prefix="IC"> +<gates> +<gate name="G$1" symbol="MKL25Z128VLK4" x="0" y="0"/> +</gates> +<devices> +<device name="" package="LQFP80"> +<connects> +<connect gate="G$1" pin="NRESET" pad="42"/> +<connect gate="G$1" pin="PTA1" pad="27"/> +<connect gate="G$1" pin="PTA12" pad="32"/> +<connect gate="G$1" pin="PTA13" pad="33"/> +<connect gate="G$1" pin="PTA14" pad="34"/> +<connect gate="G$1" pin="PTA15" pad="35"/> +<connect gate="G$1" pin="PTA16" pad="36"/> +<connect gate="G$1" pin="PTA17" pad="37"/> +<connect gate="G$1" pin="PTA2" pad="28"/> +<connect gate="G$1" pin="PTA4" pad="30"/> +<connect gate="G$1" pin="PTA5" pad="31"/> +<connect gate="G$1" pin="PTB0" pad="43"/> +<connect gate="G$1" pin="PTB1" pad="44"/> +<connect gate="G$1" pin="PTB10" pad="49"/> +<connect gate="G$1" pin="PTB11" pad="50"/> +<connect gate="G$1" pin="PTB16" pad="51"/> +<connect gate="G$1" pin="PTB17" pad="52"/> +<connect gate="G$1" pin="PTB18" pad="53"/> +<connect gate="G$1" pin="PTB19" pad="54"/> +<connect gate="G$1" pin="PTB2" pad="45"/> +<connect gate="G$1" pin="PTB3" pad="46"/> +<connect gate="G$1" pin="PTB8" pad="47"/> +<connect gate="G$1" pin="PTB9" pad="48"/> +<connect gate="G$1" pin="PTC0" pad="55"/> +<connect gate="G$1" pin="PTC1" pad="56"/> +<connect gate="G$1" pin="PTC10" pad="67"/> +<connect gate="G$1" pin="PTC11" pad="68"/> +<connect gate="G$1" pin="PTC12" pad="69"/> +<connect gate="G$1" pin="PTC13" pad="70"/> +<connect gate="G$1" pin="PTC16" pad="71"/> +<connect gate="G$1" pin="PTC17" pad="72"/> +<connect gate="G$1" pin="PTC2" pad="57"/> +<connect gate="G$1" pin="PTC3" pad="58"/> +<connect gate="G$1" pin="PTC4" pad="61"/> +<connect gate="G$1" pin="PTC5" pad="62"/> +<connect gate="G$1" pin="PTC6" pad="63"/> +<connect gate="G$1" pin="PTC7" pad="64"/> +<connect gate="G$1" pin="PTC8" pad="65"/> +<connect gate="G$1" pin="PTC9" pad="66"/> +<connect gate="G$1" pin="PTD0" pad="73"/> +<connect gate="G$1" pin="PTD1" pad="74"/> +<connect gate="G$1" pin="PTD2" pad="75"/> +<connect gate="G$1" pin="PTD3" pad="76"/> +<connect gate="G$1" pin="PTD4" pad="77"/> +<connect gate="G$1" pin="PTD5" pad="78"/> +<connect gate="G$1" pin="PTD6" pad="79"/> +<connect gate="G$1" pin="PTD7" pad="80"/> +<connect gate="G$1" pin="PTE0" pad="1"/> +<connect gate="G$1" pin="PTE1" pad="2"/> +<connect gate="G$1" pin="PTE2" pad="3"/> +<connect gate="G$1" pin="PTE20" pad="13"/> +<connect gate="G$1" pin="PTE21" pad="14"/> +<connect gate="G$1" pin="PTE22" pad="15"/> +<connect gate="G$1" pin="PTE23" pad="16"/> +<connect gate="G$1" pin="PTE24" pad="24"/> +<connect gate="G$1" pin="PTE25" pad="25"/> +<connect gate="G$1" pin="PTE29" pad="21"/> +<connect gate="G$1" pin="PTE3" pad="4"/> +<connect gate="G$1" pin="PTE30" pad="22"/> +<connect gate="G$1" pin="PTE31" pad="23"/> +<connect gate="G$1" pin="PTE4" pad="5"/> +<connect gate="G$1" pin="PTE5" pad="6"/> +<connect gate="G$1" pin="SWCLK" pad="26"/> +<connect gate="G$1" pin="SWDIO" pad="29"/> +<connect gate="G$1" pin="USB_D+" pad="9"/> +<connect gate="G$1" pin="USB_D-" pad="10"/> +<connect gate="G$1" pin="VDD1" pad="7"/> +<connect gate="G$1" pin="VDD2" pad="60"/> +<connect gate="G$1" pin="VDD3" pad="38"/> +<connect gate="G$1" pin="VDDA" pad="17"/> +<connect gate="G$1" pin="VOUT33" pad="11"/> +<connect gate="G$1" pin="VREFH" pad="18"/> +<connect gate="G$1" pin="VREFL" pad="19"/> +<connect gate="G$1" pin="VREGIN" pad="12"/> +<connect gate="G$1" pin="VSS1" pad="8"/> +<connect gate="G$1" pin="VSS2" pad="59"/> +<connect gate="G$1" pin="VSS3" pad="39"/> +<connect gate="G$1" pin="VSSA" pad="20"/> +<connect gate="G$1" pin="XTALIN" pad="40"/> +<connect gate="G$1" pin="XTALOUT" pad="41"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="USB" prefix="CON"> +<description><b>USB Connectors</b><p></description> +<gates> +<gate name="A" symbol="USB-1" x="0" y="0"/> +</gates> +<devices> +<device name="-A-H" package="USB-A-H"> +<connects> +<connect gate="A" pin="D+" pad="D+"/> +<connect gate="A" pin="D-" pad="D-"/> +<connect gate="A" pin="GND" pad="GND"/> +<connect gate="A" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-A-S" package="USB-A-S"> +<connects> +<connect gate="A" pin="D+" pad="D+"/> +<connect gate="A" pin="D-" pad="D-"/> +<connect gate="A" pin="GND" pad="GND"/> +<connect gate="A" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-B-H" package="USB-B-H"> +<connects> +<connect gate="A" pin="D+" pad="D+"/> +<connect gate="A" pin="D-" pad="D-"/> +<connect gate="A" pin="GND" pad="GND"/> +<connect gate="A" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-MB-S" package="USB-MB-S"> +<connects> +<connect gate="A" pin="D+" pad="D+"/> +<connect gate="A" pin="D-" pad="D-"/> +<connect gate="A" pin="GND" pad="GND"/> +<connect gate="A" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-A-V" package="USB-A-V"> +<connects> +<connect gate="A" pin="D+" pad="D+"/> +<connect gate="A" pin="D-" pad="D-"/> +<connect gate="A" pin="GND" pad="GND"/> +<connect gate="A" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_MICROB" package="MOLEX-47364-0001"> +<connects> +<connect gate="A" pin="D+" pad="D+"/> +<connect gate="A" pin="D-" pad="D-"/> +<connect gate="A" pin="GND" pad="GND"/> +<connect gate="A" pin="VBUS" pad="VBUS"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="C-POL" prefix="C" uservalue="yes"> +<description><b>Polarised capacitor</b><p></description> +<gates> +<gate name="G$1" symbol="C-POL" x="0" y="0"/> +</gates> +<devices> +<device name="B" package="CASE-B"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="+3.3V_IF"> +<gates> +<gate name="G$1" symbol="+3.3V_IF" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="+3.3V_TGT"> +<gates> +<gate name="G$1" symbol="+3.3V_TGT" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="GND" prefix="GND"> +<description>SUPPLY SYMBOL</description> +<gates> +<gate name="1" symbol="GND" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="+VIN" prefix="U+"> +<gates> +<gate name="G$1" symbol="+VIN" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="DP83848J" prefix="IC"> +<description><B>National Semiconductor DP83848J PHYTER Mini LS Single Port 10/100 Ethernet Transceiver</B></description> +<gates> +<gate name="A" symbol="DP83848J" x="0" y="0"/> +</gates> +<devices> +<device name="" package="LLP-40"> +<connects> +<connect gate="A" pin="AGND@1" pad="13"/> +<connect gate="A" pin="AGND@2" pad="17"/> +<connect gate="A" pin="AVDD33" pad="18"/> +<connect gate="A" pin="COL/PHYAD0" pad="35"/> +<connect gate="A" pin="CRS/CRS_DV/LED_CFG" pad="33"/> +<connect gate="A" pin="DGND" pad="29"/> +<connect gate="A" pin="GNDPAD" pad="DAP"/> +<connect gate="A" pin="IOGND@2" pad="40"/> +<connect gate="A" pin="IOVDD33@1" pad="1"/> +<connect gate="A" pin="IOVDD33@2" pad="26"/> +<connect gate="A" pin="LED_LINK/AN0" pad="22"/> +<connect gate="A" pin="LED_SPEED/AN1" pad="21"/> +<connect gate="A" pin="MDC" pad="25"/> +<connect gate="A" pin="MDIO" pad="24"/> +<connect gate="A" pin="PFBIN1" pad="16"/> +<connect gate="A" pin="PFBIN2" pad="30"/> +<connect gate="A" pin="PFBOUT" pad="19"/> +<connect gate="A" pin="RBIAS" pad="20"/> +<connect gate="A" pin="RD+" pad="12"/> +<connect gate="A" pin="RD-" pad="11"/> +<connect gate="A" pin="RESERVED@1" pad="8"/> +<connect gate="A" pin="RESERVED@2" pad="9"/> +<connect gate="A" pin="RESERVED@3" pad="10"/> +<connect gate="A" pin="RESET_N" pad="23"/> +<connect gate="A" pin="RXD_0/PHYAD1" pad="36"/> +<connect gate="A" pin="RXD_1/PHYAD2" pad="37"/> +<connect gate="A" pin="RXD_2/PHYAD3" pad="38"/> +<connect gate="A" pin="RXD_3/PHYAD4" pad="39"/> +<connect gate="A" pin="RX_CLK" pad="31"/> +<connect gate="A" pin="RX_DV/MII_MODE" pad="32"/> +<connect gate="A" pin="RX_ER/MDIX_EN" pad="34"/> +<connect gate="A" pin="TD+" pad="15"/> +<connect gate="A" pin="TD-" pad="14"/> +<connect gate="A" pin="TXD_0" pad="4"/> +<connect gate="A" pin="TXD_1" pad="5"/> +<connect gate="A" pin="TXD_2" pad="6"/> +<connect gate="A" pin="TXD_3" pad="7"/> +<connect gate="A" pin="TX_CLK" pad="2"/> +<connect gate="A" pin="TX_EN" pad="3"/> +<connect gate="A" pin="X1" pad="28"/> +<connect gate="A" pin="X2" pad="27"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="RJ45" prefix="CON"> +<description>Magjack SI-68002</description> +<gates> +<gate name="G$1" symbol="RJ45" x="-7.62" y="25.4"/> +</gates> +<devices> +<device name="" package="RJ45"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +<connect gate="G$1" pin="4" pad="4"/> +<connect gate="G$1" pin="5" pad="5"/> +<connect gate="G$1" pin="6" pad="6"/> +<connect gate="G$1" pin="7" pad="7"/> +<connect gate="G$1" pin="8" pad="8"/> +<connect gate="G$1" pin="SHIELD1" pad="P$1"/> +<connect gate="G$1" pin="SHIELD2" pad="P$2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="L" prefix="L" uservalue="yes"> +<description><b>Inductor</b></description> +<gates> +<gate name="G$1" symbol="L" x="0" y="0"/> +</gates> +<devices> +<device name="" package="0603"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="LPC812M101" prefix="IC"> +<description><H2>32-bit ARM Cortex-M0+ microcontroller</H2> +The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at +CPU frequencies of up to 30 MHz. The LPC81xM support up to 16 kB of flash memory +and 4 kB of SRAM. +The peripheral complement of the LPC81xM includes a CRC engine, one I +2 +C-bus +interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up +timer, and state-configurable timer, one comparator, function-configurable I/O ports +through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O +pins. +<p><author>AAL Eindhoven MK</author><hr><p> + <img src="http://www.nxp.com/img/NXP_logo.png"></description> +<gates> +<gate name="G$1" symbol="LPC812M101FD20-1" x="0" y="0"/> +</gates> +<devices> +<device name="FD20" package="SOT163-1"> +<connects> +<connect gate="G$1" pin="!RESET!/PIO0_5" pad="4"/> +<connect gate="G$1" pin="PIO0_0/ACMP_I1/TDO" pad="19"/> +<connect gate="G$1" pin="PIO0_1/ACMP_I2/CLKIN/TDI" pad="12"/> +<connect gate="G$1" pin="PIO0_10" pad="9"/> +<connect gate="G$1" pin="PIO0_11" pad="8"/> +<connect gate="G$1" pin="PIO0_12" pad="3"/> +<connect gate="G$1" pin="PIO0_13" pad="2"/> +<connect gate="G$1" pin="PIO0_14" pad="20"/> +<connect gate="G$1" pin="PIO0_15" pad="11"/> +<connect gate="G$1" pin="PIO0_16" pad="10"/> +<connect gate="G$1" pin="PIO0_17" pad="1"/> +<connect gate="G$1" pin="PIO0_4/WAKEUP/!TRST!" pad="5"/> +<connect gate="G$1" pin="PIO0_6/VDDCMP" pad="18"/> +<connect gate="G$1" pin="PIO0_7" pad="17"/> +<connect gate="G$1" pin="PIO0_8/XTALIN" pad="14"/> +<connect gate="G$1" pin="PIO0_9/XTALOUT" pad="13"/> +<connect gate="G$1" pin="SWCLK/PIO0_3/TCK" pad="6"/> +<connect gate="G$1" pin="SWDIO/PIO0_2/TMS" pad="7"/> +<connect gate="G$1" pin="VDD" pad="15"/> +<connect gate="G$1" pin="VSS" pad="16"/> +</connects> +<technologies> +<technology name=""> +<attribute name="COMP" value="1"/> +<attribute name="FLASH" value="16k"/> +<attribute name="GPIO" value="18"/> +<attribute name="I2C" value="1"/> +<attribute name="SPI" value="1"/> +<attribute name="SRAM" value="4k"/> +<attribute name="USART" value="2"/> +</technology> +</technologies> +</device> +<device name="FDH20" package="SOT360"> +<connects> +<connect gate="G$1" pin="!RESET!/PIO0_5" pad="4"/> +<connect gate="G$1" pin="PIO0_0/ACMP_I1/TDO" pad="19"/> +<connect gate="G$1" pin="PIO0_1/ACMP_I2/CLKIN/TDI" pad="12"/> +<connect gate="G$1" pin="PIO0_10" pad="9"/> +<connect gate="G$1" pin="PIO0_11" pad="8"/> +<connect gate="G$1" pin="PIO0_12" pad="3"/> +<connect gate="G$1" pin="PIO0_13" pad="2"/> +<connect gate="G$1" pin="PIO0_14" pad="20"/> +<connect gate="G$1" pin="PIO0_15" pad="11"/> +<connect gate="G$1" pin="PIO0_16" pad="10"/> +<connect gate="G$1" pin="PIO0_17" pad="1"/> +<connect gate="G$1" pin="PIO0_4/WAKEUP/!TRST!" pad="5"/> +<connect gate="G$1" pin="PIO0_6/VDDCMP" pad="18"/> +<connect gate="G$1" pin="PIO0_7" pad="17"/> +<connect gate="G$1" pin="PIO0_8/XTALIN" pad="14"/> +<connect gate="G$1" pin="PIO0_9/XTALOUT" pad="13"/> +<connect gate="G$1" pin="SWCLK/PIO0_3/TCK" pad="6"/> +<connect gate="G$1" pin="SWDIO/PIO0_2/TMS" pad="7"/> +<connect gate="G$1" pin="VDD" pad="15"/> +<connect gate="G$1" pin="VSS" pad="16"/> +</connects> +<technologies> +<technology name=""> +<attribute name="COMP" value="1"/> +<attribute name="FLASH" value="16k"/> +<attribute name="GPIO" value="18"/> +<attribute name="I2C" value="1"/> +<attribute name="SPI" value="2"/> +<attribute name="SRAM" value="4k"/> +<attribute name="USART" value="3"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="LPC1347FBD64" prefix="IC"> +<description><H2>32-bit ARM Cortex-M3 microcontroller; up to 64 kB flash; +up to 12 kB SRAM; USB device; USART; EEPROM</H2> +The LPC1315/16/17/45/46/47 are ARM Cortex-M3 based microcontrollers for embedded +applications featuring a high level of integration and low power consumption. The ARM +Cortex-M3 is a next generation core that offers system enhancements such as enhanced +debug features and a higher level of support block integration. +The LPC1315/16/17/45/46/47 operate at CPU frequencies of up to 72 MHz. The ARM +Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with +separate local instruction and data buses as well as a third bus for peripherals. The ARM +Cortex-M3 CPU also includes an internal prefetch unit that supports speculative +branching. +Equipped with a highly flexible and configurable Full-Speed USB 2.0 device controller +available on the LPC1345/46/47, this series brings unparalleled design flexibility and +seamless integration to today’s demanding connectivity solutions. +The peripheral complement of the LPC1315/16/17/45/46/47 includes up to 64 kB of flash +memory, 8 kB or 10 kB of SRAM data memory, one Fast-mode Plus I +2 +C-bus interface, one +RS-485/EIA-485 USART with support for synchronous mode and smart card interface, +two SSP interfaces, four general purpose counter/timers, an 8-channel, 12-bit ADC, and +up to 51 general purpose I/O pins. +<p><author>AAL Eindhoven MK</author><hr><p> + <img src="http://www.nxp.com/img/NXP_logo.png"></description> +<gates> +<gate name="G$1" symbol="LPC1347FBD64" x="0" y="0"/> +</gates> +<devices> +<device name="" package="SOT314-2"> +<connects> +<connect gate="G$1" pin="!RESET!/PIO0_0" pad="4"/> +<connect gate="G$1" pin="!TRST!/PIO0_14/AD3/CT32B1_MAT1" pad="46"/> +<connect gate="G$1" pin="PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE" pad="5"/> +<connect gate="G$1" pin="PIO0_16/AD5/CT32B1_MAT3/WAKEUP" pad="53"/> +<connect gate="G$1" pin="PIO0_17/!RTS!/CT32B0_CAP0/SCLK" pad="60"/> +<connect gate="G$1" pin="PIO0_18/RXD/CT32B0_MAT0" pad="61"/> +<connect gate="G$1" pin="PIO0_19/TXD/CT32B0_MAT1" pad="62"/> +<connect gate="G$1" pin="PIO0_2/SSEL0/CT16B0_CAP0" pad="13"/> +<connect gate="G$1" pin="PIO0_20/CT16B1_CAP0" pad="11"/> +<connect gate="G$1" pin="PIO0_21/CT16B1_MAT0/MOSI1" pad="22"/> +<connect gate="G$1" pin="PIO0_22/AD6/CT16B1_MAT1/MISO1" pad="40"/> +<connect gate="G$1" pin="PIO0_23/AD7" pad="56"/> +<connect gate="G$1" pin="PIO0_3/USB_VBUS" pad="19"/> +<connect gate="G$1" pin="PIO0_4/SCL" pad="20"/> +<connect gate="G$1" pin="PIO0_5/SDA" pad="21"/> +<connect gate="G$1" pin="PIO0_6/!USB_CONNECT!/SCK0" pad="29"/> +<connect gate="G$1" pin="PIO0_7/!CTS!" pad="30"/> +<connect gate="G$1" pin="PIO0_8/MISO0/CT16B0_MAT0" pad="36"/> +<connect gate="G$1" pin="PIO0_9/MOSI0/CT16B0_MAT1/SWO" pad="37"/> +<connect gate="G$1" pin="PIO1_0/CT32B1_MAT0" pad="1"/> +<connect gate="G$1" pin="PIO1_1/CT32B1_MAT1" pad="17"/> +<connect gate="G$1" pin="PIO1_10" pad="12"/> +<connect gate="G$1" pin="PIO1_11" pad="43"/> +<connect gate="G$1" pin="PIO1_13/!DTR!/CT16B0_MAT0/TXD" pad="47"/> +<connect gate="G$1" pin="PIO1_14/!DSR!/CT16B0_MAT1/RXD" pad="49"/> +<connect gate="G$1" pin="PIO1_15/!DCD!/CT16B0_MAT2/SCK1" pad="57"/> +<connect gate="G$1" pin="PIO1_16/!RI!/CT16B0_CAP0" pad="63"/> +<connect gate="G$1" pin="PIO1_17/CT16B0_CAP1/RXD" pad="23"/> +<connect gate="G$1" pin="PIO1_18/CT16B1_CAP1/TXD" pad="28"/> +<connect gate="G$1" pin="PIO1_19/!DTR!/SSEL1" pad="3"/> +<connect gate="G$1" pin="PIO1_2/CT32B1_MAT2" pad="34"/> +<connect gate="G$1" pin="PIO1_20/!DSR!/SCK1" pad="18"/> +<connect gate="G$1" pin="PIO1_21/!DCD!/MISO1" pad="35"/> +<connect gate="G$1" pin="PIO1_22/!RI!/MOSI1" pad="51"/> +<connect gate="G$1" pin="PIO1_23/CT16B1_MAT1/SSEL1" pad="24"/> +<connect gate="G$1" pin="PIO1_24/CT32B0_MAT0" pad="27"/> +<connect gate="G$1" pin="PIO1_25/CT32B0_MAT1" pad="2"/> +<connect gate="G$1" pin="PIO1_26/CT32B0_MAT2/RXD" pad="14"/> +<connect gate="G$1" pin="PIO1_27/CT32B0_MAT3/TXD" pad="15"/> +<connect gate="G$1" pin="PIO1_28/CT32B0_CAP0/SCLK" pad="31"/> +<connect gate="G$1" pin="PIO1_29/SCK0/CT32B0_CAP1" pad="41"/> +<connect gate="G$1" pin="PIO1_3/CT32B1_MAT3" pad="50"/> +<connect gate="G$1" pin="PIO1_4/CT32B1_CAP0" pad="16"/> +<connect gate="G$1" pin="PIO1_5/CT32B1_CAP1" pad="32"/> +<connect gate="G$1" pin="PIO1_7" pad="6"/> +<connect gate="G$1" pin="PIO1_8" pad="39"/> +<connect gate="G$1" pin="SWCLK/PIO0_10/SCK0/CT16B0_MAT2" pad="38"/> +<connect gate="G$1" pin="SWDIO/PIO0_15/AD4/CT32B1_MAT2" pad="52"/> +<connect gate="G$1" pin="TDI/PIO0_11/AD0/CT32B0_MAT3" pad="42"/> +<connect gate="G$1" pin="TDO/PIO0_13/AD2/CT32B1_MAT0" pad="45"/> +<connect gate="G$1" pin="TMS/PIO0_12/AD1/CT32B1_CAP0" pad="44"/> +<connect gate="G$1" pin="USB_DM" pad="25"/> +<connect gate="G$1" pin="USB_DP" pad="26"/> +<connect gate="G$1" pin="VDD" pad="10 33 58"/> +<connect gate="G$1" pin="VDDA" pad="59"/> +<connect gate="G$1" pin="VREFN" pad="48"/> +<connect gate="G$1" pin="VREFP" pad="64"/> +<connect gate="G$1" pin="VSS" pad="7 54"/> +<connect gate="G$1" pin="VSSA" pad="55"/> +<connect gate="G$1" pin="XTALIN" pad="8"/> +<connect gate="G$1" pin="XTALOUT" pad="9"/> +</connects> +<technologies> +<technology name=""> +<attribute name="EEPROM" value="4kB"/> +<attribute name="FLASH" value="64kB"/> +<attribute name="GPIO" value="51"/> +<attribute name="SRAM0" value="8kB"/> +<attribute name="SRAM1" value="2kB"/> +<attribute name="SRAM_USB" value="2kB"/> +<attribute name="USB" value="yes"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="LPC4088FET208" prefix="IC"> +<description><H2>32-bit ARM Cortex-M4 MCU; up to 512 kB flash, 96 kB SRAM; +USB Device/Host/OTG; Ethernet; LCD; EMC; SPIFI</H2> +The LPC408x/7x is an ARM Cortex-M4 based digital signal controller for embedded +applications requiring a high level of integration and low power dissipation. +The ARM Cortex-M4 is a next generation core that offers system enhancements such as +low power consumption, enhanced debug features, and a high level of support block +integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard +architecture with separate local instruction and data buses as well as a third bus for +peripherals, and includes an internal prefetch unit that supports speculative branching. +The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD +instructions. A hardware floating-point processor is integrated in the core for several +versions of the part. +The LPC408x/7x adds a specialized flash memory accelerator to accomplish optimal +performance when executing code from flash. The LPC408x/7x is targeted to operate at +up to 120 MHz CPU frequency. +The peripheral complement of the LPC408x/7x includes up to 512 kB of flash program +memory, up to 96 kB of SRAM data memory, up to 4032 byte of EEPROM data memory, +External Memory controller (EMC), LCD, Ethernet, USB Device/Host/OTG, an SPI Flash +Interface (SPIFI), a General Purpose DMA controller, five UARTs, three SSP controllers, +three I +2 +C-bus interfaces, a Quadrature Encoder Interface, four general purpose timers, +two general purpose PWMs with six outputs each and one motor control PWM, an +ultra-low power RTC with separate battery supply and event recorder, a windowed +watchdog timer, a CRC calculation engine and up to 165 general purpose I/O pins. +The analog peripherals include one eight-channel 12-bit ADC, two analog comparators, +and a DAC. +The pinout of LPC408x/7x is intended to allow pin function compatibility with the +LPC24xx/23xx as well as the LPC178x/7x families. +<p><author>AAL Eindhoven MK</author><hr><p> + <img src="http://www.nxp.com/img/NXP_logo.png"></description> +<gates> +<gate name="G$1" symbol="LPC40X8FYY208" x="0" y="0"/> +</gates> +<devices> +<device name="" package="SOT950-1"> +<connects> +<connect gate="G$1" pin="!RESET!" pad="M2"/> +<connect gate="G$1" pin="!RSTOUT!" pad="K3"/> +<connect gate="G$1" pin="JTAG_!TRST" pad="D1"/> +<connect gate="G$1" pin="JTAG_TCK/SWDCLK" pad="E2"/> +<connect gate="G$1" pin="JTAG_TDI" pad="C2"/> +<connect gate="G$1" pin="JTAG_TDO/SWO" pad="D3"/> +<connect gate="G$1" pin="JTAG_TMS/SWDIO" pad="E3"/> +<connect gate="G$1" pin="P0[0]" pad="U15"/> +<connect gate="G$1" pin="P0[10]" pad="T15"/> +<connect gate="G$1" pin="P0[11]" pad="R14"/> +<connect gate="G$1" pin="P0[12]" pad="R1"/> +<connect gate="G$1" pin="P0[13]" pad="R2"/> +<connect gate="G$1" pin="P0[14]" pad="T7"/> +<connect gate="G$1" pin="P0[15]" pad="J16"/> +<connect gate="G$1" pin="P0[16]" pad="J14"/> +<connect gate="G$1" pin="P0[17]" pad="K17"/> +<connect gate="G$1" pin="P0[18]" pad="K15"/> +<connect gate="G$1" pin="P0[19]" pad="L17"/> +<connect gate="G$1" pin="P0[1]" pad="T14"/> +<connect gate="G$1" pin="P0[20]" pad="M17"/> +<connect gate="G$1" pin="P0[21]" pad="M16"/> +<connect gate="G$1" pin="P0[22]" pad="N17"/> +<connect gate="G$1" pin="P0[23]" pad="H1"/> +<connect gate="G$1" pin="P0[24]" pad="G2"/> +<connect gate="G$1" pin="P0[25]" pad="F1"/> +<connect gate="G$1" pin="P0[26]" pad="E1"/> +<connect gate="G$1" pin="P0[27]" pad="T1"/> +<connect gate="G$1" pin="P0[28]" pad="R3"/> +<connect gate="G$1" pin="P0[29]" pad="U4"/> +<connect gate="G$1" pin="P0[2]" pad="C4"/> +<connect gate="G$1" pin="P0[30]" pad="R6"/> +<connect gate="G$1" pin="P0[31]" pad="T2"/> +<connect gate="G$1" pin="P0[3]" pad="D6"/> +<connect gate="G$1" pin="P0[4]" pad="B12"/> +<connect gate="G$1" pin="P0[5]" pad="C12"/> +<connect gate="G$1" pin="P0[6]" pad="D13"/> +<connect gate="G$1" pin="P0[7]" pad="C13"/> +<connect gate="G$1" pin="P0[8]" pad="A15"/> +<connect gate="G$1" pin="P0[9]" pad="C14"/> +<connect gate="G$1" pin="P1[0]" pad="A3"/> +<connect gate="G$1" pin="P1[10]" pad="C8"/> +<connect gate="G$1" pin="P1[11]" pad="A14"/> +<connect gate="G$1" pin="P1[12]" pad="A16"/> +<connect gate="G$1" pin="P1[13]" pad="D16"/> +<connect gate="G$1" pin="P1[14]" pad="A7"/> +<connect gate="G$1" pin="P1[15]" pad="A8"/> +<connect gate="G$1" pin="P1[16]" pad="D10"/> +<connect gate="G$1" pin="P1[17]" pad="A9"/> +<connect gate="G$1" pin="P1[18]" pad="P7"/> +<connect gate="G$1" pin="P1[19]" pad="U6"/> +<connect gate="G$1" pin="P1[1]" pad="B5"/> +<connect gate="G$1" pin="P1[20]" pad="U7"/> +<connect gate="G$1" pin="P1[21]" pad="R8"/> +<connect gate="G$1" pin="P1[22]" pad="U8"/> +<connect gate="G$1" pin="P1[23]" pad="P9"/> +<connect gate="G$1" pin="P1[24]" pad="T9"/> +<connect gate="G$1" pin="P1[25]" pad="T10"/> +<connect gate="G$1" pin="P1[26]" pad="R10"/> +<connect gate="G$1" pin="P1[27]" pad="T12"/> +<connect gate="G$1" pin="P1[28]" pad="T13"/> +<connect gate="G$1" pin="P1[29]" pad="U14"/> +<connect gate="G$1" pin="P1[2]" pad="D9"/> +<connect gate="G$1" pin="P1[30]" pad="P2"/> +<connect gate="G$1" pin="P1[31]" pad="P1"/> +<connect gate="G$1" pin="P1[3]" pad="A10"/> +<connect gate="G$1" pin="P1[4]" pad="A5"/> +<connect gate="G$1" pin="P1[5]" pad="A17"/> +<connect gate="G$1" pin="P1[6]" pad="B11"/> +<connect gate="G$1" pin="P1[7]" pad="D14"/> +<connect gate="G$1" pin="P1[8]" pad="C7"/> +<connect gate="G$1" pin="P1[9]" pad="A6"/> +<connect gate="G$1" pin="P2[0]" pad="B17"/> +<connect gate="G$1" pin="P2[10]" pad="N15"/> +<connect gate="G$1" pin="P2[11]" pad="T17"/> +<connect gate="G$1" pin="P2[12]" pad="N14"/> +<connect gate="G$1" pin="P2[13]" pad="T16"/> +<connect gate="G$1" pin="P2[14]" pad="R12"/> +<connect gate="G$1" pin="P2[15]" pad="P13"/> +<connect gate="G$1" pin="P2[16]" pad="R11"/> +<connect gate="G$1" pin="P2[17]" pad="R13"/> +<connect gate="G$1" pin="P2[18]" pad="U3"/> +<connect gate="G$1" pin="P2[19]" pad="R7"/> +<connect gate="G$1" pin="P2[1]" pad="E14"/> +<connect gate="G$1" pin="P2[20]" pad="T8"/> +<connect gate="G$1" pin="P2[21]" pad="U11"/> +<connect gate="G$1" pin="P2[22]" pad="U12"/> +<connect gate="G$1" pin="P2[23]" pad="U5"/> +<connect gate="G$1" pin="P2[24]" pad="P5"/> +<connect gate="G$1" pin="P2[25]" pad="R4"/> +<connect gate="G$1" pin="P2[26]" pad="T4"/> +<connect gate="G$1" pin="P2[27]" pad="P3"/> +<connect gate="G$1" pin="P2[28]" pad="P4"/> +<connect gate="G$1" pin="P2[29]" pad="N3"/> +<connect gate="G$1" pin="P2[2]" pad="D15"/> +<connect gate="G$1" pin="P2[30]" pad="L4"/> +<connect gate="G$1" pin="P2[31]" pad="N2"/> +<connect gate="G$1" pin="P2[3]" pad="E16"/> +<connect gate="G$1" pin="P2[4]" pad="D17"/> +<connect gate="G$1" pin="P2[5]" pad="F16"/> +<connect gate="G$1" pin="P2[6]" pad="E17"/> +<connect gate="G$1" pin="P2[7]" pad="G16"/> +<connect gate="G$1" pin="P2[8]" pad="H15"/> +<connect gate="G$1" pin="P2[9]" pad="H16"/> +<connect gate="G$1" pin="P3[0]" pad="B4"/> +<connect gate="G$1" pin="P3[10]" pad="B2"/> +<connect gate="G$1" pin="P3[11]" pad="D5"/> +<connect gate="G$1" pin="P3[12]" pad="D4"/> +<connect gate="G$1" pin="P3[13]" pad="C1"/> +<connect gate="G$1" pin="P3[14]" pad="H2"/> +<connect gate="G$1" pin="P3[15]" pad="M1"/> +<connect gate="G$1" pin="P3[16]" pad="F17"/> +<connect gate="G$1" pin="P3[17]" pad="F15"/> +<connect gate="G$1" pin="P3[18]" pad="C15"/> +<connect gate="G$1" pin="P3[19]" pad="B14"/> +<connect gate="G$1" pin="P3[1]" pad="B3"/> +<connect gate="G$1" pin="P3[20]" pad="A13"/> +<connect gate="G$1" pin="P3[21]" pad="C10"/> +<connect gate="G$1" pin="P3[22]" pad="C6"/> +<connect gate="G$1" pin="P3[23]" pad="T6"/> +<connect gate="G$1" pin="P3[24]" pad="R5"/> +<connect gate="G$1" pin="P3[25]" pad="U2"/> +<connect gate="G$1" pin="P3[26]" pad="T3"/> +<connect gate="G$1" pin="P3[27]" pad="A1"/> +<connect gate="G$1" pin="P3[28]" pad="D2"/> +<connect gate="G$1" pin="P3[29]" pad="F3"/> +<connect gate="G$1" pin="P3[2]" pad="B1"/> +<connect gate="G$1" pin="P3[30]" pad="H3"/> +<connect gate="G$1" pin="P3[31]" pad="J3"/> +<connect gate="G$1" pin="P3[3]" pad="E4"/> +<connect gate="G$1" pin="P3[4]" pad="F2"/> +<connect gate="G$1" pin="P3[5]" pad="G1"/> +<connect gate="G$1" pin="P3[6]" pad="J1"/> +<connect gate="G$1" pin="P3[7]" pad="L1"/> +<connect gate="G$1" pin="P3[8]" pad="D8"/> +<connect gate="G$1" pin="P3[9]" pad="C5"/> +<connect gate="G$1" pin="P4[0]" pad="U9"/> +<connect gate="G$1" pin="P4[10]" pad="G17"/> +<connect gate="G$1" pin="P4[11]" pad="F14"/> +<connect gate="G$1" pin="P4[12]" pad="C16"/> +<connect gate="G$1" pin="P4[13]" pad="B16"/> +<connect gate="G$1" pin="P4[14]" pad="B15"/> +<connect gate="G$1" pin="P4[15]" pad="A11"/> +<connect gate="G$1" pin="P4[16]" pad="U17"/> +<connect gate="G$1" pin="P4[17]" pad="P14"/> +<connect gate="G$1" pin="P4[18]" pad="P15"/> +<connect gate="G$1" pin="P4[19]" pad="P16"/> +<connect gate="G$1" pin="P4[1]" pad="U10"/> +<connect gate="G$1" pin="P4[20]" pad="R17"/> +<connect gate="G$1" pin="P4[21]" pad="M15"/> +<connect gate="G$1" pin="P4[22]" pad="K14"/> +<connect gate="G$1" pin="P4[23]" pad="J15"/> +<connect gate="G$1" pin="P4[24]" pad="B8"/> +<connect gate="G$1" pin="P4[25]" pad="B9"/> +<connect gate="G$1" pin="P4[26]" pad="L15"/> +<connect gate="G$1" pin="P4[27]" pad="G15"/> +<connect gate="G$1" pin="P4[28]" pad="C11"/> +<connect gate="G$1" pin="P4[29]" pad="B10"/> +<connect gate="G$1" pin="P4[2]" pad="T11"/> +<connect gate="G$1" pin="P4[30]" pad="B7"/> +<connect gate="G$1" pin="P4[31]" pad="A4"/> +<connect gate="G$1" pin="P4[3]" pad="U16"/> +<connect gate="G$1" pin="P4[4]" pad="R15"/> +<connect gate="G$1" pin="P4[5]" pad="R16"/> +<connect gate="G$1" pin="P4[6]" pad="M14"/> +<connect gate="G$1" pin="P4[7]" pad="L16"/> +<connect gate="G$1" pin="P4[8]" pad="J17"/> +<connect gate="G$1" pin="P4[9]" pad="H17"/> +<connect gate="G$1" pin="P5[0]" pad="F4"/> +<connect gate="G$1" pin="P5[1]" pad="J4"/> +<connect gate="G$1" pin="P5[2]" pad="L14"/> +<connect gate="G$1" pin="P5[3]" pad="G14"/> +<connect gate="G$1" pin="P5[4]" pad="C3"/> +<connect gate="G$1" pin="RTCX1" pad="K2"/> +<connect gate="G$1" pin="RTCX2" pad="L2"/> +<connect gate="G$1" pin="RTC_ALARM" pad="N1"/> +<connect gate="G$1" pin="USB_D-2" pad="U1"/> +<connect gate="G$1" pin="VBAT" pad="M3"/> +<connect gate="G$1" pin="VDD" pad="B13 C9 C17 D7 G3 K16 P6 P8 P17 U13"/> +<connect gate="G$1" pin="VDD(REG)(3V3)" pad="D11 H4 P11"/> +<connect gate="G$1" pin="VDDA" pad="G4"/> +<connect gate="G$1" pin="VREFP" pad="K1"/> +<connect gate="G$1" pin="VSS" pad="A2 A12 B6 E15 H14 L3 N16 P12 R9 T5"/> +<connect gate="G$1" pin="VSSA" pad="J2"/> +<connect gate="G$1" pin="VSSREG" pad="D12 K4 P10"/> +<connect gate="G$1" pin="XTAL1" pad="M4"/> +<connect gate="G$1" pin="XTAL2" pad="N4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="LPC1114FN28" prefix="U"> +<description><H2>32-bit ARM Cortex-M0 microcontroller; up to 64 kB flash and 8 kB SRAM</H2> +The LPC1110/11/12/13/14/15 are a ARM Cortex-M0 based, low-cost 32-bit MCU family, +designed for 8/16-bit microcontroller applications, offering performance, low power, simple +instruction set and memory addressing together with reduced code size compared to +existing 8/16-bit architectures. +The LPC1110/11/12/13/14/15 operate at CPU frequencies of up to 50 MHz. +The peripheral complement of the LPC1110/11/12/13/14/15 includes up to 64 kB of flash +memory, up to 8 kB of data memory, one Fast-mode Plus I +2 +C-bus interface, one +RS-485/EIA-485 UART, up to two SPI interfaces with SSP features, four general purpose +counter/timers, a 10-bit ADC, and up to 42 general purpose I/O pins. +Remark: The LPC111x series consists of the LPC1100 series (parts +LPC111x/101/201/301), LPC1100L series (parts LPC111x/002/102/202/302), and the +LPC1100XL series (parts LPC111x/103/203/303/323/333). The LPC1100L and +LPC1100XL series include the power profiles, a windowed watchdog timer, and a +configurable open-drain mode. +<p><author>AAL Eindhoven MK</author><hr><p> + <img src="http://www.nxp.com/img/NXP_logo.png"></description> +<gates> +<gate name="G$1" symbol="LPC1112FDH28" x="0" y="0"/> +</gates> +<devices> +<device name="" package="SOT117"> +<connects> +<connect gate="G$1" pin="PIO0_1/CLKOUT/CT32B0_MAT2" pad="24"/> +<connect gate="G$1" pin="PIO0_2/SSEL/CT16B0_CAP0" pad="25"/> +<connect gate="G$1" pin="PIO0_3" pad="26"/> +<connect gate="G$1" pin="PIO0_4/SCL" pad="27"/> +<connect gate="G$1" pin="PIO0_5/SDA" pad="5"/> +<connect gate="G$1" pin="PIO0_6/SCK0" pad="6"/> +<connect gate="G$1" pin="PIO0_7/!CTS!" pad="28"/> +<connect gate="G$1" pin="PIO0_8/MISO0/CT16B0_MAT0" pad="1"/> +<connect gate="G$1" pin="PIO0_9/MOSI0/CT16B0_MAT1" pad="2"/> +<connect gate="G$1" pin="PIO1_4/AD5/CT32B1_MAT3/WAKEUP" pad="13"/> +<connect gate="G$1" pin="PIO1_5/!RTS!/CT32B0_CAP0" pad="14"/> +<connect gate="G$1" pin="PIO1_6/RXD/CT32B0_MAT0" pad="15"/> +<connect gate="G$1" pin="PIO1_7/TXD/CT32B0_MAT1" pad="16"/> +<connect gate="G$1" pin="PIO1_8/CT16B1_CAP0" pad="17"/> +<connect gate="G$1" pin="PIO1_9/CT16B1_MAT0" pad="18"/> +<connect gate="G$1" pin="RESET/PIO0_0" pad="23"/> +<connect gate="G$1" pin="SWCLK/PIO0_10/SCK0/CT16B0_MAT2" pad="3"/> +<connect gate="G$1" pin="SWDIO/PIO1_3/AD4/CT32B1_MAT2" pad="12"/> +<connect gate="G$1" pin="TDI/PIO0_11/AD0/CT32B0_MAT3" pad="4"/> +<connect gate="G$1" pin="TDO/PIO1_1/AD2/CT32B1_MAT0" pad="10"/> +<connect gate="G$1" pin="TMS/PIO1_0/AD1/CT32B1_CAP0" pad="9"/> +<connect gate="G$1" pin="TRST/PIO1_2/AD3/CT32B1_MAT1" pad="11"/> +<connect gate="G$1" pin="VDD" pad="21"/> +<connect gate="G$1" pin="VDDA" pad="7"/> +<connect gate="G$1" pin="VSS" pad="22"/> +<connect gate="G$1" pin="VSSA" pad="8"/> +<connect gate="G$1" pin="XTALIN" pad="20"/> +<connect gate="G$1" pin="XTALOUT" pad="19"/> +</connects> +<technologies> +<technology name="/102"> +<attribute name="ADC" value="6"/> +<attribute name="FLASH" value="32kB"/> +<attribute name="GPIO" value="22"/> +<attribute name="PWR_PROFILES" value="yes"/> +<attribute name="SERIES" value="LPC1100L"/> +<attribute name="SPI" value="1"/> +<attribute name="SRAM" value="4kB"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="IF-LPC11U35" prefix="IC" uservalue="yes"> +<gates> +<gate name="G$1" symbol="IF-LPC11U35" x="0" y="2.54"/> +</gates> +<devices> +<device name="" package="HVQFN33"> +<connects> +<connect gate="G$1" pin="IF_NRESET" pad="2"/> +<connect gate="G$1" pin="LED_HID" pad="12"/> +<connect gate="G$1" pin="LED_MSD" pad="7"/> +<connect gate="G$1" pin="LED_UART" pad="21"/> +<connect gate="G$1" pin="NC10" pad="28"/> +<connect gate="G$1" pin="NC11" pad="30"/> +<connect gate="G$1" pin="NC2" pad="10"/> +<connect gate="G$1" pin="NC3" pad="11"/> +<connect gate="G$1" pin="NC4" pad="19"/> +<connect gate="G$1" pin="NC5" pad="20"/> +<connect gate="G$1" pin="NC6" pad="22"/> +<connect gate="G$1" pin="NC7" pad="23"/> +<connect gate="G$1" pin="NC8" pad="24"/> +<connect gate="G$1" pin="NC9" pad="25"/> +<connect gate="G$1" pin="NRESET_FB_BL" pad="1"/> +<connect gate="G$1" pin="NRESET_FB_ISP" pad="3"/> +<connect gate="G$1" pin="SLEEP_NREQ" pad="27"/> +<connect gate="G$1" pin="TGT_NRESET" pad="8"/> +<connect gate="G$1" pin="TGT_RX" pad="32"/> +<connect gate="G$1" pin="TGT_SWCLK" pad="16"/> +<connect gate="G$1" pin="TGT_SWDIO" pad="17"/> +<connect gate="G$1" pin="TGT_SWO" pad="18"/> +<connect gate="G$1" pin="TGT_TX" pad="31"/> +<connect gate="G$1" pin="USB_D+" pad="14"/> +<connect gate="G$1" pin="USB_D-" pad="13"/> +<connect gate="G$1" pin="USB_SCON" pad="15"/> +<connect gate="G$1" pin="USB_VBUS" pad="9"/> +<connect gate="G$1" pin="VDD1" pad="6"/> +<connect gate="G$1" pin="VDD2" pad="29"/> +<connect gate="G$1" pin="VSS" pad="EXP"/> +<connect gate="G$1" pin="WAKE_NREQ" pad="26"/> +<connect gate="G$1" pin="XTALIN" pad="4"/> +<connect gate="G$1" pin="XTALOUT" pad="5"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +</drawing> +</eagle>