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source/nordic-sdk/components/device/nrf51_bitfields.h@551:ab7a8de3ff10, 2016-01-11 (annotated)

Committer:: vcoubard
Date:: Mon Jan 11 10:19:10 2016 +0000
Revision:: 551:ab7a8de3ff10
Parent:: 504:2179e57ad950

Synchronized with git rev 6825c511

Author: Rohit Grover

Release 2.1.0

=============



Upgrading to files from v8.1 of the Nordic SDK.

Who changed what in which revision?

User	Revision	Line number	New contents of line
vcoubard	551:ab7a8de3ff10	1	/*
vcoubard	551:ab7a8de3ff10	2	* Copyright (c) Nordic Semiconductor ASA
vcoubard	551:ab7a8de3ff10	3	* All rights reserved.
vcoubard	551:ab7a8de3ff10	4	*
vcoubard	551:ab7a8de3ff10	5	* Redistribution and use in source and binary forms, with or without modification,
vcoubard	551:ab7a8de3ff10	6	* are permitted provided that the following conditions are met:
vcoubard	551:ab7a8de3ff10	7	*
vcoubard	551:ab7a8de3ff10	8	* 1. Redistributions of source code must retain the above copyright notice, this
vcoubard	551:ab7a8de3ff10	9	* list of conditions and the following disclaimer.
vcoubard	551:ab7a8de3ff10	10	*
vcoubard	551:ab7a8de3ff10	11	* 2. Redistributions in binary form must reproduce the above copyright notice, this
vcoubard	551:ab7a8de3ff10	12	* list of conditions and the following disclaimer in the documentation and/or
vcoubard	551:ab7a8de3ff10	13	* other materials provided with the distribution.
vcoubard	551:ab7a8de3ff10	14	*
vcoubard	551:ab7a8de3ff10	15	* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
vcoubard	551:ab7a8de3ff10	16	* contributors to this software may be used to endorse or promote products
vcoubard	551:ab7a8de3ff10	17	* derived from this software without specific prior written permission.
vcoubard	551:ab7a8de3ff10	18	*
vcoubard	551:ab7a8de3ff10	19	*
vcoubard	551:ab7a8de3ff10	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
vcoubard	551:ab7a8de3ff10	21	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
vcoubard	551:ab7a8de3ff10	22	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vcoubard	551:ab7a8de3ff10	23	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
vcoubard	551:ab7a8de3ff10	24	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
vcoubard	551:ab7a8de3ff10	25	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
vcoubard	551:ab7a8de3ff10	26	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
vcoubard	551:ab7a8de3ff10	27	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
vcoubard	551:ab7a8de3ff10	28	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
vcoubard	551:ab7a8de3ff10	29	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vcoubard	551:ab7a8de3ff10	30	*
vcoubard	551:ab7a8de3ff10	31	*/
vcoubard	551:ab7a8de3ff10	32	#ifndef __NRF51_BITS_H
vcoubard	551:ab7a8de3ff10	33	#define __NRF51_BITS_H
vcoubard	551:ab7a8de3ff10	34
vcoubard	551:ab7a8de3ff10	35	/lint ++flb "Enter library region /
vcoubard	551:ab7a8de3ff10	36
vcoubard	551:ab7a8de3ff10	37	#include <core_cm0.h>
vcoubard	551:ab7a8de3ff10	38
vcoubard	551:ab7a8de3ff10	39	/* Peripheral: AAR */
vcoubard	551:ab7a8de3ff10	40	/* Description: Accelerated Address Resolver. */
vcoubard	551:ab7a8de3ff10	41
vcoubard	551:ab7a8de3ff10	42	/* Register: AAR_INTENSET */
vcoubard	551:ab7a8de3ff10	43	/* Description: Interrupt enable set register. */
vcoubard	551:ab7a8de3ff10	44
vcoubard	551:ab7a8de3ff10	45	/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
vcoubard	551:ab7a8de3ff10	46	#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
vcoubard	551:ab7a8de3ff10	47	#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
vcoubard	551:ab7a8de3ff10	48	#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	49	#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	50	#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	51
vcoubard	551:ab7a8de3ff10	52	/* Bit 1 : Enable interrupt on RESOLVED event. */
vcoubard	551:ab7a8de3ff10	53	#define AAR_INTENSET_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
vcoubard	551:ab7a8de3ff10	54	#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
vcoubard	551:ab7a8de3ff10	55	#define AAR_INTENSET_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	56	#define AAR_INTENSET_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	57	#define AAR_INTENSET_RESOLVED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	58
vcoubard	551:ab7a8de3ff10	59	/* Bit 0 : Enable interrupt on END event. */
vcoubard	551:ab7a8de3ff10	60	#define AAR_INTENSET_END_Pos (0UL) /!< Position of END field. /
vcoubard	551:ab7a8de3ff10	61	#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /!< Bit mask of END field. /
vcoubard	551:ab7a8de3ff10	62	#define AAR_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	63	#define AAR_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	64	#define AAR_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	65
vcoubard	551:ab7a8de3ff10	66	/* Register: AAR_INTENCLR */
vcoubard	551:ab7a8de3ff10	67	/* Description: Interrupt enable clear register. */
vcoubard	551:ab7a8de3ff10	68
vcoubard	551:ab7a8de3ff10	69	/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
vcoubard	551:ab7a8de3ff10	70	#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
vcoubard	551:ab7a8de3ff10	71	#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
vcoubard	551:ab7a8de3ff10	72	#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	73	#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	74	#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	75
vcoubard	551:ab7a8de3ff10	76	/* Bit 1 : Disable interrupt on RESOLVED event. */
vcoubard	551:ab7a8de3ff10	77	#define AAR_INTENCLR_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
vcoubard	551:ab7a8de3ff10	78	#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
vcoubard	551:ab7a8de3ff10	79	#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	80	#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	81	#define AAR_INTENCLR_RESOLVED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	82
vcoubard	551:ab7a8de3ff10	83	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
vcoubard	551:ab7a8de3ff10	84	#define AAR_INTENCLR_END_Pos (0UL) /!< Position of END field. /
vcoubard	551:ab7a8de3ff10	85	#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /!< Bit mask of END field. /
vcoubard	551:ab7a8de3ff10	86	#define AAR_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	87	#define AAR_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	88	#define AAR_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	89
vcoubard	551:ab7a8de3ff10	90	/* Register: AAR_STATUS */
vcoubard	551:ab7a8de3ff10	91	/* Description: Resolution status. */
vcoubard	551:ab7a8de3ff10	92
vcoubard	551:ab7a8de3ff10	93	/* Bits 3..0 : The IRK used last time an address was resolved. */
vcoubard	551:ab7a8de3ff10	94	#define AAR_STATUS_STATUS_Pos (0UL) /!< Position of STATUS field. /
vcoubard	551:ab7a8de3ff10	95	#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /!< Bit mask of STATUS field. /
vcoubard	551:ab7a8de3ff10	96
vcoubard	551:ab7a8de3ff10	97	/* Register: AAR_ENABLE */
vcoubard	551:ab7a8de3ff10	98	/* Description: Enable AAR. */
vcoubard	551:ab7a8de3ff10	99
vcoubard	551:ab7a8de3ff10	100	/* Bits 1..0 : Enable AAR. */
vcoubard	551:ab7a8de3ff10	101	#define AAR_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	551:ab7a8de3ff10	102	#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	551:ab7a8de3ff10	103	#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled AAR. /
vcoubard	551:ab7a8de3ff10	104	#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /!< Enable AAR. /
vcoubard	551:ab7a8de3ff10	105
vcoubard	551:ab7a8de3ff10	106	/* Register: AAR_NIRK */
vcoubard	551:ab7a8de3ff10	107	/* Description: Number of Identity root Keys in the IRK data structure. */
vcoubard	551:ab7a8de3ff10	108
vcoubard	551:ab7a8de3ff10	109	/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
vcoubard	551:ab7a8de3ff10	110	#define AAR_NIRK_NIRK_Pos (0UL) /!< Position of NIRK field. /
vcoubard	551:ab7a8de3ff10	111	#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /!< Bit mask of NIRK field. /
vcoubard	551:ab7a8de3ff10	112
vcoubard	551:ab7a8de3ff10	113	/* Register: AAR_POWER */
vcoubard	551:ab7a8de3ff10	114	/* Description: Peripheral power control. */
vcoubard	551:ab7a8de3ff10	115
vcoubard	551:ab7a8de3ff10	116	/* Bit 0 : Peripheral power control. */
vcoubard	551:ab7a8de3ff10	117	#define AAR_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	551:ab7a8de3ff10	118	#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	551:ab7a8de3ff10	119	#define AAR_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	551:ab7a8de3ff10	120	#define AAR_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	551:ab7a8de3ff10	121
vcoubard	551:ab7a8de3ff10	122
vcoubard	551:ab7a8de3ff10	123	/* Peripheral: ADC */
vcoubard	551:ab7a8de3ff10	124	/* Description: Analog to digital converter. */
vcoubard	551:ab7a8de3ff10	125
vcoubard	551:ab7a8de3ff10	126	/* Register: ADC_INTENSET */
vcoubard	551:ab7a8de3ff10	127	/* Description: Interrupt enable set register. */
vcoubard	551:ab7a8de3ff10	128
vcoubard	551:ab7a8de3ff10	129	/* Bit 0 : Enable interrupt on END event. */
vcoubard	551:ab7a8de3ff10	130	#define ADC_INTENSET_END_Pos (0UL) /!< Position of END field. /
vcoubard	551:ab7a8de3ff10	131	#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /!< Bit mask of END field. /
vcoubard	551:ab7a8de3ff10	132	#define ADC_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	133	#define ADC_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	134	#define ADC_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	135
vcoubard	551:ab7a8de3ff10	136	/* Register: ADC_INTENCLR */
vcoubard	551:ab7a8de3ff10	137	/* Description: Interrupt enable clear register. */
vcoubard	551:ab7a8de3ff10	138
vcoubard	551:ab7a8de3ff10	139	/* Bit 0 : Disable interrupt on END event. */
vcoubard	551:ab7a8de3ff10	140	#define ADC_INTENCLR_END_Pos (0UL) /!< Position of END field. /
vcoubard	551:ab7a8de3ff10	141	#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /!< Bit mask of END field. /
vcoubard	551:ab7a8de3ff10	142	#define ADC_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	143	#define ADC_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	144	#define ADC_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	145
vcoubard	551:ab7a8de3ff10	146	/* Register: ADC_BUSY */
vcoubard	551:ab7a8de3ff10	147	/* Description: ADC busy register. */
vcoubard	551:ab7a8de3ff10	148
vcoubard	551:ab7a8de3ff10	149	/* Bit 0 : ADC busy register. */
vcoubard	551:ab7a8de3ff10	150	#define ADC_BUSY_BUSY_Pos (0UL) /!< Position of BUSY field. /
vcoubard	551:ab7a8de3ff10	151	#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /!< Bit mask of BUSY field. /
vcoubard	551:ab7a8de3ff10	152	#define ADC_BUSY_BUSY_Ready (0UL) /!< No ongoing ADC conversion is taking place. ADC is ready. /
vcoubard	551:ab7a8de3ff10	153	#define ADC_BUSY_BUSY_Busy (1UL) /!< An ADC conversion is taking place. ADC is busy. /
vcoubard	551:ab7a8de3ff10	154
vcoubard	551:ab7a8de3ff10	155	/* Register: ADC_ENABLE */
vcoubard	551:ab7a8de3ff10	156	/* Description: ADC enable. */
vcoubard	551:ab7a8de3ff10	157
vcoubard	551:ab7a8de3ff10	158	/* Bits 1..0 : ADC enable. */
vcoubard	551:ab7a8de3ff10	159	#define ADC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	551:ab7a8de3ff10	160	#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	551:ab7a8de3ff10	161	#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /!< ADC is disabled. /
vcoubard	551:ab7a8de3ff10	162	#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. /
vcoubard	551:ab7a8de3ff10	163
vcoubard	551:ab7a8de3ff10	164	/* Register: ADC_CONFIG */
vcoubard	551:ab7a8de3ff10	165	/* Description: ADC configuration register. */
vcoubard	551:ab7a8de3ff10	166
vcoubard	551:ab7a8de3ff10	167	/* Bits 17..16 : ADC external reference pin selection. */
vcoubard	551:ab7a8de3ff10	168	#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /!< Position of EXTREFSEL field. /
vcoubard	551:ab7a8de3ff10	169	#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
vcoubard	551:ab7a8de3ff10	170	#define ADC_CONFIG_EXTREFSEL_None (0UL) /!< Analog external reference inputs disabled. /
vcoubard	551:ab7a8de3ff10	171	#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /!< Use analog reference 0 as reference. /
vcoubard	551:ab7a8de3ff10	172	#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /!< Use analog reference 1 as reference. /
vcoubard	551:ab7a8de3ff10	173
vcoubard	551:ab7a8de3ff10	174	/* Bits 15..8 : ADC analog pin selection. */
vcoubard	551:ab7a8de3ff10	175	#define ADC_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
vcoubard	551:ab7a8de3ff10	176	#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
vcoubard	551:ab7a8de3ff10	177	#define ADC_CONFIG_PSEL_Disabled (0UL) /!< Analog input pins disabled. /
vcoubard	551:ab7a8de3ff10	178	#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /!< Use analog input 0 as analog input. /
vcoubard	551:ab7a8de3ff10	179	#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /!< Use analog input 1 as analog input. /
vcoubard	551:ab7a8de3ff10	180	#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /!< Use analog input 2 as analog input. /
vcoubard	551:ab7a8de3ff10	181	#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /!< Use analog input 3 as analog input. /
vcoubard	551:ab7a8de3ff10	182	#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /!< Use analog input 4 as analog input. /
vcoubard	551:ab7a8de3ff10	183	#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /!< Use analog input 5 as analog input. /
vcoubard	551:ab7a8de3ff10	184	#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /!< Use analog input 6 as analog input. /
vcoubard	551:ab7a8de3ff10	185	#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /!< Use analog input 7 as analog input. /
vcoubard	551:ab7a8de3ff10	186
vcoubard	551:ab7a8de3ff10	187	/* Bits 6..5 : ADC reference selection. */
vcoubard	551:ab7a8de3ff10	188	#define ADC_CONFIG_REFSEL_Pos (5UL) /!< Position of REFSEL field. /
vcoubard	551:ab7a8de3ff10	189	#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /!< Bit mask of REFSEL field. /
vcoubard	551:ab7a8de3ff10	190	#define ADC_CONFIG_REFSEL_VBG (0x00UL) /!< Use internal 1.2V bandgap voltage as reference for conversion. /
vcoubard	551:ab7a8de3ff10	191	#define ADC_CONFIG_REFSEL_External (0x01UL) /!< Use external source configured by EXTREFSEL as reference for conversion. /
vcoubard	551:ab7a8de3ff10	192	#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. /
vcoubard	551:ab7a8de3ff10	193	#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. /
vcoubard	551:ab7a8de3ff10	194
vcoubard	551:ab7a8de3ff10	195	/* Bits 4..2 : ADC input selection. */
vcoubard	551:ab7a8de3ff10	196	#define ADC_CONFIG_INPSEL_Pos (2UL) /!< Position of INPSEL field. /
vcoubard	551:ab7a8de3ff10	197	#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /!< Bit mask of INPSEL field. /
vcoubard	551:ab7a8de3ff10	198	#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /!< Analog input specified by PSEL with no prescaling used as input for the conversion. /
vcoubard	551:ab7a8de3ff10	199	#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. /
vcoubard	551:ab7a8de3ff10	200	#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. /
vcoubard	551:ab7a8de3ff10	201	#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /!< Supply voltage with 2/3 prescaling used as input for the conversion. /
vcoubard	551:ab7a8de3ff10	202	#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /!< Supply voltage with 1/3 prescaling used as input for the conversion. /
vcoubard	551:ab7a8de3ff10	203
vcoubard	551:ab7a8de3ff10	204	/* Bits 1..0 : ADC resolution. */
vcoubard	551:ab7a8de3ff10	205	#define ADC_CONFIG_RES_Pos (0UL) /!< Position of RES field. /
vcoubard	551:ab7a8de3ff10	206	#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /!< Bit mask of RES field. /
vcoubard	551:ab7a8de3ff10	207	#define ADC_CONFIG_RES_8bit (0x00UL) /!< 8bit ADC resolution. /
vcoubard	551:ab7a8de3ff10	208	#define ADC_CONFIG_RES_9bit (0x01UL) /!< 9bit ADC resolution. /
vcoubard	551:ab7a8de3ff10	209	#define ADC_CONFIG_RES_10bit (0x02UL) /!< 10bit ADC resolution. /
vcoubard	551:ab7a8de3ff10	210
vcoubard	551:ab7a8de3ff10	211	/* Register: ADC_RESULT */
vcoubard	551:ab7a8de3ff10	212	/* Description: Result of ADC conversion. */
vcoubard	551:ab7a8de3ff10	213
vcoubard	551:ab7a8de3ff10	214	/* Bits 9..0 : Result of ADC conversion. */
vcoubard	551:ab7a8de3ff10	215	#define ADC_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
vcoubard	551:ab7a8de3ff10	216	#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
vcoubard	551:ab7a8de3ff10	217
vcoubard	551:ab7a8de3ff10	218	/* Register: ADC_POWER */
vcoubard	551:ab7a8de3ff10	219	/* Description: Peripheral power control. */
vcoubard	551:ab7a8de3ff10	220
vcoubard	551:ab7a8de3ff10	221	/* Bit 0 : Peripheral power control. */
vcoubard	551:ab7a8de3ff10	222	#define ADC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	551:ab7a8de3ff10	223	#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	551:ab7a8de3ff10	224	#define ADC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	551:ab7a8de3ff10	225	#define ADC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	551:ab7a8de3ff10	226
vcoubard	551:ab7a8de3ff10	227
vcoubard	551:ab7a8de3ff10	228	/* Peripheral: AMLI */
vcoubard	551:ab7a8de3ff10	229	/* Description: AHB Multi-Layer Interface. */
vcoubard	551:ab7a8de3ff10	230
vcoubard	551:ab7a8de3ff10	231	/* Register: AMLI_RAMPRI_CPU0 */
vcoubard	551:ab7a8de3ff10	232	/* Description: Configurable priority configuration register for CPU0. */
vcoubard	551:ab7a8de3ff10	233
vcoubard	551:ab7a8de3ff10	234	/* Bits 31..28 : Configuration field for RAM block 7. */
vcoubard	551:ab7a8de3ff10	235	#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /!< Position of RAM7 field. /
vcoubard	551:ab7a8de3ff10	236	#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /!< Bit mask of RAM7 field. /
vcoubard	551:ab7a8de3ff10	237	#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	238	#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	239	#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	240	#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	241	#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	242	#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	243	#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	244	#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	245
vcoubard	551:ab7a8de3ff10	246	/* Bits 27..24 : Configuration field for RAM block 6. */
vcoubard	551:ab7a8de3ff10	247	#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /!< Position of RAM6 field. /
vcoubard	551:ab7a8de3ff10	248	#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /!< Bit mask of RAM6 field. /
vcoubard	551:ab7a8de3ff10	249	#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	250	#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	251	#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	252	#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	253	#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	254	#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	255	#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	256	#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	257
vcoubard	551:ab7a8de3ff10	258	/* Bits 23..20 : Configuration field for RAM block 5. */
vcoubard	551:ab7a8de3ff10	259	#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /!< Position of RAM5 field. /
vcoubard	551:ab7a8de3ff10	260	#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /!< Bit mask of RAM5 field. /
vcoubard	551:ab7a8de3ff10	261	#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	262	#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	263	#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	264	#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	265	#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	266	#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	267	#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	268	#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	269
vcoubard	551:ab7a8de3ff10	270	/* Bits 19..16 : Configuration field for RAM block 4. */
vcoubard	551:ab7a8de3ff10	271	#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /!< Position of RAM4 field. /
vcoubard	551:ab7a8de3ff10	272	#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /!< Bit mask of RAM4 field. /
vcoubard	551:ab7a8de3ff10	273	#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	274	#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	275	#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	276	#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	277	#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	278	#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	279	#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	280	#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	281
vcoubard	551:ab7a8de3ff10	282	/* Bits 15..12 : Configuration field for RAM block 3. */
vcoubard	551:ab7a8de3ff10	283	#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /!< Position of RAM3 field. /
vcoubard	551:ab7a8de3ff10	284	#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /!< Bit mask of RAM3 field. /
vcoubard	551:ab7a8de3ff10	285	#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	286	#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	287	#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	288	#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	289	#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	290	#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	291	#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	292	#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	293
vcoubard	551:ab7a8de3ff10	294	/* Bits 11..8 : Configuration field for RAM block 2. */
vcoubard	551:ab7a8de3ff10	295	#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /!< Position of RAM2 field. /
vcoubard	551:ab7a8de3ff10	296	#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /!< Bit mask of RAM2 field. /
vcoubard	551:ab7a8de3ff10	297	#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	298	#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	299	#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	300	#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	301	#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	302	#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	303	#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	304	#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	305
vcoubard	551:ab7a8de3ff10	306	/* Bits 7..4 : Configuration field for RAM block 1. */
vcoubard	551:ab7a8de3ff10	307	#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /!< Position of RAM1 field. /
vcoubard	551:ab7a8de3ff10	308	#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /!< Bit mask of RAM1 field. /
vcoubard	551:ab7a8de3ff10	309	#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	310	#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	311	#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	312	#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	313	#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	314	#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	315	#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	316	#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	317
vcoubard	551:ab7a8de3ff10	318	/* Bits 3..0 : Configuration field for RAM block 0. */
vcoubard	551:ab7a8de3ff10	319	#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /!< Position of RAM0 field. /
vcoubard	551:ab7a8de3ff10	320	#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /!< Bit mask of RAM0 field. /
vcoubard	551:ab7a8de3ff10	321	#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	322	#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	323	#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	324	#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	325	#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	326	#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	327	#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	328	#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	329
vcoubard	551:ab7a8de3ff10	330	/* Register: AMLI_RAMPRI_SPIS1 */
vcoubard	551:ab7a8de3ff10	331	/* Description: Configurable priority configuration register for SPIS1. */
vcoubard	551:ab7a8de3ff10	332
vcoubard	551:ab7a8de3ff10	333	/* Bits 31..28 : Configuration field for RAM block 7. */
vcoubard	551:ab7a8de3ff10	334	#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /!< Position of RAM7 field. /
vcoubard	551:ab7a8de3ff10	335	#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /!< Bit mask of RAM7 field. /
vcoubard	551:ab7a8de3ff10	336	#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	337	#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	338	#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	339	#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	340	#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	341	#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	342	#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	343	#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	344
vcoubard	551:ab7a8de3ff10	345	/* Bits 27..24 : Configuration field for RAM block 6. */
vcoubard	551:ab7a8de3ff10	346	#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /!< Position of RAM6 field. /
vcoubard	551:ab7a8de3ff10	347	#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /!< Bit mask of RAM6 field. /
vcoubard	551:ab7a8de3ff10	348	#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	349	#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	350	#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	351	#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	352	#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	353	#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	354	#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	355	#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	356
vcoubard	551:ab7a8de3ff10	357	/* Bits 23..20 : Configuration field for RAM block 5. */
vcoubard	551:ab7a8de3ff10	358	#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /!< Position of RAM5 field. /
vcoubard	551:ab7a8de3ff10	359	#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /!< Bit mask of RAM5 field. /
vcoubard	551:ab7a8de3ff10	360	#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	361	#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	362	#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	363	#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	364	#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	365	#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	366	#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	367	#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	368
vcoubard	551:ab7a8de3ff10	369	/* Bits 19..16 : Configuration field for RAM block 4. */
vcoubard	551:ab7a8de3ff10	370	#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /!< Position of RAM4 field. /
vcoubard	551:ab7a8de3ff10	371	#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /!< Bit mask of RAM4 field. /
vcoubard	551:ab7a8de3ff10	372	#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	373	#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	374	#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	375	#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	376	#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	377	#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	378	#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	379	#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	380
vcoubard	551:ab7a8de3ff10	381	/* Bits 15..12 : Configuration field for RAM block 3. */
vcoubard	551:ab7a8de3ff10	382	#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /!< Position of RAM3 field. /
vcoubard	551:ab7a8de3ff10	383	#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /!< Bit mask of RAM3 field. /
vcoubard	551:ab7a8de3ff10	384	#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	385	#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	386	#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	387	#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	388	#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	389	#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	390	#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	391	#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	392
vcoubard	551:ab7a8de3ff10	393	/* Bits 11..8 : Configuration field for RAM block 2. */
vcoubard	551:ab7a8de3ff10	394	#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /!< Position of RAM2 field. /
vcoubard	551:ab7a8de3ff10	395	#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /!< Bit mask of RAM2 field. /
vcoubard	551:ab7a8de3ff10	396	#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	397	#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	398	#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	399	#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	400	#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	401	#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	402	#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	403	#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	404
vcoubard	551:ab7a8de3ff10	405	/* Bits 7..4 : Configuration field for RAM block 1. */
vcoubard	551:ab7a8de3ff10	406	#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /!< Position of RAM1 field. /
vcoubard	551:ab7a8de3ff10	407	#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /!< Bit mask of RAM1 field. /
vcoubard	551:ab7a8de3ff10	408	#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	409	#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	410	#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	411	#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	412	#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	413	#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	414	#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	415	#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	416
vcoubard	551:ab7a8de3ff10	417	/* Bits 3..0 : Configuration field for RAM block 0. */
vcoubard	551:ab7a8de3ff10	418	#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /!< Position of RAM0 field. /
vcoubard	551:ab7a8de3ff10	419	#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /!< Bit mask of RAM0 field. /
vcoubard	551:ab7a8de3ff10	420	#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	421	#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	422	#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	423	#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	424	#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	425	#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	426	#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	427	#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	428
vcoubard	551:ab7a8de3ff10	429	/* Register: AMLI_RAMPRI_RADIO */
vcoubard	551:ab7a8de3ff10	430	/* Description: Configurable priority configuration register for RADIO. */
vcoubard	551:ab7a8de3ff10	431
vcoubard	551:ab7a8de3ff10	432	/* Bits 31..28 : Configuration field for RAM block 7. */
vcoubard	551:ab7a8de3ff10	433	#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /!< Position of RAM7 field. /
vcoubard	551:ab7a8de3ff10	434	#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /!< Bit mask of RAM7 field. /
vcoubard	551:ab7a8de3ff10	435	#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	436	#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	437	#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	438	#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	439	#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	440	#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	441	#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	442	#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	443
vcoubard	551:ab7a8de3ff10	444	/* Bits 27..24 : Configuration field for RAM block 6. */
vcoubard	551:ab7a8de3ff10	445	#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /!< Position of RAM6 field. /
vcoubard	551:ab7a8de3ff10	446	#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /!< Bit mask of RAM6 field. /
vcoubard	551:ab7a8de3ff10	447	#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	448	#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	449	#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	450	#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	451	#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	452	#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	453	#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	454	#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	455
vcoubard	551:ab7a8de3ff10	456	/* Bits 23..20 : Configuration field for RAM block 5. */
vcoubard	551:ab7a8de3ff10	457	#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /!< Position of RAM5 field. /
vcoubard	551:ab7a8de3ff10	458	#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /!< Bit mask of RAM5 field. /
vcoubard	551:ab7a8de3ff10	459	#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	460	#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	461	#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	462	#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	463	#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	464	#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	465	#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	466	#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	467
vcoubard	551:ab7a8de3ff10	468	/* Bits 19..16 : Configuration field for RAM block 4. */
vcoubard	551:ab7a8de3ff10	469	#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /!< Position of RAM4 field. /
vcoubard	551:ab7a8de3ff10	470	#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /!< Bit mask of RAM4 field. /
vcoubard	551:ab7a8de3ff10	471	#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	472	#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	473	#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	474	#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	475	#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	476	#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	477	#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	478	#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	479
vcoubard	551:ab7a8de3ff10	480	/* Bits 15..12 : Configuration field for RAM block 3. */
vcoubard	551:ab7a8de3ff10	481	#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /!< Position of RAM3 field. /
vcoubard	551:ab7a8de3ff10	482	#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /!< Bit mask of RAM3 field. /
vcoubard	551:ab7a8de3ff10	483	#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	484	#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	485	#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	486	#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	487	#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	488	#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	489	#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	490	#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	491
vcoubard	551:ab7a8de3ff10	492	/* Bits 11..8 : Configuration field for RAM block 2. */
vcoubard	551:ab7a8de3ff10	493	#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /!< Position of RAM2 field. /
vcoubard	551:ab7a8de3ff10	494	#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /!< Bit mask of RAM2 field. /
vcoubard	551:ab7a8de3ff10	495	#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	496	#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	497	#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	498	#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	499	#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	500	#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	501	#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	502	#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	503
vcoubard	551:ab7a8de3ff10	504	/* Bits 7..4 : Configuration field for RAM block 1. */
vcoubard	551:ab7a8de3ff10	505	#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /!< Position of RAM1 field. /
vcoubard	551:ab7a8de3ff10	506	#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /!< Bit mask of RAM1 field. /
vcoubard	551:ab7a8de3ff10	507	#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	508	#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	509	#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	510	#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	511	#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	512	#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	513	#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	514	#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	515
vcoubard	551:ab7a8de3ff10	516	/* Bits 3..0 : Configuration field for RAM block 0. */
vcoubard	551:ab7a8de3ff10	517	#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /!< Position of RAM0 field. /
vcoubard	551:ab7a8de3ff10	518	#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /!< Bit mask of RAM0 field. /
vcoubard	551:ab7a8de3ff10	519	#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	520	#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	521	#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	522	#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	523	#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	524	#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	525	#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	526	#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	527
vcoubard	551:ab7a8de3ff10	528	/* Register: AMLI_RAMPRI_ECB */
vcoubard	551:ab7a8de3ff10	529	/* Description: Configurable priority configuration register for ECB. */
vcoubard	551:ab7a8de3ff10	530
vcoubard	551:ab7a8de3ff10	531	/* Bits 31..28 : Configuration field for RAM block 7. */
vcoubard	551:ab7a8de3ff10	532	#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /!< Position of RAM7 field. /
vcoubard	551:ab7a8de3ff10	533	#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /!< Bit mask of RAM7 field. /
vcoubard	551:ab7a8de3ff10	534	#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	535	#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	536	#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	537	#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	538	#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	539	#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	540	#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	541	#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	542
vcoubard	551:ab7a8de3ff10	543	/* Bits 27..24 : Configuration field for RAM block 6. */
vcoubard	551:ab7a8de3ff10	544	#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /!< Position of RAM6 field. /
vcoubard	551:ab7a8de3ff10	545	#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /!< Bit mask of RAM6 field. /
vcoubard	551:ab7a8de3ff10	546	#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	547	#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	548	#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	549	#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	550	#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	551	#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	552	#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	553	#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	554
vcoubard	551:ab7a8de3ff10	555	/* Bits 23..20 : Configuration field for RAM block 5. */
vcoubard	551:ab7a8de3ff10	556	#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /!< Position of RAM5 field. /
vcoubard	551:ab7a8de3ff10	557	#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /!< Bit mask of RAM5 field. /
vcoubard	551:ab7a8de3ff10	558	#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	559	#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	560	#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	561	#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	562	#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	563	#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	564	#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	565	#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	566
vcoubard	551:ab7a8de3ff10	567	/* Bits 19..16 : Configuration field for RAM block 4. */
vcoubard	551:ab7a8de3ff10	568	#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /!< Position of RAM4 field. /
vcoubard	551:ab7a8de3ff10	569	#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /!< Bit mask of RAM4 field. /
vcoubard	551:ab7a8de3ff10	570	#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	571	#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	572	#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	573	#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	574	#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	575	#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	576	#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	577	#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	578
vcoubard	551:ab7a8de3ff10	579	/* Bits 15..12 : Configuration field for RAM block 3. */
vcoubard	551:ab7a8de3ff10	580	#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /!< Position of RAM3 field. /
vcoubard	551:ab7a8de3ff10	581	#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /!< Bit mask of RAM3 field. /
vcoubard	551:ab7a8de3ff10	582	#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	583	#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	584	#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	585	#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	586	#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	587	#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	588	#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	589	#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	590
vcoubard	551:ab7a8de3ff10	591	/* Bits 11..8 : Configuration field for RAM block 2. */
vcoubard	551:ab7a8de3ff10	592	#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /!< Position of RAM2 field. /
vcoubard	551:ab7a8de3ff10	593	#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /!< Bit mask of RAM2 field. /
vcoubard	551:ab7a8de3ff10	594	#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	595	#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	596	#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	597	#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	598	#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	599	#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	600	#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	601	#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	602
vcoubard	551:ab7a8de3ff10	603	/* Bits 7..4 : Configuration field for RAM block 1. */
vcoubard	551:ab7a8de3ff10	604	#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /!< Position of RAM1 field. /
vcoubard	551:ab7a8de3ff10	605	#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /!< Bit mask of RAM1 field. /
vcoubard	551:ab7a8de3ff10	606	#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	607	#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	608	#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	609	#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	610	#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	611	#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	612	#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	613	#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	614
vcoubard	551:ab7a8de3ff10	615	/* Bits 3..0 : Configuration field for RAM block 0. */
vcoubard	551:ab7a8de3ff10	616	#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /!< Position of RAM0 field. /
vcoubard	551:ab7a8de3ff10	617	#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /!< Bit mask of RAM0 field. /
vcoubard	551:ab7a8de3ff10	618	#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	619	#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	620	#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	621	#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	622	#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	623	#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	624	#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	625	#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	626
vcoubard	551:ab7a8de3ff10	627	/* Register: AMLI_RAMPRI_CCM */
vcoubard	551:ab7a8de3ff10	628	/* Description: Configurable priority configuration register for CCM. */
vcoubard	551:ab7a8de3ff10	629
vcoubard	551:ab7a8de3ff10	630	/* Bits 31..28 : Configuration field for RAM block 7. */
vcoubard	551:ab7a8de3ff10	631	#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /!< Position of RAM7 field. /
vcoubard	551:ab7a8de3ff10	632	#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /!< Bit mask of RAM7 field. /
vcoubard	551:ab7a8de3ff10	633	#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	634	#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	635	#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	636	#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	637	#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	638	#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	639	#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	640	#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	641
vcoubard	551:ab7a8de3ff10	642	/* Bits 27..24 : Configuration field for RAM block 6. */
vcoubard	551:ab7a8de3ff10	643	#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /!< Position of RAM6 field. /
vcoubard	551:ab7a8de3ff10	644	#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /!< Bit mask of RAM6 field. /
vcoubard	551:ab7a8de3ff10	645	#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	646	#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	647	#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	648	#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	649	#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	650	#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	651	#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	652	#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	653
vcoubard	551:ab7a8de3ff10	654	/* Bits 23..20 : Configuration field for RAM block 5. */
vcoubard	551:ab7a8de3ff10	655	#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /!< Position of RAM5 field. /
vcoubard	551:ab7a8de3ff10	656	#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /!< Bit mask of RAM5 field. /
vcoubard	551:ab7a8de3ff10	657	#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	658	#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	659	#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	660	#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	661	#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	662	#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	663	#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	664	#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	665
vcoubard	551:ab7a8de3ff10	666	/* Bits 19..16 : Configuration field for RAM block 4. */
vcoubard	551:ab7a8de3ff10	667	#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /!< Position of RAM4 field. /
vcoubard	551:ab7a8de3ff10	668	#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /!< Bit mask of RAM4 field. /
vcoubard	551:ab7a8de3ff10	669	#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	670	#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	671	#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	672	#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	673	#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	674	#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	675	#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	676	#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	677
vcoubard	551:ab7a8de3ff10	678	/* Bits 15..12 : Configuration field for RAM block 3. */
vcoubard	551:ab7a8de3ff10	679	#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /!< Position of RAM3 field. /
vcoubard	551:ab7a8de3ff10	680	#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /!< Bit mask of RAM3 field. /
vcoubard	551:ab7a8de3ff10	681	#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	682	#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	683	#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	684	#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	685	#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	686	#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	687	#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	688	#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	689
vcoubard	551:ab7a8de3ff10	690	/* Bits 11..8 : Configuration field for RAM block 2. */
vcoubard	551:ab7a8de3ff10	691	#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /!< Position of RAM2 field. /
vcoubard	551:ab7a8de3ff10	692	#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /!< Bit mask of RAM2 field. /
vcoubard	551:ab7a8de3ff10	693	#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	694	#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	695	#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	696	#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	697	#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	698	#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	699	#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	700	#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	701
vcoubard	551:ab7a8de3ff10	702	/* Bits 7..4 : Configuration field for RAM block 1. */
vcoubard	551:ab7a8de3ff10	703	#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /!< Position of RAM1 field. /
vcoubard	551:ab7a8de3ff10	704	#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /!< Bit mask of RAM1 field. /
vcoubard	551:ab7a8de3ff10	705	#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	706	#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	707	#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	708	#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	709	#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	710	#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	711	#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	712	#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	713
vcoubard	551:ab7a8de3ff10	714	/* Bits 3..0 : Configuration field for RAM block 0. */
vcoubard	551:ab7a8de3ff10	715	#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /!< Position of RAM0 field. /
vcoubard	551:ab7a8de3ff10	716	#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /!< Bit mask of RAM0 field. /
vcoubard	551:ab7a8de3ff10	717	#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	718	#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	719	#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	720	#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	721	#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	722	#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	723	#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	724	#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	725
vcoubard	551:ab7a8de3ff10	726	/* Register: AMLI_RAMPRI_AAR */
vcoubard	551:ab7a8de3ff10	727	/* Description: Configurable priority configuration register for AAR. */
vcoubard	551:ab7a8de3ff10	728
vcoubard	551:ab7a8de3ff10	729	/* Bits 31..28 : Configuration field for RAM block 7. */
vcoubard	551:ab7a8de3ff10	730	#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /!< Position of RAM7 field. /
vcoubard	551:ab7a8de3ff10	731	#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /!< Bit mask of RAM7 field. /
vcoubard	551:ab7a8de3ff10	732	#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	733	#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	734	#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	735	#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	736	#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	737	#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	738	#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	739	#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	740
vcoubard	551:ab7a8de3ff10	741	/* Bits 27..24 : Configuration field for RAM block 6. */
vcoubard	551:ab7a8de3ff10	742	#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /!< Position of RAM6 field. /
vcoubard	551:ab7a8de3ff10	743	#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /!< Bit mask of RAM6 field. /
vcoubard	551:ab7a8de3ff10	744	#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	745	#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	746	#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	747	#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	748	#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	749	#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	750	#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	751	#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	752
vcoubard	551:ab7a8de3ff10	753	/* Bits 23..20 : Configuration field for RAM block 5. */
vcoubard	551:ab7a8de3ff10	754	#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /!< Position of RAM5 field. /
vcoubard	551:ab7a8de3ff10	755	#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /!< Bit mask of RAM5 field. /
vcoubard	551:ab7a8de3ff10	756	#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	757	#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	758	#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	759	#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	760	#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	761	#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	762	#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	763	#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	764
vcoubard	551:ab7a8de3ff10	765	/* Bits 19..16 : Configuration field for RAM block 4. */
vcoubard	551:ab7a8de3ff10	766	#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /!< Position of RAM4 field. /
vcoubard	551:ab7a8de3ff10	767	#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /!< Bit mask of RAM4 field. /
vcoubard	551:ab7a8de3ff10	768	#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	769	#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	770	#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	771	#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	772	#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	773	#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	774	#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	775	#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	776
vcoubard	551:ab7a8de3ff10	777	/* Bits 15..12 : Configuration field for RAM block 3. */
vcoubard	551:ab7a8de3ff10	778	#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /!< Position of RAM3 field. /
vcoubard	551:ab7a8de3ff10	779	#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /!< Bit mask of RAM3 field. /
vcoubard	551:ab7a8de3ff10	780	#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	781	#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	782	#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	783	#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	784	#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	785	#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	786	#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	787	#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	788
vcoubard	551:ab7a8de3ff10	789	/* Bits 11..8 : Configuration field for RAM block 2. */
vcoubard	551:ab7a8de3ff10	790	#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /!< Position of RAM2 field. /
vcoubard	551:ab7a8de3ff10	791	#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /!< Bit mask of RAM2 field. /
vcoubard	551:ab7a8de3ff10	792	#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	793	#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	794	#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	795	#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	796	#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	797	#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	798	#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	799	#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	800
vcoubard	551:ab7a8de3ff10	801	/* Bits 7..4 : Configuration field for RAM block 1. */
vcoubard	551:ab7a8de3ff10	802	#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /!< Position of RAM1 field. /
vcoubard	551:ab7a8de3ff10	803	#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /!< Bit mask of RAM1 field. /
vcoubard	551:ab7a8de3ff10	804	#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	805	#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	806	#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	807	#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	808	#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	809	#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	810	#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	811	#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	812
vcoubard	551:ab7a8de3ff10	813	/* Bits 3..0 : Configuration field for RAM block 0. */
vcoubard	551:ab7a8de3ff10	814	#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /!< Position of RAM0 field. /
vcoubard	551:ab7a8de3ff10	815	#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /!< Bit mask of RAM0 field. /
vcoubard	551:ab7a8de3ff10	816	#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /!< Priority 0. /
vcoubard	551:ab7a8de3ff10	817	#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /!< Priority 2. /
vcoubard	551:ab7a8de3ff10	818	#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /!< Priority 4. /
vcoubard	551:ab7a8de3ff10	819	#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /!< Priority 6. /
vcoubard	551:ab7a8de3ff10	820	#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /!< Priority 8. /
vcoubard	551:ab7a8de3ff10	821	#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /!< Priority 10. /
vcoubard	551:ab7a8de3ff10	822	#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /!< Priority 12. /
vcoubard	551:ab7a8de3ff10	823	#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /!< Priority 14. /
vcoubard	551:ab7a8de3ff10	824
vcoubard	551:ab7a8de3ff10	825	/* Peripheral: CCM */
vcoubard	551:ab7a8de3ff10	826	/* Description: AES CCM Mode Encryption. */
vcoubard	551:ab7a8de3ff10	827
vcoubard	551:ab7a8de3ff10	828	/* Register: CCM_SHORTS */
vcoubard	551:ab7a8de3ff10	829	/* Description: Shortcuts for the CCM. */
vcoubard	551:ab7a8de3ff10	830
vcoubard	551:ab7a8de3ff10	831	/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
vcoubard	551:ab7a8de3ff10	832	#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /!< Position of ENDKSGEN_CRYPT field. /
vcoubard	551:ab7a8de3ff10	833	#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /!< Bit mask of ENDKSGEN_CRYPT field. /
vcoubard	551:ab7a8de3ff10	834	#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	835	#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	836
vcoubard	551:ab7a8de3ff10	837	/* Register: CCM_INTENSET */
vcoubard	551:ab7a8de3ff10	838	/* Description: Interrupt enable set register. */
vcoubard	551:ab7a8de3ff10	839
vcoubard	551:ab7a8de3ff10	840	/* Bit 2 : Enable interrupt on ERROR event. */
vcoubard	551:ab7a8de3ff10	841	#define CCM_INTENSET_ERROR_Pos (2UL) /!< Position of ERROR field. /
vcoubard	551:ab7a8de3ff10	842	#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
vcoubard	551:ab7a8de3ff10	843	#define CCM_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	844	#define CCM_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	845	#define CCM_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	846
vcoubard	551:ab7a8de3ff10	847	/* Bit 1 : Enable interrupt on ENDCRYPT event. */
vcoubard	551:ab7a8de3ff10	848	#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
vcoubard	551:ab7a8de3ff10	849	#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
vcoubard	551:ab7a8de3ff10	850	#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	851	#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	852	#define CCM_INTENSET_ENDCRYPT_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	853
vcoubard	551:ab7a8de3ff10	854	/* Bit 0 : Enable interrupt on ENDKSGEN event. */
vcoubard	551:ab7a8de3ff10	855	#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
vcoubard	551:ab7a8de3ff10	856	#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
vcoubard	551:ab7a8de3ff10	857	#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	858	#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	859	#define CCM_INTENSET_ENDKSGEN_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	860
vcoubard	551:ab7a8de3ff10	861	/* Register: CCM_INTENCLR */
vcoubard	551:ab7a8de3ff10	862	/* Description: Interrupt enable clear register. */
vcoubard	551:ab7a8de3ff10	863
vcoubard	551:ab7a8de3ff10	864	/* Bit 2 : Disable interrupt on ERROR event. */
vcoubard	551:ab7a8de3ff10	865	#define CCM_INTENCLR_ERROR_Pos (2UL) /!< Position of ERROR field. /
vcoubard	551:ab7a8de3ff10	866	#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
vcoubard	551:ab7a8de3ff10	867	#define CCM_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	868	#define CCM_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	869	#define CCM_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	870
vcoubard	551:ab7a8de3ff10	871	/* Bit 1 : Disable interrupt on ENDCRYPT event. */
vcoubard	551:ab7a8de3ff10	872	#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
vcoubard	551:ab7a8de3ff10	873	#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
vcoubard	551:ab7a8de3ff10	874	#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	875	#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	876	#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	877
vcoubard	551:ab7a8de3ff10	878	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
vcoubard	551:ab7a8de3ff10	879	#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
vcoubard	551:ab7a8de3ff10	880	#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
vcoubard	551:ab7a8de3ff10	881	#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	882	#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	883	#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	884
vcoubard	551:ab7a8de3ff10	885	/* Register: CCM_MICSTATUS */
vcoubard	551:ab7a8de3ff10	886	/* Description: CCM RX MIC check result. */
vcoubard	551:ab7a8de3ff10	887
vcoubard	551:ab7a8de3ff10	888	/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
vcoubard	551:ab7a8de3ff10	889	#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /!< Position of MICSTATUS field. /
vcoubard	551:ab7a8de3ff10	890	#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /!< Bit mask of MICSTATUS field. /
vcoubard	551:ab7a8de3ff10	891	#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /!< MIC check failed. /
vcoubard	551:ab7a8de3ff10	892	#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /!< MIC check passed. /
vcoubard	551:ab7a8de3ff10	893
vcoubard	551:ab7a8de3ff10	894	/* Register: CCM_ENABLE */
vcoubard	551:ab7a8de3ff10	895	/* Description: CCM enable. */
vcoubard	551:ab7a8de3ff10	896
vcoubard	551:ab7a8de3ff10	897	/* Bits 1..0 : CCM enable. */
vcoubard	551:ab7a8de3ff10	898	#define CCM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	551:ab7a8de3ff10	899	#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	551:ab7a8de3ff10	900	#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /!< CCM is disabled. /
vcoubard	551:ab7a8de3ff10	901	#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /!< CCM is enabled. /
vcoubard	551:ab7a8de3ff10	902
vcoubard	551:ab7a8de3ff10	903	/* Register: CCM_MODE */
vcoubard	551:ab7a8de3ff10	904	/* Description: Operation mode. */
vcoubard	551:ab7a8de3ff10	905
vcoubard	551:ab7a8de3ff10	906	/* Bit 0 : CCM mode operation. */
vcoubard	551:ab7a8de3ff10	907	#define CCM_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
vcoubard	551:ab7a8de3ff10	908	#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /!< Bit mask of MODE field. /
vcoubard	551:ab7a8de3ff10	909	#define CCM_MODE_MODE_Encryption (0UL) /!< CCM mode TX /
vcoubard	551:ab7a8de3ff10	910	#define CCM_MODE_MODE_Decryption (1UL) /!< CCM mode TX /
vcoubard	551:ab7a8de3ff10	911
vcoubard	551:ab7a8de3ff10	912	/* Register: CCM_POWER */
vcoubard	551:ab7a8de3ff10	913	/* Description: Peripheral power control. */
vcoubard	551:ab7a8de3ff10	914
vcoubard	551:ab7a8de3ff10	915	/* Bit 0 : Peripheral power control. */
vcoubard	551:ab7a8de3ff10	916	#define CCM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	551:ab7a8de3ff10	917	#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	551:ab7a8de3ff10	918	#define CCM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	551:ab7a8de3ff10	919	#define CCM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	551:ab7a8de3ff10	920
vcoubard	551:ab7a8de3ff10	921
vcoubard	551:ab7a8de3ff10	922	/* Peripheral: CLOCK */
vcoubard	551:ab7a8de3ff10	923	/* Description: Clock control. */
vcoubard	551:ab7a8de3ff10	924
vcoubard	551:ab7a8de3ff10	925	/* Register: CLOCK_INTENSET */
vcoubard	551:ab7a8de3ff10	926	/* Description: Interrupt enable set register. */
vcoubard	551:ab7a8de3ff10	927
vcoubard	551:ab7a8de3ff10	928	/* Bit 4 : Enable interrupt on CTTO event. */
vcoubard	551:ab7a8de3ff10	929	#define CLOCK_INTENSET_CTTO_Pos (4UL) /!< Position of CTTO field. /
vcoubard	551:ab7a8de3ff10	930	#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /!< Bit mask of CTTO field. /
vcoubard	551:ab7a8de3ff10	931	#define CLOCK_INTENSET_CTTO_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	932	#define CLOCK_INTENSET_CTTO_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	933	#define CLOCK_INTENSET_CTTO_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	934
vcoubard	551:ab7a8de3ff10	935	/* Bit 3 : Enable interrupt on DONE event. */
vcoubard	551:ab7a8de3ff10	936	#define CLOCK_INTENSET_DONE_Pos (3UL) /!< Position of DONE field. /
vcoubard	551:ab7a8de3ff10	937	#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /!< Bit mask of DONE field. /
vcoubard	551:ab7a8de3ff10	938	#define CLOCK_INTENSET_DONE_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	939	#define CLOCK_INTENSET_DONE_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	940	#define CLOCK_INTENSET_DONE_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	941
vcoubard	551:ab7a8de3ff10	942	/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
vcoubard	551:ab7a8de3ff10	943	#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
vcoubard	551:ab7a8de3ff10	944	#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
vcoubard	551:ab7a8de3ff10	945	#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	946	#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	947	#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	948
vcoubard	551:ab7a8de3ff10	949	/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
vcoubard	551:ab7a8de3ff10	950	#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
vcoubard	551:ab7a8de3ff10	951	#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
vcoubard	551:ab7a8de3ff10	952	#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	953	#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	954	#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	955
vcoubard	551:ab7a8de3ff10	956	/* Register: CLOCK_INTENCLR */
vcoubard	551:ab7a8de3ff10	957	/* Description: Interrupt enable clear register. */
vcoubard	551:ab7a8de3ff10	958
vcoubard	551:ab7a8de3ff10	959	/* Bit 4 : Disable interrupt on CTTO event. */
vcoubard	551:ab7a8de3ff10	960	#define CLOCK_INTENCLR_CTTO_Pos (4UL) /!< Position of CTTO field. /
vcoubard	551:ab7a8de3ff10	961	#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /!< Bit mask of CTTO field. /
vcoubard	551:ab7a8de3ff10	962	#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	963	#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	964	#define CLOCK_INTENCLR_CTTO_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	965
vcoubard	551:ab7a8de3ff10	966	/* Bit 3 : Disable interrupt on DONE event. */
vcoubard	551:ab7a8de3ff10	967	#define CLOCK_INTENCLR_DONE_Pos (3UL) /!< Position of DONE field. /
vcoubard	551:ab7a8de3ff10	968	#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /!< Bit mask of DONE field. /
vcoubard	551:ab7a8de3ff10	969	#define CLOCK_INTENCLR_DONE_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	970	#define CLOCK_INTENCLR_DONE_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	971	#define CLOCK_INTENCLR_DONE_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	972
vcoubard	551:ab7a8de3ff10	973	/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
vcoubard	551:ab7a8de3ff10	974	#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
vcoubard	551:ab7a8de3ff10	975	#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
vcoubard	551:ab7a8de3ff10	976	#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	977	#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	978	#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	979
vcoubard	551:ab7a8de3ff10	980	/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
vcoubard	551:ab7a8de3ff10	981	#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
vcoubard	551:ab7a8de3ff10	982	#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
vcoubard	551:ab7a8de3ff10	983	#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	984	#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	985	#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	986
vcoubard	551:ab7a8de3ff10	987	/* Register: CLOCK_HFCLKRUN */
vcoubard	551:ab7a8de3ff10	988	/* Description: Task HFCLKSTART trigger status. */
vcoubard	551:ab7a8de3ff10	989
vcoubard	551:ab7a8de3ff10	990	/* Bit 0 : Task HFCLKSTART trigger status. */
vcoubard	551:ab7a8de3ff10	991	#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
vcoubard	551:ab7a8de3ff10	992	#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
vcoubard	551:ab7a8de3ff10	993	#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /!< Task HFCLKSTART has not been triggered. /
vcoubard	551:ab7a8de3ff10	994	#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /!< Task HFCLKSTART has been triggered. /
vcoubard	551:ab7a8de3ff10	995
vcoubard	551:ab7a8de3ff10	996	/* Register: CLOCK_HFCLKSTAT */
vcoubard	551:ab7a8de3ff10	997	/* Description: High frequency clock status. */
vcoubard	551:ab7a8de3ff10	998
vcoubard	551:ab7a8de3ff10	999	/* Bit 16 : State for the HFCLK. */
vcoubard	551:ab7a8de3ff10	1000	#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
vcoubard	551:ab7a8de3ff10	1001	#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
vcoubard	551:ab7a8de3ff10	1002	#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /!< HFCLK clock not running. /
vcoubard	551:ab7a8de3ff10	1003	#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /!< HFCLK clock running. /
vcoubard	551:ab7a8de3ff10	1004
vcoubard	551:ab7a8de3ff10	1005	/* Bit 0 : Active clock source for the HF clock. */
vcoubard	551:ab7a8de3ff10	1006	#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
vcoubard	551:ab7a8de3ff10	1007	#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
vcoubard	551:ab7a8de3ff10	1008	#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /!< Internal 16MHz RC oscillator running and generating the HFCLK clock. /
vcoubard	551:ab7a8de3ff10	1009	#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. /
vcoubard	551:ab7a8de3ff10	1010
vcoubard	551:ab7a8de3ff10	1011	/* Register: CLOCK_LFCLKRUN */
vcoubard	551:ab7a8de3ff10	1012	/* Description: Task LFCLKSTART triggered status. */
vcoubard	551:ab7a8de3ff10	1013
vcoubard	551:ab7a8de3ff10	1014	/* Bit 0 : Task LFCLKSTART triggered status. */
vcoubard	551:ab7a8de3ff10	1015	#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
vcoubard	551:ab7a8de3ff10	1016	#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
vcoubard	551:ab7a8de3ff10	1017	#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /!< Task LFCLKSTART has not been triggered. /
vcoubard	551:ab7a8de3ff10	1018	#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /!< Task LFCLKSTART has been triggered. /
vcoubard	551:ab7a8de3ff10	1019
vcoubard	551:ab7a8de3ff10	1020	/* Register: CLOCK_LFCLKSTAT */
vcoubard	551:ab7a8de3ff10	1021	/* Description: Low frequency clock status. */
vcoubard	551:ab7a8de3ff10	1022
vcoubard	551:ab7a8de3ff10	1023	/* Bit 16 : State for the LF clock. */
vcoubard	551:ab7a8de3ff10	1024	#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
vcoubard	551:ab7a8de3ff10	1025	#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
vcoubard	551:ab7a8de3ff10	1026	#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /!< LFCLK clock not running. /
vcoubard	551:ab7a8de3ff10	1027	#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /!< LFCLK clock running. /
vcoubard	551:ab7a8de3ff10	1028
vcoubard	551:ab7a8de3ff10	1029	/* Bits 1..0 : Active clock source for the LF clock. */
vcoubard	551:ab7a8de3ff10	1030	#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
vcoubard	551:ab7a8de3ff10	1031	#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
vcoubard	551:ab7a8de3ff10	1032	#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. /
vcoubard	551:ab7a8de3ff10	1033	#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /!< External 32KiHz crystal oscillator running and generating the LFCLK clock. /
vcoubard	551:ab7a8de3ff10	1034	#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. /
vcoubard	551:ab7a8de3ff10	1035
vcoubard	551:ab7a8de3ff10	1036	/* Register: CLOCK_LFCLKSRCCOPY */
vcoubard	551:ab7a8de3ff10	1037	/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
vcoubard	551:ab7a8de3ff10	1038
vcoubard	551:ab7a8de3ff10	1039	/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
vcoubard	551:ab7a8de3ff10	1040	#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /!< Position of SRC field. /
vcoubard	551:ab7a8de3ff10	1041	#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /!< Bit mask of SRC field. /
vcoubard	551:ab7a8de3ff10	1042	#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
vcoubard	551:ab7a8de3ff10	1043	#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
vcoubard	551:ab7a8de3ff10	1044	#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
vcoubard	551:ab7a8de3ff10	1045
vcoubard	551:ab7a8de3ff10	1046	/* Register: CLOCK_LFCLKSRC */
vcoubard	551:ab7a8de3ff10	1047	/* Description: Clock source for the LFCLK clock. */
vcoubard	551:ab7a8de3ff10	1048
vcoubard	551:ab7a8de3ff10	1049	/* Bits 1..0 : Clock source. */
vcoubard	551:ab7a8de3ff10	1050	#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /!< Position of SRC field. /
vcoubard	551:ab7a8de3ff10	1051	#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /!< Bit mask of SRC field. /
vcoubard	551:ab7a8de3ff10	1052	#define CLOCK_LFCLKSRC_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
vcoubard	551:ab7a8de3ff10	1053	#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
vcoubard	551:ab7a8de3ff10	1054	#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
vcoubard	551:ab7a8de3ff10	1055
vcoubard	551:ab7a8de3ff10	1056	/* Register: CLOCK_CTIV */
vcoubard	551:ab7a8de3ff10	1057	/* Description: Calibration timer interval. */
vcoubard	551:ab7a8de3ff10	1058
vcoubard	551:ab7a8de3ff10	1059	/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
vcoubard	551:ab7a8de3ff10	1060	#define CLOCK_CTIV_CTIV_Pos (0UL) /!< Position of CTIV field. /
vcoubard	551:ab7a8de3ff10	1061	#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /!< Bit mask of CTIV field. /
vcoubard	551:ab7a8de3ff10	1062
vcoubard	551:ab7a8de3ff10	1063	/* Register: CLOCK_XTALFREQ */
vcoubard	551:ab7a8de3ff10	1064	/* Description: Crystal frequency. */
vcoubard	551:ab7a8de3ff10	1065
vcoubard	551:ab7a8de3ff10	1066	/* Bits 7..0 : External Xtal frequency selection. */
vcoubard	551:ab7a8de3ff10	1067	#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
vcoubard	551:ab7a8de3ff10	1068	#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
vcoubard	551:ab7a8de3ff10	1069	#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz xtal is used as source for the HFCLK oscillator. /
vcoubard	551:ab7a8de3ff10	1070	#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz xtal is used as source for the HFCLK oscillator. /
vcoubard	551:ab7a8de3ff10	1071
vcoubard	551:ab7a8de3ff10	1072
vcoubard	551:ab7a8de3ff10	1073	/* Peripheral: ECB */
vcoubard	551:ab7a8de3ff10	1074	/* Description: AES ECB Mode Encryption. */
vcoubard	551:ab7a8de3ff10	1075
vcoubard	551:ab7a8de3ff10	1076	/* Register: ECB_INTENSET */
vcoubard	551:ab7a8de3ff10	1077	/* Description: Interrupt enable set register. */
vcoubard	551:ab7a8de3ff10	1078
vcoubard	551:ab7a8de3ff10	1079	/* Bit 1 : Enable interrupt on ERRORECB event. */
vcoubard	551:ab7a8de3ff10	1080	#define ECB_INTENSET_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
vcoubard	551:ab7a8de3ff10	1081	#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
vcoubard	551:ab7a8de3ff10	1082	#define ECB_INTENSET_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	1083	#define ECB_INTENSET_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	1084	#define ECB_INTENSET_ERRORECB_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	1085
vcoubard	551:ab7a8de3ff10	1086	/* Bit 0 : Enable interrupt on ENDECB event. */
vcoubard	551:ab7a8de3ff10	1087	#define ECB_INTENSET_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
vcoubard	551:ab7a8de3ff10	1088	#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /!< Bit mask of ENDECB field. /
vcoubard	551:ab7a8de3ff10	1089	#define ECB_INTENSET_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	1090	#define ECB_INTENSET_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	1091	#define ECB_INTENSET_ENDECB_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	1092
vcoubard	551:ab7a8de3ff10	1093	/* Register: ECB_INTENCLR */
vcoubard	551:ab7a8de3ff10	1094	/* Description: Interrupt enable clear register. */
vcoubard	551:ab7a8de3ff10	1095
vcoubard	551:ab7a8de3ff10	1096	/* Bit 1 : Disable interrupt on ERRORECB event. */
vcoubard	551:ab7a8de3ff10	1097	#define ECB_INTENCLR_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
vcoubard	551:ab7a8de3ff10	1098	#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
vcoubard	551:ab7a8de3ff10	1099	#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	1100	#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	1101	#define ECB_INTENCLR_ERRORECB_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	1102
vcoubard	551:ab7a8de3ff10	1103	/* Bit 0 : Disable interrupt on ENDECB event. */
vcoubard	551:ab7a8de3ff10	1104	#define ECB_INTENCLR_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
vcoubard	551:ab7a8de3ff10	1105	#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /!< Bit mask of ENDECB field. /
vcoubard	551:ab7a8de3ff10	1106	#define ECB_INTENCLR_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	1107	#define ECB_INTENCLR_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	1108	#define ECB_INTENCLR_ENDECB_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	1109
vcoubard	551:ab7a8de3ff10	1110	/* Register: ECB_POWER */
vcoubard	551:ab7a8de3ff10	1111	/* Description: Peripheral power control. */
vcoubard	551:ab7a8de3ff10	1112
vcoubard	551:ab7a8de3ff10	1113	/* Bit 0 : Peripheral power control. */
vcoubard	551:ab7a8de3ff10	1114	#define ECB_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	551:ab7a8de3ff10	1115	#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	551:ab7a8de3ff10	1116	#define ECB_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	551:ab7a8de3ff10	1117	#define ECB_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	551:ab7a8de3ff10	1118
vcoubard	551:ab7a8de3ff10	1119
vcoubard	551:ab7a8de3ff10	1120	/* Peripheral: FICR */
vcoubard	551:ab7a8de3ff10	1121	/* Description: Factory Information Configuration. */
vcoubard	551:ab7a8de3ff10	1122
vcoubard	551:ab7a8de3ff10	1123	/* Register: FICR_PPFC */
vcoubard	551:ab7a8de3ff10	1124	/* Description: Pre-programmed factory code present. */
vcoubard	551:ab7a8de3ff10	1125
vcoubard	551:ab7a8de3ff10	1126	/* Bits 7..0 : Pre-programmed factory code present. */
vcoubard	551:ab7a8de3ff10	1127	#define FICR_PPFC_PPFC_Pos (0UL) /!< Position of PPFC field. /
vcoubard	551:ab7a8de3ff10	1128	#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /!< Bit mask of PPFC field. /
vcoubard	551:ab7a8de3ff10	1129	#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /!< Not present. /
vcoubard	551:ab7a8de3ff10	1130	#define FICR_PPFC_PPFC_Present (0x00UL) /!< Present. /
vcoubard	551:ab7a8de3ff10	1131
vcoubard	551:ab7a8de3ff10	1132	/* Register: FICR_CONFIGID */
vcoubard	551:ab7a8de3ff10	1133	/* Description: Configuration identifier. */
vcoubard	551:ab7a8de3ff10	1134
vcoubard	551:ab7a8de3ff10	1135	/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
vcoubard	551:ab7a8de3ff10	1136	#define FICR_CONFIGID_FWID_Pos (16UL) /!< Position of FWID field. /
vcoubard	551:ab7a8de3ff10	1137	#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /!< Bit mask of FWID field. /
vcoubard	551:ab7a8de3ff10	1138
vcoubard	551:ab7a8de3ff10	1139	/* Bits 15..0 : Hardware Identification Number. */
vcoubard	551:ab7a8de3ff10	1140	#define FICR_CONFIGID_HWID_Pos (0UL) /!< Position of HWID field. /
vcoubard	551:ab7a8de3ff10	1141	#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /!< Bit mask of HWID field. /
vcoubard	551:ab7a8de3ff10	1142
vcoubard	551:ab7a8de3ff10	1143	/* Register: FICR_DEVICEADDRTYPE */
vcoubard	551:ab7a8de3ff10	1144	/* Description: Device address type. */
vcoubard	551:ab7a8de3ff10	1145
vcoubard	551:ab7a8de3ff10	1146	/* Bit 0 : Device address type. */
vcoubard	551:ab7a8de3ff10	1147	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /!< Position of DEVICEADDRTYPE field. /
vcoubard	551:ab7a8de3ff10	1148	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /!< Bit mask of DEVICEADDRTYPE field. /
vcoubard	551:ab7a8de3ff10	1149	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /!< Public address. /
vcoubard	551:ab7a8de3ff10	1150	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /!< Random address. /
vcoubard	551:ab7a8de3ff10	1151
vcoubard	551:ab7a8de3ff10	1152	/* Register: FICR_OVERRIDEEN */
vcoubard	551:ab7a8de3ff10	1153	/* Description: Radio calibration override enable. */
vcoubard	551:ab7a8de3ff10	1154
vcoubard	551:ab7a8de3ff10	1155	/* Bit 3 : Override default values for BLE_1Mbit mode. */
vcoubard	551:ab7a8de3ff10	1156	#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /!< Position of BLE_1MBIT field. /
vcoubard	551:ab7a8de3ff10	1157	#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /!< Bit mask of BLE_1MBIT field. /
vcoubard	551:ab7a8de3ff10	1158	#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /!< Override the default values for BLE_1Mbit mode. /
vcoubard	551:ab7a8de3ff10	1159	#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /!< Do not override the default values for BLE_1Mbit mode. /
vcoubard	551:ab7a8de3ff10	1160
vcoubard	551:ab7a8de3ff10	1161	/* Bit 0 : Override default values for NRF_1Mbit mode. */
vcoubard	551:ab7a8de3ff10	1162	#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /!< Position of NRF_1MBIT field. /
vcoubard	551:ab7a8de3ff10	1163	#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /!< Bit mask of NRF_1MBIT field. /
vcoubard	551:ab7a8de3ff10	1164	#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /!< Override the default values for NRF_1Mbit mode. /
vcoubard	551:ab7a8de3ff10	1165	#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /!< Do not override the default values for NRF_1Mbit mode. /
vcoubard	551:ab7a8de3ff10	1166
vcoubard	551:ab7a8de3ff10	1167	/* Register: FICR_INFO_PART */
vcoubard	551:ab7a8de3ff10	1168	/* Description: Part code */
vcoubard	551:ab7a8de3ff10	1169
vcoubard	551:ab7a8de3ff10	1170	/* Bits 31..0 : Part code */
vcoubard	551:ab7a8de3ff10	1171	#define FICR_INFO_PART_PART_Pos (0UL) /!< Position of PART field. /
vcoubard	551:ab7a8de3ff10	1172	#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /!< Bit mask of PART field. /
vcoubard	551:ab7a8de3ff10	1173	#define FICR_INFO_PART_PART_N51822 (0x51822UL) /!< nRF51822 /
vcoubard	551:ab7a8de3ff10	1174	#define FICR_INFO_PART_PART_N51422 (0x51422UL) /!< nRF51422 /
vcoubard	551:ab7a8de3ff10	1175	#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
vcoubard	551:ab7a8de3ff10	1176
vcoubard	551:ab7a8de3ff10	1177	/* Register: FICR_INFO_VARIANT */
vcoubard	551:ab7a8de3ff10	1178	/* Description: Part variant */
vcoubard	551:ab7a8de3ff10	1179
vcoubard	551:ab7a8de3ff10	1180	/* Bits 31..0 : Part variant */
vcoubard	551:ab7a8de3ff10	1181	#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /!< Position of VARIANT field. /
vcoubard	551:ab7a8de3ff10	1182	#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /!< Bit mask of VARIANT field. /
vcoubard	551:ab7a8de3ff10	1183	#define FICR_INFO_VARIANT_VARIANT_nRF51C (0x1002UL) /!< nRF51-C (XLR3) /
vcoubard	551:ab7a8de3ff10	1184	#define FICR_INFO_VARIANT_VARIANT_nRF51D (0x1003UL) /!< nRF51-D (L3) /
vcoubard	551:ab7a8de3ff10	1185	#define FICR_INFO_VARIANT_VARIANT_nRF51E (0x1004UL) /!< nRF51-E (XLR3P) /
vcoubard	551:ab7a8de3ff10	1186	#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
vcoubard	551:ab7a8de3ff10	1187
vcoubard	551:ab7a8de3ff10	1188	/* Register: FICR_INFO_PACKAGE */
vcoubard	551:ab7a8de3ff10	1189	/* Description: Package option */
vcoubard	551:ab7a8de3ff10	1190
vcoubard	551:ab7a8de3ff10	1191	/* Bits 31..0 : Package option */
vcoubard	551:ab7a8de3ff10	1192	#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /!< Position of PACKAGE field. /
vcoubard	551:ab7a8de3ff10	1193	#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /!< Bit mask of PACKAGE field. /
vcoubard	551:ab7a8de3ff10	1194	#define FICR_INFO_PACKAGE_PACKAGE_QFN48 (0x0000UL) /!< 48-pin QFN with 31 GPIO /
vcoubard	551:ab7a8de3ff10	1195	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP56A (0x1000UL) /!< nRF51x22 CDxx - WLCSP 56 balls /
vcoubard	551:ab7a8de3ff10	1196	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62A (0x1001UL) /!< nRF51x22 CExx - WLCSP 62 balls /
vcoubard	551:ab7a8de3ff10	1197	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62B (0x1002UL) /!< nRF51x22 CFxx - WLCSP 62 balls /
vcoubard	551:ab7a8de3ff10	1198	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62C (0x1003UL) /!< nRF51x22 CTxx - WLCSP 62 balls /
vcoubard	551:ab7a8de3ff10	1199	#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
vcoubard	551:ab7a8de3ff10	1200
vcoubard	551:ab7a8de3ff10	1201	/* Register: FICR_INFO_RAM */
vcoubard	551:ab7a8de3ff10	1202	/* Description: RAM variant */
vcoubard	551:ab7a8de3ff10	1203
vcoubard	551:ab7a8de3ff10	1204	/* Bits 31..0 : RAM variant */
vcoubard	551:ab7a8de3ff10	1205	#define FICR_INFO_RAM_RAM_Pos (0UL) /!< Position of RAM field. /
vcoubard	551:ab7a8de3ff10	1206	#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /!< Bit mask of RAM field. /
vcoubard	551:ab7a8de3ff10	1207	#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
vcoubard	551:ab7a8de3ff10	1208	#define FICR_INFO_RAM_RAM_K16 (16UL) /!< 16 kByte RAM. /
vcoubard	551:ab7a8de3ff10	1209	#define FICR_INFO_RAM_RAM_K32 (32UL) /!< 32 kByte RAM. /
vcoubard	551:ab7a8de3ff10	1210
vcoubard	551:ab7a8de3ff10	1211	/* Register: FICR_INFO_FLASH */
vcoubard	551:ab7a8de3ff10	1212	/* Description: Flash variant */
vcoubard	551:ab7a8de3ff10	1213
vcoubard	551:ab7a8de3ff10	1214	/* Bits 31..0 : Flash variant */
vcoubard	551:ab7a8de3ff10	1215	#define FICR_INFO_FLASH_FLASH_Pos (0UL) /!< Position of FLASH field. /
vcoubard	551:ab7a8de3ff10	1216	#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /!< Bit mask of FLASH field. /
vcoubard	551:ab7a8de3ff10	1217	#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
vcoubard	551:ab7a8de3ff10	1218	#define FICR_INFO_FLASH_FLASH_K128 (128UL) /!< 128 kByte FLASH. /
vcoubard	551:ab7a8de3ff10	1219	#define FICR_INFO_FLASH_FLASH_K256 (256UL) /!< 256 kByte FLASH. /
vcoubard	551:ab7a8de3ff10	1220
vcoubard	551:ab7a8de3ff10	1221
vcoubard	551:ab7a8de3ff10	1222	/* Peripheral: GPIO */
vcoubard	551:ab7a8de3ff10	1223	/* Description: General purpose input and output. */
vcoubard	551:ab7a8de3ff10	1224
vcoubard	551:ab7a8de3ff10	1225	/* Register: GPIO_OUT */
vcoubard	551:ab7a8de3ff10	1226	/* Description: Write GPIO port. */
vcoubard	551:ab7a8de3ff10	1227
vcoubard	551:ab7a8de3ff10	1228	/* Bit 31 : Pin 31. */
vcoubard	551:ab7a8de3ff10	1229	#define GPIO_OUT_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	551:ab7a8de3ff10	1230	#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	551:ab7a8de3ff10	1231	#define GPIO_OUT_PIN31_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1232	#define GPIO_OUT_PIN31_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1233
vcoubard	551:ab7a8de3ff10	1234	/* Bit 30 : Pin 30. */
vcoubard	551:ab7a8de3ff10	1235	#define GPIO_OUT_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	551:ab7a8de3ff10	1236	#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	551:ab7a8de3ff10	1237	#define GPIO_OUT_PIN30_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1238	#define GPIO_OUT_PIN30_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1239
vcoubard	551:ab7a8de3ff10	1240	/* Bit 29 : Pin 29. */
vcoubard	551:ab7a8de3ff10	1241	#define GPIO_OUT_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	551:ab7a8de3ff10	1242	#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	551:ab7a8de3ff10	1243	#define GPIO_OUT_PIN29_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1244	#define GPIO_OUT_PIN29_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1245
vcoubard	551:ab7a8de3ff10	1246	/* Bit 28 : Pin 28. */
vcoubard	551:ab7a8de3ff10	1247	#define GPIO_OUT_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	551:ab7a8de3ff10	1248	#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	551:ab7a8de3ff10	1249	#define GPIO_OUT_PIN28_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1250	#define GPIO_OUT_PIN28_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1251
vcoubard	551:ab7a8de3ff10	1252	/* Bit 27 : Pin 27. */
vcoubard	551:ab7a8de3ff10	1253	#define GPIO_OUT_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	551:ab7a8de3ff10	1254	#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	551:ab7a8de3ff10	1255	#define GPIO_OUT_PIN27_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1256	#define GPIO_OUT_PIN27_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1257
vcoubard	551:ab7a8de3ff10	1258	/* Bit 26 : Pin 26. */
vcoubard	551:ab7a8de3ff10	1259	#define GPIO_OUT_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	551:ab7a8de3ff10	1260	#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	551:ab7a8de3ff10	1261	#define GPIO_OUT_PIN26_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1262	#define GPIO_OUT_PIN26_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1263
vcoubard	551:ab7a8de3ff10	1264	/* Bit 25 : Pin 25. */
vcoubard	551:ab7a8de3ff10	1265	#define GPIO_OUT_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	551:ab7a8de3ff10	1266	#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	551:ab7a8de3ff10	1267	#define GPIO_OUT_PIN25_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1268	#define GPIO_OUT_PIN25_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1269
vcoubard	551:ab7a8de3ff10	1270	/* Bit 24 : Pin 24. */
vcoubard	551:ab7a8de3ff10	1271	#define GPIO_OUT_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	551:ab7a8de3ff10	1272	#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	551:ab7a8de3ff10	1273	#define GPIO_OUT_PIN24_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1274	#define GPIO_OUT_PIN24_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1275
vcoubard	551:ab7a8de3ff10	1276	/* Bit 23 : Pin 23. */
vcoubard	551:ab7a8de3ff10	1277	#define GPIO_OUT_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	551:ab7a8de3ff10	1278	#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	551:ab7a8de3ff10	1279	#define GPIO_OUT_PIN23_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1280	#define GPIO_OUT_PIN23_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1281
vcoubard	551:ab7a8de3ff10	1282	/* Bit 22 : Pin 22. */
vcoubard	551:ab7a8de3ff10	1283	#define GPIO_OUT_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	551:ab7a8de3ff10	1284	#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	551:ab7a8de3ff10	1285	#define GPIO_OUT_PIN22_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1286	#define GPIO_OUT_PIN22_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1287
vcoubard	551:ab7a8de3ff10	1288	/* Bit 21 : Pin 21. */
vcoubard	551:ab7a8de3ff10	1289	#define GPIO_OUT_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	551:ab7a8de3ff10	1290	#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	551:ab7a8de3ff10	1291	#define GPIO_OUT_PIN21_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1292	#define GPIO_OUT_PIN21_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1293
vcoubard	551:ab7a8de3ff10	1294	/* Bit 20 : Pin 20. */
vcoubard	551:ab7a8de3ff10	1295	#define GPIO_OUT_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	551:ab7a8de3ff10	1296	#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	551:ab7a8de3ff10	1297	#define GPIO_OUT_PIN20_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1298	#define GPIO_OUT_PIN20_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1299
vcoubard	551:ab7a8de3ff10	1300	/* Bit 19 : Pin 19. */
vcoubard	551:ab7a8de3ff10	1301	#define GPIO_OUT_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	551:ab7a8de3ff10	1302	#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	551:ab7a8de3ff10	1303	#define GPIO_OUT_PIN19_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1304	#define GPIO_OUT_PIN19_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1305
vcoubard	551:ab7a8de3ff10	1306	/* Bit 18 : Pin 18. */
vcoubard	551:ab7a8de3ff10	1307	#define GPIO_OUT_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	551:ab7a8de3ff10	1308	#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	551:ab7a8de3ff10	1309	#define GPIO_OUT_PIN18_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1310	#define GPIO_OUT_PIN18_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1311
vcoubard	551:ab7a8de3ff10	1312	/* Bit 17 : Pin 17. */
vcoubard	551:ab7a8de3ff10	1313	#define GPIO_OUT_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	551:ab7a8de3ff10	1314	#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	551:ab7a8de3ff10	1315	#define GPIO_OUT_PIN17_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1316	#define GPIO_OUT_PIN17_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1317
vcoubard	551:ab7a8de3ff10	1318	/* Bit 16 : Pin 16. */
vcoubard	551:ab7a8de3ff10	1319	#define GPIO_OUT_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	551:ab7a8de3ff10	1320	#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	551:ab7a8de3ff10	1321	#define GPIO_OUT_PIN16_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1322	#define GPIO_OUT_PIN16_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1323
vcoubard	551:ab7a8de3ff10	1324	/* Bit 15 : Pin 15. */
vcoubard	551:ab7a8de3ff10	1325	#define GPIO_OUT_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	551:ab7a8de3ff10	1326	#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	551:ab7a8de3ff10	1327	#define GPIO_OUT_PIN15_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1328	#define GPIO_OUT_PIN15_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1329
vcoubard	551:ab7a8de3ff10	1330	/* Bit 14 : Pin 14. */
vcoubard	551:ab7a8de3ff10	1331	#define GPIO_OUT_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	551:ab7a8de3ff10	1332	#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	551:ab7a8de3ff10	1333	#define GPIO_OUT_PIN14_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1334	#define GPIO_OUT_PIN14_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1335
vcoubard	551:ab7a8de3ff10	1336	/* Bit 13 : Pin 13. */
vcoubard	551:ab7a8de3ff10	1337	#define GPIO_OUT_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	551:ab7a8de3ff10	1338	#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	551:ab7a8de3ff10	1339	#define GPIO_OUT_PIN13_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1340	#define GPIO_OUT_PIN13_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1341
vcoubard	551:ab7a8de3ff10	1342	/* Bit 12 : Pin 12. */
vcoubard	551:ab7a8de3ff10	1343	#define GPIO_OUT_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	551:ab7a8de3ff10	1344	#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	551:ab7a8de3ff10	1345	#define GPIO_OUT_PIN12_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1346	#define GPIO_OUT_PIN12_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1347
vcoubard	551:ab7a8de3ff10	1348	/* Bit 11 : Pin 11. */
vcoubard	551:ab7a8de3ff10	1349	#define GPIO_OUT_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	551:ab7a8de3ff10	1350	#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	551:ab7a8de3ff10	1351	#define GPIO_OUT_PIN11_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1352	#define GPIO_OUT_PIN11_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1353
vcoubard	551:ab7a8de3ff10	1354	/* Bit 10 : Pin 10. */
vcoubard	551:ab7a8de3ff10	1355	#define GPIO_OUT_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	551:ab7a8de3ff10	1356	#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	551:ab7a8de3ff10	1357	#define GPIO_OUT_PIN10_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1358	#define GPIO_OUT_PIN10_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1359
vcoubard	551:ab7a8de3ff10	1360	/* Bit 9 : Pin 9. */
vcoubard	551:ab7a8de3ff10	1361	#define GPIO_OUT_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	551:ab7a8de3ff10	1362	#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	551:ab7a8de3ff10	1363	#define GPIO_OUT_PIN9_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1364	#define GPIO_OUT_PIN9_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1365
vcoubard	551:ab7a8de3ff10	1366	/* Bit 8 : Pin 8. */
vcoubard	551:ab7a8de3ff10	1367	#define GPIO_OUT_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	551:ab7a8de3ff10	1368	#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	551:ab7a8de3ff10	1369	#define GPIO_OUT_PIN8_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1370	#define GPIO_OUT_PIN8_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1371
vcoubard	551:ab7a8de3ff10	1372	/* Bit 7 : Pin 7. */
vcoubard	551:ab7a8de3ff10	1373	#define GPIO_OUT_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	551:ab7a8de3ff10	1374	#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	551:ab7a8de3ff10	1375	#define GPIO_OUT_PIN7_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1376	#define GPIO_OUT_PIN7_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1377
vcoubard	551:ab7a8de3ff10	1378	/* Bit 6 : Pin 6. */
vcoubard	551:ab7a8de3ff10	1379	#define GPIO_OUT_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	551:ab7a8de3ff10	1380	#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	551:ab7a8de3ff10	1381	#define GPIO_OUT_PIN6_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1382	#define GPIO_OUT_PIN6_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1383
vcoubard	551:ab7a8de3ff10	1384	/* Bit 5 : Pin 5. */
vcoubard	551:ab7a8de3ff10	1385	#define GPIO_OUT_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	551:ab7a8de3ff10	1386	#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	551:ab7a8de3ff10	1387	#define GPIO_OUT_PIN5_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1388	#define GPIO_OUT_PIN5_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1389
vcoubard	551:ab7a8de3ff10	1390	/* Bit 4 : Pin 4. */
vcoubard	551:ab7a8de3ff10	1391	#define GPIO_OUT_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	551:ab7a8de3ff10	1392	#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	551:ab7a8de3ff10	1393	#define GPIO_OUT_PIN4_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1394	#define GPIO_OUT_PIN4_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1395
vcoubard	551:ab7a8de3ff10	1396	/* Bit 3 : Pin 3. */
vcoubard	551:ab7a8de3ff10	1397	#define GPIO_OUT_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	551:ab7a8de3ff10	1398	#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	551:ab7a8de3ff10	1399	#define GPIO_OUT_PIN3_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1400	#define GPIO_OUT_PIN3_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1401
vcoubard	551:ab7a8de3ff10	1402	/* Bit 2 : Pin 2. */
vcoubard	551:ab7a8de3ff10	1403	#define GPIO_OUT_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	551:ab7a8de3ff10	1404	#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	551:ab7a8de3ff10	1405	#define GPIO_OUT_PIN2_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1406	#define GPIO_OUT_PIN2_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1407
vcoubard	551:ab7a8de3ff10	1408	/* Bit 1 : Pin 1. */
vcoubard	551:ab7a8de3ff10	1409	#define GPIO_OUT_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	551:ab7a8de3ff10	1410	#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	551:ab7a8de3ff10	1411	#define GPIO_OUT_PIN1_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1412	#define GPIO_OUT_PIN1_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1413
vcoubard	551:ab7a8de3ff10	1414	/* Bit 0 : Pin 0. */
vcoubard	551:ab7a8de3ff10	1415	#define GPIO_OUT_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	551:ab7a8de3ff10	1416	#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	551:ab7a8de3ff10	1417	#define GPIO_OUT_PIN0_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1418	#define GPIO_OUT_PIN0_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1419
vcoubard	551:ab7a8de3ff10	1420	/* Register: GPIO_OUTSET */
vcoubard	551:ab7a8de3ff10	1421	/* Description: Set individual bits in GPIO port. */
vcoubard	551:ab7a8de3ff10	1422
vcoubard	551:ab7a8de3ff10	1423	/* Bit 31 : Pin 31. */
vcoubard	551:ab7a8de3ff10	1424	#define GPIO_OUTSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	551:ab7a8de3ff10	1425	#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	551:ab7a8de3ff10	1426	#define GPIO_OUTSET_PIN31_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1427	#define GPIO_OUTSET_PIN31_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1428	#define GPIO_OUTSET_PIN31_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1429
vcoubard	551:ab7a8de3ff10	1430	/* Bit 30 : Pin 30. */
vcoubard	551:ab7a8de3ff10	1431	#define GPIO_OUTSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	551:ab7a8de3ff10	1432	#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	551:ab7a8de3ff10	1433	#define GPIO_OUTSET_PIN30_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1434	#define GPIO_OUTSET_PIN30_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1435	#define GPIO_OUTSET_PIN30_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1436
vcoubard	551:ab7a8de3ff10	1437	/* Bit 29 : Pin 29. */
vcoubard	551:ab7a8de3ff10	1438	#define GPIO_OUTSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	551:ab7a8de3ff10	1439	#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	551:ab7a8de3ff10	1440	#define GPIO_OUTSET_PIN29_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1441	#define GPIO_OUTSET_PIN29_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1442	#define GPIO_OUTSET_PIN29_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1443
vcoubard	551:ab7a8de3ff10	1444	/* Bit 28 : Pin 28. */
vcoubard	551:ab7a8de3ff10	1445	#define GPIO_OUTSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	551:ab7a8de3ff10	1446	#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	551:ab7a8de3ff10	1447	#define GPIO_OUTSET_PIN28_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1448	#define GPIO_OUTSET_PIN28_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1449	#define GPIO_OUTSET_PIN28_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1450
vcoubard	551:ab7a8de3ff10	1451	/* Bit 27 : Pin 27. */
vcoubard	551:ab7a8de3ff10	1452	#define GPIO_OUTSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	551:ab7a8de3ff10	1453	#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	551:ab7a8de3ff10	1454	#define GPIO_OUTSET_PIN27_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1455	#define GPIO_OUTSET_PIN27_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1456	#define GPIO_OUTSET_PIN27_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1457
vcoubard	551:ab7a8de3ff10	1458	/* Bit 26 : Pin 26. */
vcoubard	551:ab7a8de3ff10	1459	#define GPIO_OUTSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	551:ab7a8de3ff10	1460	#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	551:ab7a8de3ff10	1461	#define GPIO_OUTSET_PIN26_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1462	#define GPIO_OUTSET_PIN26_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1463	#define GPIO_OUTSET_PIN26_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1464
vcoubard	551:ab7a8de3ff10	1465	/* Bit 25 : Pin 25. */
vcoubard	551:ab7a8de3ff10	1466	#define GPIO_OUTSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	551:ab7a8de3ff10	1467	#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	551:ab7a8de3ff10	1468	#define GPIO_OUTSET_PIN25_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1469	#define GPIO_OUTSET_PIN25_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1470	#define GPIO_OUTSET_PIN25_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1471
vcoubard	551:ab7a8de3ff10	1472	/* Bit 24 : Pin 24. */
vcoubard	551:ab7a8de3ff10	1473	#define GPIO_OUTSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	551:ab7a8de3ff10	1474	#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	551:ab7a8de3ff10	1475	#define GPIO_OUTSET_PIN24_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1476	#define GPIO_OUTSET_PIN24_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1477	#define GPIO_OUTSET_PIN24_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1478
vcoubard	551:ab7a8de3ff10	1479	/* Bit 23 : Pin 23. */
vcoubard	551:ab7a8de3ff10	1480	#define GPIO_OUTSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	551:ab7a8de3ff10	1481	#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	551:ab7a8de3ff10	1482	#define GPIO_OUTSET_PIN23_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1483	#define GPIO_OUTSET_PIN23_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1484	#define GPIO_OUTSET_PIN23_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1485
vcoubard	551:ab7a8de3ff10	1486	/* Bit 22 : Pin 22. */
vcoubard	551:ab7a8de3ff10	1487	#define GPIO_OUTSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	551:ab7a8de3ff10	1488	#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	551:ab7a8de3ff10	1489	#define GPIO_OUTSET_PIN22_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1490	#define GPIO_OUTSET_PIN22_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1491	#define GPIO_OUTSET_PIN22_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1492
vcoubard	551:ab7a8de3ff10	1493	/* Bit 21 : Pin 21. */
vcoubard	551:ab7a8de3ff10	1494	#define GPIO_OUTSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	551:ab7a8de3ff10	1495	#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	551:ab7a8de3ff10	1496	#define GPIO_OUTSET_PIN21_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1497	#define GPIO_OUTSET_PIN21_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1498	#define GPIO_OUTSET_PIN21_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1499
vcoubard	551:ab7a8de3ff10	1500	/* Bit 20 : Pin 20. */
vcoubard	551:ab7a8de3ff10	1501	#define GPIO_OUTSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	551:ab7a8de3ff10	1502	#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	551:ab7a8de3ff10	1503	#define GPIO_OUTSET_PIN20_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1504	#define GPIO_OUTSET_PIN20_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1505	#define GPIO_OUTSET_PIN20_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1506
vcoubard	551:ab7a8de3ff10	1507	/* Bit 19 : Pin 19. */
vcoubard	551:ab7a8de3ff10	1508	#define GPIO_OUTSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	551:ab7a8de3ff10	1509	#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	551:ab7a8de3ff10	1510	#define GPIO_OUTSET_PIN19_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1511	#define GPIO_OUTSET_PIN19_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1512	#define GPIO_OUTSET_PIN19_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1513
vcoubard	551:ab7a8de3ff10	1514	/* Bit 18 : Pin 18. */
vcoubard	551:ab7a8de3ff10	1515	#define GPIO_OUTSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	551:ab7a8de3ff10	1516	#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	551:ab7a8de3ff10	1517	#define GPIO_OUTSET_PIN18_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1518	#define GPIO_OUTSET_PIN18_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1519	#define GPIO_OUTSET_PIN18_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1520
vcoubard	551:ab7a8de3ff10	1521	/* Bit 17 : Pin 17. */
vcoubard	551:ab7a8de3ff10	1522	#define GPIO_OUTSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	551:ab7a8de3ff10	1523	#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	551:ab7a8de3ff10	1524	#define GPIO_OUTSET_PIN17_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1525	#define GPIO_OUTSET_PIN17_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1526	#define GPIO_OUTSET_PIN17_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1527
vcoubard	551:ab7a8de3ff10	1528	/* Bit 16 : Pin 16. */
vcoubard	551:ab7a8de3ff10	1529	#define GPIO_OUTSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	551:ab7a8de3ff10	1530	#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	551:ab7a8de3ff10	1531	#define GPIO_OUTSET_PIN16_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1532	#define GPIO_OUTSET_PIN16_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1533	#define GPIO_OUTSET_PIN16_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1534
vcoubard	551:ab7a8de3ff10	1535	/* Bit 15 : Pin 15. */
vcoubard	551:ab7a8de3ff10	1536	#define GPIO_OUTSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	551:ab7a8de3ff10	1537	#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	551:ab7a8de3ff10	1538	#define GPIO_OUTSET_PIN15_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1539	#define GPIO_OUTSET_PIN15_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1540	#define GPIO_OUTSET_PIN15_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1541
vcoubard	551:ab7a8de3ff10	1542	/* Bit 14 : Pin 14. */
vcoubard	551:ab7a8de3ff10	1543	#define GPIO_OUTSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	551:ab7a8de3ff10	1544	#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	551:ab7a8de3ff10	1545	#define GPIO_OUTSET_PIN14_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1546	#define GPIO_OUTSET_PIN14_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1547	#define GPIO_OUTSET_PIN14_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1548
vcoubard	551:ab7a8de3ff10	1549	/* Bit 13 : Pin 13. */
vcoubard	551:ab7a8de3ff10	1550	#define GPIO_OUTSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	551:ab7a8de3ff10	1551	#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	551:ab7a8de3ff10	1552	#define GPIO_OUTSET_PIN13_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1553	#define GPIO_OUTSET_PIN13_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1554	#define GPIO_OUTSET_PIN13_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1555
vcoubard	551:ab7a8de3ff10	1556	/* Bit 12 : Pin 12. */
vcoubard	551:ab7a8de3ff10	1557	#define GPIO_OUTSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	551:ab7a8de3ff10	1558	#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	551:ab7a8de3ff10	1559	#define GPIO_OUTSET_PIN12_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1560	#define GPIO_OUTSET_PIN12_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1561	#define GPIO_OUTSET_PIN12_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1562
vcoubard	551:ab7a8de3ff10	1563	/* Bit 11 : Pin 11. */
vcoubard	551:ab7a8de3ff10	1564	#define GPIO_OUTSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	551:ab7a8de3ff10	1565	#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	551:ab7a8de3ff10	1566	#define GPIO_OUTSET_PIN11_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1567	#define GPIO_OUTSET_PIN11_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1568	#define GPIO_OUTSET_PIN11_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1569
vcoubard	551:ab7a8de3ff10	1570	/* Bit 10 : Pin 10. */
vcoubard	551:ab7a8de3ff10	1571	#define GPIO_OUTSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	551:ab7a8de3ff10	1572	#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	551:ab7a8de3ff10	1573	#define GPIO_OUTSET_PIN10_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1574	#define GPIO_OUTSET_PIN10_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1575	#define GPIO_OUTSET_PIN10_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1576
vcoubard	551:ab7a8de3ff10	1577	/* Bit 9 : Pin 9. */
vcoubard	551:ab7a8de3ff10	1578	#define GPIO_OUTSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	551:ab7a8de3ff10	1579	#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	551:ab7a8de3ff10	1580	#define GPIO_OUTSET_PIN9_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1581	#define GPIO_OUTSET_PIN9_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1582	#define GPIO_OUTSET_PIN9_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1583
vcoubard	551:ab7a8de3ff10	1584	/* Bit 8 : Pin 8. */
vcoubard	551:ab7a8de3ff10	1585	#define GPIO_OUTSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	551:ab7a8de3ff10	1586	#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	551:ab7a8de3ff10	1587	#define GPIO_OUTSET_PIN8_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1588	#define GPIO_OUTSET_PIN8_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1589	#define GPIO_OUTSET_PIN8_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1590
vcoubard	551:ab7a8de3ff10	1591	/* Bit 7 : Pin 7. */
vcoubard	551:ab7a8de3ff10	1592	#define GPIO_OUTSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	551:ab7a8de3ff10	1593	#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	551:ab7a8de3ff10	1594	#define GPIO_OUTSET_PIN7_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1595	#define GPIO_OUTSET_PIN7_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1596	#define GPIO_OUTSET_PIN7_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1597
vcoubard	551:ab7a8de3ff10	1598	/* Bit 6 : Pin 6. */
vcoubard	551:ab7a8de3ff10	1599	#define GPIO_OUTSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	551:ab7a8de3ff10	1600	#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	551:ab7a8de3ff10	1601	#define GPIO_OUTSET_PIN6_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1602	#define GPIO_OUTSET_PIN6_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1603	#define GPIO_OUTSET_PIN6_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1604
vcoubard	551:ab7a8de3ff10	1605	/* Bit 5 : Pin 5. */
vcoubard	551:ab7a8de3ff10	1606	#define GPIO_OUTSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	551:ab7a8de3ff10	1607	#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	551:ab7a8de3ff10	1608	#define GPIO_OUTSET_PIN5_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1609	#define GPIO_OUTSET_PIN5_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1610	#define GPIO_OUTSET_PIN5_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1611
vcoubard	551:ab7a8de3ff10	1612	/* Bit 4 : Pin 4. */
vcoubard	551:ab7a8de3ff10	1613	#define GPIO_OUTSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	551:ab7a8de3ff10	1614	#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	551:ab7a8de3ff10	1615	#define GPIO_OUTSET_PIN4_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1616	#define GPIO_OUTSET_PIN4_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1617	#define GPIO_OUTSET_PIN4_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1618
vcoubard	551:ab7a8de3ff10	1619	/* Bit 3 : Pin 3. */
vcoubard	551:ab7a8de3ff10	1620	#define GPIO_OUTSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	551:ab7a8de3ff10	1621	#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	551:ab7a8de3ff10	1622	#define GPIO_OUTSET_PIN3_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1623	#define GPIO_OUTSET_PIN3_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1624	#define GPIO_OUTSET_PIN3_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1625
vcoubard	551:ab7a8de3ff10	1626	/* Bit 2 : Pin 2. */
vcoubard	551:ab7a8de3ff10	1627	#define GPIO_OUTSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	551:ab7a8de3ff10	1628	#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	551:ab7a8de3ff10	1629	#define GPIO_OUTSET_PIN2_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1630	#define GPIO_OUTSET_PIN2_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1631	#define GPIO_OUTSET_PIN2_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1632
vcoubard	551:ab7a8de3ff10	1633	/* Bit 1 : Pin 1. */
vcoubard	551:ab7a8de3ff10	1634	#define GPIO_OUTSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	551:ab7a8de3ff10	1635	#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	551:ab7a8de3ff10	1636	#define GPIO_OUTSET_PIN1_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1637	#define GPIO_OUTSET_PIN1_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1638	#define GPIO_OUTSET_PIN1_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1639
vcoubard	551:ab7a8de3ff10	1640	/* Bit 0 : Pin 0. */
vcoubard	551:ab7a8de3ff10	1641	#define GPIO_OUTSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	551:ab7a8de3ff10	1642	#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	551:ab7a8de3ff10	1643	#define GPIO_OUTSET_PIN0_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1644	#define GPIO_OUTSET_PIN0_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1645	#define GPIO_OUTSET_PIN0_Set (1UL) /!< Set pin driver high. /
vcoubard	551:ab7a8de3ff10	1646
vcoubard	551:ab7a8de3ff10	1647	/* Register: GPIO_OUTCLR */
vcoubard	551:ab7a8de3ff10	1648	/* Description: Clear individual bits in GPIO port. */
vcoubard	551:ab7a8de3ff10	1649
vcoubard	551:ab7a8de3ff10	1650	/* Bit 31 : Pin 31. */
vcoubard	551:ab7a8de3ff10	1651	#define GPIO_OUTCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	551:ab7a8de3ff10	1652	#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	551:ab7a8de3ff10	1653	#define GPIO_OUTCLR_PIN31_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1654	#define GPIO_OUTCLR_PIN31_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1655	#define GPIO_OUTCLR_PIN31_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1656
vcoubard	551:ab7a8de3ff10	1657	/* Bit 30 : Pin 30. */
vcoubard	551:ab7a8de3ff10	1658	#define GPIO_OUTCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	551:ab7a8de3ff10	1659	#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	551:ab7a8de3ff10	1660	#define GPIO_OUTCLR_PIN30_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1661	#define GPIO_OUTCLR_PIN30_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1662	#define GPIO_OUTCLR_PIN30_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1663
vcoubard	551:ab7a8de3ff10	1664	/* Bit 29 : Pin 29. */
vcoubard	551:ab7a8de3ff10	1665	#define GPIO_OUTCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	551:ab7a8de3ff10	1666	#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	551:ab7a8de3ff10	1667	#define GPIO_OUTCLR_PIN29_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1668	#define GPIO_OUTCLR_PIN29_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1669	#define GPIO_OUTCLR_PIN29_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1670
vcoubard	551:ab7a8de3ff10	1671	/* Bit 28 : Pin 28. */
vcoubard	551:ab7a8de3ff10	1672	#define GPIO_OUTCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	551:ab7a8de3ff10	1673	#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	551:ab7a8de3ff10	1674	#define GPIO_OUTCLR_PIN28_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1675	#define GPIO_OUTCLR_PIN28_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1676	#define GPIO_OUTCLR_PIN28_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1677
vcoubard	551:ab7a8de3ff10	1678	/* Bit 27 : Pin 27. */
vcoubard	551:ab7a8de3ff10	1679	#define GPIO_OUTCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	551:ab7a8de3ff10	1680	#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	551:ab7a8de3ff10	1681	#define GPIO_OUTCLR_PIN27_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1682	#define GPIO_OUTCLR_PIN27_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1683	#define GPIO_OUTCLR_PIN27_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1684
vcoubard	551:ab7a8de3ff10	1685	/* Bit 26 : Pin 26. */
vcoubard	551:ab7a8de3ff10	1686	#define GPIO_OUTCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	551:ab7a8de3ff10	1687	#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	551:ab7a8de3ff10	1688	#define GPIO_OUTCLR_PIN26_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1689	#define GPIO_OUTCLR_PIN26_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1690	#define GPIO_OUTCLR_PIN26_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1691
vcoubard	551:ab7a8de3ff10	1692	/* Bit 25 : Pin 25. */
vcoubard	551:ab7a8de3ff10	1693	#define GPIO_OUTCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	551:ab7a8de3ff10	1694	#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	551:ab7a8de3ff10	1695	#define GPIO_OUTCLR_PIN25_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1696	#define GPIO_OUTCLR_PIN25_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1697	#define GPIO_OUTCLR_PIN25_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1698
vcoubard	551:ab7a8de3ff10	1699	/* Bit 24 : Pin 24. */
vcoubard	551:ab7a8de3ff10	1700	#define GPIO_OUTCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	551:ab7a8de3ff10	1701	#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	551:ab7a8de3ff10	1702	#define GPIO_OUTCLR_PIN24_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1703	#define GPIO_OUTCLR_PIN24_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1704	#define GPIO_OUTCLR_PIN24_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1705
vcoubard	551:ab7a8de3ff10	1706	/* Bit 23 : Pin 23. */
vcoubard	551:ab7a8de3ff10	1707	#define GPIO_OUTCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	551:ab7a8de3ff10	1708	#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	551:ab7a8de3ff10	1709	#define GPIO_OUTCLR_PIN23_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1710	#define GPIO_OUTCLR_PIN23_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1711	#define GPIO_OUTCLR_PIN23_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1712
vcoubard	551:ab7a8de3ff10	1713	/* Bit 22 : Pin 22. */
vcoubard	551:ab7a8de3ff10	1714	#define GPIO_OUTCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	551:ab7a8de3ff10	1715	#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	551:ab7a8de3ff10	1716	#define GPIO_OUTCLR_PIN22_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1717	#define GPIO_OUTCLR_PIN22_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1718	#define GPIO_OUTCLR_PIN22_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1719
vcoubard	551:ab7a8de3ff10	1720	/* Bit 21 : Pin 21. */
vcoubard	551:ab7a8de3ff10	1721	#define GPIO_OUTCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	551:ab7a8de3ff10	1722	#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	551:ab7a8de3ff10	1723	#define GPIO_OUTCLR_PIN21_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1724	#define GPIO_OUTCLR_PIN21_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1725	#define GPIO_OUTCLR_PIN21_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1726
vcoubard	551:ab7a8de3ff10	1727	/* Bit 20 : Pin 20. */
vcoubard	551:ab7a8de3ff10	1728	#define GPIO_OUTCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	551:ab7a8de3ff10	1729	#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	551:ab7a8de3ff10	1730	#define GPIO_OUTCLR_PIN20_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1731	#define GPIO_OUTCLR_PIN20_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1732	#define GPIO_OUTCLR_PIN20_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1733
vcoubard	551:ab7a8de3ff10	1734	/* Bit 19 : Pin 19. */
vcoubard	551:ab7a8de3ff10	1735	#define GPIO_OUTCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	551:ab7a8de3ff10	1736	#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	551:ab7a8de3ff10	1737	#define GPIO_OUTCLR_PIN19_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1738	#define GPIO_OUTCLR_PIN19_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1739	#define GPIO_OUTCLR_PIN19_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1740
vcoubard	551:ab7a8de3ff10	1741	/* Bit 18 : Pin 18. */
vcoubard	551:ab7a8de3ff10	1742	#define GPIO_OUTCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	551:ab7a8de3ff10	1743	#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	551:ab7a8de3ff10	1744	#define GPIO_OUTCLR_PIN18_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1745	#define GPIO_OUTCLR_PIN18_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1746	#define GPIO_OUTCLR_PIN18_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1747
vcoubard	551:ab7a8de3ff10	1748	/* Bit 17 : Pin 17. */
vcoubard	551:ab7a8de3ff10	1749	#define GPIO_OUTCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	551:ab7a8de3ff10	1750	#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	551:ab7a8de3ff10	1751	#define GPIO_OUTCLR_PIN17_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1752	#define GPIO_OUTCLR_PIN17_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1753	#define GPIO_OUTCLR_PIN17_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1754
vcoubard	551:ab7a8de3ff10	1755	/* Bit 16 : Pin 16. */
vcoubard	551:ab7a8de3ff10	1756	#define GPIO_OUTCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	551:ab7a8de3ff10	1757	#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	551:ab7a8de3ff10	1758	#define GPIO_OUTCLR_PIN16_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1759	#define GPIO_OUTCLR_PIN16_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1760	#define GPIO_OUTCLR_PIN16_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1761
vcoubard	551:ab7a8de3ff10	1762	/* Bit 15 : Pin 15. */
vcoubard	551:ab7a8de3ff10	1763	#define GPIO_OUTCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	551:ab7a8de3ff10	1764	#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	551:ab7a8de3ff10	1765	#define GPIO_OUTCLR_PIN15_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1766	#define GPIO_OUTCLR_PIN15_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1767	#define GPIO_OUTCLR_PIN15_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1768
vcoubard	551:ab7a8de3ff10	1769	/* Bit 14 : Pin 14. */
vcoubard	551:ab7a8de3ff10	1770	#define GPIO_OUTCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	551:ab7a8de3ff10	1771	#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	551:ab7a8de3ff10	1772	#define GPIO_OUTCLR_PIN14_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1773	#define GPIO_OUTCLR_PIN14_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1774	#define GPIO_OUTCLR_PIN14_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1775
vcoubard	551:ab7a8de3ff10	1776	/* Bit 13 : Pin 13. */
vcoubard	551:ab7a8de3ff10	1777	#define GPIO_OUTCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	551:ab7a8de3ff10	1778	#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	551:ab7a8de3ff10	1779	#define GPIO_OUTCLR_PIN13_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1780	#define GPIO_OUTCLR_PIN13_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1781	#define GPIO_OUTCLR_PIN13_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1782
vcoubard	551:ab7a8de3ff10	1783	/* Bit 12 : Pin 12. */
vcoubard	551:ab7a8de3ff10	1784	#define GPIO_OUTCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	551:ab7a8de3ff10	1785	#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	551:ab7a8de3ff10	1786	#define GPIO_OUTCLR_PIN12_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1787	#define GPIO_OUTCLR_PIN12_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1788	#define GPIO_OUTCLR_PIN12_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1789
vcoubard	551:ab7a8de3ff10	1790	/* Bit 11 : Pin 11. */
vcoubard	551:ab7a8de3ff10	1791	#define GPIO_OUTCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	551:ab7a8de3ff10	1792	#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	551:ab7a8de3ff10	1793	#define GPIO_OUTCLR_PIN11_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1794	#define GPIO_OUTCLR_PIN11_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1795	#define GPIO_OUTCLR_PIN11_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1796
vcoubard	551:ab7a8de3ff10	1797	/* Bit 10 : Pin 10. */
vcoubard	551:ab7a8de3ff10	1798	#define GPIO_OUTCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	551:ab7a8de3ff10	1799	#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	551:ab7a8de3ff10	1800	#define GPIO_OUTCLR_PIN10_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1801	#define GPIO_OUTCLR_PIN10_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1802	#define GPIO_OUTCLR_PIN10_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1803
vcoubard	551:ab7a8de3ff10	1804	/* Bit 9 : Pin 9. */
vcoubard	551:ab7a8de3ff10	1805	#define GPIO_OUTCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	551:ab7a8de3ff10	1806	#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	551:ab7a8de3ff10	1807	#define GPIO_OUTCLR_PIN9_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1808	#define GPIO_OUTCLR_PIN9_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1809	#define GPIO_OUTCLR_PIN9_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1810
vcoubard	551:ab7a8de3ff10	1811	/* Bit 8 : Pin 8. */
vcoubard	551:ab7a8de3ff10	1812	#define GPIO_OUTCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	551:ab7a8de3ff10	1813	#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	551:ab7a8de3ff10	1814	#define GPIO_OUTCLR_PIN8_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1815	#define GPIO_OUTCLR_PIN8_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1816	#define GPIO_OUTCLR_PIN8_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1817
vcoubard	551:ab7a8de3ff10	1818	/* Bit 7 : Pin 7. */
vcoubard	551:ab7a8de3ff10	1819	#define GPIO_OUTCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	551:ab7a8de3ff10	1820	#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	551:ab7a8de3ff10	1821	#define GPIO_OUTCLR_PIN7_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1822	#define GPIO_OUTCLR_PIN7_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1823	#define GPIO_OUTCLR_PIN7_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1824
vcoubard	551:ab7a8de3ff10	1825	/* Bit 6 : Pin 6. */
vcoubard	551:ab7a8de3ff10	1826	#define GPIO_OUTCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	551:ab7a8de3ff10	1827	#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	551:ab7a8de3ff10	1828	#define GPIO_OUTCLR_PIN6_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1829	#define GPIO_OUTCLR_PIN6_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1830	#define GPIO_OUTCLR_PIN6_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1831
vcoubard	551:ab7a8de3ff10	1832	/* Bit 5 : Pin 5. */
vcoubard	551:ab7a8de3ff10	1833	#define GPIO_OUTCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	551:ab7a8de3ff10	1834	#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	551:ab7a8de3ff10	1835	#define GPIO_OUTCLR_PIN5_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1836	#define GPIO_OUTCLR_PIN5_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1837	#define GPIO_OUTCLR_PIN5_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1838
vcoubard	551:ab7a8de3ff10	1839	/* Bit 4 : Pin 4. */
vcoubard	551:ab7a8de3ff10	1840	#define GPIO_OUTCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	551:ab7a8de3ff10	1841	#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	551:ab7a8de3ff10	1842	#define GPIO_OUTCLR_PIN4_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1843	#define GPIO_OUTCLR_PIN4_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1844	#define GPIO_OUTCLR_PIN4_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1845
vcoubard	551:ab7a8de3ff10	1846	/* Bit 3 : Pin 3. */
vcoubard	551:ab7a8de3ff10	1847	#define GPIO_OUTCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	551:ab7a8de3ff10	1848	#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	551:ab7a8de3ff10	1849	#define GPIO_OUTCLR_PIN3_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1850	#define GPIO_OUTCLR_PIN3_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1851	#define GPIO_OUTCLR_PIN3_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1852
vcoubard	551:ab7a8de3ff10	1853	/* Bit 2 : Pin 2. */
vcoubard	551:ab7a8de3ff10	1854	#define GPIO_OUTCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	551:ab7a8de3ff10	1855	#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	551:ab7a8de3ff10	1856	#define GPIO_OUTCLR_PIN2_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1857	#define GPIO_OUTCLR_PIN2_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1858	#define GPIO_OUTCLR_PIN2_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1859
vcoubard	551:ab7a8de3ff10	1860	/* Bit 1 : Pin 1. */
vcoubard	551:ab7a8de3ff10	1861	#define GPIO_OUTCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	551:ab7a8de3ff10	1862	#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	551:ab7a8de3ff10	1863	#define GPIO_OUTCLR_PIN1_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1864	#define GPIO_OUTCLR_PIN1_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1865	#define GPIO_OUTCLR_PIN1_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1866
vcoubard	551:ab7a8de3ff10	1867	/* Bit 0 : Pin 0. */
vcoubard	551:ab7a8de3ff10	1868	#define GPIO_OUTCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	551:ab7a8de3ff10	1869	#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	551:ab7a8de3ff10	1870	#define GPIO_OUTCLR_PIN0_Low (0UL) /!< Pin driver is low. /
vcoubard	551:ab7a8de3ff10	1871	#define GPIO_OUTCLR_PIN0_High (1UL) /!< Pin driver is high. /
vcoubard	551:ab7a8de3ff10	1872	#define GPIO_OUTCLR_PIN0_Clear (1UL) /!< Set pin driver low. /
vcoubard	551:ab7a8de3ff10	1873
vcoubard	551:ab7a8de3ff10	1874	/* Register: GPIO_IN */
vcoubard	551:ab7a8de3ff10	1875	/* Description: Read GPIO port. */
vcoubard	551:ab7a8de3ff10	1876
vcoubard	551:ab7a8de3ff10	1877	/* Bit 31 : Pin 31. */
vcoubard	551:ab7a8de3ff10	1878	#define GPIO_IN_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	551:ab7a8de3ff10	1879	#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	551:ab7a8de3ff10	1880	#define GPIO_IN_PIN31_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	1881	#define GPIO_IN_PIN31_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	1882
vcoubard	551:ab7a8de3ff10	1883	/* Bit 30 : Pin 30. */
vcoubard	551:ab7a8de3ff10	1884	#define GPIO_IN_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	551:ab7a8de3ff10	1885	#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	551:ab7a8de3ff10	1886	#define GPIO_IN_PIN30_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	1887	#define GPIO_IN_PIN30_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	1888
vcoubard	551:ab7a8de3ff10	1889	/* Bit 29 : Pin 29. */
vcoubard	551:ab7a8de3ff10	1890	#define GPIO_IN_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	551:ab7a8de3ff10	1891	#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	551:ab7a8de3ff10	1892	#define GPIO_IN_PIN29_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	1893	#define GPIO_IN_PIN29_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	1894
vcoubard	551:ab7a8de3ff10	1895	/* Bit 28 : Pin 28. */
vcoubard	551:ab7a8de3ff10	1896	#define GPIO_IN_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	551:ab7a8de3ff10	1897	#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	551:ab7a8de3ff10	1898	#define GPIO_IN_PIN28_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	1899	#define GPIO_IN_PIN28_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	1900
vcoubard	551:ab7a8de3ff10	1901	/* Bit 27 : Pin 27. */
vcoubard	551:ab7a8de3ff10	1902	#define GPIO_IN_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	551:ab7a8de3ff10	1903	#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	551:ab7a8de3ff10	1904	#define GPIO_IN_PIN27_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	1905	#define GPIO_IN_PIN27_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	1906
vcoubard	551:ab7a8de3ff10	1907	/* Bit 26 : Pin 26. */
vcoubard	551:ab7a8de3ff10	1908	#define GPIO_IN_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	551:ab7a8de3ff10	1909	#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	551:ab7a8de3ff10	1910	#define GPIO_IN_PIN26_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	1911	#define GPIO_IN_PIN26_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	1912
vcoubard	551:ab7a8de3ff10	1913	/* Bit 25 : Pin 25. */
vcoubard	551:ab7a8de3ff10	1914	#define GPIO_IN_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	551:ab7a8de3ff10	1915	#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	551:ab7a8de3ff10	1916	#define GPIO_IN_PIN25_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	1917	#define GPIO_IN_PIN25_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	1918
vcoubard	551:ab7a8de3ff10	1919	/* Bit 24 : Pin 24. */
vcoubard	551:ab7a8de3ff10	1920	#define GPIO_IN_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	551:ab7a8de3ff10	1921	#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	551:ab7a8de3ff10	1922	#define GPIO_IN_PIN24_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	1923	#define GPIO_IN_PIN24_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	1924
vcoubard	551:ab7a8de3ff10	1925	/* Bit 23 : Pin 23. */
vcoubard	551:ab7a8de3ff10	1926	#define GPIO_IN_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	551:ab7a8de3ff10	1927	#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	551:ab7a8de3ff10	1928	#define GPIO_IN_PIN23_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	1929	#define GPIO_IN_PIN23_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	1930
vcoubard	551:ab7a8de3ff10	1931	/* Bit 22 : Pin 22. */
vcoubard	551:ab7a8de3ff10	1932	#define GPIO_IN_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	551:ab7a8de3ff10	1933	#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	551:ab7a8de3ff10	1934	#define GPIO_IN_PIN22_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	1935	#define GPIO_IN_PIN22_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	1936
vcoubard	551:ab7a8de3ff10	1937	/* Bit 21 : Pin 21. */
vcoubard	551:ab7a8de3ff10	1938	#define GPIO_IN_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	551:ab7a8de3ff10	1939	#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	551:ab7a8de3ff10	1940	#define GPIO_IN_PIN21_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	1941	#define GPIO_IN_PIN21_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	1942
vcoubard	551:ab7a8de3ff10	1943	/* Bit 20 : Pin 20. */
vcoubard	551:ab7a8de3ff10	1944	#define GPIO_IN_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	551:ab7a8de3ff10	1945	#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	551:ab7a8de3ff10	1946	#define GPIO_IN_PIN20_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	1947	#define GPIO_IN_PIN20_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	1948
vcoubard	551:ab7a8de3ff10	1949	/* Bit 19 : Pin 19. */
vcoubard	551:ab7a8de3ff10	1950	#define GPIO_IN_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	551:ab7a8de3ff10	1951	#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	551:ab7a8de3ff10	1952	#define GPIO_IN_PIN19_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	1953	#define GPIO_IN_PIN19_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	1954
vcoubard	551:ab7a8de3ff10	1955	/* Bit 18 : Pin 18. */
vcoubard	551:ab7a8de3ff10	1956	#define GPIO_IN_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	551:ab7a8de3ff10	1957	#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	551:ab7a8de3ff10	1958	#define GPIO_IN_PIN18_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	1959	#define GPIO_IN_PIN18_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	1960
vcoubard	551:ab7a8de3ff10	1961	/* Bit 17 : Pin 17. */
vcoubard	551:ab7a8de3ff10	1962	#define GPIO_IN_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	551:ab7a8de3ff10	1963	#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	551:ab7a8de3ff10	1964	#define GPIO_IN_PIN17_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	1965	#define GPIO_IN_PIN17_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	1966
vcoubard	551:ab7a8de3ff10	1967	/* Bit 16 : Pin 16. */
vcoubard	551:ab7a8de3ff10	1968	#define GPIO_IN_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	551:ab7a8de3ff10	1969	#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	551:ab7a8de3ff10	1970	#define GPIO_IN_PIN16_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	1971	#define GPIO_IN_PIN16_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	1972
vcoubard	551:ab7a8de3ff10	1973	/* Bit 15 : Pin 15. */
vcoubard	551:ab7a8de3ff10	1974	#define GPIO_IN_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	551:ab7a8de3ff10	1975	#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	551:ab7a8de3ff10	1976	#define GPIO_IN_PIN15_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	1977	#define GPIO_IN_PIN15_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	1978
vcoubard	551:ab7a8de3ff10	1979	/* Bit 14 : Pin 14. */
vcoubard	551:ab7a8de3ff10	1980	#define GPIO_IN_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	551:ab7a8de3ff10	1981	#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	551:ab7a8de3ff10	1982	#define GPIO_IN_PIN14_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	1983	#define GPIO_IN_PIN14_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	1984
vcoubard	551:ab7a8de3ff10	1985	/* Bit 13 : Pin 13. */
vcoubard	551:ab7a8de3ff10	1986	#define GPIO_IN_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	551:ab7a8de3ff10	1987	#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	551:ab7a8de3ff10	1988	#define GPIO_IN_PIN13_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	1989	#define GPIO_IN_PIN13_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	1990
vcoubard	551:ab7a8de3ff10	1991	/* Bit 12 : Pin 12. */
vcoubard	551:ab7a8de3ff10	1992	#define GPIO_IN_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	551:ab7a8de3ff10	1993	#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	551:ab7a8de3ff10	1994	#define GPIO_IN_PIN12_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	1995	#define GPIO_IN_PIN12_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	1996
vcoubard	551:ab7a8de3ff10	1997	/* Bit 11 : Pin 11. */
vcoubard	551:ab7a8de3ff10	1998	#define GPIO_IN_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	551:ab7a8de3ff10	1999	#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	551:ab7a8de3ff10	2000	#define GPIO_IN_PIN11_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	2001	#define GPIO_IN_PIN11_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	2002
vcoubard	551:ab7a8de3ff10	2003	/* Bit 10 : Pin 10. */
vcoubard	551:ab7a8de3ff10	2004	#define GPIO_IN_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	551:ab7a8de3ff10	2005	#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	551:ab7a8de3ff10	2006	#define GPIO_IN_PIN10_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	2007	#define GPIO_IN_PIN10_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	2008
vcoubard	551:ab7a8de3ff10	2009	/* Bit 9 : Pin 9. */
vcoubard	551:ab7a8de3ff10	2010	#define GPIO_IN_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	551:ab7a8de3ff10	2011	#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	551:ab7a8de3ff10	2012	#define GPIO_IN_PIN9_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	2013	#define GPIO_IN_PIN9_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	2014
vcoubard	551:ab7a8de3ff10	2015	/* Bit 8 : Pin 8. */
vcoubard	551:ab7a8de3ff10	2016	#define GPIO_IN_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	551:ab7a8de3ff10	2017	#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	551:ab7a8de3ff10	2018	#define GPIO_IN_PIN8_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	2019	#define GPIO_IN_PIN8_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	2020
vcoubard	551:ab7a8de3ff10	2021	/* Bit 7 : Pin 7. */
vcoubard	551:ab7a8de3ff10	2022	#define GPIO_IN_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	551:ab7a8de3ff10	2023	#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	551:ab7a8de3ff10	2024	#define GPIO_IN_PIN7_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	2025	#define GPIO_IN_PIN7_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	2026
vcoubard	551:ab7a8de3ff10	2027	/* Bit 6 : Pin 6. */
vcoubard	551:ab7a8de3ff10	2028	#define GPIO_IN_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	551:ab7a8de3ff10	2029	#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	551:ab7a8de3ff10	2030	#define GPIO_IN_PIN6_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	2031	#define GPIO_IN_PIN6_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	2032
vcoubard	551:ab7a8de3ff10	2033	/* Bit 5 : Pin 5. */
vcoubard	551:ab7a8de3ff10	2034	#define GPIO_IN_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	551:ab7a8de3ff10	2035	#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	551:ab7a8de3ff10	2036	#define GPIO_IN_PIN5_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	2037	#define GPIO_IN_PIN5_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	2038
vcoubard	551:ab7a8de3ff10	2039	/* Bit 4 : Pin 4. */
vcoubard	551:ab7a8de3ff10	2040	#define GPIO_IN_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	551:ab7a8de3ff10	2041	#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	551:ab7a8de3ff10	2042	#define GPIO_IN_PIN4_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	2043	#define GPIO_IN_PIN4_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	2044
vcoubard	551:ab7a8de3ff10	2045	/* Bit 3 : Pin 3. */
vcoubard	551:ab7a8de3ff10	2046	#define GPIO_IN_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	551:ab7a8de3ff10	2047	#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	551:ab7a8de3ff10	2048	#define GPIO_IN_PIN3_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	2049	#define GPIO_IN_PIN3_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	2050
vcoubard	551:ab7a8de3ff10	2051	/* Bit 2 : Pin 2. */
vcoubard	551:ab7a8de3ff10	2052	#define GPIO_IN_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	551:ab7a8de3ff10	2053	#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	551:ab7a8de3ff10	2054	#define GPIO_IN_PIN2_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	2055	#define GPIO_IN_PIN2_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	2056
vcoubard	551:ab7a8de3ff10	2057	/* Bit 1 : Pin 1. */
vcoubard	551:ab7a8de3ff10	2058	#define GPIO_IN_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	551:ab7a8de3ff10	2059	#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	551:ab7a8de3ff10	2060	#define GPIO_IN_PIN1_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	2061	#define GPIO_IN_PIN1_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	2062
vcoubard	551:ab7a8de3ff10	2063	/* Bit 0 : Pin 0. */
vcoubard	551:ab7a8de3ff10	2064	#define GPIO_IN_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	551:ab7a8de3ff10	2065	#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	551:ab7a8de3ff10	2066	#define GPIO_IN_PIN0_Low (0UL) /!< Pin input is low. /
vcoubard	551:ab7a8de3ff10	2067	#define GPIO_IN_PIN0_High (1UL) /!< Pin input is high. /
vcoubard	551:ab7a8de3ff10	2068
vcoubard	551:ab7a8de3ff10	2069	/* Register: GPIO_DIR */
vcoubard	551:ab7a8de3ff10	2070	/* Description: Direction of GPIO pins. */
vcoubard	551:ab7a8de3ff10	2071
vcoubard	551:ab7a8de3ff10	2072	/* Bit 31 : Pin 31. */
vcoubard	551:ab7a8de3ff10	2073	#define GPIO_DIR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	551:ab7a8de3ff10	2074	#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	551:ab7a8de3ff10	2075	#define GPIO_DIR_PIN31_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2076	#define GPIO_DIR_PIN31_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2077
vcoubard	551:ab7a8de3ff10	2078	/* Bit 30 : Pin 30. */
vcoubard	551:ab7a8de3ff10	2079	#define GPIO_DIR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	551:ab7a8de3ff10	2080	#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	551:ab7a8de3ff10	2081	#define GPIO_DIR_PIN30_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2082	#define GPIO_DIR_PIN30_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2083
vcoubard	551:ab7a8de3ff10	2084	/* Bit 29 : Pin 29. */
vcoubard	551:ab7a8de3ff10	2085	#define GPIO_DIR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	551:ab7a8de3ff10	2086	#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	551:ab7a8de3ff10	2087	#define GPIO_DIR_PIN29_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2088	#define GPIO_DIR_PIN29_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2089
vcoubard	551:ab7a8de3ff10	2090	/* Bit 28 : Pin 28. */
vcoubard	551:ab7a8de3ff10	2091	#define GPIO_DIR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	551:ab7a8de3ff10	2092	#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	551:ab7a8de3ff10	2093	#define GPIO_DIR_PIN28_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2094	#define GPIO_DIR_PIN28_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2095
vcoubard	551:ab7a8de3ff10	2096	/* Bit 27 : Pin 27. */
vcoubard	551:ab7a8de3ff10	2097	#define GPIO_DIR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	551:ab7a8de3ff10	2098	#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	551:ab7a8de3ff10	2099	#define GPIO_DIR_PIN27_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2100	#define GPIO_DIR_PIN27_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2101
vcoubard	551:ab7a8de3ff10	2102	/* Bit 26 : Pin 26. */
vcoubard	551:ab7a8de3ff10	2103	#define GPIO_DIR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	551:ab7a8de3ff10	2104	#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	551:ab7a8de3ff10	2105	#define GPIO_DIR_PIN26_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2106	#define GPIO_DIR_PIN26_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2107
vcoubard	551:ab7a8de3ff10	2108	/* Bit 25 : Pin 25. */
vcoubard	551:ab7a8de3ff10	2109	#define GPIO_DIR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	551:ab7a8de3ff10	2110	#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	551:ab7a8de3ff10	2111	#define GPIO_DIR_PIN25_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2112	#define GPIO_DIR_PIN25_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2113
vcoubard	551:ab7a8de3ff10	2114	/* Bit 24 : Pin 24. */
vcoubard	551:ab7a8de3ff10	2115	#define GPIO_DIR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	551:ab7a8de3ff10	2116	#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	551:ab7a8de3ff10	2117	#define GPIO_DIR_PIN24_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2118	#define GPIO_DIR_PIN24_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2119
vcoubard	551:ab7a8de3ff10	2120	/* Bit 23 : Pin 23. */
vcoubard	551:ab7a8de3ff10	2121	#define GPIO_DIR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	551:ab7a8de3ff10	2122	#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	551:ab7a8de3ff10	2123	#define GPIO_DIR_PIN23_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2124	#define GPIO_DIR_PIN23_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2125
vcoubard	551:ab7a8de3ff10	2126	/* Bit 22 : Pin 22. */
vcoubard	551:ab7a8de3ff10	2127	#define GPIO_DIR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	551:ab7a8de3ff10	2128	#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	551:ab7a8de3ff10	2129	#define GPIO_DIR_PIN22_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2130	#define GPIO_DIR_PIN22_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2131
vcoubard	551:ab7a8de3ff10	2132	/* Bit 21 : Pin 21. */
vcoubard	551:ab7a8de3ff10	2133	#define GPIO_DIR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	551:ab7a8de3ff10	2134	#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	551:ab7a8de3ff10	2135	#define GPIO_DIR_PIN21_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2136	#define GPIO_DIR_PIN21_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2137
vcoubard	551:ab7a8de3ff10	2138	/* Bit 20 : Pin 20. */
vcoubard	551:ab7a8de3ff10	2139	#define GPIO_DIR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	551:ab7a8de3ff10	2140	#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	551:ab7a8de3ff10	2141	#define GPIO_DIR_PIN20_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2142	#define GPIO_DIR_PIN20_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2143
vcoubard	551:ab7a8de3ff10	2144	/* Bit 19 : Pin 19. */
vcoubard	551:ab7a8de3ff10	2145	#define GPIO_DIR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	551:ab7a8de3ff10	2146	#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	551:ab7a8de3ff10	2147	#define GPIO_DIR_PIN19_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2148	#define GPIO_DIR_PIN19_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2149
vcoubard	551:ab7a8de3ff10	2150	/* Bit 18 : Pin 18. */
vcoubard	551:ab7a8de3ff10	2151	#define GPIO_DIR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	551:ab7a8de3ff10	2152	#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	551:ab7a8de3ff10	2153	#define GPIO_DIR_PIN18_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2154	#define GPIO_DIR_PIN18_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2155
vcoubard	551:ab7a8de3ff10	2156	/* Bit 17 : Pin 17. */
vcoubard	551:ab7a8de3ff10	2157	#define GPIO_DIR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	551:ab7a8de3ff10	2158	#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	551:ab7a8de3ff10	2159	#define GPIO_DIR_PIN17_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2160	#define GPIO_DIR_PIN17_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2161
vcoubard	551:ab7a8de3ff10	2162	/* Bit 16 : Pin 16. */
vcoubard	551:ab7a8de3ff10	2163	#define GPIO_DIR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	551:ab7a8de3ff10	2164	#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	551:ab7a8de3ff10	2165	#define GPIO_DIR_PIN16_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2166	#define GPIO_DIR_PIN16_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2167
vcoubard	551:ab7a8de3ff10	2168	/* Bit 15 : Pin 15. */
vcoubard	551:ab7a8de3ff10	2169	#define GPIO_DIR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	551:ab7a8de3ff10	2170	#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	551:ab7a8de3ff10	2171	#define GPIO_DIR_PIN15_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2172	#define GPIO_DIR_PIN15_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2173
vcoubard	551:ab7a8de3ff10	2174	/* Bit 14 : Pin 14. */
vcoubard	551:ab7a8de3ff10	2175	#define GPIO_DIR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	551:ab7a8de3ff10	2176	#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	551:ab7a8de3ff10	2177	#define GPIO_DIR_PIN14_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2178	#define GPIO_DIR_PIN14_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2179
vcoubard	551:ab7a8de3ff10	2180	/* Bit 13 : Pin 13. */
vcoubard	551:ab7a8de3ff10	2181	#define GPIO_DIR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	551:ab7a8de3ff10	2182	#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	551:ab7a8de3ff10	2183	#define GPIO_DIR_PIN13_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2184	#define GPIO_DIR_PIN13_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2185
vcoubard	551:ab7a8de3ff10	2186	/* Bit 12 : Pin 12. */
vcoubard	551:ab7a8de3ff10	2187	#define GPIO_DIR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	551:ab7a8de3ff10	2188	#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	551:ab7a8de3ff10	2189	#define GPIO_DIR_PIN12_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2190	#define GPIO_DIR_PIN12_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2191
vcoubard	551:ab7a8de3ff10	2192	/* Bit 11 : Pin 11. */
vcoubard	551:ab7a8de3ff10	2193	#define GPIO_DIR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	551:ab7a8de3ff10	2194	#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	551:ab7a8de3ff10	2195	#define GPIO_DIR_PIN11_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2196	#define GPIO_DIR_PIN11_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2197
vcoubard	551:ab7a8de3ff10	2198	/* Bit 10 : Pin 10. */
vcoubard	551:ab7a8de3ff10	2199	#define GPIO_DIR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	551:ab7a8de3ff10	2200	#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	551:ab7a8de3ff10	2201	#define GPIO_DIR_PIN10_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2202	#define GPIO_DIR_PIN10_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2203
vcoubard	551:ab7a8de3ff10	2204	/* Bit 9 : Pin 9. */
vcoubard	551:ab7a8de3ff10	2205	#define GPIO_DIR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	551:ab7a8de3ff10	2206	#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	551:ab7a8de3ff10	2207	#define GPIO_DIR_PIN9_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2208	#define GPIO_DIR_PIN9_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2209
vcoubard	551:ab7a8de3ff10	2210	/* Bit 8 : Pin 8. */
vcoubard	551:ab7a8de3ff10	2211	#define GPIO_DIR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	551:ab7a8de3ff10	2212	#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	551:ab7a8de3ff10	2213	#define GPIO_DIR_PIN8_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2214	#define GPIO_DIR_PIN8_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2215
vcoubard	551:ab7a8de3ff10	2216	/* Bit 7 : Pin 7. */
vcoubard	551:ab7a8de3ff10	2217	#define GPIO_DIR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	551:ab7a8de3ff10	2218	#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	551:ab7a8de3ff10	2219	#define GPIO_DIR_PIN7_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2220	#define GPIO_DIR_PIN7_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2221
vcoubard	551:ab7a8de3ff10	2222	/* Bit 6 : Pin 6. */
vcoubard	551:ab7a8de3ff10	2223	#define GPIO_DIR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	551:ab7a8de3ff10	2224	#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	551:ab7a8de3ff10	2225	#define GPIO_DIR_PIN6_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2226	#define GPIO_DIR_PIN6_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2227
vcoubard	551:ab7a8de3ff10	2228	/* Bit 5 : Pin 5. */
vcoubard	551:ab7a8de3ff10	2229	#define GPIO_DIR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	551:ab7a8de3ff10	2230	#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	551:ab7a8de3ff10	2231	#define GPIO_DIR_PIN5_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2232	#define GPIO_DIR_PIN5_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2233
vcoubard	551:ab7a8de3ff10	2234	/* Bit 4 : Pin 4. */
vcoubard	551:ab7a8de3ff10	2235	#define GPIO_DIR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	551:ab7a8de3ff10	2236	#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	551:ab7a8de3ff10	2237	#define GPIO_DIR_PIN4_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2238	#define GPIO_DIR_PIN4_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2239
vcoubard	551:ab7a8de3ff10	2240	/* Bit 3 : Pin 3. */
vcoubard	551:ab7a8de3ff10	2241	#define GPIO_DIR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	551:ab7a8de3ff10	2242	#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	551:ab7a8de3ff10	2243	#define GPIO_DIR_PIN3_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2244	#define GPIO_DIR_PIN3_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2245
vcoubard	551:ab7a8de3ff10	2246	/* Bit 2 : Pin 2. */
vcoubard	551:ab7a8de3ff10	2247	#define GPIO_DIR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	551:ab7a8de3ff10	2248	#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	551:ab7a8de3ff10	2249	#define GPIO_DIR_PIN2_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2250	#define GPIO_DIR_PIN2_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2251
vcoubard	551:ab7a8de3ff10	2252	/* Bit 1 : Pin 1. */
vcoubard	551:ab7a8de3ff10	2253	#define GPIO_DIR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	551:ab7a8de3ff10	2254	#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	551:ab7a8de3ff10	2255	#define GPIO_DIR_PIN1_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2256	#define GPIO_DIR_PIN1_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2257
vcoubard	551:ab7a8de3ff10	2258	/* Bit 0 : Pin 0. */
vcoubard	551:ab7a8de3ff10	2259	#define GPIO_DIR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	551:ab7a8de3ff10	2260	#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	551:ab7a8de3ff10	2261	#define GPIO_DIR_PIN0_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2262	#define GPIO_DIR_PIN0_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2263
vcoubard	551:ab7a8de3ff10	2264	/* Register: GPIO_DIRSET */
vcoubard	551:ab7a8de3ff10	2265	/* Description: DIR set register. */
vcoubard	551:ab7a8de3ff10	2266
vcoubard	551:ab7a8de3ff10	2267	/* Bit 31 : Set as output pin 31. */
vcoubard	551:ab7a8de3ff10	2268	#define GPIO_DIRSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	551:ab7a8de3ff10	2269	#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	551:ab7a8de3ff10	2270	#define GPIO_DIRSET_PIN31_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2271	#define GPIO_DIRSET_PIN31_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2272	#define GPIO_DIRSET_PIN31_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2273
vcoubard	551:ab7a8de3ff10	2274	/* Bit 30 : Set as output pin 30. */
vcoubard	551:ab7a8de3ff10	2275	#define GPIO_DIRSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	551:ab7a8de3ff10	2276	#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	551:ab7a8de3ff10	2277	#define GPIO_DIRSET_PIN30_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2278	#define GPIO_DIRSET_PIN30_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2279	#define GPIO_DIRSET_PIN30_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2280
vcoubard	551:ab7a8de3ff10	2281	/* Bit 29 : Set as output pin 29. */
vcoubard	551:ab7a8de3ff10	2282	#define GPIO_DIRSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	551:ab7a8de3ff10	2283	#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	551:ab7a8de3ff10	2284	#define GPIO_DIRSET_PIN29_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2285	#define GPIO_DIRSET_PIN29_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2286	#define GPIO_DIRSET_PIN29_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2287
vcoubard	551:ab7a8de3ff10	2288	/* Bit 28 : Set as output pin 28. */
vcoubard	551:ab7a8de3ff10	2289	#define GPIO_DIRSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	551:ab7a8de3ff10	2290	#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	551:ab7a8de3ff10	2291	#define GPIO_DIRSET_PIN28_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2292	#define GPIO_DIRSET_PIN28_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2293	#define GPIO_DIRSET_PIN28_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2294
vcoubard	551:ab7a8de3ff10	2295	/* Bit 27 : Set as output pin 27. */
vcoubard	551:ab7a8de3ff10	2296	#define GPIO_DIRSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	551:ab7a8de3ff10	2297	#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	551:ab7a8de3ff10	2298	#define GPIO_DIRSET_PIN27_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2299	#define GPIO_DIRSET_PIN27_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2300	#define GPIO_DIRSET_PIN27_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2301
vcoubard	551:ab7a8de3ff10	2302	/* Bit 26 : Set as output pin 26. */
vcoubard	551:ab7a8de3ff10	2303	#define GPIO_DIRSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	551:ab7a8de3ff10	2304	#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	551:ab7a8de3ff10	2305	#define GPIO_DIRSET_PIN26_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2306	#define GPIO_DIRSET_PIN26_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2307	#define GPIO_DIRSET_PIN26_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2308
vcoubard	551:ab7a8de3ff10	2309	/* Bit 25 : Set as output pin 25. */
vcoubard	551:ab7a8de3ff10	2310	#define GPIO_DIRSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	551:ab7a8de3ff10	2311	#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	551:ab7a8de3ff10	2312	#define GPIO_DIRSET_PIN25_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2313	#define GPIO_DIRSET_PIN25_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2314	#define GPIO_DIRSET_PIN25_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2315
vcoubard	551:ab7a8de3ff10	2316	/* Bit 24 : Set as output pin 24. */
vcoubard	551:ab7a8de3ff10	2317	#define GPIO_DIRSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	551:ab7a8de3ff10	2318	#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	551:ab7a8de3ff10	2319	#define GPIO_DIRSET_PIN24_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2320	#define GPIO_DIRSET_PIN24_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2321	#define GPIO_DIRSET_PIN24_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2322
vcoubard	551:ab7a8de3ff10	2323	/* Bit 23 : Set as output pin 23. */
vcoubard	551:ab7a8de3ff10	2324	#define GPIO_DIRSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	551:ab7a8de3ff10	2325	#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	551:ab7a8de3ff10	2326	#define GPIO_DIRSET_PIN23_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2327	#define GPIO_DIRSET_PIN23_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2328	#define GPIO_DIRSET_PIN23_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2329
vcoubard	551:ab7a8de3ff10	2330	/* Bit 22 : Set as output pin 22. */
vcoubard	551:ab7a8de3ff10	2331	#define GPIO_DIRSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	551:ab7a8de3ff10	2332	#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	551:ab7a8de3ff10	2333	#define GPIO_DIRSET_PIN22_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2334	#define GPIO_DIRSET_PIN22_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2335	#define GPIO_DIRSET_PIN22_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2336
vcoubard	551:ab7a8de3ff10	2337	/* Bit 21 : Set as output pin 21. */
vcoubard	551:ab7a8de3ff10	2338	#define GPIO_DIRSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	551:ab7a8de3ff10	2339	#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	551:ab7a8de3ff10	2340	#define GPIO_DIRSET_PIN21_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2341	#define GPIO_DIRSET_PIN21_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2342	#define GPIO_DIRSET_PIN21_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2343
vcoubard	551:ab7a8de3ff10	2344	/* Bit 20 : Set as output pin 20. */
vcoubard	551:ab7a8de3ff10	2345	#define GPIO_DIRSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	551:ab7a8de3ff10	2346	#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	551:ab7a8de3ff10	2347	#define GPIO_DIRSET_PIN20_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2348	#define GPIO_DIRSET_PIN20_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2349	#define GPIO_DIRSET_PIN20_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2350
vcoubard	551:ab7a8de3ff10	2351	/* Bit 19 : Set as output pin 19. */
vcoubard	551:ab7a8de3ff10	2352	#define GPIO_DIRSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	551:ab7a8de3ff10	2353	#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	551:ab7a8de3ff10	2354	#define GPIO_DIRSET_PIN19_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2355	#define GPIO_DIRSET_PIN19_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2356	#define GPIO_DIRSET_PIN19_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2357
vcoubard	551:ab7a8de3ff10	2358	/* Bit 18 : Set as output pin 18. */
vcoubard	551:ab7a8de3ff10	2359	#define GPIO_DIRSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	551:ab7a8de3ff10	2360	#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	551:ab7a8de3ff10	2361	#define GPIO_DIRSET_PIN18_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2362	#define GPIO_DIRSET_PIN18_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2363	#define GPIO_DIRSET_PIN18_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2364
vcoubard	551:ab7a8de3ff10	2365	/* Bit 17 : Set as output pin 17. */
vcoubard	551:ab7a8de3ff10	2366	#define GPIO_DIRSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	551:ab7a8de3ff10	2367	#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	551:ab7a8de3ff10	2368	#define GPIO_DIRSET_PIN17_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2369	#define GPIO_DIRSET_PIN17_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2370	#define GPIO_DIRSET_PIN17_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2371
vcoubard	551:ab7a8de3ff10	2372	/* Bit 16 : Set as output pin 16. */
vcoubard	551:ab7a8de3ff10	2373	#define GPIO_DIRSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	551:ab7a8de3ff10	2374	#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	551:ab7a8de3ff10	2375	#define GPIO_DIRSET_PIN16_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2376	#define GPIO_DIRSET_PIN16_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2377	#define GPIO_DIRSET_PIN16_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2378
vcoubard	551:ab7a8de3ff10	2379	/* Bit 15 : Set as output pin 15. */
vcoubard	551:ab7a8de3ff10	2380	#define GPIO_DIRSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	551:ab7a8de3ff10	2381	#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	551:ab7a8de3ff10	2382	#define GPIO_DIRSET_PIN15_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2383	#define GPIO_DIRSET_PIN15_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2384	#define GPIO_DIRSET_PIN15_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2385
vcoubard	551:ab7a8de3ff10	2386	/* Bit 14 : Set as output pin 14. */
vcoubard	551:ab7a8de3ff10	2387	#define GPIO_DIRSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	551:ab7a8de3ff10	2388	#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	551:ab7a8de3ff10	2389	#define GPIO_DIRSET_PIN14_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2390	#define GPIO_DIRSET_PIN14_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2391	#define GPIO_DIRSET_PIN14_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2392
vcoubard	551:ab7a8de3ff10	2393	/* Bit 13 : Set as output pin 13. */
vcoubard	551:ab7a8de3ff10	2394	#define GPIO_DIRSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	551:ab7a8de3ff10	2395	#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	551:ab7a8de3ff10	2396	#define GPIO_DIRSET_PIN13_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2397	#define GPIO_DIRSET_PIN13_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2398	#define GPIO_DIRSET_PIN13_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2399
vcoubard	551:ab7a8de3ff10	2400	/* Bit 12 : Set as output pin 12. */
vcoubard	551:ab7a8de3ff10	2401	#define GPIO_DIRSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	551:ab7a8de3ff10	2402	#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	551:ab7a8de3ff10	2403	#define GPIO_DIRSET_PIN12_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2404	#define GPIO_DIRSET_PIN12_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2405	#define GPIO_DIRSET_PIN12_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2406
vcoubard	551:ab7a8de3ff10	2407	/* Bit 11 : Set as output pin 11. */
vcoubard	551:ab7a8de3ff10	2408	#define GPIO_DIRSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	551:ab7a8de3ff10	2409	#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	551:ab7a8de3ff10	2410	#define GPIO_DIRSET_PIN11_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2411	#define GPIO_DIRSET_PIN11_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2412	#define GPIO_DIRSET_PIN11_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2413
vcoubard	551:ab7a8de3ff10	2414	/* Bit 10 : Set as output pin 10. */
vcoubard	551:ab7a8de3ff10	2415	#define GPIO_DIRSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	551:ab7a8de3ff10	2416	#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	551:ab7a8de3ff10	2417	#define GPIO_DIRSET_PIN10_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2418	#define GPIO_DIRSET_PIN10_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2419	#define GPIO_DIRSET_PIN10_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2420
vcoubard	551:ab7a8de3ff10	2421	/* Bit 9 : Set as output pin 9. */
vcoubard	551:ab7a8de3ff10	2422	#define GPIO_DIRSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	551:ab7a8de3ff10	2423	#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	551:ab7a8de3ff10	2424	#define GPIO_DIRSET_PIN9_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2425	#define GPIO_DIRSET_PIN9_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2426	#define GPIO_DIRSET_PIN9_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2427
vcoubard	551:ab7a8de3ff10	2428	/* Bit 8 : Set as output pin 8. */
vcoubard	551:ab7a8de3ff10	2429	#define GPIO_DIRSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	551:ab7a8de3ff10	2430	#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	551:ab7a8de3ff10	2431	#define GPIO_DIRSET_PIN8_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2432	#define GPIO_DIRSET_PIN8_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2433	#define GPIO_DIRSET_PIN8_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2434
vcoubard	551:ab7a8de3ff10	2435	/* Bit 7 : Set as output pin 7. */
vcoubard	551:ab7a8de3ff10	2436	#define GPIO_DIRSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	551:ab7a8de3ff10	2437	#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	551:ab7a8de3ff10	2438	#define GPIO_DIRSET_PIN7_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2439	#define GPIO_DIRSET_PIN7_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2440	#define GPIO_DIRSET_PIN7_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2441
vcoubard	551:ab7a8de3ff10	2442	/* Bit 6 : Set as output pin 6. */
vcoubard	551:ab7a8de3ff10	2443	#define GPIO_DIRSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	551:ab7a8de3ff10	2444	#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	551:ab7a8de3ff10	2445	#define GPIO_DIRSET_PIN6_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2446	#define GPIO_DIRSET_PIN6_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2447	#define GPIO_DIRSET_PIN6_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2448
vcoubard	551:ab7a8de3ff10	2449	/* Bit 5 : Set as output pin 5. */
vcoubard	551:ab7a8de3ff10	2450	#define GPIO_DIRSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	551:ab7a8de3ff10	2451	#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	551:ab7a8de3ff10	2452	#define GPIO_DIRSET_PIN5_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2453	#define GPIO_DIRSET_PIN5_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2454	#define GPIO_DIRSET_PIN5_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2455
vcoubard	551:ab7a8de3ff10	2456	/* Bit 4 : Set as output pin 4. */
vcoubard	551:ab7a8de3ff10	2457	#define GPIO_DIRSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	551:ab7a8de3ff10	2458	#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	551:ab7a8de3ff10	2459	#define GPIO_DIRSET_PIN4_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2460	#define GPIO_DIRSET_PIN4_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2461	#define GPIO_DIRSET_PIN4_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2462
vcoubard	551:ab7a8de3ff10	2463	/* Bit 3 : Set as output pin 3. */
vcoubard	551:ab7a8de3ff10	2464	#define GPIO_DIRSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	551:ab7a8de3ff10	2465	#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	551:ab7a8de3ff10	2466	#define GPIO_DIRSET_PIN3_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2467	#define GPIO_DIRSET_PIN3_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2468	#define GPIO_DIRSET_PIN3_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2469
vcoubard	551:ab7a8de3ff10	2470	/* Bit 2 : Set as output pin 2. */
vcoubard	551:ab7a8de3ff10	2471	#define GPIO_DIRSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	551:ab7a8de3ff10	2472	#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	551:ab7a8de3ff10	2473	#define GPIO_DIRSET_PIN2_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2474	#define GPIO_DIRSET_PIN2_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2475	#define GPIO_DIRSET_PIN2_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2476
vcoubard	551:ab7a8de3ff10	2477	/* Bit 1 : Set as output pin 1. */
vcoubard	551:ab7a8de3ff10	2478	#define GPIO_DIRSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	551:ab7a8de3ff10	2479	#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	551:ab7a8de3ff10	2480	#define GPIO_DIRSET_PIN1_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2481	#define GPIO_DIRSET_PIN1_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2482	#define GPIO_DIRSET_PIN1_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2483
vcoubard	551:ab7a8de3ff10	2484	/* Bit 0 : Set as output pin 0. */
vcoubard	551:ab7a8de3ff10	2485	#define GPIO_DIRSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	551:ab7a8de3ff10	2486	#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	551:ab7a8de3ff10	2487	#define GPIO_DIRSET_PIN0_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2488	#define GPIO_DIRSET_PIN0_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2489	#define GPIO_DIRSET_PIN0_Set (1UL) /!< Set pin as output. /
vcoubard	551:ab7a8de3ff10	2490
vcoubard	551:ab7a8de3ff10	2491	/* Register: GPIO_DIRCLR */
vcoubard	551:ab7a8de3ff10	2492	/* Description: DIR clear register. */
vcoubard	551:ab7a8de3ff10	2493
vcoubard	551:ab7a8de3ff10	2494	/* Bit 31 : Set as input pin 31. */
vcoubard	551:ab7a8de3ff10	2495	#define GPIO_DIRCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
vcoubard	551:ab7a8de3ff10	2496	#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
vcoubard	551:ab7a8de3ff10	2497	#define GPIO_DIRCLR_PIN31_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2498	#define GPIO_DIRCLR_PIN31_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2499	#define GPIO_DIRCLR_PIN31_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2500
vcoubard	551:ab7a8de3ff10	2501	/* Bit 30 : Set as input pin 30. */
vcoubard	551:ab7a8de3ff10	2502	#define GPIO_DIRCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
vcoubard	551:ab7a8de3ff10	2503	#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
vcoubard	551:ab7a8de3ff10	2504	#define GPIO_DIRCLR_PIN30_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2505	#define GPIO_DIRCLR_PIN30_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2506	#define GPIO_DIRCLR_PIN30_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2507
vcoubard	551:ab7a8de3ff10	2508	/* Bit 29 : Set as input pin 29. */
vcoubard	551:ab7a8de3ff10	2509	#define GPIO_DIRCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
vcoubard	551:ab7a8de3ff10	2510	#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
vcoubard	551:ab7a8de3ff10	2511	#define GPIO_DIRCLR_PIN29_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2512	#define GPIO_DIRCLR_PIN29_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2513	#define GPIO_DIRCLR_PIN29_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2514
vcoubard	551:ab7a8de3ff10	2515	/* Bit 28 : Set as input pin 28. */
vcoubard	551:ab7a8de3ff10	2516	#define GPIO_DIRCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
vcoubard	551:ab7a8de3ff10	2517	#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
vcoubard	551:ab7a8de3ff10	2518	#define GPIO_DIRCLR_PIN28_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2519	#define GPIO_DIRCLR_PIN28_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2520	#define GPIO_DIRCLR_PIN28_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2521
vcoubard	551:ab7a8de3ff10	2522	/* Bit 27 : Set as input pin 27. */
vcoubard	551:ab7a8de3ff10	2523	#define GPIO_DIRCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
vcoubard	551:ab7a8de3ff10	2524	#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
vcoubard	551:ab7a8de3ff10	2525	#define GPIO_DIRCLR_PIN27_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2526	#define GPIO_DIRCLR_PIN27_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2527	#define GPIO_DIRCLR_PIN27_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2528
vcoubard	551:ab7a8de3ff10	2529	/* Bit 26 : Set as input pin 26. */
vcoubard	551:ab7a8de3ff10	2530	#define GPIO_DIRCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
vcoubard	551:ab7a8de3ff10	2531	#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
vcoubard	551:ab7a8de3ff10	2532	#define GPIO_DIRCLR_PIN26_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2533	#define GPIO_DIRCLR_PIN26_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2534	#define GPIO_DIRCLR_PIN26_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2535
vcoubard	551:ab7a8de3ff10	2536	/* Bit 25 : Set as input pin 25. */
vcoubard	551:ab7a8de3ff10	2537	#define GPIO_DIRCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
vcoubard	551:ab7a8de3ff10	2538	#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
vcoubard	551:ab7a8de3ff10	2539	#define GPIO_DIRCLR_PIN25_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2540	#define GPIO_DIRCLR_PIN25_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2541	#define GPIO_DIRCLR_PIN25_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2542
vcoubard	551:ab7a8de3ff10	2543	/* Bit 24 : Set as input pin 24. */
vcoubard	551:ab7a8de3ff10	2544	#define GPIO_DIRCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
vcoubard	551:ab7a8de3ff10	2545	#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
vcoubard	551:ab7a8de3ff10	2546	#define GPIO_DIRCLR_PIN24_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2547	#define GPIO_DIRCLR_PIN24_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2548	#define GPIO_DIRCLR_PIN24_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2549
vcoubard	551:ab7a8de3ff10	2550	/* Bit 23 : Set as input pin 23. */
vcoubard	551:ab7a8de3ff10	2551	#define GPIO_DIRCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
vcoubard	551:ab7a8de3ff10	2552	#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
vcoubard	551:ab7a8de3ff10	2553	#define GPIO_DIRCLR_PIN23_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2554	#define GPIO_DIRCLR_PIN23_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2555	#define GPIO_DIRCLR_PIN23_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2556
vcoubard	551:ab7a8de3ff10	2557	/* Bit 22 : Set as input pin 22. */
vcoubard	551:ab7a8de3ff10	2558	#define GPIO_DIRCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
vcoubard	551:ab7a8de3ff10	2559	#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
vcoubard	551:ab7a8de3ff10	2560	#define GPIO_DIRCLR_PIN22_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2561	#define GPIO_DIRCLR_PIN22_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2562	#define GPIO_DIRCLR_PIN22_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2563
vcoubard	551:ab7a8de3ff10	2564	/* Bit 21 : Set as input pin 21. */
vcoubard	551:ab7a8de3ff10	2565	#define GPIO_DIRCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
vcoubard	551:ab7a8de3ff10	2566	#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
vcoubard	551:ab7a8de3ff10	2567	#define GPIO_DIRCLR_PIN21_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2568	#define GPIO_DIRCLR_PIN21_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2569	#define GPIO_DIRCLR_PIN21_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2570
vcoubard	551:ab7a8de3ff10	2571	/* Bit 20 : Set as input pin 20. */
vcoubard	551:ab7a8de3ff10	2572	#define GPIO_DIRCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
vcoubard	551:ab7a8de3ff10	2573	#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
vcoubard	551:ab7a8de3ff10	2574	#define GPIO_DIRCLR_PIN20_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2575	#define GPIO_DIRCLR_PIN20_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2576	#define GPIO_DIRCLR_PIN20_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2577
vcoubard	551:ab7a8de3ff10	2578	/* Bit 19 : Set as input pin 19. */
vcoubard	551:ab7a8de3ff10	2579	#define GPIO_DIRCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
vcoubard	551:ab7a8de3ff10	2580	#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
vcoubard	551:ab7a8de3ff10	2581	#define GPIO_DIRCLR_PIN19_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2582	#define GPIO_DIRCLR_PIN19_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2583	#define GPIO_DIRCLR_PIN19_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2584
vcoubard	551:ab7a8de3ff10	2585	/* Bit 18 : Set as input pin 18. */
vcoubard	551:ab7a8de3ff10	2586	#define GPIO_DIRCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
vcoubard	551:ab7a8de3ff10	2587	#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
vcoubard	551:ab7a8de3ff10	2588	#define GPIO_DIRCLR_PIN18_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2589	#define GPIO_DIRCLR_PIN18_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2590	#define GPIO_DIRCLR_PIN18_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2591
vcoubard	551:ab7a8de3ff10	2592	/* Bit 17 : Set as input pin 17. */
vcoubard	551:ab7a8de3ff10	2593	#define GPIO_DIRCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
vcoubard	551:ab7a8de3ff10	2594	#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
vcoubard	551:ab7a8de3ff10	2595	#define GPIO_DIRCLR_PIN17_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2596	#define GPIO_DIRCLR_PIN17_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2597	#define GPIO_DIRCLR_PIN17_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2598
vcoubard	551:ab7a8de3ff10	2599	/* Bit 16 : Set as input pin 16. */
vcoubard	551:ab7a8de3ff10	2600	#define GPIO_DIRCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
vcoubard	551:ab7a8de3ff10	2601	#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
vcoubard	551:ab7a8de3ff10	2602	#define GPIO_DIRCLR_PIN16_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2603	#define GPIO_DIRCLR_PIN16_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2604	#define GPIO_DIRCLR_PIN16_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2605
vcoubard	551:ab7a8de3ff10	2606	/* Bit 15 : Set as input pin 15. */
vcoubard	551:ab7a8de3ff10	2607	#define GPIO_DIRCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
vcoubard	551:ab7a8de3ff10	2608	#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
vcoubard	551:ab7a8de3ff10	2609	#define GPIO_DIRCLR_PIN15_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2610	#define GPIO_DIRCLR_PIN15_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2611	#define GPIO_DIRCLR_PIN15_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2612
vcoubard	551:ab7a8de3ff10	2613	/* Bit 14 : Set as input pin 14. */
vcoubard	551:ab7a8de3ff10	2614	#define GPIO_DIRCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
vcoubard	551:ab7a8de3ff10	2615	#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
vcoubard	551:ab7a8de3ff10	2616	#define GPIO_DIRCLR_PIN14_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2617	#define GPIO_DIRCLR_PIN14_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2618	#define GPIO_DIRCLR_PIN14_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2619
vcoubard	551:ab7a8de3ff10	2620	/* Bit 13 : Set as input pin 13. */
vcoubard	551:ab7a8de3ff10	2621	#define GPIO_DIRCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
vcoubard	551:ab7a8de3ff10	2622	#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
vcoubard	551:ab7a8de3ff10	2623	#define GPIO_DIRCLR_PIN13_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2624	#define GPIO_DIRCLR_PIN13_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2625	#define GPIO_DIRCLR_PIN13_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2626
vcoubard	551:ab7a8de3ff10	2627	/* Bit 12 : Set as input pin 12. */
vcoubard	551:ab7a8de3ff10	2628	#define GPIO_DIRCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
vcoubard	551:ab7a8de3ff10	2629	#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
vcoubard	551:ab7a8de3ff10	2630	#define GPIO_DIRCLR_PIN12_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2631	#define GPIO_DIRCLR_PIN12_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2632	#define GPIO_DIRCLR_PIN12_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2633
vcoubard	551:ab7a8de3ff10	2634	/* Bit 11 : Set as input pin 11. */
vcoubard	551:ab7a8de3ff10	2635	#define GPIO_DIRCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
vcoubard	551:ab7a8de3ff10	2636	#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
vcoubard	551:ab7a8de3ff10	2637	#define GPIO_DIRCLR_PIN11_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2638	#define GPIO_DIRCLR_PIN11_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2639	#define GPIO_DIRCLR_PIN11_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2640
vcoubard	551:ab7a8de3ff10	2641	/* Bit 10 : Set as input pin 10. */
vcoubard	551:ab7a8de3ff10	2642	#define GPIO_DIRCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
vcoubard	551:ab7a8de3ff10	2643	#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
vcoubard	551:ab7a8de3ff10	2644	#define GPIO_DIRCLR_PIN10_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2645	#define GPIO_DIRCLR_PIN10_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2646	#define GPIO_DIRCLR_PIN10_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2647
vcoubard	551:ab7a8de3ff10	2648	/* Bit 9 : Set as input pin 9. */
vcoubard	551:ab7a8de3ff10	2649	#define GPIO_DIRCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
vcoubard	551:ab7a8de3ff10	2650	#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
vcoubard	551:ab7a8de3ff10	2651	#define GPIO_DIRCLR_PIN9_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2652	#define GPIO_DIRCLR_PIN9_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2653	#define GPIO_DIRCLR_PIN9_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2654
vcoubard	551:ab7a8de3ff10	2655	/* Bit 8 : Set as input pin 8. */
vcoubard	551:ab7a8de3ff10	2656	#define GPIO_DIRCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
vcoubard	551:ab7a8de3ff10	2657	#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
vcoubard	551:ab7a8de3ff10	2658	#define GPIO_DIRCLR_PIN8_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2659	#define GPIO_DIRCLR_PIN8_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2660	#define GPIO_DIRCLR_PIN8_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2661
vcoubard	551:ab7a8de3ff10	2662	/* Bit 7 : Set as input pin 7. */
vcoubard	551:ab7a8de3ff10	2663	#define GPIO_DIRCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
vcoubard	551:ab7a8de3ff10	2664	#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
vcoubard	551:ab7a8de3ff10	2665	#define GPIO_DIRCLR_PIN7_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2666	#define GPIO_DIRCLR_PIN7_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2667	#define GPIO_DIRCLR_PIN7_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2668
vcoubard	551:ab7a8de3ff10	2669	/* Bit 6 : Set as input pin 6. */
vcoubard	551:ab7a8de3ff10	2670	#define GPIO_DIRCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
vcoubard	551:ab7a8de3ff10	2671	#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
vcoubard	551:ab7a8de3ff10	2672	#define GPIO_DIRCLR_PIN6_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2673	#define GPIO_DIRCLR_PIN6_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2674	#define GPIO_DIRCLR_PIN6_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2675
vcoubard	551:ab7a8de3ff10	2676	/* Bit 5 : Set as input pin 5. */
vcoubard	551:ab7a8de3ff10	2677	#define GPIO_DIRCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
vcoubard	551:ab7a8de3ff10	2678	#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
vcoubard	551:ab7a8de3ff10	2679	#define GPIO_DIRCLR_PIN5_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2680	#define GPIO_DIRCLR_PIN5_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2681	#define GPIO_DIRCLR_PIN5_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2682
vcoubard	551:ab7a8de3ff10	2683	/* Bit 4 : Set as input pin 4. */
vcoubard	551:ab7a8de3ff10	2684	#define GPIO_DIRCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
vcoubard	551:ab7a8de3ff10	2685	#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
vcoubard	551:ab7a8de3ff10	2686	#define GPIO_DIRCLR_PIN4_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2687	#define GPIO_DIRCLR_PIN4_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2688	#define GPIO_DIRCLR_PIN4_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2689
vcoubard	551:ab7a8de3ff10	2690	/* Bit 3 : Set as input pin 3. */
vcoubard	551:ab7a8de3ff10	2691	#define GPIO_DIRCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
vcoubard	551:ab7a8de3ff10	2692	#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
vcoubard	551:ab7a8de3ff10	2693	#define GPIO_DIRCLR_PIN3_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2694	#define GPIO_DIRCLR_PIN3_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2695	#define GPIO_DIRCLR_PIN3_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2696
vcoubard	551:ab7a8de3ff10	2697	/* Bit 2 : Set as input pin 2. */
vcoubard	551:ab7a8de3ff10	2698	#define GPIO_DIRCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
vcoubard	551:ab7a8de3ff10	2699	#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
vcoubard	551:ab7a8de3ff10	2700	#define GPIO_DIRCLR_PIN2_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2701	#define GPIO_DIRCLR_PIN2_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2702	#define GPIO_DIRCLR_PIN2_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2703
vcoubard	551:ab7a8de3ff10	2704	/* Bit 1 : Set as input pin 1. */
vcoubard	551:ab7a8de3ff10	2705	#define GPIO_DIRCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
vcoubard	551:ab7a8de3ff10	2706	#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
vcoubard	551:ab7a8de3ff10	2707	#define GPIO_DIRCLR_PIN1_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2708	#define GPIO_DIRCLR_PIN1_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2709	#define GPIO_DIRCLR_PIN1_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2710
vcoubard	551:ab7a8de3ff10	2711	/* Bit 0 : Set as input pin 0. */
vcoubard	551:ab7a8de3ff10	2712	#define GPIO_DIRCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
vcoubard	551:ab7a8de3ff10	2713	#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
vcoubard	551:ab7a8de3ff10	2714	#define GPIO_DIRCLR_PIN0_Input (0UL) /!< Pin set as input. /
vcoubard	551:ab7a8de3ff10	2715	#define GPIO_DIRCLR_PIN0_Output (1UL) /!< Pin set as output. /
vcoubard	551:ab7a8de3ff10	2716	#define GPIO_DIRCLR_PIN0_Clear (1UL) /!< Set pin as input. /
vcoubard	551:ab7a8de3ff10	2717
vcoubard	551:ab7a8de3ff10	2718	/* Register: GPIO_PIN_CNF */
vcoubard	551:ab7a8de3ff10	2719	/* Description: Configuration of GPIO pins. */
vcoubard	551:ab7a8de3ff10	2720
vcoubard	551:ab7a8de3ff10	2721	/* Bits 17..16 : Pin sensing mechanism. */
vcoubard	551:ab7a8de3ff10	2722	#define GPIO_PIN_CNF_SENSE_Pos (16UL) /!< Position of SENSE field. /
vcoubard	551:ab7a8de3ff10	2723	#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /!< Bit mask of SENSE field. /
vcoubard	551:ab7a8de3ff10	2724	#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /!< Disabled. /
vcoubard	551:ab7a8de3ff10	2725	#define GPIO_PIN_CNF_SENSE_High (0x02UL) /!< Wakeup on high level. /
vcoubard	551:ab7a8de3ff10	2726	#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /!< Wakeup on low level. /
vcoubard	551:ab7a8de3ff10	2727
vcoubard	551:ab7a8de3ff10	2728	/* Bits 10..8 : Drive configuration. */
vcoubard	551:ab7a8de3ff10	2729	#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /!< Position of DRIVE field. /
vcoubard	551:ab7a8de3ff10	2730	#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /!< Bit mask of DRIVE field. /
vcoubard	551:ab7a8de3ff10	2731	#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /!< Standard '0', Standard '1'. /
vcoubard	551:ab7a8de3ff10	2732	#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /!< High '0', Standard '1'. /
vcoubard	551:ab7a8de3ff10	2733	#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /!< Standard '0', High '1'. /
vcoubard	551:ab7a8de3ff10	2734	#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /!< High '0', High '1'. /
vcoubard	551:ab7a8de3ff10	2735	#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /!< Disconnected '0', Standard '1'. /
vcoubard	551:ab7a8de3ff10	2736	#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /!< Disconnected '0', High '1'. /
vcoubard	551:ab7a8de3ff10	2737	#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /!< Standard '0', Disconnected '1'. /
vcoubard	551:ab7a8de3ff10	2738	#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /!< High '0', Disconnected '1'. /
vcoubard	551:ab7a8de3ff10	2739
vcoubard	551:ab7a8de3ff10	2740	/* Bits 3..2 : Pull-up or -down configuration. */
vcoubard	551:ab7a8de3ff10	2741	#define GPIO_PIN_CNF_PULL_Pos (2UL) /!< Position of PULL field. /
vcoubard	551:ab7a8de3ff10	2742	#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /!< Bit mask of PULL field. /
vcoubard	551:ab7a8de3ff10	2743	#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /!< No pull. /
vcoubard	551:ab7a8de3ff10	2744	#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /!< Pulldown on pin. /
vcoubard	551:ab7a8de3ff10	2745	#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /!< Pullup on pin. /
vcoubard	551:ab7a8de3ff10	2746
vcoubard	551:ab7a8de3ff10	2747	/* Bit 1 : Connect or disconnect input path. */
vcoubard	551:ab7a8de3ff10	2748	#define GPIO_PIN_CNF_INPUT_Pos (1UL) /!< Position of INPUT field. /
vcoubard	551:ab7a8de3ff10	2749	#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /!< Bit mask of INPUT field. /
vcoubard	551:ab7a8de3ff10	2750	#define GPIO_PIN_CNF_INPUT_Connect (0UL) /!< Connect input pin. /
vcoubard	551:ab7a8de3ff10	2751	#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /!< Disconnect input pin. /
vcoubard	551:ab7a8de3ff10	2752
vcoubard	551:ab7a8de3ff10	2753	/* Bit 0 : Pin direction. */
vcoubard	551:ab7a8de3ff10	2754	#define GPIO_PIN_CNF_DIR_Pos (0UL) /!< Position of DIR field. /
vcoubard	551:ab7a8de3ff10	2755	#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /!< Bit mask of DIR field. /
vcoubard	551:ab7a8de3ff10	2756	#define GPIO_PIN_CNF_DIR_Input (0UL) /!< Configure pin as an input pin. /
vcoubard	551:ab7a8de3ff10	2757	#define GPIO_PIN_CNF_DIR_Output (1UL) /!< Configure pin as an output pin. /
vcoubard	551:ab7a8de3ff10	2758
vcoubard	551:ab7a8de3ff10	2759
vcoubard	551:ab7a8de3ff10	2760	/* Peripheral: GPIOTE */
vcoubard	551:ab7a8de3ff10	2761	/* Description: GPIO tasks and events. */
vcoubard	551:ab7a8de3ff10	2762
vcoubard	551:ab7a8de3ff10	2763	/* Register: GPIOTE_INTENSET */
vcoubard	551:ab7a8de3ff10	2764	/* Description: Interrupt enable set register. */
vcoubard	551:ab7a8de3ff10	2765
vcoubard	551:ab7a8de3ff10	2766	/* Bit 31 : Enable interrupt on PORT event. */
vcoubard	551:ab7a8de3ff10	2767	#define GPIOTE_INTENSET_PORT_Pos (31UL) /!< Position of PORT field. /
vcoubard	551:ab7a8de3ff10	2768	#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /!< Bit mask of PORT field. /
vcoubard	551:ab7a8de3ff10	2769	#define GPIOTE_INTENSET_PORT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	2770	#define GPIOTE_INTENSET_PORT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	2771	#define GPIOTE_INTENSET_PORT_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	2772
vcoubard	551:ab7a8de3ff10	2773	/* Bit 3 : Enable interrupt on IN[3] event. */
vcoubard	551:ab7a8de3ff10	2774	#define GPIOTE_INTENSET_IN3_Pos (3UL) /!< Position of IN3 field. /
vcoubard	551:ab7a8de3ff10	2775	#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /!< Bit mask of IN3 field. /
vcoubard	551:ab7a8de3ff10	2776	#define GPIOTE_INTENSET_IN3_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	2777	#define GPIOTE_INTENSET_IN3_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	2778	#define GPIOTE_INTENSET_IN3_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	2779
vcoubard	551:ab7a8de3ff10	2780	/* Bit 2 : Enable interrupt on IN[2] event. */
vcoubard	551:ab7a8de3ff10	2781	#define GPIOTE_INTENSET_IN2_Pos (2UL) /!< Position of IN2 field. /
vcoubard	551:ab7a8de3ff10	2782	#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /!< Bit mask of IN2 field. /
vcoubard	551:ab7a8de3ff10	2783	#define GPIOTE_INTENSET_IN2_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	2784	#define GPIOTE_INTENSET_IN2_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	2785	#define GPIOTE_INTENSET_IN2_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	2786
vcoubard	551:ab7a8de3ff10	2787	/* Bit 1 : Enable interrupt on IN[1] event. */
vcoubard	551:ab7a8de3ff10	2788	#define GPIOTE_INTENSET_IN1_Pos (1UL) /!< Position of IN1 field. /
vcoubard	551:ab7a8de3ff10	2789	#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /!< Bit mask of IN1 field. /
vcoubard	551:ab7a8de3ff10	2790	#define GPIOTE_INTENSET_IN1_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	2791	#define GPIOTE_INTENSET_IN1_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	2792	#define GPIOTE_INTENSET_IN1_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	2793
vcoubard	551:ab7a8de3ff10	2794	/* Bit 0 : Enable interrupt on IN[0] event. */
vcoubard	551:ab7a8de3ff10	2795	#define GPIOTE_INTENSET_IN0_Pos (0UL) /!< Position of IN0 field. /
vcoubard	551:ab7a8de3ff10	2796	#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /!< Bit mask of IN0 field. /
vcoubard	551:ab7a8de3ff10	2797	#define GPIOTE_INTENSET_IN0_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	2798	#define GPIOTE_INTENSET_IN0_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	2799	#define GPIOTE_INTENSET_IN0_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	2800
vcoubard	551:ab7a8de3ff10	2801	/* Register: GPIOTE_INTENCLR */
vcoubard	551:ab7a8de3ff10	2802	/* Description: Interrupt enable clear register. */
vcoubard	551:ab7a8de3ff10	2803
vcoubard	551:ab7a8de3ff10	2804	/* Bit 31 : Disable interrupt on PORT event. */
vcoubard	551:ab7a8de3ff10	2805	#define GPIOTE_INTENCLR_PORT_Pos (31UL) /!< Position of PORT field. /
vcoubard	551:ab7a8de3ff10	2806	#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /!< Bit mask of PORT field. /
vcoubard	551:ab7a8de3ff10	2807	#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	2808	#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	2809	#define GPIOTE_INTENCLR_PORT_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	2810
vcoubard	551:ab7a8de3ff10	2811	/* Bit 3 : Disable interrupt on IN[3] event. */
vcoubard	551:ab7a8de3ff10	2812	#define GPIOTE_INTENCLR_IN3_Pos (3UL) /!< Position of IN3 field. /
vcoubard	551:ab7a8de3ff10	2813	#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /!< Bit mask of IN3 field. /
vcoubard	551:ab7a8de3ff10	2814	#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	2815	#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	2816	#define GPIOTE_INTENCLR_IN3_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	2817
vcoubard	551:ab7a8de3ff10	2818	/* Bit 2 : Disable interrupt on IN[2] event. */
vcoubard	551:ab7a8de3ff10	2819	#define GPIOTE_INTENCLR_IN2_Pos (2UL) /!< Position of IN2 field. /
vcoubard	551:ab7a8de3ff10	2820	#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /!< Bit mask of IN2 field. /
vcoubard	551:ab7a8de3ff10	2821	#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	2822	#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	2823	#define GPIOTE_INTENCLR_IN2_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	2824
vcoubard	551:ab7a8de3ff10	2825	/* Bit 1 : Disable interrupt on IN[1] event. */
vcoubard	551:ab7a8de3ff10	2826	#define GPIOTE_INTENCLR_IN1_Pos (1UL) /!< Position of IN1 field. /
vcoubard	551:ab7a8de3ff10	2827	#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /!< Bit mask of IN1 field. /
vcoubard	551:ab7a8de3ff10	2828	#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	2829	#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	2830	#define GPIOTE_INTENCLR_IN1_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	2831
vcoubard	551:ab7a8de3ff10	2832	/* Bit 0 : Disable interrupt on IN[0] event. */
vcoubard	551:ab7a8de3ff10	2833	#define GPIOTE_INTENCLR_IN0_Pos (0UL) /!< Position of IN0 field. /
vcoubard	551:ab7a8de3ff10	2834	#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /!< Bit mask of IN0 field. /
vcoubard	551:ab7a8de3ff10	2835	#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	2836	#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	2837	#define GPIOTE_INTENCLR_IN0_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	2838
vcoubard	551:ab7a8de3ff10	2839	/* Register: GPIOTE_CONFIG */
vcoubard	551:ab7a8de3ff10	2840	/* Description: Channel configuration registers. */
vcoubard	551:ab7a8de3ff10	2841
vcoubard	551:ab7a8de3ff10	2842	/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
vcoubard	551:ab7a8de3ff10	2843	#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /!< Position of OUTINIT field. /
vcoubard	551:ab7a8de3ff10	2844	#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /!< Bit mask of OUTINIT field. /
vcoubard	551:ab7a8de3ff10	2845	#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /!< Initial low output when in task mode. /
vcoubard	551:ab7a8de3ff10	2846	#define GPIOTE_CONFIG_OUTINIT_High (1UL) /!< Initial high output when in task mode. /
vcoubard	551:ab7a8de3ff10	2847
vcoubard	551:ab7a8de3ff10	2848	/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
vcoubard	551:ab7a8de3ff10	2849	#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /!< Position of POLARITY field. /
vcoubard	551:ab7a8de3ff10	2850	#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /!< Bit mask of POLARITY field. /
vcoubard	551:ab7a8de3ff10	2851	#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /!< Low to high. /
vcoubard	551:ab7a8de3ff10	2852	#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /!< High to low. /
vcoubard	551:ab7a8de3ff10	2853	#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /!< Toggle. /
vcoubard	551:ab7a8de3ff10	2854
vcoubard	551:ab7a8de3ff10	2855	/* Bits 12..8 : Pin select. */
vcoubard	551:ab7a8de3ff10	2856	#define GPIOTE_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
vcoubard	551:ab7a8de3ff10	2857	#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
vcoubard	551:ab7a8de3ff10	2858
vcoubard	551:ab7a8de3ff10	2859	/* Bits 1..0 : Mode */
vcoubard	551:ab7a8de3ff10	2860	#define GPIOTE_CONFIG_MODE_Pos (0UL) /!< Position of MODE field. /
vcoubard	551:ab7a8de3ff10	2861	#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /!< Bit mask of MODE field. /
vcoubard	551:ab7a8de3ff10	2862	#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /!< Disabled. /
vcoubard	551:ab7a8de3ff10	2863	#define GPIOTE_CONFIG_MODE_Event (0x01UL) /!< Channel configure in event mode. /
vcoubard	551:ab7a8de3ff10	2864	#define GPIOTE_CONFIG_MODE_Task (0x03UL) /!< Channel configure in task mode. /
vcoubard	551:ab7a8de3ff10	2865
vcoubard	551:ab7a8de3ff10	2866	/* Register: GPIOTE_POWER */
vcoubard	551:ab7a8de3ff10	2867	/* Description: Peripheral power control. */
vcoubard	551:ab7a8de3ff10	2868
vcoubard	551:ab7a8de3ff10	2869	/* Bit 0 : Peripheral power control. */
vcoubard	551:ab7a8de3ff10	2870	#define GPIOTE_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	551:ab7a8de3ff10	2871	#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	551:ab7a8de3ff10	2872	#define GPIOTE_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	551:ab7a8de3ff10	2873	#define GPIOTE_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	551:ab7a8de3ff10	2874
vcoubard	551:ab7a8de3ff10	2875
vcoubard	551:ab7a8de3ff10	2876	/* Peripheral: LPCOMP */
vcoubard	551:ab7a8de3ff10	2877	/* Description: Low power comparator. */
vcoubard	551:ab7a8de3ff10	2878
vcoubard	551:ab7a8de3ff10	2879	/* Register: LPCOMP_SHORTS */
vcoubard	551:ab7a8de3ff10	2880	/* Description: Shortcuts for the LPCOMP. */
vcoubard	551:ab7a8de3ff10	2881
vcoubard	551:ab7a8de3ff10	2882	/* Bit 4 : Shortcut between CROSS event and STOP task. */
vcoubard	551:ab7a8de3ff10	2883	#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /!< Position of CROSS_STOP field. /
vcoubard	551:ab7a8de3ff10	2884	#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /!< Bit mask of CROSS_STOP field. /
vcoubard	551:ab7a8de3ff10	2885	#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	2886	#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	2887
vcoubard	551:ab7a8de3ff10	2888	/* Bit 3 : Shortcut between UP event and STOP task. */
vcoubard	551:ab7a8de3ff10	2889	#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /!< Position of UP_STOP field. /
vcoubard	551:ab7a8de3ff10	2890	#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /!< Bit mask of UP_STOP field. /
vcoubard	551:ab7a8de3ff10	2891	#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	2892	#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	2893
vcoubard	551:ab7a8de3ff10	2894	/* Bit 2 : Shortcut between DOWN event and STOP task. */
vcoubard	551:ab7a8de3ff10	2895	#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /!< Position of DOWN_STOP field. /
vcoubard	551:ab7a8de3ff10	2896	#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /!< Bit mask of DOWN_STOP field. /
vcoubard	551:ab7a8de3ff10	2897	#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	2898	#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	2899
vcoubard	551:ab7a8de3ff10	2900	/* Bit 1 : Shortcut between RADY event and STOP task. */
vcoubard	551:ab7a8de3ff10	2901	#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /!< Position of READY_STOP field. /
vcoubard	551:ab7a8de3ff10	2902	#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /!< Bit mask of READY_STOP field. /
vcoubard	551:ab7a8de3ff10	2903	#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	2904	#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	2905
vcoubard	551:ab7a8de3ff10	2906	/* Bit 0 : Shortcut between READY event and SAMPLE task. */
vcoubard	551:ab7a8de3ff10	2907	#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /!< Position of READY_SAMPLE field. /
vcoubard	551:ab7a8de3ff10	2908	#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /!< Bit mask of READY_SAMPLE field. /
vcoubard	551:ab7a8de3ff10	2909	#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	2910	#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	2911
vcoubard	551:ab7a8de3ff10	2912	/* Register: LPCOMP_INTENSET */
vcoubard	551:ab7a8de3ff10	2913	/* Description: Interrupt enable set register. */
vcoubard	551:ab7a8de3ff10	2914
vcoubard	551:ab7a8de3ff10	2915	/* Bit 3 : Enable interrupt on CROSS event. */
vcoubard	551:ab7a8de3ff10	2916	#define LPCOMP_INTENSET_CROSS_Pos (3UL) /!< Position of CROSS field. /
vcoubard	551:ab7a8de3ff10	2917	#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /!< Bit mask of CROSS field. /
vcoubard	551:ab7a8de3ff10	2918	#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	2919	#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	2920	#define LPCOMP_INTENSET_CROSS_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	2921
vcoubard	551:ab7a8de3ff10	2922	/* Bit 2 : Enable interrupt on UP event. */
vcoubard	551:ab7a8de3ff10	2923	#define LPCOMP_INTENSET_UP_Pos (2UL) /!< Position of UP field. /
vcoubard	551:ab7a8de3ff10	2924	#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /!< Bit mask of UP field. /
vcoubard	551:ab7a8de3ff10	2925	#define LPCOMP_INTENSET_UP_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	2926	#define LPCOMP_INTENSET_UP_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	2927	#define LPCOMP_INTENSET_UP_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	2928
vcoubard	551:ab7a8de3ff10	2929	/* Bit 1 : Enable interrupt on DOWN event. */
vcoubard	551:ab7a8de3ff10	2930	#define LPCOMP_INTENSET_DOWN_Pos (1UL) /!< Position of DOWN field. /
vcoubard	551:ab7a8de3ff10	2931	#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /!< Bit mask of DOWN field. /
vcoubard	551:ab7a8de3ff10	2932	#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	2933	#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	2934	#define LPCOMP_INTENSET_DOWN_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	2935
vcoubard	551:ab7a8de3ff10	2936	/* Bit 0 : Enable interrupt on READY event. */
vcoubard	551:ab7a8de3ff10	2937	#define LPCOMP_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
vcoubard	551:ab7a8de3ff10	2938	#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /!< Bit mask of READY field. /
vcoubard	551:ab7a8de3ff10	2939	#define LPCOMP_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	2940	#define LPCOMP_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	2941	#define LPCOMP_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	2942
vcoubard	551:ab7a8de3ff10	2943	/* Register: LPCOMP_INTENCLR */
vcoubard	551:ab7a8de3ff10	2944	/* Description: Interrupt enable clear register. */
vcoubard	551:ab7a8de3ff10	2945
vcoubard	551:ab7a8de3ff10	2946	/* Bit 3 : Disable interrupt on CROSS event. */
vcoubard	551:ab7a8de3ff10	2947	#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /!< Position of CROSS field. /
vcoubard	551:ab7a8de3ff10	2948	#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /!< Bit mask of CROSS field. /
vcoubard	551:ab7a8de3ff10	2949	#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	2950	#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	2951	#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	2952
vcoubard	551:ab7a8de3ff10	2953	/* Bit 2 : Disable interrupt on UP event. */
vcoubard	551:ab7a8de3ff10	2954	#define LPCOMP_INTENCLR_UP_Pos (2UL) /!< Position of UP field. /
vcoubard	551:ab7a8de3ff10	2955	#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /!< Bit mask of UP field. /
vcoubard	551:ab7a8de3ff10	2956	#define LPCOMP_INTENCLR_UP_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	2957	#define LPCOMP_INTENCLR_UP_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	2958	#define LPCOMP_INTENCLR_UP_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	2959
vcoubard	551:ab7a8de3ff10	2960	/* Bit 1 : Disable interrupt on DOWN event. */
vcoubard	551:ab7a8de3ff10	2961	#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /!< Position of DOWN field. /
vcoubard	551:ab7a8de3ff10	2962	#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /!< Bit mask of DOWN field. /
vcoubard	551:ab7a8de3ff10	2963	#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	2964	#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	2965	#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	2966
vcoubard	551:ab7a8de3ff10	2967	/* Bit 0 : Disable interrupt on READY event. */
vcoubard	551:ab7a8de3ff10	2968	#define LPCOMP_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
vcoubard	551:ab7a8de3ff10	2969	#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
vcoubard	551:ab7a8de3ff10	2970	#define LPCOMP_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	2971	#define LPCOMP_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	2972	#define LPCOMP_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	2973
vcoubard	551:ab7a8de3ff10	2974	/* Register: LPCOMP_RESULT */
vcoubard	551:ab7a8de3ff10	2975	/* Description: Result of last compare. */
vcoubard	551:ab7a8de3ff10	2976
vcoubard	551:ab7a8de3ff10	2977	/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
vcoubard	551:ab7a8de3ff10	2978	#define LPCOMP_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
vcoubard	551:ab7a8de3ff10	2979	#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
vcoubard	551:ab7a8de3ff10	2980	#define LPCOMP_RESULT_RESULT_Bellow (0UL) /!< Input voltage is bellow the reference threshold. /
vcoubard	551:ab7a8de3ff10	2981	#define LPCOMP_RESULT_RESULT_Above (1UL) /!< Input voltage is above the reference threshold. /
vcoubard	551:ab7a8de3ff10	2982
vcoubard	551:ab7a8de3ff10	2983	/* Register: LPCOMP_ENABLE */
vcoubard	551:ab7a8de3ff10	2984	/* Description: Enable the LPCOMP. */
vcoubard	551:ab7a8de3ff10	2985
vcoubard	551:ab7a8de3ff10	2986	/* Bits 1..0 : Enable or disable LPCOMP. */
vcoubard	551:ab7a8de3ff10	2987	#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	551:ab7a8de3ff10	2988	#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	551:ab7a8de3ff10	2989	#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled LPCOMP. /
vcoubard	551:ab7a8de3ff10	2990	#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable LPCOMP. /
vcoubard	551:ab7a8de3ff10	2991
vcoubard	551:ab7a8de3ff10	2992	/* Register: LPCOMP_PSEL */
vcoubard	551:ab7a8de3ff10	2993	/* Description: Input pin select. */
vcoubard	551:ab7a8de3ff10	2994
vcoubard	551:ab7a8de3ff10	2995	/* Bits 2..0 : Analog input pin select. */
vcoubard	551:ab7a8de3ff10	2996	#define LPCOMP_PSEL_PSEL_Pos (0UL) /!< Position of PSEL field. /
vcoubard	551:ab7a8de3ff10	2997	#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /!< Bit mask of PSEL field. /
vcoubard	551:ab7a8de3ff10	2998	#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /!< Use analog input 0 as analog input. /
vcoubard	551:ab7a8de3ff10	2999	#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /!< Use analog input 1 as analog input. /
vcoubard	551:ab7a8de3ff10	3000	#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /!< Use analog input 2 as analog input. /
vcoubard	551:ab7a8de3ff10	3001	#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /!< Use analog input 3 as analog input. /
vcoubard	551:ab7a8de3ff10	3002	#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /!< Use analog input 4 as analog input. /
vcoubard	551:ab7a8de3ff10	3003	#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /!< Use analog input 5 as analog input. /
vcoubard	551:ab7a8de3ff10	3004	#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /!< Use analog input 6 as analog input. /
vcoubard	551:ab7a8de3ff10	3005	#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /!< Use analog input 7 as analog input. /
vcoubard	551:ab7a8de3ff10	3006
vcoubard	551:ab7a8de3ff10	3007	/* Register: LPCOMP_REFSEL */
vcoubard	551:ab7a8de3ff10	3008	/* Description: Reference select. */
vcoubard	551:ab7a8de3ff10	3009
vcoubard	551:ab7a8de3ff10	3010	/* Bits 2..0 : Reference select. */
vcoubard	551:ab7a8de3ff10	3011	#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /!< Position of REFSEL field. /
vcoubard	551:ab7a8de3ff10	3012	#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /!< Bit mask of REFSEL field. /
vcoubard	551:ab7a8de3ff10	3013	#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /!< Use supply with a 1/8 prescaler as reference. /
vcoubard	551:ab7a8de3ff10	3014	#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /!< Use supply with a 2/8 prescaler as reference. /
vcoubard	551:ab7a8de3ff10	3015	#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /!< Use supply with a 3/8 prescaler as reference. /
vcoubard	551:ab7a8de3ff10	3016	#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /!< Use supply with a 4/8 prescaler as reference. /
vcoubard	551:ab7a8de3ff10	3017	#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /!< Use supply with a 5/8 prescaler as reference. /
vcoubard	551:ab7a8de3ff10	3018	#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /!< Use supply with a 6/8 prescaler as reference. /
vcoubard	551:ab7a8de3ff10	3019	#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /!< Use supply with a 7/8 prescaler as reference. /
vcoubard	551:ab7a8de3ff10	3020	#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /!< Use external analog reference as reference. /
vcoubard	551:ab7a8de3ff10	3021
vcoubard	551:ab7a8de3ff10	3022	/* Register: LPCOMP_EXTREFSEL */
vcoubard	551:ab7a8de3ff10	3023	/* Description: External reference select. */
vcoubard	551:ab7a8de3ff10	3024
vcoubard	551:ab7a8de3ff10	3025	/* Bit 0 : External analog reference pin selection. */
vcoubard	551:ab7a8de3ff10	3026	#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /!< Position of EXTREFSEL field. /
vcoubard	551:ab7a8de3ff10	3027	#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
vcoubard	551:ab7a8de3ff10	3028	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /!< Use analog reference 0 as reference. /
vcoubard	551:ab7a8de3ff10	3029	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /!< Use analog reference 1 as reference. /
vcoubard	551:ab7a8de3ff10	3030
vcoubard	551:ab7a8de3ff10	3031	/* Register: LPCOMP_ANADETECT */
vcoubard	551:ab7a8de3ff10	3032	/* Description: Analog detect configuration. */
vcoubard	551:ab7a8de3ff10	3033
vcoubard	551:ab7a8de3ff10	3034	/* Bits 1..0 : Analog detect configuration. */
vcoubard	551:ab7a8de3ff10	3035	#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /!< Position of ANADETECT field. /
vcoubard	551:ab7a8de3ff10	3036	#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /!< Bit mask of ANADETECT field. /
vcoubard	551:ab7a8de3ff10	3037	#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /!< Generate ANADETEC on crossing, both upwards and downwards crossing. /
vcoubard	551:ab7a8de3ff10	3038	#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /!< Generate ANADETEC on upwards crossing only. /
vcoubard	551:ab7a8de3ff10	3039	#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /!< Generate ANADETEC on downwards crossing only. /
vcoubard	551:ab7a8de3ff10	3040
vcoubard	551:ab7a8de3ff10	3041	/* Register: LPCOMP_POWER */
vcoubard	551:ab7a8de3ff10	3042	/* Description: Peripheral power control. */
vcoubard	551:ab7a8de3ff10	3043
vcoubard	551:ab7a8de3ff10	3044	/* Bit 0 : Peripheral power control. */
vcoubard	551:ab7a8de3ff10	3045	#define LPCOMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	551:ab7a8de3ff10	3046	#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	551:ab7a8de3ff10	3047	#define LPCOMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	551:ab7a8de3ff10	3048	#define LPCOMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	551:ab7a8de3ff10	3049
vcoubard	551:ab7a8de3ff10	3050
vcoubard	551:ab7a8de3ff10	3051	/* Peripheral: MPU */
vcoubard	551:ab7a8de3ff10	3052	/* Description: Memory Protection Unit. */
vcoubard	551:ab7a8de3ff10	3053
vcoubard	551:ab7a8de3ff10	3054	/* Register: MPU_PERR0 */
vcoubard	551:ab7a8de3ff10	3055	/* Description: Configuration of peripherals in mpu regions. */
vcoubard	551:ab7a8de3ff10	3056
vcoubard	551:ab7a8de3ff10	3057	/* Bit 31 : PPI region configuration. */
vcoubard	551:ab7a8de3ff10	3058	#define MPU_PERR0_PPI_Pos (31UL) /!< Position of PPI field. /
vcoubard	551:ab7a8de3ff10	3059	#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /!< Bit mask of PPI field. /
vcoubard	551:ab7a8de3ff10	3060	#define MPU_PERR0_PPI_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3061	#define MPU_PERR0_PPI_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3062
vcoubard	551:ab7a8de3ff10	3063	/* Bit 30 : NVMC region configuration. */
vcoubard	551:ab7a8de3ff10	3064	#define MPU_PERR0_NVMC_Pos (30UL) /!< Position of NVMC field. /
vcoubard	551:ab7a8de3ff10	3065	#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /!< Bit mask of NVMC field. /
vcoubard	551:ab7a8de3ff10	3066	#define MPU_PERR0_NVMC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3067	#define MPU_PERR0_NVMC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3068
vcoubard	551:ab7a8de3ff10	3069	/* Bit 19 : LPCOMP region configuration. */
vcoubard	551:ab7a8de3ff10	3070	#define MPU_PERR0_LPCOMP_Pos (19UL) /!< Position of LPCOMP field. /
vcoubard	551:ab7a8de3ff10	3071	#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
vcoubard	551:ab7a8de3ff10	3072	#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3073	#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3074
vcoubard	551:ab7a8de3ff10	3075	/* Bit 18 : QDEC region configuration. */
vcoubard	551:ab7a8de3ff10	3076	#define MPU_PERR0_QDEC_Pos (18UL) /!< Position of QDEC field. /
vcoubard	551:ab7a8de3ff10	3077	#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /!< Bit mask of QDEC field. /
vcoubard	551:ab7a8de3ff10	3078	#define MPU_PERR0_QDEC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3079	#define MPU_PERR0_QDEC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3080
vcoubard	551:ab7a8de3ff10	3081	/* Bit 17 : RTC1 region configuration. */
vcoubard	551:ab7a8de3ff10	3082	#define MPU_PERR0_RTC1_Pos (17UL) /!< Position of RTC1 field. /
vcoubard	551:ab7a8de3ff10	3083	#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /!< Bit mask of RTC1 field. /
vcoubard	551:ab7a8de3ff10	3084	#define MPU_PERR0_RTC1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3085	#define MPU_PERR0_RTC1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3086
vcoubard	551:ab7a8de3ff10	3087	/* Bit 16 : WDT region configuration. */
vcoubard	551:ab7a8de3ff10	3088	#define MPU_PERR0_WDT_Pos (16UL) /!< Position of WDT field. /
vcoubard	551:ab7a8de3ff10	3089	#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /!< Bit mask of WDT field. /
vcoubard	551:ab7a8de3ff10	3090	#define MPU_PERR0_WDT_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3091	#define MPU_PERR0_WDT_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3092
vcoubard	551:ab7a8de3ff10	3093	/* Bit 15 : CCM and AAR region configuration. */
vcoubard	551:ab7a8de3ff10	3094	#define MPU_PERR0_CCM_AAR_Pos (15UL) /!< Position of CCM_AAR field. /
vcoubard	551:ab7a8de3ff10	3095	#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /!< Bit mask of CCM_AAR field. /
vcoubard	551:ab7a8de3ff10	3096	#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3097	#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3098
vcoubard	551:ab7a8de3ff10	3099	/* Bit 14 : ECB region configuration. */
vcoubard	551:ab7a8de3ff10	3100	#define MPU_PERR0_ECB_Pos (14UL) /!< Position of ECB field. /
vcoubard	551:ab7a8de3ff10	3101	#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /!< Bit mask of ECB field. /
vcoubard	551:ab7a8de3ff10	3102	#define MPU_PERR0_ECB_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3103	#define MPU_PERR0_ECB_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3104
vcoubard	551:ab7a8de3ff10	3105	/* Bit 13 : RNG region configuration. */
vcoubard	551:ab7a8de3ff10	3106	#define MPU_PERR0_RNG_Pos (13UL) /!< Position of RNG field. /
vcoubard	551:ab7a8de3ff10	3107	#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /!< Bit mask of RNG field. /
vcoubard	551:ab7a8de3ff10	3108	#define MPU_PERR0_RNG_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3109	#define MPU_PERR0_RNG_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3110
vcoubard	551:ab7a8de3ff10	3111	/* Bit 12 : TEMP region configuration. */
vcoubard	551:ab7a8de3ff10	3112	#define MPU_PERR0_TEMP_Pos (12UL) /!< Position of TEMP field. /
vcoubard	551:ab7a8de3ff10	3113	#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /!< Bit mask of TEMP field. /
vcoubard	551:ab7a8de3ff10	3114	#define MPU_PERR0_TEMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3115	#define MPU_PERR0_TEMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3116
vcoubard	551:ab7a8de3ff10	3117	/* Bit 11 : RTC0 region configuration. */
vcoubard	551:ab7a8de3ff10	3118	#define MPU_PERR0_RTC0_Pos (11UL) /!< Position of RTC0 field. /
vcoubard	551:ab7a8de3ff10	3119	#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /!< Bit mask of RTC0 field. /
vcoubard	551:ab7a8de3ff10	3120	#define MPU_PERR0_RTC0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3121	#define MPU_PERR0_RTC0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3122
vcoubard	551:ab7a8de3ff10	3123	/* Bit 10 : TIMER2 region configuration. */
vcoubard	551:ab7a8de3ff10	3124	#define MPU_PERR0_TIMER2_Pos (10UL) /!< Position of TIMER2 field. /
vcoubard	551:ab7a8de3ff10	3125	#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /!< Bit mask of TIMER2 field. /
vcoubard	551:ab7a8de3ff10	3126	#define MPU_PERR0_TIMER2_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3127	#define MPU_PERR0_TIMER2_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3128
vcoubard	551:ab7a8de3ff10	3129	/* Bit 9 : TIMER1 region configuration. */
vcoubard	551:ab7a8de3ff10	3130	#define MPU_PERR0_TIMER1_Pos (9UL) /!< Position of TIMER1 field. /
vcoubard	551:ab7a8de3ff10	3131	#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /!< Bit mask of TIMER1 field. /
vcoubard	551:ab7a8de3ff10	3132	#define MPU_PERR0_TIMER1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3133	#define MPU_PERR0_TIMER1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3134
vcoubard	551:ab7a8de3ff10	3135	/* Bit 8 : TIMER0 region configuration. */
vcoubard	551:ab7a8de3ff10	3136	#define MPU_PERR0_TIMER0_Pos (8UL) /!< Position of TIMER0 field. /
vcoubard	551:ab7a8de3ff10	3137	#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /!< Bit mask of TIMER0 field. /
vcoubard	551:ab7a8de3ff10	3138	#define MPU_PERR0_TIMER0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3139	#define MPU_PERR0_TIMER0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3140
vcoubard	551:ab7a8de3ff10	3141	/* Bit 7 : ADC region configuration. */
vcoubard	551:ab7a8de3ff10	3142	#define MPU_PERR0_ADC_Pos (7UL) /!< Position of ADC field. /
vcoubard	551:ab7a8de3ff10	3143	#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /!< Bit mask of ADC field. /
vcoubard	551:ab7a8de3ff10	3144	#define MPU_PERR0_ADC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3145	#define MPU_PERR0_ADC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3146
vcoubard	551:ab7a8de3ff10	3147	/* Bit 6 : GPIOTE region configuration. */
vcoubard	551:ab7a8de3ff10	3148	#define MPU_PERR0_GPIOTE_Pos (6UL) /!< Position of GPIOTE field. /
vcoubard	551:ab7a8de3ff10	3149	#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /!< Bit mask of GPIOTE field. /
vcoubard	551:ab7a8de3ff10	3150	#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3151	#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3152
vcoubard	551:ab7a8de3ff10	3153	/* Bit 4 : SPI1 and TWI1 region configuration. */
vcoubard	551:ab7a8de3ff10	3154	#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /!< Position of SPI1_TWI1 field. /
vcoubard	551:ab7a8de3ff10	3155	#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /!< Bit mask of SPI1_TWI1 field. /
vcoubard	551:ab7a8de3ff10	3156	#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3157	#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3158
vcoubard	551:ab7a8de3ff10	3159	/* Bit 3 : SPI0 and TWI0 region configuration. */
vcoubard	551:ab7a8de3ff10	3160	#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /!< Position of SPI0_TWI0 field. /
vcoubard	551:ab7a8de3ff10	3161	#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /!< Bit mask of SPI0_TWI0 field. /
vcoubard	551:ab7a8de3ff10	3162	#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3163	#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3164
vcoubard	551:ab7a8de3ff10	3165	/* Bit 2 : UART0 region configuration. */
vcoubard	551:ab7a8de3ff10	3166	#define MPU_PERR0_UART0_Pos (2UL) /!< Position of UART0 field. /
vcoubard	551:ab7a8de3ff10	3167	#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /!< Bit mask of UART0 field. /
vcoubard	551:ab7a8de3ff10	3168	#define MPU_PERR0_UART0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3169	#define MPU_PERR0_UART0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3170
vcoubard	551:ab7a8de3ff10	3171	/* Bit 1 : RADIO region configuration. */
vcoubard	551:ab7a8de3ff10	3172	#define MPU_PERR0_RADIO_Pos (1UL) /!< Position of RADIO field. /
vcoubard	551:ab7a8de3ff10	3173	#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /!< Bit mask of RADIO field. /
vcoubard	551:ab7a8de3ff10	3174	#define MPU_PERR0_RADIO_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3175	#define MPU_PERR0_RADIO_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3176
vcoubard	551:ab7a8de3ff10	3177	/* Bit 0 : POWER_CLOCK region configuration. */
vcoubard	551:ab7a8de3ff10	3178	#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /!< Position of POWER_CLOCK field. /
vcoubard	551:ab7a8de3ff10	3179	#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /!< Bit mask of POWER_CLOCK field. /
vcoubard	551:ab7a8de3ff10	3180	#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /!< Peripheral configured in region 1. /
vcoubard	551:ab7a8de3ff10	3181	#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /!< Peripheral configured in region 0. /
vcoubard	551:ab7a8de3ff10	3182
vcoubard	551:ab7a8de3ff10	3183	/* Register: MPU_PROTENSET0 */
vcoubard	551:ab7a8de3ff10	3184	/* Description: Erase and write protection bit enable set register. */
vcoubard	551:ab7a8de3ff10	3185
vcoubard	551:ab7a8de3ff10	3186	/* Bit 31 : Protection enable for region 31. */
vcoubard	551:ab7a8de3ff10	3187	#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /!< Position of PROTREG31 field. /
vcoubard	551:ab7a8de3ff10	3188	#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /!< Bit mask of PROTREG31 field. /
vcoubard	551:ab7a8de3ff10	3189	#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3190	#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3191	#define MPU_PROTENSET0_PROTREG31_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3192
vcoubard	551:ab7a8de3ff10	3193	/* Bit 30 : Protection enable for region 30. */
vcoubard	551:ab7a8de3ff10	3194	#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /!< Position of PROTREG30 field. /
vcoubard	551:ab7a8de3ff10	3195	#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /!< Bit mask of PROTREG30 field. /
vcoubard	551:ab7a8de3ff10	3196	#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3197	#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3198	#define MPU_PROTENSET0_PROTREG30_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3199
vcoubard	551:ab7a8de3ff10	3200	/* Bit 29 : Protection enable for region 29. */
vcoubard	551:ab7a8de3ff10	3201	#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /!< Position of PROTREG29 field. /
vcoubard	551:ab7a8de3ff10	3202	#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /!< Bit mask of PROTREG29 field. /
vcoubard	551:ab7a8de3ff10	3203	#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3204	#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3205	#define MPU_PROTENSET0_PROTREG29_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3206
vcoubard	551:ab7a8de3ff10	3207	/* Bit 28 : Protection enable for region 28. */
vcoubard	551:ab7a8de3ff10	3208	#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /!< Position of PROTREG28 field. /
vcoubard	551:ab7a8de3ff10	3209	#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /!< Bit mask of PROTREG28 field. /
vcoubard	551:ab7a8de3ff10	3210	#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3211	#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3212	#define MPU_PROTENSET0_PROTREG28_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3213
vcoubard	551:ab7a8de3ff10	3214	/* Bit 27 : Protection enable for region 27. */
vcoubard	551:ab7a8de3ff10	3215	#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /!< Position of PROTREG27 field. /
vcoubard	551:ab7a8de3ff10	3216	#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /!< Bit mask of PROTREG27 field. /
vcoubard	551:ab7a8de3ff10	3217	#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3218	#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3219	#define MPU_PROTENSET0_PROTREG27_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3220
vcoubard	551:ab7a8de3ff10	3221	/* Bit 26 : Protection enable for region 26. */
vcoubard	551:ab7a8de3ff10	3222	#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /!< Position of PROTREG26 field. /
vcoubard	551:ab7a8de3ff10	3223	#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /!< Bit mask of PROTREG26 field. /
vcoubard	551:ab7a8de3ff10	3224	#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3225	#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3226	#define MPU_PROTENSET0_PROTREG26_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3227
vcoubard	551:ab7a8de3ff10	3228	/* Bit 25 : Protection enable for region 25. */
vcoubard	551:ab7a8de3ff10	3229	#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /!< Position of PROTREG25 field. /
vcoubard	551:ab7a8de3ff10	3230	#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /!< Bit mask of PROTREG25 field. /
vcoubard	551:ab7a8de3ff10	3231	#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3232	#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3233	#define MPU_PROTENSET0_PROTREG25_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3234
vcoubard	551:ab7a8de3ff10	3235	/* Bit 24 : Protection enable for region 24. */
vcoubard	551:ab7a8de3ff10	3236	#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /!< Position of PROTREG24 field. /
vcoubard	551:ab7a8de3ff10	3237	#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /!< Bit mask of PROTREG24 field. /
vcoubard	551:ab7a8de3ff10	3238	#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3239	#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3240	#define MPU_PROTENSET0_PROTREG24_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3241
vcoubard	551:ab7a8de3ff10	3242	/* Bit 23 : Protection enable for region 23. */
vcoubard	551:ab7a8de3ff10	3243	#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /!< Position of PROTREG23 field. /
vcoubard	551:ab7a8de3ff10	3244	#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /!< Bit mask of PROTREG23 field. /
vcoubard	551:ab7a8de3ff10	3245	#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3246	#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3247	#define MPU_PROTENSET0_PROTREG23_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3248
vcoubard	551:ab7a8de3ff10	3249	/* Bit 22 : Protection enable for region 22. */
vcoubard	551:ab7a8de3ff10	3250	#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /!< Position of PROTREG22 field. /
vcoubard	551:ab7a8de3ff10	3251	#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /!< Bit mask of PROTREG22 field. /
vcoubard	551:ab7a8de3ff10	3252	#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3253	#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3254	#define MPU_PROTENSET0_PROTREG22_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3255
vcoubard	551:ab7a8de3ff10	3256	/* Bit 21 : Protection enable for region 21. */
vcoubard	551:ab7a8de3ff10	3257	#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /!< Position of PROTREG21 field. /
vcoubard	551:ab7a8de3ff10	3258	#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /!< Bit mask of PROTREG21 field. /
vcoubard	551:ab7a8de3ff10	3259	#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3260	#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3261	#define MPU_PROTENSET0_PROTREG21_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3262
vcoubard	551:ab7a8de3ff10	3263	/* Bit 20 : Protection enable for region 20. */
vcoubard	551:ab7a8de3ff10	3264	#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /!< Position of PROTREG20 field. /
vcoubard	551:ab7a8de3ff10	3265	#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /!< Bit mask of PROTREG20 field. /
vcoubard	551:ab7a8de3ff10	3266	#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3267	#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3268	#define MPU_PROTENSET0_PROTREG20_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3269
vcoubard	551:ab7a8de3ff10	3270	/* Bit 19 : Protection enable for region 19. */
vcoubard	551:ab7a8de3ff10	3271	#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /!< Position of PROTREG19 field. /
vcoubard	551:ab7a8de3ff10	3272	#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /!< Bit mask of PROTREG19 field. /
vcoubard	551:ab7a8de3ff10	3273	#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3274	#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3275	#define MPU_PROTENSET0_PROTREG19_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3276
vcoubard	551:ab7a8de3ff10	3277	/* Bit 18 : Protection enable for region 18. */
vcoubard	551:ab7a8de3ff10	3278	#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /!< Position of PROTREG18 field. /
vcoubard	551:ab7a8de3ff10	3279	#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /!< Bit mask of PROTREG18 field. /
vcoubard	551:ab7a8de3ff10	3280	#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3281	#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3282	#define MPU_PROTENSET0_PROTREG18_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3283
vcoubard	551:ab7a8de3ff10	3284	/* Bit 17 : Protection enable for region 17. */
vcoubard	551:ab7a8de3ff10	3285	#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /!< Position of PROTREG17 field. /
vcoubard	551:ab7a8de3ff10	3286	#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /!< Bit mask of PROTREG17 field. /
vcoubard	551:ab7a8de3ff10	3287	#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3288	#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3289	#define MPU_PROTENSET0_PROTREG17_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3290
vcoubard	551:ab7a8de3ff10	3291	/* Bit 16 : Protection enable for region 16. */
vcoubard	551:ab7a8de3ff10	3292	#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /!< Position of PROTREG16 field. /
vcoubard	551:ab7a8de3ff10	3293	#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /!< Bit mask of PROTREG16 field. /
vcoubard	551:ab7a8de3ff10	3294	#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3295	#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3296	#define MPU_PROTENSET0_PROTREG16_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3297
vcoubard	551:ab7a8de3ff10	3298	/* Bit 15 : Protection enable for region 15. */
vcoubard	551:ab7a8de3ff10	3299	#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /!< Position of PROTREG15 field. /
vcoubard	551:ab7a8de3ff10	3300	#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /!< Bit mask of PROTREG15 field. /
vcoubard	551:ab7a8de3ff10	3301	#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3302	#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3303	#define MPU_PROTENSET0_PROTREG15_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3304
vcoubard	551:ab7a8de3ff10	3305	/* Bit 14 : Protection enable for region 14. */
vcoubard	551:ab7a8de3ff10	3306	#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /!< Position of PROTREG14 field. /
vcoubard	551:ab7a8de3ff10	3307	#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /!< Bit mask of PROTREG14 field. /
vcoubard	551:ab7a8de3ff10	3308	#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3309	#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3310	#define MPU_PROTENSET0_PROTREG14_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3311
vcoubard	551:ab7a8de3ff10	3312	/* Bit 13 : Protection enable for region 13. */
vcoubard	551:ab7a8de3ff10	3313	#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /!< Position of PROTREG13 field. /
vcoubard	551:ab7a8de3ff10	3314	#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /!< Bit mask of PROTREG13 field. /
vcoubard	551:ab7a8de3ff10	3315	#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3316	#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3317	#define MPU_PROTENSET0_PROTREG13_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3318
vcoubard	551:ab7a8de3ff10	3319	/* Bit 12 : Protection enable for region 12. */
vcoubard	551:ab7a8de3ff10	3320	#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /!< Position of PROTREG12 field. /
vcoubard	551:ab7a8de3ff10	3321	#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /!< Bit mask of PROTREG12 field. /
vcoubard	551:ab7a8de3ff10	3322	#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3323	#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3324	#define MPU_PROTENSET0_PROTREG12_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3325
vcoubard	551:ab7a8de3ff10	3326	/* Bit 11 : Protection enable for region 11. */
vcoubard	551:ab7a8de3ff10	3327	#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /!< Position of PROTREG11 field. /
vcoubard	551:ab7a8de3ff10	3328	#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /!< Bit mask of PROTREG11 field. /
vcoubard	551:ab7a8de3ff10	3329	#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3330	#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3331	#define MPU_PROTENSET0_PROTREG11_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3332
vcoubard	551:ab7a8de3ff10	3333	/* Bit 10 : Protection enable for region 10. */
vcoubard	551:ab7a8de3ff10	3334	#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /!< Position of PROTREG10 field. /
vcoubard	551:ab7a8de3ff10	3335	#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /!< Bit mask of PROTREG10 field. /
vcoubard	551:ab7a8de3ff10	3336	#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3337	#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3338	#define MPU_PROTENSET0_PROTREG10_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3339
vcoubard	551:ab7a8de3ff10	3340	/* Bit 9 : Protection enable for region 9. */
vcoubard	551:ab7a8de3ff10	3341	#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /!< Position of PROTREG9 field. /
vcoubard	551:ab7a8de3ff10	3342	#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /!< Bit mask of PROTREG9 field. /
vcoubard	551:ab7a8de3ff10	3343	#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3344	#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3345	#define MPU_PROTENSET0_PROTREG9_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3346
vcoubard	551:ab7a8de3ff10	3347	/* Bit 8 : Protection enable for region 8. */
vcoubard	551:ab7a8de3ff10	3348	#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /!< Position of PROTREG8 field. /
vcoubard	551:ab7a8de3ff10	3349	#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /!< Bit mask of PROTREG8 field. /
vcoubard	551:ab7a8de3ff10	3350	#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3351	#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3352	#define MPU_PROTENSET0_PROTREG8_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3353
vcoubard	551:ab7a8de3ff10	3354	/* Bit 7 : Protection enable for region 7. */
vcoubard	551:ab7a8de3ff10	3355	#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /!< Position of PROTREG7 field. /
vcoubard	551:ab7a8de3ff10	3356	#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /!< Bit mask of PROTREG7 field. /
vcoubard	551:ab7a8de3ff10	3357	#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3358	#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3359	#define MPU_PROTENSET0_PROTREG7_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3360
vcoubard	551:ab7a8de3ff10	3361	/* Bit 6 : Protection enable for region 6. */
vcoubard	551:ab7a8de3ff10	3362	#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /!< Position of PROTREG6 field. /
vcoubard	551:ab7a8de3ff10	3363	#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /!< Bit mask of PROTREG6 field. /
vcoubard	551:ab7a8de3ff10	3364	#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3365	#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3366	#define MPU_PROTENSET0_PROTREG6_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3367
vcoubard	551:ab7a8de3ff10	3368	/* Bit 5 : Protection enable for region 5. */
vcoubard	551:ab7a8de3ff10	3369	#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /!< Position of PROTREG5 field. /
vcoubard	551:ab7a8de3ff10	3370	#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /!< Bit mask of PROTREG5 field. /
vcoubard	551:ab7a8de3ff10	3371	#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3372	#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3373	#define MPU_PROTENSET0_PROTREG5_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3374
vcoubard	551:ab7a8de3ff10	3375	/* Bit 4 : Protection enable for region 4. */
vcoubard	551:ab7a8de3ff10	3376	#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /!< Position of PROTREG4 field. /
vcoubard	551:ab7a8de3ff10	3377	#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /!< Bit mask of PROTREG4 field. /
vcoubard	551:ab7a8de3ff10	3378	#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3379	#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3380	#define MPU_PROTENSET0_PROTREG4_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3381
vcoubard	551:ab7a8de3ff10	3382	/* Bit 3 : Protection enable for region 3. */
vcoubard	551:ab7a8de3ff10	3383	#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /!< Position of PROTREG3 field. /
vcoubard	551:ab7a8de3ff10	3384	#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /!< Bit mask of PROTREG3 field. /
vcoubard	551:ab7a8de3ff10	3385	#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3386	#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3387	#define MPU_PROTENSET0_PROTREG3_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3388
vcoubard	551:ab7a8de3ff10	3389	/* Bit 2 : Protection enable for region 2. */
vcoubard	551:ab7a8de3ff10	3390	#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /!< Position of PROTREG2 field. /
vcoubard	551:ab7a8de3ff10	3391	#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /!< Bit mask of PROTREG2 field. /
vcoubard	551:ab7a8de3ff10	3392	#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3393	#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3394	#define MPU_PROTENSET0_PROTREG2_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3395
vcoubard	551:ab7a8de3ff10	3396	/* Bit 1 : Protection enable for region 1. */
vcoubard	551:ab7a8de3ff10	3397	#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /!< Position of PROTREG1 field. /
vcoubard	551:ab7a8de3ff10	3398	#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /!< Bit mask of PROTREG1 field. /
vcoubard	551:ab7a8de3ff10	3399	#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3400	#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3401	#define MPU_PROTENSET0_PROTREG1_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3402
vcoubard	551:ab7a8de3ff10	3403	/* Bit 0 : Protection enable for region 0. */
vcoubard	551:ab7a8de3ff10	3404	#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /!< Position of PROTREG0 field. /
vcoubard	551:ab7a8de3ff10	3405	#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /!< Bit mask of PROTREG0 field. /
vcoubard	551:ab7a8de3ff10	3406	#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3407	#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3408	#define MPU_PROTENSET0_PROTREG0_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3409
vcoubard	551:ab7a8de3ff10	3410	/* Register: MPU_PROTENSET1 */
vcoubard	551:ab7a8de3ff10	3411	/* Description: Erase and write protection bit enable set register. */
vcoubard	551:ab7a8de3ff10	3412
vcoubard	551:ab7a8de3ff10	3413	/* Bit 31 : Protection enable for region 63. */
vcoubard	551:ab7a8de3ff10	3414	#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /!< Position of PROTREG63 field. /
vcoubard	551:ab7a8de3ff10	3415	#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /!< Bit mask of PROTREG63 field. /
vcoubard	551:ab7a8de3ff10	3416	#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3417	#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3418	#define MPU_PROTENSET1_PROTREG63_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3419
vcoubard	551:ab7a8de3ff10	3420	/* Bit 30 : Protection enable for region 62. */
vcoubard	551:ab7a8de3ff10	3421	#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /!< Position of PROTREG62 field. /
vcoubard	551:ab7a8de3ff10	3422	#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /!< Bit mask of PROTREG62 field. /
vcoubard	551:ab7a8de3ff10	3423	#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3424	#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3425	#define MPU_PROTENSET1_PROTREG62_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3426
vcoubard	551:ab7a8de3ff10	3427	/* Bit 29 : Protection enable for region 61. */
vcoubard	551:ab7a8de3ff10	3428	#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /!< Position of PROTREG61 field. /
vcoubard	551:ab7a8de3ff10	3429	#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /!< Bit mask of PROTREG61 field. /
vcoubard	551:ab7a8de3ff10	3430	#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3431	#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3432	#define MPU_PROTENSET1_PROTREG61_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3433
vcoubard	551:ab7a8de3ff10	3434	/* Bit 28 : Protection enable for region 60. */
vcoubard	551:ab7a8de3ff10	3435	#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /!< Position of PROTREG60 field. /
vcoubard	551:ab7a8de3ff10	3436	#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /!< Bit mask of PROTREG60 field. /
vcoubard	551:ab7a8de3ff10	3437	#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3438	#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3439	#define MPU_PROTENSET1_PROTREG60_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3440
vcoubard	551:ab7a8de3ff10	3441	/* Bit 27 : Protection enable for region 59. */
vcoubard	551:ab7a8de3ff10	3442	#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /!< Position of PROTREG59 field. /
vcoubard	551:ab7a8de3ff10	3443	#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /!< Bit mask of PROTREG59 field. /
vcoubard	551:ab7a8de3ff10	3444	#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3445	#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3446	#define MPU_PROTENSET1_PROTREG59_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3447
vcoubard	551:ab7a8de3ff10	3448	/* Bit 26 : Protection enable for region 58. */
vcoubard	551:ab7a8de3ff10	3449	#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /!< Position of PROTREG58 field. /
vcoubard	551:ab7a8de3ff10	3450	#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /!< Bit mask of PROTREG58 field. /
vcoubard	551:ab7a8de3ff10	3451	#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3452	#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3453	#define MPU_PROTENSET1_PROTREG58_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3454
vcoubard	551:ab7a8de3ff10	3455	/* Bit 25 : Protection enable for region 57. */
vcoubard	551:ab7a8de3ff10	3456	#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /!< Position of PROTREG57 field. /
vcoubard	551:ab7a8de3ff10	3457	#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /!< Bit mask of PROTREG57 field. /
vcoubard	551:ab7a8de3ff10	3458	#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3459	#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3460	#define MPU_PROTENSET1_PROTREG57_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3461
vcoubard	551:ab7a8de3ff10	3462	/* Bit 24 : Protection enable for region 56. */
vcoubard	551:ab7a8de3ff10	3463	#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /!< Position of PROTREG56 field. /
vcoubard	551:ab7a8de3ff10	3464	#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /!< Bit mask of PROTREG56 field. /
vcoubard	551:ab7a8de3ff10	3465	#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3466	#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3467	#define MPU_PROTENSET1_PROTREG56_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3468
vcoubard	551:ab7a8de3ff10	3469	/* Bit 23 : Protection enable for region 55. */
vcoubard	551:ab7a8de3ff10	3470	#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /!< Position of PROTREG55 field. /
vcoubard	551:ab7a8de3ff10	3471	#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /!< Bit mask of PROTREG55 field. /
vcoubard	551:ab7a8de3ff10	3472	#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3473	#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3474	#define MPU_PROTENSET1_PROTREG55_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3475
vcoubard	551:ab7a8de3ff10	3476	/* Bit 22 : Protection enable for region 54. */
vcoubard	551:ab7a8de3ff10	3477	#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /!< Position of PROTREG54 field. /
vcoubard	551:ab7a8de3ff10	3478	#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /!< Bit mask of PROTREG54 field. /
vcoubard	551:ab7a8de3ff10	3479	#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3480	#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3481	#define MPU_PROTENSET1_PROTREG54_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3482
vcoubard	551:ab7a8de3ff10	3483	/* Bit 21 : Protection enable for region 53. */
vcoubard	551:ab7a8de3ff10	3484	#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /!< Position of PROTREG53 field. /
vcoubard	551:ab7a8de3ff10	3485	#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /!< Bit mask of PROTREG53 field. /
vcoubard	551:ab7a8de3ff10	3486	#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3487	#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3488	#define MPU_PROTENSET1_PROTREG53_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3489
vcoubard	551:ab7a8de3ff10	3490	/* Bit 20 : Protection enable for region 52. */
vcoubard	551:ab7a8de3ff10	3491	#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /!< Position of PROTREG52 field. /
vcoubard	551:ab7a8de3ff10	3492	#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /!< Bit mask of PROTREG52 field. /
vcoubard	551:ab7a8de3ff10	3493	#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3494	#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3495	#define MPU_PROTENSET1_PROTREG52_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3496
vcoubard	551:ab7a8de3ff10	3497	/* Bit 19 : Protection enable for region 51. */
vcoubard	551:ab7a8de3ff10	3498	#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /!< Position of PROTREG51 field. /
vcoubard	551:ab7a8de3ff10	3499	#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /!< Bit mask of PROTREG51 field. /
vcoubard	551:ab7a8de3ff10	3500	#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3501	#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3502	#define MPU_PROTENSET1_PROTREG51_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3503
vcoubard	551:ab7a8de3ff10	3504	/* Bit 18 : Protection enable for region 50. */
vcoubard	551:ab7a8de3ff10	3505	#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /!< Position of PROTREG50 field. /
vcoubard	551:ab7a8de3ff10	3506	#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /!< Bit mask of PROTREG50 field. /
vcoubard	551:ab7a8de3ff10	3507	#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3508	#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3509	#define MPU_PROTENSET1_PROTREG50_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3510
vcoubard	551:ab7a8de3ff10	3511	/* Bit 17 : Protection enable for region 49. */
vcoubard	551:ab7a8de3ff10	3512	#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /!< Position of PROTREG49 field. /
vcoubard	551:ab7a8de3ff10	3513	#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /!< Bit mask of PROTREG49 field. /
vcoubard	551:ab7a8de3ff10	3514	#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3515	#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3516	#define MPU_PROTENSET1_PROTREG49_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3517
vcoubard	551:ab7a8de3ff10	3518	/* Bit 16 : Protection enable for region 48. */
vcoubard	551:ab7a8de3ff10	3519	#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /!< Position of PROTREG48 field. /
vcoubard	551:ab7a8de3ff10	3520	#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /!< Bit mask of PROTREG48 field. /
vcoubard	551:ab7a8de3ff10	3521	#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3522	#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3523	#define MPU_PROTENSET1_PROTREG48_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3524
vcoubard	551:ab7a8de3ff10	3525	/* Bit 15 : Protection enable for region 47. */
vcoubard	551:ab7a8de3ff10	3526	#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /!< Position of PROTREG47 field. /
vcoubard	551:ab7a8de3ff10	3527	#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /!< Bit mask of PROTREG47 field. /
vcoubard	551:ab7a8de3ff10	3528	#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3529	#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3530	#define MPU_PROTENSET1_PROTREG47_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3531
vcoubard	551:ab7a8de3ff10	3532	/* Bit 14 : Protection enable for region 46. */
vcoubard	551:ab7a8de3ff10	3533	#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /!< Position of PROTREG46 field. /
vcoubard	551:ab7a8de3ff10	3534	#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /!< Bit mask of PROTREG46 field. /
vcoubard	551:ab7a8de3ff10	3535	#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3536	#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3537	#define MPU_PROTENSET1_PROTREG46_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3538
vcoubard	551:ab7a8de3ff10	3539	/* Bit 13 : Protection enable for region 45. */
vcoubard	551:ab7a8de3ff10	3540	#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /!< Position of PROTREG45 field. /
vcoubard	551:ab7a8de3ff10	3541	#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /!< Bit mask of PROTREG45 field. /
vcoubard	551:ab7a8de3ff10	3542	#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3543	#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3544	#define MPU_PROTENSET1_PROTREG45_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3545
vcoubard	551:ab7a8de3ff10	3546	/* Bit 12 : Protection enable for region 44. */
vcoubard	551:ab7a8de3ff10	3547	#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /!< Position of PROTREG44 field. /
vcoubard	551:ab7a8de3ff10	3548	#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /!< Bit mask of PROTREG44 field. /
vcoubard	551:ab7a8de3ff10	3549	#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3550	#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3551	#define MPU_PROTENSET1_PROTREG44_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3552
vcoubard	551:ab7a8de3ff10	3553	/* Bit 11 : Protection enable for region 43. */
vcoubard	551:ab7a8de3ff10	3554	#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /!< Position of PROTREG43 field. /
vcoubard	551:ab7a8de3ff10	3555	#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /!< Bit mask of PROTREG43 field. /
vcoubard	551:ab7a8de3ff10	3556	#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3557	#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3558	#define MPU_PROTENSET1_PROTREG43_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3559
vcoubard	551:ab7a8de3ff10	3560	/* Bit 10 : Protection enable for region 42. */
vcoubard	551:ab7a8de3ff10	3561	#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /!< Position of PROTREG42 field. /
vcoubard	551:ab7a8de3ff10	3562	#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /!< Bit mask of PROTREG42 field. /
vcoubard	551:ab7a8de3ff10	3563	#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3564	#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3565	#define MPU_PROTENSET1_PROTREG42_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3566
vcoubard	551:ab7a8de3ff10	3567	/* Bit 9 : Protection enable for region 41. */
vcoubard	551:ab7a8de3ff10	3568	#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /!< Position of PROTREG41 field. /
vcoubard	551:ab7a8de3ff10	3569	#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /!< Bit mask of PROTREG41 field. /
vcoubard	551:ab7a8de3ff10	3570	#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3571	#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3572	#define MPU_PROTENSET1_PROTREG41_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3573
vcoubard	551:ab7a8de3ff10	3574	/* Bit 8 : Protection enable for region 40. */
vcoubard	551:ab7a8de3ff10	3575	#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /!< Position of PROTREG40 field. /
vcoubard	551:ab7a8de3ff10	3576	#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /!< Bit mask of PROTREG40 field. /
vcoubard	551:ab7a8de3ff10	3577	#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3578	#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3579	#define MPU_PROTENSET1_PROTREG40_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3580
vcoubard	551:ab7a8de3ff10	3581	/* Bit 7 : Protection enable for region 39. */
vcoubard	551:ab7a8de3ff10	3582	#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /!< Position of PROTREG39 field. /
vcoubard	551:ab7a8de3ff10	3583	#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /!< Bit mask of PROTREG39 field. /
vcoubard	551:ab7a8de3ff10	3584	#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3585	#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3586	#define MPU_PROTENSET1_PROTREG39_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3587
vcoubard	551:ab7a8de3ff10	3588	/* Bit 6 : Protection enable for region 38. */
vcoubard	551:ab7a8de3ff10	3589	#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /!< Position of PROTREG38 field. /
vcoubard	551:ab7a8de3ff10	3590	#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /!< Bit mask of PROTREG38 field. /
vcoubard	551:ab7a8de3ff10	3591	#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3592	#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3593	#define MPU_PROTENSET1_PROTREG38_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3594
vcoubard	551:ab7a8de3ff10	3595	/* Bit 5 : Protection enable for region 37. */
vcoubard	551:ab7a8de3ff10	3596	#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /!< Position of PROTREG37 field. /
vcoubard	551:ab7a8de3ff10	3597	#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /!< Bit mask of PROTREG37 field. /
vcoubard	551:ab7a8de3ff10	3598	#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3599	#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3600	#define MPU_PROTENSET1_PROTREG37_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3601
vcoubard	551:ab7a8de3ff10	3602	/* Bit 4 : Protection enable for region 36. */
vcoubard	551:ab7a8de3ff10	3603	#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /!< Position of PROTREG36 field. /
vcoubard	551:ab7a8de3ff10	3604	#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /!< Bit mask of PROTREG36 field. /
vcoubard	551:ab7a8de3ff10	3605	#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3606	#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3607	#define MPU_PROTENSET1_PROTREG36_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3608
vcoubard	551:ab7a8de3ff10	3609	/* Bit 3 : Protection enable for region 35. */
vcoubard	551:ab7a8de3ff10	3610	#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /!< Position of PROTREG35 field. /
vcoubard	551:ab7a8de3ff10	3611	#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /!< Bit mask of PROTREG35 field. /
vcoubard	551:ab7a8de3ff10	3612	#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3613	#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3614	#define MPU_PROTENSET1_PROTREG35_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3615
vcoubard	551:ab7a8de3ff10	3616	/* Bit 2 : Protection enable for region 34. */
vcoubard	551:ab7a8de3ff10	3617	#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /!< Position of PROTREG34 field. /
vcoubard	551:ab7a8de3ff10	3618	#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /!< Bit mask of PROTREG34 field. /
vcoubard	551:ab7a8de3ff10	3619	#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3620	#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3621	#define MPU_PROTENSET1_PROTREG34_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3622
vcoubard	551:ab7a8de3ff10	3623	/* Bit 1 : Protection enable for region 33. */
vcoubard	551:ab7a8de3ff10	3624	#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /!< Position of PROTREG33 field. /
vcoubard	551:ab7a8de3ff10	3625	#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /!< Bit mask of PROTREG33 field. /
vcoubard	551:ab7a8de3ff10	3626	#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3627	#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3628	#define MPU_PROTENSET1_PROTREG33_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3629
vcoubard	551:ab7a8de3ff10	3630	/* Bit 0 : Protection enable for region 32. */
vcoubard	551:ab7a8de3ff10	3631	#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /!< Position of PROTREG32 field. /
vcoubard	551:ab7a8de3ff10	3632	#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /!< Bit mask of PROTREG32 field. /
vcoubard	551:ab7a8de3ff10	3633	#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3634	#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3635	#define MPU_PROTENSET1_PROTREG32_Set (1UL) /!< Enable protection on write. /
vcoubard	551:ab7a8de3ff10	3636
vcoubard	551:ab7a8de3ff10	3637	/* Register: MPU_DISABLEINDEBUG */
vcoubard	551:ab7a8de3ff10	3638	/* Description: Disable erase and write protection mechanism in debug mode. */
vcoubard	551:ab7a8de3ff10	3639
vcoubard	551:ab7a8de3ff10	3640	/* Bit 0 : Disable protection mechanism in debug mode. */
vcoubard	551:ab7a8de3ff10	3641	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /!< Position of DISABLEINDEBUG field. /
vcoubard	551:ab7a8de3ff10	3642	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /!< Bit mask of DISABLEINDEBUG field. /
vcoubard	551:ab7a8de3ff10	3643	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /!< Protection enabled. /
vcoubard	551:ab7a8de3ff10	3644	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /!< Protection disabled. /
vcoubard	551:ab7a8de3ff10	3645
vcoubard	551:ab7a8de3ff10	3646	/* Register: MPU_PROTBLOCKSIZE */
vcoubard	551:ab7a8de3ff10	3647	/* Description: Erase and write protection block size. */
vcoubard	551:ab7a8de3ff10	3648
vcoubard	551:ab7a8de3ff10	3649	/* Bits 1..0 : Erase and write protection block size. */
vcoubard	551:ab7a8de3ff10	3650	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /!< Position of PROTBLOCKSIZE field. /
vcoubard	551:ab7a8de3ff10	3651	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /!< Bit mask of PROTBLOCKSIZE field. /
vcoubard	551:ab7a8de3ff10	3652	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /!< Erase and write protection block size is 4k. /
vcoubard	551:ab7a8de3ff10	3653
vcoubard	551:ab7a8de3ff10	3654
vcoubard	551:ab7a8de3ff10	3655	/* Peripheral: NVMC */
vcoubard	551:ab7a8de3ff10	3656	/* Description: Non Volatile Memory Controller. */
vcoubard	551:ab7a8de3ff10	3657
vcoubard	551:ab7a8de3ff10	3658	/* Register: NVMC_READY */
vcoubard	551:ab7a8de3ff10	3659	/* Description: Ready flag. */
vcoubard	551:ab7a8de3ff10	3660
vcoubard	551:ab7a8de3ff10	3661	/* Bit 0 : NVMC ready. */
vcoubard	551:ab7a8de3ff10	3662	#define NVMC_READY_READY_Pos (0UL) /!< Position of READY field. /
vcoubard	551:ab7a8de3ff10	3663	#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /!< Bit mask of READY field. /
vcoubard	551:ab7a8de3ff10	3664	#define NVMC_READY_READY_Busy (0UL) /!< NVMC is busy (on-going write or erase operation). /
vcoubard	551:ab7a8de3ff10	3665	#define NVMC_READY_READY_Ready (1UL) /!< NVMC is ready. /
vcoubard	551:ab7a8de3ff10	3666
vcoubard	551:ab7a8de3ff10	3667	/* Register: NVMC_CONFIG */
vcoubard	551:ab7a8de3ff10	3668	/* Description: Configuration register. */
vcoubard	551:ab7a8de3ff10	3669
vcoubard	551:ab7a8de3ff10	3670	/* Bits 1..0 : Program write enable. */
vcoubard	551:ab7a8de3ff10	3671	#define NVMC_CONFIG_WEN_Pos (0UL) /!< Position of WEN field. /
vcoubard	551:ab7a8de3ff10	3672	#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /!< Bit mask of WEN field. /
vcoubard	551:ab7a8de3ff10	3673	#define NVMC_CONFIG_WEN_Ren (0x00UL) /!< Read only access. /
vcoubard	551:ab7a8de3ff10	3674	#define NVMC_CONFIG_WEN_Wen (0x01UL) /!< Write enabled. /
vcoubard	551:ab7a8de3ff10	3675	#define NVMC_CONFIG_WEN_Een (0x02UL) /!< Erase enabled. /
vcoubard	551:ab7a8de3ff10	3676
vcoubard	551:ab7a8de3ff10	3677	/* Register: NVMC_ERASEALL */
vcoubard	551:ab7a8de3ff10	3678	/* Description: Register for erasing all non-volatile user memory. */
vcoubard	551:ab7a8de3ff10	3679
vcoubard	551:ab7a8de3ff10	3680	/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
vcoubard	551:ab7a8de3ff10	3681	#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /!< Position of ERASEALL field. /
vcoubard	551:ab7a8de3ff10	3682	#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /!< Bit mask of ERASEALL field. /
vcoubard	551:ab7a8de3ff10	3683	#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /!< No operation. /
vcoubard	551:ab7a8de3ff10	3684	#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /!< Start chip erase. /
vcoubard	551:ab7a8de3ff10	3685
vcoubard	551:ab7a8de3ff10	3686	/* Register: NVMC_ERASEUICR */
vcoubard	551:ab7a8de3ff10	3687	/* Description: Register for start erasing User Information Congfiguration Registers. */
vcoubard	551:ab7a8de3ff10	3688
vcoubard	551:ab7a8de3ff10	3689	/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
vcoubard	551:ab7a8de3ff10	3690	#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /!< Position of ERASEUICR field. /
vcoubard	551:ab7a8de3ff10	3691	#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /!< Bit mask of ERASEUICR field. /
vcoubard	551:ab7a8de3ff10	3692	#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /!< No operation. /
vcoubard	551:ab7a8de3ff10	3693	#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /!< Start UICR erase. /
vcoubard	551:ab7a8de3ff10	3694
vcoubard	551:ab7a8de3ff10	3695
vcoubard	551:ab7a8de3ff10	3696	/* Peripheral: POWER */
vcoubard	551:ab7a8de3ff10	3697	/* Description: Power Control. */
vcoubard	551:ab7a8de3ff10	3698
vcoubard	551:ab7a8de3ff10	3699	/* Register: POWER_INTENSET */
vcoubard	551:ab7a8de3ff10	3700	/* Description: Interrupt enable set register. */
vcoubard	551:ab7a8de3ff10	3701
vcoubard	551:ab7a8de3ff10	3702	/* Bit 2 : Enable interrupt on POFWARN event. */
vcoubard	551:ab7a8de3ff10	3703	#define POWER_INTENSET_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
vcoubard	551:ab7a8de3ff10	3704	#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /!< Bit mask of POFWARN field. /
vcoubard	551:ab7a8de3ff10	3705	#define POWER_INTENSET_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	3706	#define POWER_INTENSET_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	3707	#define POWER_INTENSET_POFWARN_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	3708
vcoubard	551:ab7a8de3ff10	3709	/* Register: POWER_INTENCLR */
vcoubard	551:ab7a8de3ff10	3710	/* Description: Interrupt enable clear register. */
vcoubard	551:ab7a8de3ff10	3711
vcoubard	551:ab7a8de3ff10	3712	/* Bit 2 : Disable interrupt on POFWARN event. */
vcoubard	551:ab7a8de3ff10	3713	#define POWER_INTENCLR_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
vcoubard	551:ab7a8de3ff10	3714	#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /!< Bit mask of POFWARN field. /
vcoubard	551:ab7a8de3ff10	3715	#define POWER_INTENCLR_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	3716	#define POWER_INTENCLR_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	3717	#define POWER_INTENCLR_POFWARN_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	3718
vcoubard	551:ab7a8de3ff10	3719	/* Register: POWER_RESETREAS */
vcoubard	551:ab7a8de3ff10	3720	/* Description: Reset reason. */
vcoubard	551:ab7a8de3ff10	3721
vcoubard	551:ab7a8de3ff10	3722	/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
vcoubard	551:ab7a8de3ff10	3723	#define POWER_RESETREAS_DIF_Pos (18UL) /!< Position of DIF field. /
vcoubard	551:ab7a8de3ff10	3724	#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /!< Bit mask of DIF field. /
vcoubard	551:ab7a8de3ff10	3725
vcoubard	551:ab7a8de3ff10	3726	/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
vcoubard	551:ab7a8de3ff10	3727	#define POWER_RESETREAS_LPCOMP_Pos (17UL) /!< Position of LPCOMP field. /
vcoubard	551:ab7a8de3ff10	3728	#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
vcoubard	551:ab7a8de3ff10	3729
vcoubard	551:ab7a8de3ff10	3730	/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
vcoubard	551:ab7a8de3ff10	3731	#define POWER_RESETREAS_OFF_Pos (16UL) /!< Position of OFF field. /
vcoubard	551:ab7a8de3ff10	3732	#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /!< Bit mask of OFF field. /
vcoubard	551:ab7a8de3ff10	3733
vcoubard	551:ab7a8de3ff10	3734	/* Bit 3 : Reset from CPU lock-up detected. */
vcoubard	551:ab7a8de3ff10	3735	#define POWER_RESETREAS_LOCKUP_Pos (3UL) /!< Position of LOCKUP field. /
vcoubard	551:ab7a8de3ff10	3736	#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /!< Bit mask of LOCKUP field. /
vcoubard	551:ab7a8de3ff10	3737
vcoubard	551:ab7a8de3ff10	3738	/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
vcoubard	551:ab7a8de3ff10	3739	#define POWER_RESETREAS_SREQ_Pos (2UL) /!< Position of SREQ field. /
vcoubard	551:ab7a8de3ff10	3740	#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /!< Bit mask of SREQ field. /
vcoubard	551:ab7a8de3ff10	3741
vcoubard	551:ab7a8de3ff10	3742	/* Bit 1 : Reset from watchdog detected. */
vcoubard	551:ab7a8de3ff10	3743	#define POWER_RESETREAS_DOG_Pos (1UL) /!< Position of DOG field. /
vcoubard	551:ab7a8de3ff10	3744	#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /!< Bit mask of DOG field. /
vcoubard	551:ab7a8de3ff10	3745
vcoubard	551:ab7a8de3ff10	3746	/* Bit 0 : Reset from pin-reset detected. */
vcoubard	551:ab7a8de3ff10	3747	#define POWER_RESETREAS_RESETPIN_Pos (0UL) /!< Position of RESETPIN field. /
vcoubard	551:ab7a8de3ff10	3748	#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /!< Bit mask of RESETPIN field. /
vcoubard	551:ab7a8de3ff10	3749
vcoubard	551:ab7a8de3ff10	3750	/* Register: POWER_RAMSTATUS */
vcoubard	551:ab7a8de3ff10	3751	/* Description: Ram status register. */
vcoubard	551:ab7a8de3ff10	3752
vcoubard	551:ab7a8de3ff10	3753	/* Bit 3 : RAM block 3 status. */
vcoubard	551:ab7a8de3ff10	3754	#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /!< Position of RAMBLOCK3 field. /
vcoubard	551:ab7a8de3ff10	3755	#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /!< Bit mask of RAMBLOCK3 field. /
vcoubard	551:ab7a8de3ff10	3756	#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /!< RAM block 3 is off or powering up. /
vcoubard	551:ab7a8de3ff10	3757	#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /!< RAM block 3 is on. /
vcoubard	551:ab7a8de3ff10	3758
vcoubard	551:ab7a8de3ff10	3759	/* Bit 2 : RAM block 2 status. */
vcoubard	551:ab7a8de3ff10	3760	#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /!< Position of RAMBLOCK2 field. /
vcoubard	551:ab7a8de3ff10	3761	#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /!< Bit mask of RAMBLOCK2 field. /
vcoubard	551:ab7a8de3ff10	3762	#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /!< RAM block 2 is off or powering up. /
vcoubard	551:ab7a8de3ff10	3763	#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /!< RAM block 2 is on. /
vcoubard	551:ab7a8de3ff10	3764
vcoubard	551:ab7a8de3ff10	3765	/* Bit 1 : RAM block 1 status. */
vcoubard	551:ab7a8de3ff10	3766	#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /!< Position of RAMBLOCK1 field. /
vcoubard	551:ab7a8de3ff10	3767	#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /!< Bit mask of RAMBLOCK1 field. /
vcoubard	551:ab7a8de3ff10	3768	#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /!< RAM block 1 is off or powering up. /
vcoubard	551:ab7a8de3ff10	3769	#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /!< RAM block 1 is on. /
vcoubard	551:ab7a8de3ff10	3770
vcoubard	551:ab7a8de3ff10	3771	/* Bit 0 : RAM block 0 status. */
vcoubard	551:ab7a8de3ff10	3772	#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /!< Position of RAMBLOCK0 field. /
vcoubard	551:ab7a8de3ff10	3773	#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /!< Bit mask of RAMBLOCK0 field. /
vcoubard	551:ab7a8de3ff10	3774	#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /!< RAM block 0 is off or powering up. /
vcoubard	551:ab7a8de3ff10	3775	#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /!< RAM block 0 is on. /
vcoubard	551:ab7a8de3ff10	3776
vcoubard	551:ab7a8de3ff10	3777	/* Register: POWER_SYSTEMOFF */
vcoubard	551:ab7a8de3ff10	3778	/* Description: System off register. */
vcoubard	551:ab7a8de3ff10	3779
vcoubard	551:ab7a8de3ff10	3780	/* Bit 0 : Enter system off mode. */
vcoubard	551:ab7a8de3ff10	3781	#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /!< Position of SYSTEMOFF field. /
vcoubard	551:ab7a8de3ff10	3782	#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /!< Bit mask of SYSTEMOFF field. /
vcoubard	551:ab7a8de3ff10	3783	#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /!< Enter system off mode. /
vcoubard	551:ab7a8de3ff10	3784
vcoubard	551:ab7a8de3ff10	3785	/* Register: POWER_POFCON */
vcoubard	551:ab7a8de3ff10	3786	/* Description: Power failure configuration. */
vcoubard	551:ab7a8de3ff10	3787
vcoubard	551:ab7a8de3ff10	3788	/* Bits 2..1 : Set threshold level. */
vcoubard	551:ab7a8de3ff10	3789	#define POWER_POFCON_THRESHOLD_Pos (1UL) /!< Position of THRESHOLD field. /
vcoubard	551:ab7a8de3ff10	3790	#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /!< Bit mask of THRESHOLD field. /
vcoubard	551:ab7a8de3ff10	3791	#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /!< Set threshold to 2.1Volts. /
vcoubard	551:ab7a8de3ff10	3792	#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /!< Set threshold to 2.3Volts. /
vcoubard	551:ab7a8de3ff10	3793	#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /!< Set threshold to 2.5Volts. /
vcoubard	551:ab7a8de3ff10	3794	#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /!< Set threshold to 2.7Volts. /
vcoubard	551:ab7a8de3ff10	3795
vcoubard	551:ab7a8de3ff10	3796	/* Bit 0 : Power failure comparator enable. */
vcoubard	551:ab7a8de3ff10	3797	#define POWER_POFCON_POF_Pos (0UL) /!< Position of POF field. /
vcoubard	551:ab7a8de3ff10	3798	#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /!< Bit mask of POF field. /
vcoubard	551:ab7a8de3ff10	3799	#define POWER_POFCON_POF_Disabled (0UL) /!< Disabled. /
vcoubard	551:ab7a8de3ff10	3800	#define POWER_POFCON_POF_Enabled (1UL) /!< Enabled. /
vcoubard	551:ab7a8de3ff10	3801
vcoubard	551:ab7a8de3ff10	3802	/* Register: POWER_GPREGRET */
vcoubard	551:ab7a8de3ff10	3803	/* Description: General purpose retention register. This register is a retained register. */
vcoubard	551:ab7a8de3ff10	3804
vcoubard	551:ab7a8de3ff10	3805	/* Bits 7..0 : General purpose retention register. */
vcoubard	551:ab7a8de3ff10	3806	#define POWER_GPREGRET_GPREGRET_Pos (0UL) /!< Position of GPREGRET field. /
vcoubard	551:ab7a8de3ff10	3807	#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /!< Bit mask of GPREGRET field. /
vcoubard	551:ab7a8de3ff10	3808
vcoubard	551:ab7a8de3ff10	3809	/* Register: POWER_RAMON */
vcoubard	551:ab7a8de3ff10	3810	/* Description: Ram on/off. */
vcoubard	551:ab7a8de3ff10	3811
vcoubard	551:ab7a8de3ff10	3812	/* Bit 17 : RAM block 1 behaviour in OFF mode. */
vcoubard	551:ab7a8de3ff10	3813	#define POWER_RAMON_OFFRAM1_Pos (17UL) /!< Position of OFFRAM1 field. /
vcoubard	551:ab7a8de3ff10	3814	#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /!< Bit mask of OFFRAM1 field. /
vcoubard	551:ab7a8de3ff10	3815	#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in OFF mode. /
vcoubard	551:ab7a8de3ff10	3816	#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /!< RAM block 1 ON in OFF mode. /
vcoubard	551:ab7a8de3ff10	3817
vcoubard	551:ab7a8de3ff10	3818	/* Bit 16 : RAM block 0 behaviour in OFF mode. */
vcoubard	551:ab7a8de3ff10	3819	#define POWER_RAMON_OFFRAM0_Pos (16UL) /!< Position of OFFRAM0 field. /
vcoubard	551:ab7a8de3ff10	3820	#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /!< Bit mask of OFFRAM0 field. /
vcoubard	551:ab7a8de3ff10	3821	#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in OFF mode. /
vcoubard	551:ab7a8de3ff10	3822	#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /!< RAM block 0 ON in OFF mode. /
vcoubard	551:ab7a8de3ff10	3823
vcoubard	551:ab7a8de3ff10	3824	/* Bit 1 : RAM block 1 behaviour in ON mode. */
vcoubard	551:ab7a8de3ff10	3825	#define POWER_RAMON_ONRAM1_Pos (1UL) /!< Position of ONRAM1 field. /
vcoubard	551:ab7a8de3ff10	3826	#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /!< Bit mask of ONRAM1 field. /
vcoubard	551:ab7a8de3ff10	3827	#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in ON mode. /
vcoubard	551:ab7a8de3ff10	3828	#define POWER_RAMON_ONRAM1_RAM1On (1UL) /!< RAM block 1 ON in ON mode. /
vcoubard	551:ab7a8de3ff10	3829
vcoubard	551:ab7a8de3ff10	3830	/* Bit 0 : RAM block 0 behaviour in ON mode. */
vcoubard	551:ab7a8de3ff10	3831	#define POWER_RAMON_ONRAM0_Pos (0UL) /!< Position of ONRAM0 field. /
vcoubard	551:ab7a8de3ff10	3832	#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /!< Bit mask of ONRAM0 field. /
vcoubard	551:ab7a8de3ff10	3833	#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in ON mode. /
vcoubard	551:ab7a8de3ff10	3834	#define POWER_RAMON_ONRAM0_RAM0On (1UL) /!< RAM block 0 ON in ON mode. /
vcoubard	551:ab7a8de3ff10	3835
vcoubard	551:ab7a8de3ff10	3836	/* Register: POWER_RESET */
vcoubard	551:ab7a8de3ff10	3837	/* Description: Pin reset functionality configuration register. This register is a retained register. */
vcoubard	551:ab7a8de3ff10	3838
vcoubard	551:ab7a8de3ff10	3839	/* Bit 0 : Enable or disable pin reset in debug interface mode. */
vcoubard	551:ab7a8de3ff10	3840	#define POWER_RESET_RESET_Pos (0UL) /!< Position of RESET field. /
vcoubard	551:ab7a8de3ff10	3841	#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /!< Bit mask of RESET field. /
vcoubard	551:ab7a8de3ff10	3842	#define POWER_RESET_RESET_Disabled (0UL) /!< Pin reset in debug interface mode disabled. /
vcoubard	551:ab7a8de3ff10	3843	#define POWER_RESET_RESET_Enabled (1UL) /!< Pin reset in debug interface mode enabled. /
vcoubard	551:ab7a8de3ff10	3844
vcoubard	551:ab7a8de3ff10	3845	/* Register: POWER_RAMONB */
vcoubard	551:ab7a8de3ff10	3846	/* Description: Ram on/off. */
vcoubard	551:ab7a8de3ff10	3847
vcoubard	551:ab7a8de3ff10	3848	/* Bit 17 : RAM block 3 behaviour in OFF mode. */
vcoubard	551:ab7a8de3ff10	3849	#define POWER_RAMONB_OFFRAM3_Pos (17UL) /!< Position of OFFRAM3 field. /
vcoubard	551:ab7a8de3ff10	3850	#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /!< Bit mask of OFFRAM3 field. /
vcoubard	551:ab7a8de3ff10	3851	#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /!< RAM block 3 OFF in OFF mode. /
vcoubard	551:ab7a8de3ff10	3852	#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /!< RAM block 3 ON in OFF mode. /
vcoubard	551:ab7a8de3ff10	3853
vcoubard	551:ab7a8de3ff10	3854	/* Bit 16 : RAM block 2 behaviour in OFF mode. */
vcoubard	551:ab7a8de3ff10	3855	#define POWER_RAMONB_OFFRAM2_Pos (16UL) /!< Position of OFFRAM2 field. /
vcoubard	551:ab7a8de3ff10	3856	#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /!< Bit mask of OFFRAM2 field. /
vcoubard	551:ab7a8de3ff10	3857	#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in OFF mode. /
vcoubard	551:ab7a8de3ff10	3858	#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /!< RAM block 2 ON in OFF mode. /
vcoubard	551:ab7a8de3ff10	3859
vcoubard	551:ab7a8de3ff10	3860	/* Bit 1 : RAM block 3 behaviour in ON mode. */
vcoubard	551:ab7a8de3ff10	3861	#define POWER_RAMONB_ONRAM3_Pos (1UL) /!< Position of ONRAM3 field. /
vcoubard	551:ab7a8de3ff10	3862	#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /!< Bit mask of ONRAM3 field. /
vcoubard	551:ab7a8de3ff10	3863	#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /!< RAM block 33 OFF in ON mode. /
vcoubard	551:ab7a8de3ff10	3864	#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /!< RAM block 3 ON in ON mode. /
vcoubard	551:ab7a8de3ff10	3865
vcoubard	551:ab7a8de3ff10	3866	/* Bit 0 : RAM block 2 behaviour in ON mode. */
vcoubard	551:ab7a8de3ff10	3867	#define POWER_RAMONB_ONRAM2_Pos (0UL) /!< Position of ONRAM2 field. /
vcoubard	551:ab7a8de3ff10	3868	#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /!< Bit mask of ONRAM2 field. /
vcoubard	551:ab7a8de3ff10	3869	#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in ON mode. /
vcoubard	551:ab7a8de3ff10	3870	#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /!< RAM block 2 ON in ON mode. /
vcoubard	551:ab7a8de3ff10	3871
vcoubard	551:ab7a8de3ff10	3872	/* Register: POWER_DCDCEN */
vcoubard	551:ab7a8de3ff10	3873	/* Description: DCDC converter enable configuration register. */
vcoubard	551:ab7a8de3ff10	3874
vcoubard	551:ab7a8de3ff10	3875	/* Bit 0 : Enable DCDC converter. */
vcoubard	551:ab7a8de3ff10	3876	#define POWER_DCDCEN_DCDCEN_Pos (0UL) /!< Position of DCDCEN field. /
vcoubard	551:ab7a8de3ff10	3877	#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /!< Bit mask of DCDCEN field. /
vcoubard	551:ab7a8de3ff10	3878	#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /!< DCDC converter disabled. /
vcoubard	551:ab7a8de3ff10	3879	#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /!< DCDC converter enabled. /
vcoubard	551:ab7a8de3ff10	3880
vcoubard	551:ab7a8de3ff10	3881	/* Register: POWER_DCDCFORCE */
vcoubard	551:ab7a8de3ff10	3882	/* Description: DCDC power-up force register. */
vcoubard	551:ab7a8de3ff10	3883
vcoubard	551:ab7a8de3ff10	3884	/* Bit 1 : DCDC power-up force on. */
vcoubard	551:ab7a8de3ff10	3885	#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /!< Position of FORCEON field. /
vcoubard	551:ab7a8de3ff10	3886	#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /!< Bit mask of FORCEON field. /
vcoubard	551:ab7a8de3ff10	3887	#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /!< No force. /
vcoubard	551:ab7a8de3ff10	3888	#define POWER_DCDCFORCE_FORCEON_Force (1UL) /!< Force. /
vcoubard	551:ab7a8de3ff10	3889
vcoubard	551:ab7a8de3ff10	3890	/* Bit 0 : DCDC power-up force off. */
vcoubard	551:ab7a8de3ff10	3891	#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /!< Position of FORCEOFF field. /
vcoubard	551:ab7a8de3ff10	3892	#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /!< Bit mask of FORCEOFF field. /
vcoubard	551:ab7a8de3ff10	3893	#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /!< No force. /
vcoubard	551:ab7a8de3ff10	3894	#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /!< Force. /
vcoubard	551:ab7a8de3ff10	3895
vcoubard	551:ab7a8de3ff10	3896
vcoubard	551:ab7a8de3ff10	3897	/* Peripheral: PPI */
vcoubard	551:ab7a8de3ff10	3898	/* Description: PPI controller. */
vcoubard	551:ab7a8de3ff10	3899
vcoubard	551:ab7a8de3ff10	3900	/* Register: PPI_CHEN */
vcoubard	551:ab7a8de3ff10	3901	/* Description: Channel enable. */
vcoubard	551:ab7a8de3ff10	3902
vcoubard	551:ab7a8de3ff10	3903	/* Bit 31 : Enable PPI channel 31. */
vcoubard	551:ab7a8de3ff10	3904	#define PPI_CHEN_CH31_Pos (31UL) /!< Position of CH31 field. /
vcoubard	551:ab7a8de3ff10	3905	#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /!< Bit mask of CH31 field. /
vcoubard	551:ab7a8de3ff10	3906	#define PPI_CHEN_CH31_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	3907	#define PPI_CHEN_CH31_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	3908
vcoubard	551:ab7a8de3ff10	3909	/* Bit 30 : Enable PPI channel 30. */
vcoubard	551:ab7a8de3ff10	3910	#define PPI_CHEN_CH30_Pos (30UL) /!< Position of CH30 field. /
vcoubard	551:ab7a8de3ff10	3911	#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /!< Bit mask of CH30 field. /
vcoubard	551:ab7a8de3ff10	3912	#define PPI_CHEN_CH30_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	3913	#define PPI_CHEN_CH30_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	3914
vcoubard	551:ab7a8de3ff10	3915	/* Bit 29 : Enable PPI channel 29. */
vcoubard	551:ab7a8de3ff10	3916	#define PPI_CHEN_CH29_Pos (29UL) /!< Position of CH29 field. /
vcoubard	551:ab7a8de3ff10	3917	#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /!< Bit mask of CH29 field. /
vcoubard	551:ab7a8de3ff10	3918	#define PPI_CHEN_CH29_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	3919	#define PPI_CHEN_CH29_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	3920
vcoubard	551:ab7a8de3ff10	3921	/* Bit 28 : Enable PPI channel 28. */
vcoubard	551:ab7a8de3ff10	3922	#define PPI_CHEN_CH28_Pos (28UL) /!< Position of CH28 field. /
vcoubard	551:ab7a8de3ff10	3923	#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /!< Bit mask of CH28 field. /
vcoubard	551:ab7a8de3ff10	3924	#define PPI_CHEN_CH28_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	3925	#define PPI_CHEN_CH28_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	3926
vcoubard	551:ab7a8de3ff10	3927	/* Bit 27 : Enable PPI channel 27. */
vcoubard	551:ab7a8de3ff10	3928	#define PPI_CHEN_CH27_Pos (27UL) /!< Position of CH27 field. /
vcoubard	551:ab7a8de3ff10	3929	#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /!< Bit mask of CH27 field. /
vcoubard	551:ab7a8de3ff10	3930	#define PPI_CHEN_CH27_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	3931	#define PPI_CHEN_CH27_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	3932
vcoubard	551:ab7a8de3ff10	3933	/* Bit 26 : Enable PPI channel 26. */
vcoubard	551:ab7a8de3ff10	3934	#define PPI_CHEN_CH26_Pos (26UL) /!< Position of CH26 field. /
vcoubard	551:ab7a8de3ff10	3935	#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /!< Bit mask of CH26 field. /
vcoubard	551:ab7a8de3ff10	3936	#define PPI_CHEN_CH26_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	3937	#define PPI_CHEN_CH26_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	3938
vcoubard	551:ab7a8de3ff10	3939	/* Bit 25 : Enable PPI channel 25. */
vcoubard	551:ab7a8de3ff10	3940	#define PPI_CHEN_CH25_Pos (25UL) /!< Position of CH25 field. /
vcoubard	551:ab7a8de3ff10	3941	#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /!< Bit mask of CH25 field. /
vcoubard	551:ab7a8de3ff10	3942	#define PPI_CHEN_CH25_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	3943	#define PPI_CHEN_CH25_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	3944
vcoubard	551:ab7a8de3ff10	3945	/* Bit 24 : Enable PPI channel 24. */
vcoubard	551:ab7a8de3ff10	3946	#define PPI_CHEN_CH24_Pos (24UL) /!< Position of CH24 field. /
vcoubard	551:ab7a8de3ff10	3947	#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /!< Bit mask of CH24 field. /
vcoubard	551:ab7a8de3ff10	3948	#define PPI_CHEN_CH24_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	3949	#define PPI_CHEN_CH24_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	3950
vcoubard	551:ab7a8de3ff10	3951	/* Bit 23 : Enable PPI channel 23. */
vcoubard	551:ab7a8de3ff10	3952	#define PPI_CHEN_CH23_Pos (23UL) /!< Position of CH23 field. /
vcoubard	551:ab7a8de3ff10	3953	#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /!< Bit mask of CH23 field. /
vcoubard	551:ab7a8de3ff10	3954	#define PPI_CHEN_CH23_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	3955	#define PPI_CHEN_CH23_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	3956
vcoubard	551:ab7a8de3ff10	3957	/* Bit 22 : Enable PPI channel 22. */
vcoubard	551:ab7a8de3ff10	3958	#define PPI_CHEN_CH22_Pos (22UL) /!< Position of CH22 field. /
vcoubard	551:ab7a8de3ff10	3959	#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /!< Bit mask of CH22 field. /
vcoubard	551:ab7a8de3ff10	3960	#define PPI_CHEN_CH22_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	3961	#define PPI_CHEN_CH22_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	3962
vcoubard	551:ab7a8de3ff10	3963	/* Bit 21 : Enable PPI channel 21. */
vcoubard	551:ab7a8de3ff10	3964	#define PPI_CHEN_CH21_Pos (21UL) /!< Position of CH21 field. /
vcoubard	551:ab7a8de3ff10	3965	#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /!< Bit mask of CH21 field. /
vcoubard	551:ab7a8de3ff10	3966	#define PPI_CHEN_CH21_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	3967	#define PPI_CHEN_CH21_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	3968
vcoubard	551:ab7a8de3ff10	3969	/* Bit 20 : Enable PPI channel 20. */
vcoubard	551:ab7a8de3ff10	3970	#define PPI_CHEN_CH20_Pos (20UL) /!< Position of CH20 field. /
vcoubard	551:ab7a8de3ff10	3971	#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /!< Bit mask of CH20 field. /
vcoubard	551:ab7a8de3ff10	3972	#define PPI_CHEN_CH20_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	3973	#define PPI_CHEN_CH20_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	3974
vcoubard	551:ab7a8de3ff10	3975	/* Bit 15 : Enable PPI channel 15. */
vcoubard	551:ab7a8de3ff10	3976	#define PPI_CHEN_CH15_Pos (15UL) /!< Position of CH15 field. /
vcoubard	551:ab7a8de3ff10	3977	#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /!< Bit mask of CH15 field. /
vcoubard	551:ab7a8de3ff10	3978	#define PPI_CHEN_CH15_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	3979	#define PPI_CHEN_CH15_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	3980
vcoubard	551:ab7a8de3ff10	3981	/* Bit 14 : Enable PPI channel 14. */
vcoubard	551:ab7a8de3ff10	3982	#define PPI_CHEN_CH14_Pos (14UL) /!< Position of CH14 field. /
vcoubard	551:ab7a8de3ff10	3983	#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /!< Bit mask of CH14 field. /
vcoubard	551:ab7a8de3ff10	3984	#define PPI_CHEN_CH14_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	3985	#define PPI_CHEN_CH14_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	3986
vcoubard	551:ab7a8de3ff10	3987	/* Bit 13 : Enable PPI channel 13. */
vcoubard	551:ab7a8de3ff10	3988	#define PPI_CHEN_CH13_Pos (13UL) /!< Position of CH13 field. /
vcoubard	551:ab7a8de3ff10	3989	#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /!< Bit mask of CH13 field. /
vcoubard	551:ab7a8de3ff10	3990	#define PPI_CHEN_CH13_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	3991	#define PPI_CHEN_CH13_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	3992
vcoubard	551:ab7a8de3ff10	3993	/* Bit 12 : Enable PPI channel 12. */
vcoubard	551:ab7a8de3ff10	3994	#define PPI_CHEN_CH12_Pos (12UL) /!< Position of CH12 field. /
vcoubard	551:ab7a8de3ff10	3995	#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /!< Bit mask of CH12 field. /
vcoubard	551:ab7a8de3ff10	3996	#define PPI_CHEN_CH12_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	3997	#define PPI_CHEN_CH12_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	3998
vcoubard	551:ab7a8de3ff10	3999	/* Bit 11 : Enable PPI channel 11. */
vcoubard	551:ab7a8de3ff10	4000	#define PPI_CHEN_CH11_Pos (11UL) /!< Position of CH11 field. /
vcoubard	551:ab7a8de3ff10	4001	#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /!< Bit mask of CH11 field. /
vcoubard	551:ab7a8de3ff10	4002	#define PPI_CHEN_CH11_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4003	#define PPI_CHEN_CH11_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4004
vcoubard	551:ab7a8de3ff10	4005	/* Bit 10 : Enable PPI channel 10. */
vcoubard	551:ab7a8de3ff10	4006	#define PPI_CHEN_CH10_Pos (10UL) /!< Position of CH10 field. /
vcoubard	551:ab7a8de3ff10	4007	#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /!< Bit mask of CH10 field. /
vcoubard	551:ab7a8de3ff10	4008	#define PPI_CHEN_CH10_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4009	#define PPI_CHEN_CH10_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4010
vcoubard	551:ab7a8de3ff10	4011	/* Bit 9 : Enable PPI channel 9. */
vcoubard	551:ab7a8de3ff10	4012	#define PPI_CHEN_CH9_Pos (9UL) /!< Position of CH9 field. /
vcoubard	551:ab7a8de3ff10	4013	#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /!< Bit mask of CH9 field. /
vcoubard	551:ab7a8de3ff10	4014	#define PPI_CHEN_CH9_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4015	#define PPI_CHEN_CH9_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4016
vcoubard	551:ab7a8de3ff10	4017	/* Bit 8 : Enable PPI channel 8. */
vcoubard	551:ab7a8de3ff10	4018	#define PPI_CHEN_CH8_Pos (8UL) /!< Position of CH8 field. /
vcoubard	551:ab7a8de3ff10	4019	#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /!< Bit mask of CH8 field. /
vcoubard	551:ab7a8de3ff10	4020	#define PPI_CHEN_CH8_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4021	#define PPI_CHEN_CH8_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4022
vcoubard	551:ab7a8de3ff10	4023	/* Bit 7 : Enable PPI channel 7. */
vcoubard	551:ab7a8de3ff10	4024	#define PPI_CHEN_CH7_Pos (7UL) /!< Position of CH7 field. /
vcoubard	551:ab7a8de3ff10	4025	#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /!< Bit mask of CH7 field. /
vcoubard	551:ab7a8de3ff10	4026	#define PPI_CHEN_CH7_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4027	#define PPI_CHEN_CH7_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4028
vcoubard	551:ab7a8de3ff10	4029	/* Bit 6 : Enable PPI channel 6. */
vcoubard	551:ab7a8de3ff10	4030	#define PPI_CHEN_CH6_Pos (6UL) /!< Position of CH6 field. /
vcoubard	551:ab7a8de3ff10	4031	#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /!< Bit mask of CH6 field. /
vcoubard	551:ab7a8de3ff10	4032	#define PPI_CHEN_CH6_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4033	#define PPI_CHEN_CH6_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4034
vcoubard	551:ab7a8de3ff10	4035	/* Bit 5 : Enable PPI channel 5. */
vcoubard	551:ab7a8de3ff10	4036	#define PPI_CHEN_CH5_Pos (5UL) /!< Position of CH5 field. /
vcoubard	551:ab7a8de3ff10	4037	#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /!< Bit mask of CH5 field. /
vcoubard	551:ab7a8de3ff10	4038	#define PPI_CHEN_CH5_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4039	#define PPI_CHEN_CH5_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4040
vcoubard	551:ab7a8de3ff10	4041	/* Bit 4 : Enable PPI channel 4. */
vcoubard	551:ab7a8de3ff10	4042	#define PPI_CHEN_CH4_Pos (4UL) /!< Position of CH4 field. /
vcoubard	551:ab7a8de3ff10	4043	#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /!< Bit mask of CH4 field. /
vcoubard	551:ab7a8de3ff10	4044	#define PPI_CHEN_CH4_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4045	#define PPI_CHEN_CH4_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4046
vcoubard	551:ab7a8de3ff10	4047	/* Bit 3 : Enable PPI channel 3. */
vcoubard	551:ab7a8de3ff10	4048	#define PPI_CHEN_CH3_Pos (3UL) /!< Position of CH3 field. /
vcoubard	551:ab7a8de3ff10	4049	#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /!< Bit mask of CH3 field. /
vcoubard	551:ab7a8de3ff10	4050	#define PPI_CHEN_CH3_Disabled (0UL) /!< Channel disabled /
vcoubard	551:ab7a8de3ff10	4051	#define PPI_CHEN_CH3_Enabled (1UL) /!< Channel enabled /
vcoubard	551:ab7a8de3ff10	4052
vcoubard	551:ab7a8de3ff10	4053	/* Bit 2 : Enable PPI channel 2. */
vcoubard	551:ab7a8de3ff10	4054	#define PPI_CHEN_CH2_Pos (2UL) /!< Position of CH2 field. /
vcoubard	551:ab7a8de3ff10	4055	#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /!< Bit mask of CH2 field. /
vcoubard	551:ab7a8de3ff10	4056	#define PPI_CHEN_CH2_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4057	#define PPI_CHEN_CH2_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4058
vcoubard	551:ab7a8de3ff10	4059	/* Bit 1 : Enable PPI channel 1. */
vcoubard	551:ab7a8de3ff10	4060	#define PPI_CHEN_CH1_Pos (1UL) /!< Position of CH1 field. /
vcoubard	551:ab7a8de3ff10	4061	#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /!< Bit mask of CH1 field. /
vcoubard	551:ab7a8de3ff10	4062	#define PPI_CHEN_CH1_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4063	#define PPI_CHEN_CH1_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4064
vcoubard	551:ab7a8de3ff10	4065	/* Bit 0 : Enable PPI channel 0. */
vcoubard	551:ab7a8de3ff10	4066	#define PPI_CHEN_CH0_Pos (0UL) /!< Position of CH0 field. /
vcoubard	551:ab7a8de3ff10	4067	#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /!< Bit mask of CH0 field. /
vcoubard	551:ab7a8de3ff10	4068	#define PPI_CHEN_CH0_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4069	#define PPI_CHEN_CH0_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4070
vcoubard	551:ab7a8de3ff10	4071	/* Register: PPI_CHENSET */
vcoubard	551:ab7a8de3ff10	4072	/* Description: Channel enable set. */
vcoubard	551:ab7a8de3ff10	4073
vcoubard	551:ab7a8de3ff10	4074	/* Bit 31 : Enable PPI channel 31. */
vcoubard	551:ab7a8de3ff10	4075	#define PPI_CHENSET_CH31_Pos (31UL) /!< Position of CH31 field. /
vcoubard	551:ab7a8de3ff10	4076	#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /!< Bit mask of CH31 field. /
vcoubard	551:ab7a8de3ff10	4077	#define PPI_CHENSET_CH31_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4078	#define PPI_CHENSET_CH31_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4079	#define PPI_CHENSET_CH31_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4080
vcoubard	551:ab7a8de3ff10	4081	/* Bit 30 : Enable PPI channel 30. */
vcoubard	551:ab7a8de3ff10	4082	#define PPI_CHENSET_CH30_Pos (30UL) /!< Position of CH30 field. /
vcoubard	551:ab7a8de3ff10	4083	#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /!< Bit mask of CH30 field. /
vcoubard	551:ab7a8de3ff10	4084	#define PPI_CHENSET_CH30_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4085	#define PPI_CHENSET_CH30_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4086	#define PPI_CHENSET_CH30_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4087
vcoubard	551:ab7a8de3ff10	4088	/* Bit 29 : Enable PPI channel 29. */
vcoubard	551:ab7a8de3ff10	4089	#define PPI_CHENSET_CH29_Pos (29UL) /!< Position of CH29 field. /
vcoubard	551:ab7a8de3ff10	4090	#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /!< Bit mask of CH29 field. /
vcoubard	551:ab7a8de3ff10	4091	#define PPI_CHENSET_CH29_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4092	#define PPI_CHENSET_CH29_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4093	#define PPI_CHENSET_CH29_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4094
vcoubard	551:ab7a8de3ff10	4095	/* Bit 28 : Enable PPI channel 28. */
vcoubard	551:ab7a8de3ff10	4096	#define PPI_CHENSET_CH28_Pos (28UL) /!< Position of CH28 field. /
vcoubard	551:ab7a8de3ff10	4097	#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /!< Bit mask of CH28 field. /
vcoubard	551:ab7a8de3ff10	4098	#define PPI_CHENSET_CH28_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4099	#define PPI_CHENSET_CH28_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4100	#define PPI_CHENSET_CH28_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4101
vcoubard	551:ab7a8de3ff10	4102	/* Bit 27 : Enable PPI channel 27. */
vcoubard	551:ab7a8de3ff10	4103	#define PPI_CHENSET_CH27_Pos (27UL) /!< Position of CH27 field. /
vcoubard	551:ab7a8de3ff10	4104	#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /!< Bit mask of CH27 field. /
vcoubard	551:ab7a8de3ff10	4105	#define PPI_CHENSET_CH27_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4106	#define PPI_CHENSET_CH27_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4107	#define PPI_CHENSET_CH27_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4108
vcoubard	551:ab7a8de3ff10	4109	/* Bit 26 : Enable PPI channel 26. */
vcoubard	551:ab7a8de3ff10	4110	#define PPI_CHENSET_CH26_Pos (26UL) /!< Position of CH26 field. /
vcoubard	551:ab7a8de3ff10	4111	#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /!< Bit mask of CH26 field. /
vcoubard	551:ab7a8de3ff10	4112	#define PPI_CHENSET_CH26_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4113	#define PPI_CHENSET_CH26_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4114	#define PPI_CHENSET_CH26_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4115
vcoubard	551:ab7a8de3ff10	4116	/* Bit 25 : Enable PPI channel 25. */
vcoubard	551:ab7a8de3ff10	4117	#define PPI_CHENSET_CH25_Pos (25UL) /!< Position of CH25 field. /
vcoubard	551:ab7a8de3ff10	4118	#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /!< Bit mask of CH25 field. /
vcoubard	551:ab7a8de3ff10	4119	#define PPI_CHENSET_CH25_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4120	#define PPI_CHENSET_CH25_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4121	#define PPI_CHENSET_CH25_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4122
vcoubard	551:ab7a8de3ff10	4123	/* Bit 24 : Enable PPI channel 24. */
vcoubard	551:ab7a8de3ff10	4124	#define PPI_CHENSET_CH24_Pos (24UL) /!< Position of CH24 field. /
vcoubard	551:ab7a8de3ff10	4125	#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /!< Bit mask of CH24 field. /
vcoubard	551:ab7a8de3ff10	4126	#define PPI_CHENSET_CH24_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4127	#define PPI_CHENSET_CH24_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4128	#define PPI_CHENSET_CH24_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4129
vcoubard	551:ab7a8de3ff10	4130	/* Bit 23 : Enable PPI channel 23. */
vcoubard	551:ab7a8de3ff10	4131	#define PPI_CHENSET_CH23_Pos (23UL) /!< Position of CH23 field. /
vcoubard	551:ab7a8de3ff10	4132	#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /!< Bit mask of CH23 field. /
vcoubard	551:ab7a8de3ff10	4133	#define PPI_CHENSET_CH23_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4134	#define PPI_CHENSET_CH23_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4135	#define PPI_CHENSET_CH23_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4136
vcoubard	551:ab7a8de3ff10	4137	/* Bit 22 : Enable PPI channel 22. */
vcoubard	551:ab7a8de3ff10	4138	#define PPI_CHENSET_CH22_Pos (22UL) /!< Position of CH22 field. /
vcoubard	551:ab7a8de3ff10	4139	#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /!< Bit mask of CH22 field. /
vcoubard	551:ab7a8de3ff10	4140	#define PPI_CHENSET_CH22_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4141	#define PPI_CHENSET_CH22_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4142	#define PPI_CHENSET_CH22_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4143
vcoubard	551:ab7a8de3ff10	4144	/* Bit 21 : Enable PPI channel 21. */
vcoubard	551:ab7a8de3ff10	4145	#define PPI_CHENSET_CH21_Pos (21UL) /!< Position of CH21 field. /
vcoubard	551:ab7a8de3ff10	4146	#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /!< Bit mask of CH21 field. /
vcoubard	551:ab7a8de3ff10	4147	#define PPI_CHENSET_CH21_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4148	#define PPI_CHENSET_CH21_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4149	#define PPI_CHENSET_CH21_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4150
vcoubard	551:ab7a8de3ff10	4151	/* Bit 20 : Enable PPI channel 20. */
vcoubard	551:ab7a8de3ff10	4152	#define PPI_CHENSET_CH20_Pos (20UL) /!< Position of CH20 field. /
vcoubard	551:ab7a8de3ff10	4153	#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /!< Bit mask of CH20 field. /
vcoubard	551:ab7a8de3ff10	4154	#define PPI_CHENSET_CH20_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4155	#define PPI_CHENSET_CH20_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4156	#define PPI_CHENSET_CH20_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4157
vcoubard	551:ab7a8de3ff10	4158	/* Bit 15 : Enable PPI channel 15. */
vcoubard	551:ab7a8de3ff10	4159	#define PPI_CHENSET_CH15_Pos (15UL) /!< Position of CH15 field. /
vcoubard	551:ab7a8de3ff10	4160	#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /!< Bit mask of CH15 field. /
vcoubard	551:ab7a8de3ff10	4161	#define PPI_CHENSET_CH15_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4162	#define PPI_CHENSET_CH15_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4163	#define PPI_CHENSET_CH15_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4164
vcoubard	551:ab7a8de3ff10	4165	/* Bit 14 : Enable PPI channel 14. */
vcoubard	551:ab7a8de3ff10	4166	#define PPI_CHENSET_CH14_Pos (14UL) /!< Position of CH14 field. /
vcoubard	551:ab7a8de3ff10	4167	#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /!< Bit mask of CH14 field. /
vcoubard	551:ab7a8de3ff10	4168	#define PPI_CHENSET_CH14_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4169	#define PPI_CHENSET_CH14_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4170	#define PPI_CHENSET_CH14_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4171
vcoubard	551:ab7a8de3ff10	4172	/* Bit 13 : Enable PPI channel 13. */
vcoubard	551:ab7a8de3ff10	4173	#define PPI_CHENSET_CH13_Pos (13UL) /!< Position of CH13 field. /
vcoubard	551:ab7a8de3ff10	4174	#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /!< Bit mask of CH13 field. /
vcoubard	551:ab7a8de3ff10	4175	#define PPI_CHENSET_CH13_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4176	#define PPI_CHENSET_CH13_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4177	#define PPI_CHENSET_CH13_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4178
vcoubard	551:ab7a8de3ff10	4179	/* Bit 12 : Enable PPI channel 12. */
vcoubard	551:ab7a8de3ff10	4180	#define PPI_CHENSET_CH12_Pos (12UL) /!< Position of CH12 field. /
vcoubard	551:ab7a8de3ff10	4181	#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /!< Bit mask of CH12 field. /
vcoubard	551:ab7a8de3ff10	4182	#define PPI_CHENSET_CH12_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4183	#define PPI_CHENSET_CH12_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4184	#define PPI_CHENSET_CH12_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4185
vcoubard	551:ab7a8de3ff10	4186	/* Bit 11 : Enable PPI channel 11. */
vcoubard	551:ab7a8de3ff10	4187	#define PPI_CHENSET_CH11_Pos (11UL) /!< Position of CH11 field. /
vcoubard	551:ab7a8de3ff10	4188	#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /!< Bit mask of CH11 field. /
vcoubard	551:ab7a8de3ff10	4189	#define PPI_CHENSET_CH11_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4190	#define PPI_CHENSET_CH11_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4191	#define PPI_CHENSET_CH11_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4192
vcoubard	551:ab7a8de3ff10	4193	/* Bit 10 : Enable PPI channel 10. */
vcoubard	551:ab7a8de3ff10	4194	#define PPI_CHENSET_CH10_Pos (10UL) /!< Position of CH10 field. /
vcoubard	551:ab7a8de3ff10	4195	#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /!< Bit mask of CH10 field. /
vcoubard	551:ab7a8de3ff10	4196	#define PPI_CHENSET_CH10_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4197	#define PPI_CHENSET_CH10_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4198	#define PPI_CHENSET_CH10_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4199
vcoubard	551:ab7a8de3ff10	4200	/* Bit 9 : Enable PPI channel 9. */
vcoubard	551:ab7a8de3ff10	4201	#define PPI_CHENSET_CH9_Pos (9UL) /!< Position of CH9 field. /
vcoubard	551:ab7a8de3ff10	4202	#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /!< Bit mask of CH9 field. /
vcoubard	551:ab7a8de3ff10	4203	#define PPI_CHENSET_CH9_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4204	#define PPI_CHENSET_CH9_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4205	#define PPI_CHENSET_CH9_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4206
vcoubard	551:ab7a8de3ff10	4207	/* Bit 8 : Enable PPI channel 8. */
vcoubard	551:ab7a8de3ff10	4208	#define PPI_CHENSET_CH8_Pos (8UL) /!< Position of CH8 field. /
vcoubard	551:ab7a8de3ff10	4209	#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /!< Bit mask of CH8 field. /
vcoubard	551:ab7a8de3ff10	4210	#define PPI_CHENSET_CH8_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4211	#define PPI_CHENSET_CH8_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4212	#define PPI_CHENSET_CH8_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4213
vcoubard	551:ab7a8de3ff10	4214	/* Bit 7 : Enable PPI channel 7. */
vcoubard	551:ab7a8de3ff10	4215	#define PPI_CHENSET_CH7_Pos (7UL) /!< Position of CH7 field. /
vcoubard	551:ab7a8de3ff10	4216	#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /!< Bit mask of CH7 field. /
vcoubard	551:ab7a8de3ff10	4217	#define PPI_CHENSET_CH7_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4218	#define PPI_CHENSET_CH7_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4219	#define PPI_CHENSET_CH7_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4220
vcoubard	551:ab7a8de3ff10	4221	/* Bit 6 : Enable PPI channel 6. */
vcoubard	551:ab7a8de3ff10	4222	#define PPI_CHENSET_CH6_Pos (6UL) /!< Position of CH6 field. /
vcoubard	551:ab7a8de3ff10	4223	#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /!< Bit mask of CH6 field. /
vcoubard	551:ab7a8de3ff10	4224	#define PPI_CHENSET_CH6_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4225	#define PPI_CHENSET_CH6_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4226	#define PPI_CHENSET_CH6_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4227
vcoubard	551:ab7a8de3ff10	4228	/* Bit 5 : Enable PPI channel 5. */
vcoubard	551:ab7a8de3ff10	4229	#define PPI_CHENSET_CH5_Pos (5UL) /!< Position of CH5 field. /
vcoubard	551:ab7a8de3ff10	4230	#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /!< Bit mask of CH5 field. /
vcoubard	551:ab7a8de3ff10	4231	#define PPI_CHENSET_CH5_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4232	#define PPI_CHENSET_CH5_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4233	#define PPI_CHENSET_CH5_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4234
vcoubard	551:ab7a8de3ff10	4235	/* Bit 4 : Enable PPI channel 4. */
vcoubard	551:ab7a8de3ff10	4236	#define PPI_CHENSET_CH4_Pos (4UL) /!< Position of CH4 field. /
vcoubard	551:ab7a8de3ff10	4237	#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /!< Bit mask of CH4 field. /
vcoubard	551:ab7a8de3ff10	4238	#define PPI_CHENSET_CH4_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4239	#define PPI_CHENSET_CH4_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4240	#define PPI_CHENSET_CH4_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4241
vcoubard	551:ab7a8de3ff10	4242	/* Bit 3 : Enable PPI channel 3. */
vcoubard	551:ab7a8de3ff10	4243	#define PPI_CHENSET_CH3_Pos (3UL) /!< Position of CH3 field. /
vcoubard	551:ab7a8de3ff10	4244	#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /!< Bit mask of CH3 field. /
vcoubard	551:ab7a8de3ff10	4245	#define PPI_CHENSET_CH3_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4246	#define PPI_CHENSET_CH3_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4247	#define PPI_CHENSET_CH3_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4248
vcoubard	551:ab7a8de3ff10	4249	/* Bit 2 : Enable PPI channel 2. */
vcoubard	551:ab7a8de3ff10	4250	#define PPI_CHENSET_CH2_Pos (2UL) /!< Position of CH2 field. /
vcoubard	551:ab7a8de3ff10	4251	#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /!< Bit mask of CH2 field. /
vcoubard	551:ab7a8de3ff10	4252	#define PPI_CHENSET_CH2_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4253	#define PPI_CHENSET_CH2_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4254	#define PPI_CHENSET_CH2_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4255
vcoubard	551:ab7a8de3ff10	4256	/* Bit 1 : Enable PPI channel 1. */
vcoubard	551:ab7a8de3ff10	4257	#define PPI_CHENSET_CH1_Pos (1UL) /!< Position of CH1 field. /
vcoubard	551:ab7a8de3ff10	4258	#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /!< Bit mask of CH1 field. /
vcoubard	551:ab7a8de3ff10	4259	#define PPI_CHENSET_CH1_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4260	#define PPI_CHENSET_CH1_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4261	#define PPI_CHENSET_CH1_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4262
vcoubard	551:ab7a8de3ff10	4263	/* Bit 0 : Enable PPI channel 0. */
vcoubard	551:ab7a8de3ff10	4264	#define PPI_CHENSET_CH0_Pos (0UL) /!< Position of CH0 field. /
vcoubard	551:ab7a8de3ff10	4265	#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /!< Bit mask of CH0 field. /
vcoubard	551:ab7a8de3ff10	4266	#define PPI_CHENSET_CH0_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4267	#define PPI_CHENSET_CH0_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4268	#define PPI_CHENSET_CH0_Set (1UL) /!< Enable channel on write. /
vcoubard	551:ab7a8de3ff10	4269
vcoubard	551:ab7a8de3ff10	4270	/* Register: PPI_CHENCLR */
vcoubard	551:ab7a8de3ff10	4271	/* Description: Channel enable clear. */
vcoubard	551:ab7a8de3ff10	4272
vcoubard	551:ab7a8de3ff10	4273	/* Bit 31 : Disable PPI channel 31. */
vcoubard	551:ab7a8de3ff10	4274	#define PPI_CHENCLR_CH31_Pos (31UL) /!< Position of CH31 field. /
vcoubard	551:ab7a8de3ff10	4275	#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /!< Bit mask of CH31 field. /
vcoubard	551:ab7a8de3ff10	4276	#define PPI_CHENCLR_CH31_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4277	#define PPI_CHENCLR_CH31_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4278	#define PPI_CHENCLR_CH31_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4279
vcoubard	551:ab7a8de3ff10	4280	/* Bit 30 : Disable PPI channel 30. */
vcoubard	551:ab7a8de3ff10	4281	#define PPI_CHENCLR_CH30_Pos (30UL) /!< Position of CH30 field. /
vcoubard	551:ab7a8de3ff10	4282	#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /!< Bit mask of CH30 field. /
vcoubard	551:ab7a8de3ff10	4283	#define PPI_CHENCLR_CH30_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4284	#define PPI_CHENCLR_CH30_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4285	#define PPI_CHENCLR_CH30_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4286
vcoubard	551:ab7a8de3ff10	4287	/* Bit 29 : Disable PPI channel 29. */
vcoubard	551:ab7a8de3ff10	4288	#define PPI_CHENCLR_CH29_Pos (29UL) /!< Position of CH29 field. /
vcoubard	551:ab7a8de3ff10	4289	#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /!< Bit mask of CH29 field. /
vcoubard	551:ab7a8de3ff10	4290	#define PPI_CHENCLR_CH29_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4291	#define PPI_CHENCLR_CH29_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4292	#define PPI_CHENCLR_CH29_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4293
vcoubard	551:ab7a8de3ff10	4294	/* Bit 28 : Disable PPI channel 28. */
vcoubard	551:ab7a8de3ff10	4295	#define PPI_CHENCLR_CH28_Pos (28UL) /!< Position of CH28 field. /
vcoubard	551:ab7a8de3ff10	4296	#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /!< Bit mask of CH28 field. /
vcoubard	551:ab7a8de3ff10	4297	#define PPI_CHENCLR_CH28_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4298	#define PPI_CHENCLR_CH28_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4299	#define PPI_CHENCLR_CH28_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4300
vcoubard	551:ab7a8de3ff10	4301	/* Bit 27 : Disable PPI channel 27. */
vcoubard	551:ab7a8de3ff10	4302	#define PPI_CHENCLR_CH27_Pos (27UL) /!< Position of CH27 field. /
vcoubard	551:ab7a8de3ff10	4303	#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /!< Bit mask of CH27 field. /
vcoubard	551:ab7a8de3ff10	4304	#define PPI_CHENCLR_CH27_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4305	#define PPI_CHENCLR_CH27_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4306	#define PPI_CHENCLR_CH27_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4307
vcoubard	551:ab7a8de3ff10	4308	/* Bit 26 : Disable PPI channel 26. */
vcoubard	551:ab7a8de3ff10	4309	#define PPI_CHENCLR_CH26_Pos (26UL) /!< Position of CH26 field. /
vcoubard	551:ab7a8de3ff10	4310	#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /!< Bit mask of CH26 field. /
vcoubard	551:ab7a8de3ff10	4311	#define PPI_CHENCLR_CH26_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4312	#define PPI_CHENCLR_CH26_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4313	#define PPI_CHENCLR_CH26_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4314
vcoubard	551:ab7a8de3ff10	4315	/* Bit 25 : Disable PPI channel 25. */
vcoubard	551:ab7a8de3ff10	4316	#define PPI_CHENCLR_CH25_Pos (25UL) /!< Position of CH25 field. /
vcoubard	551:ab7a8de3ff10	4317	#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /!< Bit mask of CH25 field. /
vcoubard	551:ab7a8de3ff10	4318	#define PPI_CHENCLR_CH25_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4319	#define PPI_CHENCLR_CH25_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4320	#define PPI_CHENCLR_CH25_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4321
vcoubard	551:ab7a8de3ff10	4322	/* Bit 24 : Disable PPI channel 24. */
vcoubard	551:ab7a8de3ff10	4323	#define PPI_CHENCLR_CH24_Pos (24UL) /!< Position of CH24 field. /
vcoubard	551:ab7a8de3ff10	4324	#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /!< Bit mask of CH24 field. /
vcoubard	551:ab7a8de3ff10	4325	#define PPI_CHENCLR_CH24_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4326	#define PPI_CHENCLR_CH24_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4327	#define PPI_CHENCLR_CH24_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4328
vcoubard	551:ab7a8de3ff10	4329	/* Bit 23 : Disable PPI channel 23. */
vcoubard	551:ab7a8de3ff10	4330	#define PPI_CHENCLR_CH23_Pos (23UL) /!< Position of CH23 field. /
vcoubard	551:ab7a8de3ff10	4331	#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /!< Bit mask of CH23 field. /
vcoubard	551:ab7a8de3ff10	4332	#define PPI_CHENCLR_CH23_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4333	#define PPI_CHENCLR_CH23_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4334	#define PPI_CHENCLR_CH23_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4335
vcoubard	551:ab7a8de3ff10	4336	/* Bit 22 : Disable PPI channel 22. */
vcoubard	551:ab7a8de3ff10	4337	#define PPI_CHENCLR_CH22_Pos (22UL) /!< Position of CH22 field. /
vcoubard	551:ab7a8de3ff10	4338	#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /!< Bit mask of CH22 field. /
vcoubard	551:ab7a8de3ff10	4339	#define PPI_CHENCLR_CH22_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4340	#define PPI_CHENCLR_CH22_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4341	#define PPI_CHENCLR_CH22_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4342
vcoubard	551:ab7a8de3ff10	4343	/* Bit 21 : Disable PPI channel 21. */
vcoubard	551:ab7a8de3ff10	4344	#define PPI_CHENCLR_CH21_Pos (21UL) /!< Position of CH21 field. /
vcoubard	551:ab7a8de3ff10	4345	#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /!< Bit mask of CH21 field. /
vcoubard	551:ab7a8de3ff10	4346	#define PPI_CHENCLR_CH21_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4347	#define PPI_CHENCLR_CH21_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4348	#define PPI_CHENCLR_CH21_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4349
vcoubard	551:ab7a8de3ff10	4350	/* Bit 20 : Disable PPI channel 20. */
vcoubard	551:ab7a8de3ff10	4351	#define PPI_CHENCLR_CH20_Pos (20UL) /!< Position of CH20 field. /
vcoubard	551:ab7a8de3ff10	4352	#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /!< Bit mask of CH20 field. /
vcoubard	551:ab7a8de3ff10	4353	#define PPI_CHENCLR_CH20_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4354	#define PPI_CHENCLR_CH20_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4355	#define PPI_CHENCLR_CH20_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4356
vcoubard	551:ab7a8de3ff10	4357	/* Bit 15 : Disable PPI channel 15. */
vcoubard	551:ab7a8de3ff10	4358	#define PPI_CHENCLR_CH15_Pos (15UL) /!< Position of CH15 field. /
vcoubard	551:ab7a8de3ff10	4359	#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /!< Bit mask of CH15 field. /
vcoubard	551:ab7a8de3ff10	4360	#define PPI_CHENCLR_CH15_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4361	#define PPI_CHENCLR_CH15_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4362	#define PPI_CHENCLR_CH15_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4363
vcoubard	551:ab7a8de3ff10	4364	/* Bit 14 : Disable PPI channel 14. */
vcoubard	551:ab7a8de3ff10	4365	#define PPI_CHENCLR_CH14_Pos (14UL) /!< Position of CH14 field. /
vcoubard	551:ab7a8de3ff10	4366	#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /!< Bit mask of CH14 field. /
vcoubard	551:ab7a8de3ff10	4367	#define PPI_CHENCLR_CH14_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4368	#define PPI_CHENCLR_CH14_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4369	#define PPI_CHENCLR_CH14_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4370
vcoubard	551:ab7a8de3ff10	4371	/* Bit 13 : Disable PPI channel 13. */
vcoubard	551:ab7a8de3ff10	4372	#define PPI_CHENCLR_CH13_Pos (13UL) /!< Position of CH13 field. /
vcoubard	551:ab7a8de3ff10	4373	#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /!< Bit mask of CH13 field. /
vcoubard	551:ab7a8de3ff10	4374	#define PPI_CHENCLR_CH13_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4375	#define PPI_CHENCLR_CH13_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4376	#define PPI_CHENCLR_CH13_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4377
vcoubard	551:ab7a8de3ff10	4378	/* Bit 12 : Disable PPI channel 12. */
vcoubard	551:ab7a8de3ff10	4379	#define PPI_CHENCLR_CH12_Pos (12UL) /!< Position of CH12 field. /
vcoubard	551:ab7a8de3ff10	4380	#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /!< Bit mask of CH12 field. /
vcoubard	551:ab7a8de3ff10	4381	#define PPI_CHENCLR_CH12_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4382	#define PPI_CHENCLR_CH12_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4383	#define PPI_CHENCLR_CH12_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4384
vcoubard	551:ab7a8de3ff10	4385	/* Bit 11 : Disable PPI channel 11. */
vcoubard	551:ab7a8de3ff10	4386	#define PPI_CHENCLR_CH11_Pos (11UL) /!< Position of CH11 field. /
vcoubard	551:ab7a8de3ff10	4387	#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /!< Bit mask of CH11 field. /
vcoubard	551:ab7a8de3ff10	4388	#define PPI_CHENCLR_CH11_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4389	#define PPI_CHENCLR_CH11_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4390	#define PPI_CHENCLR_CH11_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4391
vcoubard	551:ab7a8de3ff10	4392	/* Bit 10 : Disable PPI channel 10. */
vcoubard	551:ab7a8de3ff10	4393	#define PPI_CHENCLR_CH10_Pos (10UL) /!< Position of CH10 field. /
vcoubard	551:ab7a8de3ff10	4394	#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /!< Bit mask of CH10 field. /
vcoubard	551:ab7a8de3ff10	4395	#define PPI_CHENCLR_CH10_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4396	#define PPI_CHENCLR_CH10_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4397	#define PPI_CHENCLR_CH10_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4398
vcoubard	551:ab7a8de3ff10	4399	/* Bit 9 : Disable PPI channel 9. */
vcoubard	551:ab7a8de3ff10	4400	#define PPI_CHENCLR_CH9_Pos (9UL) /!< Position of CH9 field. /
vcoubard	551:ab7a8de3ff10	4401	#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /!< Bit mask of CH9 field. /
vcoubard	551:ab7a8de3ff10	4402	#define PPI_CHENCLR_CH9_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4403	#define PPI_CHENCLR_CH9_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4404	#define PPI_CHENCLR_CH9_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4405
vcoubard	551:ab7a8de3ff10	4406	/* Bit 8 : Disable PPI channel 8. */
vcoubard	551:ab7a8de3ff10	4407	#define PPI_CHENCLR_CH8_Pos (8UL) /!< Position of CH8 field. /
vcoubard	551:ab7a8de3ff10	4408	#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /!< Bit mask of CH8 field. /
vcoubard	551:ab7a8de3ff10	4409	#define PPI_CHENCLR_CH8_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4410	#define PPI_CHENCLR_CH8_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4411	#define PPI_CHENCLR_CH8_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4412
vcoubard	551:ab7a8de3ff10	4413	/* Bit 7 : Disable PPI channel 7. */
vcoubard	551:ab7a8de3ff10	4414	#define PPI_CHENCLR_CH7_Pos (7UL) /!< Position of CH7 field. /
vcoubard	551:ab7a8de3ff10	4415	#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /!< Bit mask of CH7 field. /
vcoubard	551:ab7a8de3ff10	4416	#define PPI_CHENCLR_CH7_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4417	#define PPI_CHENCLR_CH7_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4418	#define PPI_CHENCLR_CH7_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4419
vcoubard	551:ab7a8de3ff10	4420	/* Bit 6 : Disable PPI channel 6. */
vcoubard	551:ab7a8de3ff10	4421	#define PPI_CHENCLR_CH6_Pos (6UL) /!< Position of CH6 field. /
vcoubard	551:ab7a8de3ff10	4422	#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /!< Bit mask of CH6 field. /
vcoubard	551:ab7a8de3ff10	4423	#define PPI_CHENCLR_CH6_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4424	#define PPI_CHENCLR_CH6_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4425	#define PPI_CHENCLR_CH6_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4426
vcoubard	551:ab7a8de3ff10	4427	/* Bit 5 : Disable PPI channel 5. */
vcoubard	551:ab7a8de3ff10	4428	#define PPI_CHENCLR_CH5_Pos (5UL) /!< Position of CH5 field. /
vcoubard	551:ab7a8de3ff10	4429	#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /!< Bit mask of CH5 field. /
vcoubard	551:ab7a8de3ff10	4430	#define PPI_CHENCLR_CH5_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4431	#define PPI_CHENCLR_CH5_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4432	#define PPI_CHENCLR_CH5_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4433
vcoubard	551:ab7a8de3ff10	4434	/* Bit 4 : Disable PPI channel 4. */
vcoubard	551:ab7a8de3ff10	4435	#define PPI_CHENCLR_CH4_Pos (4UL) /!< Position of CH4 field. /
vcoubard	551:ab7a8de3ff10	4436	#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /!< Bit mask of CH4 field. /
vcoubard	551:ab7a8de3ff10	4437	#define PPI_CHENCLR_CH4_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4438	#define PPI_CHENCLR_CH4_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4439	#define PPI_CHENCLR_CH4_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4440
vcoubard	551:ab7a8de3ff10	4441	/* Bit 3 : Disable PPI channel 3. */
vcoubard	551:ab7a8de3ff10	4442	#define PPI_CHENCLR_CH3_Pos (3UL) /!< Position of CH3 field. /
vcoubard	551:ab7a8de3ff10	4443	#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /!< Bit mask of CH3 field. /
vcoubard	551:ab7a8de3ff10	4444	#define PPI_CHENCLR_CH3_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4445	#define PPI_CHENCLR_CH3_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4446	#define PPI_CHENCLR_CH3_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4447
vcoubard	551:ab7a8de3ff10	4448	/* Bit 2 : Disable PPI channel 2. */
vcoubard	551:ab7a8de3ff10	4449	#define PPI_CHENCLR_CH2_Pos (2UL) /!< Position of CH2 field. /
vcoubard	551:ab7a8de3ff10	4450	#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /!< Bit mask of CH2 field. /
vcoubard	551:ab7a8de3ff10	4451	#define PPI_CHENCLR_CH2_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4452	#define PPI_CHENCLR_CH2_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4453	#define PPI_CHENCLR_CH2_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4454
vcoubard	551:ab7a8de3ff10	4455	/* Bit 1 : Disable PPI channel 1. */
vcoubard	551:ab7a8de3ff10	4456	#define PPI_CHENCLR_CH1_Pos (1UL) /!< Position of CH1 field. /
vcoubard	551:ab7a8de3ff10	4457	#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /!< Bit mask of CH1 field. /
vcoubard	551:ab7a8de3ff10	4458	#define PPI_CHENCLR_CH1_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4459	#define PPI_CHENCLR_CH1_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4460	#define PPI_CHENCLR_CH1_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4461
vcoubard	551:ab7a8de3ff10	4462	/* Bit 0 : Disable PPI channel 0. */
vcoubard	551:ab7a8de3ff10	4463	#define PPI_CHENCLR_CH0_Pos (0UL) /!< Position of CH0 field. /
vcoubard	551:ab7a8de3ff10	4464	#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /!< Bit mask of CH0 field. /
vcoubard	551:ab7a8de3ff10	4465	#define PPI_CHENCLR_CH0_Disabled (0UL) /!< Channel disabled. /
vcoubard	551:ab7a8de3ff10	4466	#define PPI_CHENCLR_CH0_Enabled (1UL) /!< Channel enabled. /
vcoubard	551:ab7a8de3ff10	4467	#define PPI_CHENCLR_CH0_Clear (1UL) /!< Disable channel on write. /
vcoubard	551:ab7a8de3ff10	4468
vcoubard	551:ab7a8de3ff10	4469	/* Register: PPI_CHG */
vcoubard	551:ab7a8de3ff10	4470	/* Description: Channel group configuration. */
vcoubard	551:ab7a8de3ff10	4471
vcoubard	551:ab7a8de3ff10	4472	/* Bit 31 : Include CH31 in channel group. */
vcoubard	551:ab7a8de3ff10	4473	#define PPI_CHG_CH31_Pos (31UL) /!< Position of CH31 field. /
vcoubard	551:ab7a8de3ff10	4474	#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /!< Bit mask of CH31 field. /
vcoubard	551:ab7a8de3ff10	4475	#define PPI_CHG_CH31_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4476	#define PPI_CHG_CH31_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4477
vcoubard	551:ab7a8de3ff10	4478	/* Bit 30 : Include CH30 in channel group. */
vcoubard	551:ab7a8de3ff10	4479	#define PPI_CHG_CH30_Pos (30UL) /!< Position of CH30 field. /
vcoubard	551:ab7a8de3ff10	4480	#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /!< Bit mask of CH30 field. /
vcoubard	551:ab7a8de3ff10	4481	#define PPI_CHG_CH30_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4482	#define PPI_CHG_CH30_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4483
vcoubard	551:ab7a8de3ff10	4484	/* Bit 29 : Include CH29 in channel group. */
vcoubard	551:ab7a8de3ff10	4485	#define PPI_CHG_CH29_Pos (29UL) /!< Position of CH29 field. /
vcoubard	551:ab7a8de3ff10	4486	#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /!< Bit mask of CH29 field. /
vcoubard	551:ab7a8de3ff10	4487	#define PPI_CHG_CH29_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4488	#define PPI_CHG_CH29_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4489
vcoubard	551:ab7a8de3ff10	4490	/* Bit 28 : Include CH28 in channel group. */
vcoubard	551:ab7a8de3ff10	4491	#define PPI_CHG_CH28_Pos (28UL) /!< Position of CH28 field. /
vcoubard	551:ab7a8de3ff10	4492	#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /!< Bit mask of CH28 field. /
vcoubard	551:ab7a8de3ff10	4493	#define PPI_CHG_CH28_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4494	#define PPI_CHG_CH28_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4495
vcoubard	551:ab7a8de3ff10	4496	/* Bit 27 : Include CH27 in channel group. */
vcoubard	551:ab7a8de3ff10	4497	#define PPI_CHG_CH27_Pos (27UL) /!< Position of CH27 field. /
vcoubard	551:ab7a8de3ff10	4498	#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /!< Bit mask of CH27 field. /
vcoubard	551:ab7a8de3ff10	4499	#define PPI_CHG_CH27_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4500	#define PPI_CHG_CH27_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4501
vcoubard	551:ab7a8de3ff10	4502	/* Bit 26 : Include CH26 in channel group. */
vcoubard	551:ab7a8de3ff10	4503	#define PPI_CHG_CH26_Pos (26UL) /!< Position of CH26 field. /
vcoubard	551:ab7a8de3ff10	4504	#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /!< Bit mask of CH26 field. /
vcoubard	551:ab7a8de3ff10	4505	#define PPI_CHG_CH26_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4506	#define PPI_CHG_CH26_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4507
vcoubard	551:ab7a8de3ff10	4508	/* Bit 25 : Include CH25 in channel group. */
vcoubard	551:ab7a8de3ff10	4509	#define PPI_CHG_CH25_Pos (25UL) /!< Position of CH25 field. /
vcoubard	551:ab7a8de3ff10	4510	#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /!< Bit mask of CH25 field. /
vcoubard	551:ab7a8de3ff10	4511	#define PPI_CHG_CH25_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4512	#define PPI_CHG_CH25_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4513
vcoubard	551:ab7a8de3ff10	4514	/* Bit 24 : Include CH24 in channel group. */
vcoubard	551:ab7a8de3ff10	4515	#define PPI_CHG_CH24_Pos (24UL) /!< Position of CH24 field. /
vcoubard	551:ab7a8de3ff10	4516	#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /!< Bit mask of CH24 field. /
vcoubard	551:ab7a8de3ff10	4517	#define PPI_CHG_CH24_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4518	#define PPI_CHG_CH24_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4519
vcoubard	551:ab7a8de3ff10	4520	/* Bit 23 : Include CH23 in channel group. */
vcoubard	551:ab7a8de3ff10	4521	#define PPI_CHG_CH23_Pos (23UL) /!< Position of CH23 field. /
vcoubard	551:ab7a8de3ff10	4522	#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /!< Bit mask of CH23 field. /
vcoubard	551:ab7a8de3ff10	4523	#define PPI_CHG_CH23_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4524	#define PPI_CHG_CH23_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4525
vcoubard	551:ab7a8de3ff10	4526	/* Bit 22 : Include CH22 in channel group. */
vcoubard	551:ab7a8de3ff10	4527	#define PPI_CHG_CH22_Pos (22UL) /!< Position of CH22 field. /
vcoubard	551:ab7a8de3ff10	4528	#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /!< Bit mask of CH22 field. /
vcoubard	551:ab7a8de3ff10	4529	#define PPI_CHG_CH22_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4530	#define PPI_CHG_CH22_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4531
vcoubard	551:ab7a8de3ff10	4532	/* Bit 21 : Include CH21 in channel group. */
vcoubard	551:ab7a8de3ff10	4533	#define PPI_CHG_CH21_Pos (21UL) /!< Position of CH21 field. /
vcoubard	551:ab7a8de3ff10	4534	#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /!< Bit mask of CH21 field. /
vcoubard	551:ab7a8de3ff10	4535	#define PPI_CHG_CH21_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4536	#define PPI_CHG_CH21_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4537
vcoubard	551:ab7a8de3ff10	4538	/* Bit 20 : Include CH20 in channel group. */
vcoubard	551:ab7a8de3ff10	4539	#define PPI_CHG_CH20_Pos (20UL) /!< Position of CH20 field. /
vcoubard	551:ab7a8de3ff10	4540	#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /!< Bit mask of CH20 field. /
vcoubard	551:ab7a8de3ff10	4541	#define PPI_CHG_CH20_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4542	#define PPI_CHG_CH20_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4543
vcoubard	551:ab7a8de3ff10	4544	/* Bit 15 : Include CH15 in channel group. */
vcoubard	551:ab7a8de3ff10	4545	#define PPI_CHG_CH15_Pos (15UL) /!< Position of CH15 field. /
vcoubard	551:ab7a8de3ff10	4546	#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /!< Bit mask of CH15 field. /
vcoubard	551:ab7a8de3ff10	4547	#define PPI_CHG_CH15_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4548	#define PPI_CHG_CH15_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4549
vcoubard	551:ab7a8de3ff10	4550	/* Bit 14 : Include CH14 in channel group. */
vcoubard	551:ab7a8de3ff10	4551	#define PPI_CHG_CH14_Pos (14UL) /!< Position of CH14 field. /
vcoubard	551:ab7a8de3ff10	4552	#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /!< Bit mask of CH14 field. /
vcoubard	551:ab7a8de3ff10	4553	#define PPI_CHG_CH14_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4554	#define PPI_CHG_CH14_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4555
vcoubard	551:ab7a8de3ff10	4556	/* Bit 13 : Include CH13 in channel group. */
vcoubard	551:ab7a8de3ff10	4557	#define PPI_CHG_CH13_Pos (13UL) /!< Position of CH13 field. /
vcoubard	551:ab7a8de3ff10	4558	#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /!< Bit mask of CH13 field. /
vcoubard	551:ab7a8de3ff10	4559	#define PPI_CHG_CH13_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4560	#define PPI_CHG_CH13_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4561
vcoubard	551:ab7a8de3ff10	4562	/* Bit 12 : Include CH12 in channel group. */
vcoubard	551:ab7a8de3ff10	4563	#define PPI_CHG_CH12_Pos (12UL) /!< Position of CH12 field. /
vcoubard	551:ab7a8de3ff10	4564	#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /!< Bit mask of CH12 field. /
vcoubard	551:ab7a8de3ff10	4565	#define PPI_CHG_CH12_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4566	#define PPI_CHG_CH12_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4567
vcoubard	551:ab7a8de3ff10	4568	/* Bit 11 : Include CH11 in channel group. */
vcoubard	551:ab7a8de3ff10	4569	#define PPI_CHG_CH11_Pos (11UL) /!< Position of CH11 field. /
vcoubard	551:ab7a8de3ff10	4570	#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /!< Bit mask of CH11 field. /
vcoubard	551:ab7a8de3ff10	4571	#define PPI_CHG_CH11_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4572	#define PPI_CHG_CH11_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4573
vcoubard	551:ab7a8de3ff10	4574	/* Bit 10 : Include CH10 in channel group. */
vcoubard	551:ab7a8de3ff10	4575	#define PPI_CHG_CH10_Pos (10UL) /!< Position of CH10 field. /
vcoubard	551:ab7a8de3ff10	4576	#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /!< Bit mask of CH10 field. /
vcoubard	551:ab7a8de3ff10	4577	#define PPI_CHG_CH10_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4578	#define PPI_CHG_CH10_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4579
vcoubard	551:ab7a8de3ff10	4580	/* Bit 9 : Include CH9 in channel group. */
vcoubard	551:ab7a8de3ff10	4581	#define PPI_CHG_CH9_Pos (9UL) /!< Position of CH9 field. /
vcoubard	551:ab7a8de3ff10	4582	#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /!< Bit mask of CH9 field. /
vcoubard	551:ab7a8de3ff10	4583	#define PPI_CHG_CH9_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4584	#define PPI_CHG_CH9_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4585
vcoubard	551:ab7a8de3ff10	4586	/* Bit 8 : Include CH8 in channel group. */
vcoubard	551:ab7a8de3ff10	4587	#define PPI_CHG_CH8_Pos (8UL) /!< Position of CH8 field. /
vcoubard	551:ab7a8de3ff10	4588	#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /!< Bit mask of CH8 field. /
vcoubard	551:ab7a8de3ff10	4589	#define PPI_CHG_CH8_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4590	#define PPI_CHG_CH8_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4591
vcoubard	551:ab7a8de3ff10	4592	/* Bit 7 : Include CH7 in channel group. */
vcoubard	551:ab7a8de3ff10	4593	#define PPI_CHG_CH7_Pos (7UL) /!< Position of CH7 field. /
vcoubard	551:ab7a8de3ff10	4594	#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /!< Bit mask of CH7 field. /
vcoubard	551:ab7a8de3ff10	4595	#define PPI_CHG_CH7_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4596	#define PPI_CHG_CH7_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4597
vcoubard	551:ab7a8de3ff10	4598	/* Bit 6 : Include CH6 in channel group. */
vcoubard	551:ab7a8de3ff10	4599	#define PPI_CHG_CH6_Pos (6UL) /!< Position of CH6 field. /
vcoubard	551:ab7a8de3ff10	4600	#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /!< Bit mask of CH6 field. /
vcoubard	551:ab7a8de3ff10	4601	#define PPI_CHG_CH6_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4602	#define PPI_CHG_CH6_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4603
vcoubard	551:ab7a8de3ff10	4604	/* Bit 5 : Include CH5 in channel group. */
vcoubard	551:ab7a8de3ff10	4605	#define PPI_CHG_CH5_Pos (5UL) /!< Position of CH5 field. /
vcoubard	551:ab7a8de3ff10	4606	#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /!< Bit mask of CH5 field. /
vcoubard	551:ab7a8de3ff10	4607	#define PPI_CHG_CH5_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4608	#define PPI_CHG_CH5_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4609
vcoubard	551:ab7a8de3ff10	4610	/* Bit 4 : Include CH4 in channel group. */
vcoubard	551:ab7a8de3ff10	4611	#define PPI_CHG_CH4_Pos (4UL) /!< Position of CH4 field. /
vcoubard	551:ab7a8de3ff10	4612	#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /!< Bit mask of CH4 field. /
vcoubard	551:ab7a8de3ff10	4613	#define PPI_CHG_CH4_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4614	#define PPI_CHG_CH4_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4615
vcoubard	551:ab7a8de3ff10	4616	/* Bit 3 : Include CH3 in channel group. */
vcoubard	551:ab7a8de3ff10	4617	#define PPI_CHG_CH3_Pos (3UL) /!< Position of CH3 field. /
vcoubard	551:ab7a8de3ff10	4618	#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /!< Bit mask of CH3 field. /
vcoubard	551:ab7a8de3ff10	4619	#define PPI_CHG_CH3_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4620	#define PPI_CHG_CH3_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4621
vcoubard	551:ab7a8de3ff10	4622	/* Bit 2 : Include CH2 in channel group. */
vcoubard	551:ab7a8de3ff10	4623	#define PPI_CHG_CH2_Pos (2UL) /!< Position of CH2 field. /
vcoubard	551:ab7a8de3ff10	4624	#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /!< Bit mask of CH2 field. /
vcoubard	551:ab7a8de3ff10	4625	#define PPI_CHG_CH2_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4626	#define PPI_CHG_CH2_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4627
vcoubard	551:ab7a8de3ff10	4628	/* Bit 1 : Include CH1 in channel group. */
vcoubard	551:ab7a8de3ff10	4629	#define PPI_CHG_CH1_Pos (1UL) /!< Position of CH1 field. /
vcoubard	551:ab7a8de3ff10	4630	#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /!< Bit mask of CH1 field. /
vcoubard	551:ab7a8de3ff10	4631	#define PPI_CHG_CH1_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4632	#define PPI_CHG_CH1_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4633
vcoubard	551:ab7a8de3ff10	4634	/* Bit 0 : Include CH0 in channel group. */
vcoubard	551:ab7a8de3ff10	4635	#define PPI_CHG_CH0_Pos (0UL) /!< Position of CH0 field. /
vcoubard	551:ab7a8de3ff10	4636	#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /!< Bit mask of CH0 field. /
vcoubard	551:ab7a8de3ff10	4637	#define PPI_CHG_CH0_Excluded (0UL) /!< Channel excluded. /
vcoubard	551:ab7a8de3ff10	4638	#define PPI_CHG_CH0_Included (1UL) /!< Channel included. /
vcoubard	551:ab7a8de3ff10	4639
vcoubard	551:ab7a8de3ff10	4640
vcoubard	551:ab7a8de3ff10	4641	/* Peripheral: PU */
vcoubard	551:ab7a8de3ff10	4642	/* Description: Patch unit. */
vcoubard	551:ab7a8de3ff10	4643
vcoubard	551:ab7a8de3ff10	4644	/* Register: PU_PATCHADDR */
vcoubard	551:ab7a8de3ff10	4645	/* Description: Relative address of patch instructions. */
vcoubard	551:ab7a8de3ff10	4646
vcoubard	551:ab7a8de3ff10	4647	/* Bits 24..0 : Relative address of patch instructions. */
vcoubard	551:ab7a8de3ff10	4648	#define PU_PATCHADDR_PATCHADDR_Pos (0UL) /!< Position of PATCHADDR field. /
vcoubard	551:ab7a8de3ff10	4649	#define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /!< Bit mask of PATCHADDR field. /
vcoubard	551:ab7a8de3ff10	4650
vcoubard	551:ab7a8de3ff10	4651	/* Register: PU_PATCHEN */
vcoubard	551:ab7a8de3ff10	4652	/* Description: Patch enable register. */
vcoubard	551:ab7a8de3ff10	4653
vcoubard	551:ab7a8de3ff10	4654	/* Bit 7 : Patch 7 enabled. */
vcoubard	551:ab7a8de3ff10	4655	#define PU_PATCHEN_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
vcoubard	551:ab7a8de3ff10	4656	#define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
vcoubard	551:ab7a8de3ff10	4657	#define PU_PATCHEN_PATCH7_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4658	#define PU_PATCHEN_PATCH7_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4659
vcoubard	551:ab7a8de3ff10	4660	/* Bit 6 : Patch 6 enabled. */
vcoubard	551:ab7a8de3ff10	4661	#define PU_PATCHEN_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
vcoubard	551:ab7a8de3ff10	4662	#define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
vcoubard	551:ab7a8de3ff10	4663	#define PU_PATCHEN_PATCH6_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4664	#define PU_PATCHEN_PATCH6_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4665
vcoubard	551:ab7a8de3ff10	4666	/* Bit 5 : Patch 5 enabled. */
vcoubard	551:ab7a8de3ff10	4667	#define PU_PATCHEN_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
vcoubard	551:ab7a8de3ff10	4668	#define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
vcoubard	551:ab7a8de3ff10	4669	#define PU_PATCHEN_PATCH5_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4670	#define PU_PATCHEN_PATCH5_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4671
vcoubard	551:ab7a8de3ff10	4672	/* Bit 4 : Patch 4 enabled. */
vcoubard	551:ab7a8de3ff10	4673	#define PU_PATCHEN_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
vcoubard	551:ab7a8de3ff10	4674	#define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
vcoubard	551:ab7a8de3ff10	4675	#define PU_PATCHEN_PATCH4_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4676	#define PU_PATCHEN_PATCH4_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4677
vcoubard	551:ab7a8de3ff10	4678	/* Bit 3 : Patch 3 enabled. */
vcoubard	551:ab7a8de3ff10	4679	#define PU_PATCHEN_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
vcoubard	551:ab7a8de3ff10	4680	#define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
vcoubard	551:ab7a8de3ff10	4681	#define PU_PATCHEN_PATCH3_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4682	#define PU_PATCHEN_PATCH3_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4683
vcoubard	551:ab7a8de3ff10	4684	/* Bit 2 : Patch 2 enabled. */
vcoubard	551:ab7a8de3ff10	4685	#define PU_PATCHEN_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
vcoubard	551:ab7a8de3ff10	4686	#define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
vcoubard	551:ab7a8de3ff10	4687	#define PU_PATCHEN_PATCH2_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4688	#define PU_PATCHEN_PATCH2_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4689
vcoubard	551:ab7a8de3ff10	4690	/* Bit 1 : Patch 1 enabled. */
vcoubard	551:ab7a8de3ff10	4691	#define PU_PATCHEN_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
vcoubard	551:ab7a8de3ff10	4692	#define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
vcoubard	551:ab7a8de3ff10	4693	#define PU_PATCHEN_PATCH1_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4694	#define PU_PATCHEN_PATCH1_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4695
vcoubard	551:ab7a8de3ff10	4696	/* Bit 0 : Patch 0 enabled. */
vcoubard	551:ab7a8de3ff10	4697	#define PU_PATCHEN_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
vcoubard	551:ab7a8de3ff10	4698	#define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
vcoubard	551:ab7a8de3ff10	4699	#define PU_PATCHEN_PATCH0_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4700	#define PU_PATCHEN_PATCH0_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4701
vcoubard	551:ab7a8de3ff10	4702	/* Register: PU_PATCHENSET */
vcoubard	551:ab7a8de3ff10	4703	/* Description: Patch enable register. */
vcoubard	551:ab7a8de3ff10	4704
vcoubard	551:ab7a8de3ff10	4705	/* Bit 7 : Patch 7 enabled. */
vcoubard	551:ab7a8de3ff10	4706	#define PU_PATCHENSET_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
vcoubard	551:ab7a8de3ff10	4707	#define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
vcoubard	551:ab7a8de3ff10	4708	#define PU_PATCHENSET_PATCH7_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4709	#define PU_PATCHENSET_PATCH7_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4710	#define PU_PATCHENSET_PATCH7_Set (1UL) /!< Enable patch on write. /
vcoubard	551:ab7a8de3ff10	4711
vcoubard	551:ab7a8de3ff10	4712	/* Bit 6 : Patch 6 enabled. */
vcoubard	551:ab7a8de3ff10	4713	#define PU_PATCHENSET_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
vcoubard	551:ab7a8de3ff10	4714	#define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
vcoubard	551:ab7a8de3ff10	4715	#define PU_PATCHENSET_PATCH6_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4716	#define PU_PATCHENSET_PATCH6_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4717	#define PU_PATCHENSET_PATCH6_Set (1UL) /!< Enable patch on write. /
vcoubard	551:ab7a8de3ff10	4718
vcoubard	551:ab7a8de3ff10	4719	/* Bit 5 : Patch 5 enabled. */
vcoubard	551:ab7a8de3ff10	4720	#define PU_PATCHENSET_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
vcoubard	551:ab7a8de3ff10	4721	#define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
vcoubard	551:ab7a8de3ff10	4722	#define PU_PATCHENSET_PATCH5_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4723	#define PU_PATCHENSET_PATCH5_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4724	#define PU_PATCHENSET_PATCH5_Set (1UL) /!< Enable patch on write. /
vcoubard	551:ab7a8de3ff10	4725
vcoubard	551:ab7a8de3ff10	4726	/* Bit 4 : Patch 4 enabled. */
vcoubard	551:ab7a8de3ff10	4727	#define PU_PATCHENSET_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
vcoubard	551:ab7a8de3ff10	4728	#define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
vcoubard	551:ab7a8de3ff10	4729	#define PU_PATCHENSET_PATCH4_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4730	#define PU_PATCHENSET_PATCH4_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4731	#define PU_PATCHENSET_PATCH4_Set (1UL) /!< Enable patch on write. /
vcoubard	551:ab7a8de3ff10	4732
vcoubard	551:ab7a8de3ff10	4733	/* Bit 3 : Patch 3 enabled. */
vcoubard	551:ab7a8de3ff10	4734	#define PU_PATCHENSET_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
vcoubard	551:ab7a8de3ff10	4735	#define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
vcoubard	551:ab7a8de3ff10	4736	#define PU_PATCHENSET_PATCH3_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4737	#define PU_PATCHENSET_PATCH3_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4738	#define PU_PATCHENSET_PATCH3_Set (1UL) /!< Enable patch on write. /
vcoubard	551:ab7a8de3ff10	4739
vcoubard	551:ab7a8de3ff10	4740	/* Bit 2 : Patch 2 enabled. */
vcoubard	551:ab7a8de3ff10	4741	#define PU_PATCHENSET_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
vcoubard	551:ab7a8de3ff10	4742	#define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
vcoubard	551:ab7a8de3ff10	4743	#define PU_PATCHENSET_PATCH2_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4744	#define PU_PATCHENSET_PATCH2_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4745	#define PU_PATCHENSET_PATCH2_Set (1UL) /!< Enable patch on write. /
vcoubard	551:ab7a8de3ff10	4746
vcoubard	551:ab7a8de3ff10	4747	/* Bit 1 : Patch 1 enabled. */
vcoubard	551:ab7a8de3ff10	4748	#define PU_PATCHENSET_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
vcoubard	551:ab7a8de3ff10	4749	#define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
vcoubard	551:ab7a8de3ff10	4750	#define PU_PATCHENSET_PATCH1_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4751	#define PU_PATCHENSET_PATCH1_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4752	#define PU_PATCHENSET_PATCH1_Set (1UL) /!< Enable patch on write. /
vcoubard	551:ab7a8de3ff10	4753
vcoubard	551:ab7a8de3ff10	4754	/* Bit 0 : Patch 0 enabled. */
vcoubard	551:ab7a8de3ff10	4755	#define PU_PATCHENSET_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
vcoubard	551:ab7a8de3ff10	4756	#define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
vcoubard	551:ab7a8de3ff10	4757	#define PU_PATCHENSET_PATCH0_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4758	#define PU_PATCHENSET_PATCH0_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4759	#define PU_PATCHENSET_PATCH0_Set (1UL) /!< Enable patch on write. /
vcoubard	551:ab7a8de3ff10	4760
vcoubard	551:ab7a8de3ff10	4761	/* Register: PU_PATCHENCLR */
vcoubard	551:ab7a8de3ff10	4762	/* Description: Patch disable register. */
vcoubard	551:ab7a8de3ff10	4763
vcoubard	551:ab7a8de3ff10	4764	/* Bit 7 : Patch 7 enabled. */
vcoubard	551:ab7a8de3ff10	4765	#define PU_PATCHENCLR_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
vcoubard	551:ab7a8de3ff10	4766	#define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
vcoubard	551:ab7a8de3ff10	4767	#define PU_PATCHENCLR_PATCH7_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4768	#define PU_PATCHENCLR_PATCH7_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4769	#define PU_PATCHENCLR_PATCH7_Clear (1UL) /!< Disable patch on write. /
vcoubard	551:ab7a8de3ff10	4770
vcoubard	551:ab7a8de3ff10	4771	/* Bit 6 : Patch 6 enabled. */
vcoubard	551:ab7a8de3ff10	4772	#define PU_PATCHENCLR_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
vcoubard	551:ab7a8de3ff10	4773	#define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
vcoubard	551:ab7a8de3ff10	4774	#define PU_PATCHENCLR_PATCH6_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4775	#define PU_PATCHENCLR_PATCH6_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4776	#define PU_PATCHENCLR_PATCH6_Clear (1UL) /!< Disable patch on write. /
vcoubard	551:ab7a8de3ff10	4777
vcoubard	551:ab7a8de3ff10	4778	/* Bit 5 : Patch 5 enabled. */
vcoubard	551:ab7a8de3ff10	4779	#define PU_PATCHENCLR_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
vcoubard	551:ab7a8de3ff10	4780	#define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
vcoubard	551:ab7a8de3ff10	4781	#define PU_PATCHENCLR_PATCH5_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4782	#define PU_PATCHENCLR_PATCH5_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4783	#define PU_PATCHENCLR_PATCH5_Clear (1UL) /!< Disable patch on write. /
vcoubard	551:ab7a8de3ff10	4784
vcoubard	551:ab7a8de3ff10	4785	/* Bit 4 : Patch 4 enabled. */
vcoubard	551:ab7a8de3ff10	4786	#define PU_PATCHENCLR_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
vcoubard	551:ab7a8de3ff10	4787	#define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
vcoubard	551:ab7a8de3ff10	4788	#define PU_PATCHENCLR_PATCH4_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4789	#define PU_PATCHENCLR_PATCH4_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4790	#define PU_PATCHENCLR_PATCH4_Clear (1UL) /!< Disable patch on write. /
vcoubard	551:ab7a8de3ff10	4791
vcoubard	551:ab7a8de3ff10	4792	/* Bit 3 : Patch 3 enabled. */
vcoubard	551:ab7a8de3ff10	4793	#define PU_PATCHENCLR_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
vcoubard	551:ab7a8de3ff10	4794	#define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
vcoubard	551:ab7a8de3ff10	4795	#define PU_PATCHENCLR_PATCH3_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4796	#define PU_PATCHENCLR_PATCH3_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4797	#define PU_PATCHENCLR_PATCH3_Clear (1UL) /!< Disable patch on write. /
vcoubard	551:ab7a8de3ff10	4798
vcoubard	551:ab7a8de3ff10	4799	/* Bit 2 : Patch 2 enabled. */
vcoubard	551:ab7a8de3ff10	4800	#define PU_PATCHENCLR_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
vcoubard	551:ab7a8de3ff10	4801	#define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
vcoubard	551:ab7a8de3ff10	4802	#define PU_PATCHENCLR_PATCH2_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4803	#define PU_PATCHENCLR_PATCH2_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4804	#define PU_PATCHENCLR_PATCH2_Clear (1UL) /!< Disable patch on write. /
vcoubard	551:ab7a8de3ff10	4805
vcoubard	551:ab7a8de3ff10	4806	/* Bit 1 : Patch 1 enabled. */
vcoubard	551:ab7a8de3ff10	4807	#define PU_PATCHENCLR_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
vcoubard	551:ab7a8de3ff10	4808	#define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
vcoubard	551:ab7a8de3ff10	4809	#define PU_PATCHENCLR_PATCH1_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4810	#define PU_PATCHENCLR_PATCH1_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4811	#define PU_PATCHENCLR_PATCH1_Clear (1UL) /!< Disable patch on write. /
vcoubard	551:ab7a8de3ff10	4812
vcoubard	551:ab7a8de3ff10	4813	/* Bit 0 : Patch 0 enabled. */
vcoubard	551:ab7a8de3ff10	4814	#define PU_PATCHENCLR_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
vcoubard	551:ab7a8de3ff10	4815	#define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
vcoubard	551:ab7a8de3ff10	4816	#define PU_PATCHENCLR_PATCH0_Disabled (0UL) /!< Patch disabled. /
vcoubard	551:ab7a8de3ff10	4817	#define PU_PATCHENCLR_PATCH0_Enabled (1UL) /!< Patch enabled. /
vcoubard	551:ab7a8de3ff10	4818	#define PU_PATCHENCLR_PATCH0_Clear (1UL) /!< Disable patch on write. /
vcoubard	551:ab7a8de3ff10	4819
vcoubard	551:ab7a8de3ff10	4820
vcoubard	551:ab7a8de3ff10	4821	/* Peripheral: QDEC */
vcoubard	551:ab7a8de3ff10	4822	/* Description: Rotary decoder. */
vcoubard	551:ab7a8de3ff10	4823
vcoubard	551:ab7a8de3ff10	4824	/* Register: QDEC_SHORTS */
vcoubard	551:ab7a8de3ff10	4825	/* Description: Shortcuts for the QDEC. */
vcoubard	551:ab7a8de3ff10	4826
vcoubard	551:ab7a8de3ff10	4827	/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
vcoubard	551:ab7a8de3ff10	4828	#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /!< Position of SAMPLERDY_STOP field. /
vcoubard	551:ab7a8de3ff10	4829	#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /!< Bit mask of SAMPLERDY_STOP field. /
vcoubard	551:ab7a8de3ff10	4830	#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	4831	#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	4832
vcoubard	551:ab7a8de3ff10	4833	/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
vcoubard	551:ab7a8de3ff10	4834	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /!< Position of REPORTRDY_READCLRACC field. /
vcoubard	551:ab7a8de3ff10	4835	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /!< Bit mask of REPORTRDY_READCLRACC field. /
vcoubard	551:ab7a8de3ff10	4836	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	4837	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	4838
vcoubard	551:ab7a8de3ff10	4839	/* Register: QDEC_INTENSET */
vcoubard	551:ab7a8de3ff10	4840	/* Description: Interrupt enable set register. */
vcoubard	551:ab7a8de3ff10	4841
vcoubard	551:ab7a8de3ff10	4842	/* Bit 2 : Enable interrupt on ACCOF event. */
vcoubard	551:ab7a8de3ff10	4843	#define QDEC_INTENSET_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
vcoubard	551:ab7a8de3ff10	4844	#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /!< Bit mask of ACCOF field. /
vcoubard	551:ab7a8de3ff10	4845	#define QDEC_INTENSET_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	4846	#define QDEC_INTENSET_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	4847	#define QDEC_INTENSET_ACCOF_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	4848
vcoubard	551:ab7a8de3ff10	4849	/* Bit 1 : Enable interrupt on REPORTRDY event. */
vcoubard	551:ab7a8de3ff10	4850	#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
vcoubard	551:ab7a8de3ff10	4851	#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
vcoubard	551:ab7a8de3ff10	4852	#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	4853	#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	4854	#define QDEC_INTENSET_REPORTRDY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	4855
vcoubard	551:ab7a8de3ff10	4856	/* Bit 0 : Enable interrupt on SAMPLERDY event. */
vcoubard	551:ab7a8de3ff10	4857	#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
vcoubard	551:ab7a8de3ff10	4858	#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
vcoubard	551:ab7a8de3ff10	4859	#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	4860	#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	4861	#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	4862
vcoubard	551:ab7a8de3ff10	4863	/* Register: QDEC_INTENCLR */
vcoubard	551:ab7a8de3ff10	4864	/* Description: Interrupt enable clear register. */
vcoubard	551:ab7a8de3ff10	4865
vcoubard	551:ab7a8de3ff10	4866	/* Bit 2 : Disable interrupt on ACCOF event. */
vcoubard	551:ab7a8de3ff10	4867	#define QDEC_INTENCLR_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
vcoubard	551:ab7a8de3ff10	4868	#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /!< Bit mask of ACCOF field. /
vcoubard	551:ab7a8de3ff10	4869	#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	4870	#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	4871	#define QDEC_INTENCLR_ACCOF_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	4872
vcoubard	551:ab7a8de3ff10	4873	/* Bit 1 : Disable interrupt on REPORTRDY event. */
vcoubard	551:ab7a8de3ff10	4874	#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
vcoubard	551:ab7a8de3ff10	4875	#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
vcoubard	551:ab7a8de3ff10	4876	#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	4877	#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	4878	#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	4879
vcoubard	551:ab7a8de3ff10	4880	/* Bit 0 : Disable interrupt on SAMPLERDY event. */
vcoubard	551:ab7a8de3ff10	4881	#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
vcoubard	551:ab7a8de3ff10	4882	#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
vcoubard	551:ab7a8de3ff10	4883	#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	4884	#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	4885	#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	4886
vcoubard	551:ab7a8de3ff10	4887	/* Register: QDEC_ENABLE */
vcoubard	551:ab7a8de3ff10	4888	/* Description: Enable the QDEC. */
vcoubard	551:ab7a8de3ff10	4889
vcoubard	551:ab7a8de3ff10	4890	/* Bit 0 : Enable or disable QDEC. */
vcoubard	551:ab7a8de3ff10	4891	#define QDEC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	551:ab7a8de3ff10	4892	#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	551:ab7a8de3ff10	4893	#define QDEC_ENABLE_ENABLE_Disabled (0UL) /!< Disabled QDEC. /
vcoubard	551:ab7a8de3ff10	4894	#define QDEC_ENABLE_ENABLE_Enabled (1UL) /!< Enable QDEC. /
vcoubard	551:ab7a8de3ff10	4895
vcoubard	551:ab7a8de3ff10	4896	/* Register: QDEC_LEDPOL */
vcoubard	551:ab7a8de3ff10	4897	/* Description: LED output pin polarity. */
vcoubard	551:ab7a8de3ff10	4898
vcoubard	551:ab7a8de3ff10	4899	/* Bit 0 : LED output pin polarity. */
vcoubard	551:ab7a8de3ff10	4900	#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /!< Position of LEDPOL field. /
vcoubard	551:ab7a8de3ff10	4901	#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /!< Bit mask of LEDPOL field. /
vcoubard	551:ab7a8de3ff10	4902	#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /!< LED output is active low. /
vcoubard	551:ab7a8de3ff10	4903	#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /!< LED output is active high. /
vcoubard	551:ab7a8de3ff10	4904
vcoubard	551:ab7a8de3ff10	4905	/* Register: QDEC_SAMPLEPER */
vcoubard	551:ab7a8de3ff10	4906	/* Description: Sample period. */
vcoubard	551:ab7a8de3ff10	4907
vcoubard	551:ab7a8de3ff10	4908	/* Bits 2..0 : Sample period. */
vcoubard	551:ab7a8de3ff10	4909	#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /!< Position of SAMPLEPER field. /
vcoubard	551:ab7a8de3ff10	4910	#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /!< Bit mask of SAMPLEPER field. /
vcoubard	551:ab7a8de3ff10	4911	#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /!< 128us sample period. /
vcoubard	551:ab7a8de3ff10	4912	#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /!< 256us sample period. /
vcoubard	551:ab7a8de3ff10	4913	#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /!< 512us sample period. /
vcoubard	551:ab7a8de3ff10	4914	#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /!< 1024us sample period. /
vcoubard	551:ab7a8de3ff10	4915	#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /!< 2048us sample period. /
vcoubard	551:ab7a8de3ff10	4916	#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /!< 4096us sample period. /
vcoubard	551:ab7a8de3ff10	4917	#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /!< 8192us sample period. /
vcoubard	551:ab7a8de3ff10	4918	#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /!< 16384us sample period. /
vcoubard	551:ab7a8de3ff10	4919
vcoubard	551:ab7a8de3ff10	4920	/* Register: QDEC_SAMPLE */
vcoubard	551:ab7a8de3ff10	4921	/* Description: Motion sample value. */
vcoubard	551:ab7a8de3ff10	4922
vcoubard	551:ab7a8de3ff10	4923	/* Bits 31..0 : Last sample taken in compliment to 2. */
vcoubard	551:ab7a8de3ff10	4924	#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /!< Position of SAMPLE field. /
vcoubard	551:ab7a8de3ff10	4925	#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /!< Bit mask of SAMPLE field. /
vcoubard	551:ab7a8de3ff10	4926
vcoubard	551:ab7a8de3ff10	4927	/* Register: QDEC_REPORTPER */
vcoubard	551:ab7a8de3ff10	4928	/* Description: Number of samples to generate an EVENT_REPORTRDY. */
vcoubard	551:ab7a8de3ff10	4929
vcoubard	551:ab7a8de3ff10	4930	/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
vcoubard	551:ab7a8de3ff10	4931	#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /!< Position of REPORTPER field. /
vcoubard	551:ab7a8de3ff10	4932	#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /!< Bit mask of REPORTPER field. /
vcoubard	551:ab7a8de3ff10	4933	#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /!< 10 samples per report. /
vcoubard	551:ab7a8de3ff10	4934	#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /!< 40 samples per report. /
vcoubard	551:ab7a8de3ff10	4935	#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /!< 80 samples per report. /
vcoubard	551:ab7a8de3ff10	4936	#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /!< 120 samples per report. /
vcoubard	551:ab7a8de3ff10	4937	#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /!< 160 samples per report. /
vcoubard	551:ab7a8de3ff10	4938	#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /!< 200 samples per report. /
vcoubard	551:ab7a8de3ff10	4939	#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /!< 240 samples per report. /
vcoubard	551:ab7a8de3ff10	4940	#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /!< 280 samples per report. /
vcoubard	551:ab7a8de3ff10	4941
vcoubard	551:ab7a8de3ff10	4942	/* Register: QDEC_DBFEN */
vcoubard	551:ab7a8de3ff10	4943	/* Description: Enable debouncer input filters. */
vcoubard	551:ab7a8de3ff10	4944
vcoubard	551:ab7a8de3ff10	4945	/* Bit 0 : Enable debounce input filters. */
vcoubard	551:ab7a8de3ff10	4946	#define QDEC_DBFEN_DBFEN_Pos (0UL) /!< Position of DBFEN field. /
vcoubard	551:ab7a8de3ff10	4947	#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /!< Bit mask of DBFEN field. /
vcoubard	551:ab7a8de3ff10	4948	#define QDEC_DBFEN_DBFEN_Disabled (0UL) /!< Debounce input filters disabled. /
vcoubard	551:ab7a8de3ff10	4949	#define QDEC_DBFEN_DBFEN_Enabled (1UL) /!< Debounce input filters enabled. /
vcoubard	551:ab7a8de3ff10	4950
vcoubard	551:ab7a8de3ff10	4951	/* Register: QDEC_LEDPRE */
vcoubard	551:ab7a8de3ff10	4952	/* Description: Time LED is switched ON before the sample. */
vcoubard	551:ab7a8de3ff10	4953
vcoubard	551:ab7a8de3ff10	4954	/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
vcoubard	551:ab7a8de3ff10	4955	#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /!< Position of LEDPRE field. /
vcoubard	551:ab7a8de3ff10	4956	#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /!< Bit mask of LEDPRE field. /
vcoubard	551:ab7a8de3ff10	4957
vcoubard	551:ab7a8de3ff10	4958	/* Register: QDEC_ACCDBL */
vcoubard	551:ab7a8de3ff10	4959	/* Description: Accumulated double (error) transitions register. */
vcoubard	551:ab7a8de3ff10	4960
vcoubard	551:ab7a8de3ff10	4961	/* Bits 3..0 : Accumulated double (error) transitions. */
vcoubard	551:ab7a8de3ff10	4962	#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /!< Position of ACCDBL field. /
vcoubard	551:ab7a8de3ff10	4963	#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /!< Bit mask of ACCDBL field. /
vcoubard	551:ab7a8de3ff10	4964
vcoubard	551:ab7a8de3ff10	4965	/* Register: QDEC_ACCDBLREAD */
vcoubard	551:ab7a8de3ff10	4966	/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
vcoubard	551:ab7a8de3ff10	4967
vcoubard	551:ab7a8de3ff10	4968	/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
vcoubard	551:ab7a8de3ff10	4969	#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /!< Position of ACCDBLREAD field. /
vcoubard	551:ab7a8de3ff10	4970	#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /!< Bit mask of ACCDBLREAD field. /
vcoubard	551:ab7a8de3ff10	4971
vcoubard	551:ab7a8de3ff10	4972	/* Register: QDEC_POWER */
vcoubard	551:ab7a8de3ff10	4973	/* Description: Peripheral power control. */
vcoubard	551:ab7a8de3ff10	4974
vcoubard	551:ab7a8de3ff10	4975	/* Bit 0 : Peripheral power control. */
vcoubard	551:ab7a8de3ff10	4976	#define QDEC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	551:ab7a8de3ff10	4977	#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	551:ab7a8de3ff10	4978	#define QDEC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	551:ab7a8de3ff10	4979	#define QDEC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	551:ab7a8de3ff10	4980
vcoubard	551:ab7a8de3ff10	4981
vcoubard	551:ab7a8de3ff10	4982	/* Peripheral: RADIO */
vcoubard	551:ab7a8de3ff10	4983	/* Description: The radio. */
vcoubard	551:ab7a8de3ff10	4984
vcoubard	551:ab7a8de3ff10	4985	/* Register: RADIO_SHORTS */
vcoubard	551:ab7a8de3ff10	4986	/* Description: Shortcuts for the radio. */
vcoubard	551:ab7a8de3ff10	4987
vcoubard	551:ab7a8de3ff10	4988	/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
vcoubard	551:ab7a8de3ff10	4989	#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /!< Position of DISABLED_RSSISTOP field. /
vcoubard	551:ab7a8de3ff10	4990	#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /!< Bit mask of DISABLED_RSSISTOP field. /
vcoubard	551:ab7a8de3ff10	4991	#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	4992	#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	4993
vcoubard	551:ab7a8de3ff10	4994	/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
vcoubard	551:ab7a8de3ff10	4995	#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /!< Position of ADDRESS_BCSTART field. /
vcoubard	551:ab7a8de3ff10	4996	#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /!< Bit mask of ADDRESS_BCSTART field. /
vcoubard	551:ab7a8de3ff10	4997	#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	4998	#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	4999
vcoubard	551:ab7a8de3ff10	5000	/* Bit 5 : Shortcut between END event and START task. */
vcoubard	551:ab7a8de3ff10	5001	#define RADIO_SHORTS_END_START_Pos (5UL) /!< Position of END_START field. /
vcoubard	551:ab7a8de3ff10	5002	#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /!< Bit mask of END_START field. /
vcoubard	551:ab7a8de3ff10	5003	#define RADIO_SHORTS_END_START_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	5004	#define RADIO_SHORTS_END_START_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	5005
vcoubard	551:ab7a8de3ff10	5006	/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
vcoubard	551:ab7a8de3ff10	5007	#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /!< Position of ADDRESS_RSSISTART field. /
vcoubard	551:ab7a8de3ff10	5008	#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /!< Bit mask of ADDRESS_RSSISTART field. /
vcoubard	551:ab7a8de3ff10	5009	#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	5010	#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	5011
vcoubard	551:ab7a8de3ff10	5012	/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
vcoubard	551:ab7a8de3ff10	5013	#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /!< Position of DISABLED_RXEN field. /
vcoubard	551:ab7a8de3ff10	5014	#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /!< Bit mask of DISABLED_RXEN field. /
vcoubard	551:ab7a8de3ff10	5015	#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	5016	#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	5017
vcoubard	551:ab7a8de3ff10	5018	/* Bit 2 : Shortcut between DISABLED event and TXEN task. */
vcoubard	551:ab7a8de3ff10	5019	#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /!< Position of DISABLED_TXEN field. /
vcoubard	551:ab7a8de3ff10	5020	#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /!< Bit mask of DISABLED_TXEN field. /
vcoubard	551:ab7a8de3ff10	5021	#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	5022	#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	5023
vcoubard	551:ab7a8de3ff10	5024	/* Bit 1 : Shortcut between END event and DISABLE task. */
vcoubard	551:ab7a8de3ff10	5025	#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /!< Position of END_DISABLE field. /
vcoubard	551:ab7a8de3ff10	5026	#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /!< Bit mask of END_DISABLE field. /
vcoubard	551:ab7a8de3ff10	5027	#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	5028	#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	5029
vcoubard	551:ab7a8de3ff10	5030	/* Bit 0 : Shortcut between READY event and START task. */
vcoubard	551:ab7a8de3ff10	5031	#define RADIO_SHORTS_READY_START_Pos (0UL) /!< Position of READY_START field. /
vcoubard	551:ab7a8de3ff10	5032	#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /!< Bit mask of READY_START field. /
vcoubard	551:ab7a8de3ff10	5033	#define RADIO_SHORTS_READY_START_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	5034	#define RADIO_SHORTS_READY_START_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	5035
vcoubard	551:ab7a8de3ff10	5036	/* Register: RADIO_INTENSET */
vcoubard	551:ab7a8de3ff10	5037	/* Description: Interrupt enable set register. */
vcoubard	551:ab7a8de3ff10	5038
vcoubard	551:ab7a8de3ff10	5039	/* Bit 10 : Enable interrupt on BCMATCH event. */
vcoubard	551:ab7a8de3ff10	5040	#define RADIO_INTENSET_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
vcoubard	551:ab7a8de3ff10	5041	#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
vcoubard	551:ab7a8de3ff10	5042	#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5043	#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5044	#define RADIO_INTENSET_BCMATCH_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5045
vcoubard	551:ab7a8de3ff10	5046	/* Bit 7 : Enable interrupt on RSSIEND event. */
vcoubard	551:ab7a8de3ff10	5047	#define RADIO_INTENSET_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
vcoubard	551:ab7a8de3ff10	5048	#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
vcoubard	551:ab7a8de3ff10	5049	#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5050	#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5051	#define RADIO_INTENSET_RSSIEND_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5052
vcoubard	551:ab7a8de3ff10	5053	/* Bit 6 : Enable interrupt on DEVMISS event. */
vcoubard	551:ab7a8de3ff10	5054	#define RADIO_INTENSET_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
vcoubard	551:ab7a8de3ff10	5055	#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
vcoubard	551:ab7a8de3ff10	5056	#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5057	#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5058	#define RADIO_INTENSET_DEVMISS_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5059
vcoubard	551:ab7a8de3ff10	5060	/* Bit 5 : Enable interrupt on DEVMATCH event. */
vcoubard	551:ab7a8de3ff10	5061	#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
vcoubard	551:ab7a8de3ff10	5062	#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
vcoubard	551:ab7a8de3ff10	5063	#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5064	#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5065	#define RADIO_INTENSET_DEVMATCH_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5066
vcoubard	551:ab7a8de3ff10	5067	/* Bit 4 : Enable interrupt on DISABLED event. */
vcoubard	551:ab7a8de3ff10	5068	#define RADIO_INTENSET_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
vcoubard	551:ab7a8de3ff10	5069	#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /!< Bit mask of DISABLED field. /
vcoubard	551:ab7a8de3ff10	5070	#define RADIO_INTENSET_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5071	#define RADIO_INTENSET_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5072	#define RADIO_INTENSET_DISABLED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5073
vcoubard	551:ab7a8de3ff10	5074	/* Bit 3 : Enable interrupt on END event. */
vcoubard	551:ab7a8de3ff10	5075	#define RADIO_INTENSET_END_Pos (3UL) /!< Position of END field. /
vcoubard	551:ab7a8de3ff10	5076	#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /!< Bit mask of END field. /
vcoubard	551:ab7a8de3ff10	5077	#define RADIO_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5078	#define RADIO_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5079	#define RADIO_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5080
vcoubard	551:ab7a8de3ff10	5081	/* Bit 2 : Enable interrupt on PAYLOAD event. */
vcoubard	551:ab7a8de3ff10	5082	#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
vcoubard	551:ab7a8de3ff10	5083	#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
vcoubard	551:ab7a8de3ff10	5084	#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5085	#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5086	#define RADIO_INTENSET_PAYLOAD_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5087
vcoubard	551:ab7a8de3ff10	5088	/* Bit 1 : Enable interrupt on ADDRESS event. */
vcoubard	551:ab7a8de3ff10	5089	#define RADIO_INTENSET_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
vcoubard	551:ab7a8de3ff10	5090	#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
vcoubard	551:ab7a8de3ff10	5091	#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5092	#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5093	#define RADIO_INTENSET_ADDRESS_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5094
vcoubard	551:ab7a8de3ff10	5095	/* Bit 0 : Enable interrupt on READY event. */
vcoubard	551:ab7a8de3ff10	5096	#define RADIO_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
vcoubard	551:ab7a8de3ff10	5097	#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /!< Bit mask of READY field. /
vcoubard	551:ab7a8de3ff10	5098	#define RADIO_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5099	#define RADIO_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5100	#define RADIO_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5101
vcoubard	551:ab7a8de3ff10	5102	/* Register: RADIO_INTENCLR */
vcoubard	551:ab7a8de3ff10	5103	/* Description: Interrupt enable clear register. */
vcoubard	551:ab7a8de3ff10	5104
vcoubard	551:ab7a8de3ff10	5105	/* Bit 10 : Disable interrupt on BCMATCH event. */
vcoubard	551:ab7a8de3ff10	5106	#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
vcoubard	551:ab7a8de3ff10	5107	#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
vcoubard	551:ab7a8de3ff10	5108	#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5109	#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5110	#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5111
vcoubard	551:ab7a8de3ff10	5112	/* Bit 7 : Disable interrupt on RSSIEND event. */
vcoubard	551:ab7a8de3ff10	5113	#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
vcoubard	551:ab7a8de3ff10	5114	#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
vcoubard	551:ab7a8de3ff10	5115	#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5116	#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5117	#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5118
vcoubard	551:ab7a8de3ff10	5119	/* Bit 6 : Disable interrupt on DEVMISS event. */
vcoubard	551:ab7a8de3ff10	5120	#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
vcoubard	551:ab7a8de3ff10	5121	#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
vcoubard	551:ab7a8de3ff10	5122	#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5123	#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5124	#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5125
vcoubard	551:ab7a8de3ff10	5126	/* Bit 5 : Disable interrupt on DEVMATCH event. */
vcoubard	551:ab7a8de3ff10	5127	#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
vcoubard	551:ab7a8de3ff10	5128	#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
vcoubard	551:ab7a8de3ff10	5129	#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5130	#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5131	#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5132
vcoubard	551:ab7a8de3ff10	5133	/* Bit 4 : Disable interrupt on DISABLED event. */
vcoubard	551:ab7a8de3ff10	5134	#define RADIO_INTENCLR_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
vcoubard	551:ab7a8de3ff10	5135	#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /!< Bit mask of DISABLED field. /
vcoubard	551:ab7a8de3ff10	5136	#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5137	#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5138	#define RADIO_INTENCLR_DISABLED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5139
vcoubard	551:ab7a8de3ff10	5140	/* Bit 3 : Disable interrupt on END event. */
vcoubard	551:ab7a8de3ff10	5141	#define RADIO_INTENCLR_END_Pos (3UL) /!< Position of END field. /
vcoubard	551:ab7a8de3ff10	5142	#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /!< Bit mask of END field. /
vcoubard	551:ab7a8de3ff10	5143	#define RADIO_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5144	#define RADIO_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5145	#define RADIO_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5146
vcoubard	551:ab7a8de3ff10	5147	/* Bit 2 : Disable interrupt on PAYLOAD event. */
vcoubard	551:ab7a8de3ff10	5148	#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
vcoubard	551:ab7a8de3ff10	5149	#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
vcoubard	551:ab7a8de3ff10	5150	#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5151	#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5152	#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5153
vcoubard	551:ab7a8de3ff10	5154	/* Bit 1 : Disable interrupt on ADDRESS event. */
vcoubard	551:ab7a8de3ff10	5155	#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
vcoubard	551:ab7a8de3ff10	5156	#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
vcoubard	551:ab7a8de3ff10	5157	#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5158	#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5159	#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5160
vcoubard	551:ab7a8de3ff10	5161	/* Bit 0 : Disable interrupt on READY event. */
vcoubard	551:ab7a8de3ff10	5162	#define RADIO_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
vcoubard	551:ab7a8de3ff10	5163	#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
vcoubard	551:ab7a8de3ff10	5164	#define RADIO_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5165	#define RADIO_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5166	#define RADIO_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5167
vcoubard	551:ab7a8de3ff10	5168	/* Register: RADIO_CRCSTATUS */
vcoubard	551:ab7a8de3ff10	5169	/* Description: CRC status of received packet. */
vcoubard	551:ab7a8de3ff10	5170
vcoubard	551:ab7a8de3ff10	5171	/* Bit 0 : CRC status of received packet. */
vcoubard	551:ab7a8de3ff10	5172	#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /!< Position of CRCSTATUS field. /
vcoubard	551:ab7a8de3ff10	5173	#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /!< Bit mask of CRCSTATUS field. /
vcoubard	551:ab7a8de3ff10	5174	#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /!< Packet received with CRC error. /
vcoubard	551:ab7a8de3ff10	5175	#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /!< Packet received with CRC ok. /
vcoubard	551:ab7a8de3ff10	5176
vcoubard	551:ab7a8de3ff10	5177	/* Register: RADIO_CD */
vcoubard	551:ab7a8de3ff10	5178	/* Description: Carrier detect. */
vcoubard	551:ab7a8de3ff10	5179
vcoubard	551:ab7a8de3ff10	5180	/* Bit 0 : Carrier detect. */
vcoubard	551:ab7a8de3ff10	5181	#define RADIO_CD_CD_Pos (0UL) /!< Position of CD field. /
vcoubard	551:ab7a8de3ff10	5182	#define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /!< Bit mask of CD field. /
vcoubard	551:ab7a8de3ff10	5183
vcoubard	551:ab7a8de3ff10	5184	/* Register: RADIO_RXMATCH */
vcoubard	551:ab7a8de3ff10	5185	/* Description: Received address. */
vcoubard	551:ab7a8de3ff10	5186
vcoubard	551:ab7a8de3ff10	5187	/* Bits 2..0 : Logical address in which previous packet was received. */
vcoubard	551:ab7a8de3ff10	5188	#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /!< Position of RXMATCH field. /
vcoubard	551:ab7a8de3ff10	5189	#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /!< Bit mask of RXMATCH field. /
vcoubard	551:ab7a8de3ff10	5190
vcoubard	551:ab7a8de3ff10	5191	/* Register: RADIO_RXCRC */
vcoubard	551:ab7a8de3ff10	5192	/* Description: Received CRC. */
vcoubard	551:ab7a8de3ff10	5193
vcoubard	551:ab7a8de3ff10	5194	/* Bits 23..0 : CRC field of previously received packet. */
vcoubard	551:ab7a8de3ff10	5195	#define RADIO_RXCRC_RXCRC_Pos (0UL) /!< Position of RXCRC field. /
vcoubard	551:ab7a8de3ff10	5196	#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /!< Bit mask of RXCRC field. /
vcoubard	551:ab7a8de3ff10	5197
vcoubard	551:ab7a8de3ff10	5198	/* Register: RADIO_DAI */
vcoubard	551:ab7a8de3ff10	5199	/* Description: Device address match index. */
vcoubard	551:ab7a8de3ff10	5200
vcoubard	551:ab7a8de3ff10	5201	/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
vcoubard	551:ab7a8de3ff10	5202	#define RADIO_DAI_DAI_Pos (0UL) /!< Position of DAI field. /
vcoubard	551:ab7a8de3ff10	5203	#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /!< Bit mask of DAI field. /
vcoubard	551:ab7a8de3ff10	5204
vcoubard	551:ab7a8de3ff10	5205	/* Register: RADIO_FREQUENCY */
vcoubard	551:ab7a8de3ff10	5206	/* Description: Frequency. */
vcoubard	551:ab7a8de3ff10	5207
vcoubard	551:ab7a8de3ff10	5208	/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
vcoubard	551:ab7a8de3ff10	5209	#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
vcoubard	551:ab7a8de3ff10	5210	#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
vcoubard	551:ab7a8de3ff10	5211
vcoubard	551:ab7a8de3ff10	5212	/* Register: RADIO_TXPOWER */
vcoubard	551:ab7a8de3ff10	5213	/* Description: Output power. */
vcoubard	551:ab7a8de3ff10	5214
vcoubard	551:ab7a8de3ff10	5215	/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
vcoubard	551:ab7a8de3ff10	5216	#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /!< Position of TXPOWER field. /
vcoubard	551:ab7a8de3ff10	5217	#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /!< Bit mask of TXPOWER field. /
vcoubard	551:ab7a8de3ff10	5218	#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /!< +4dBm. /
vcoubard	551:ab7a8de3ff10	5219	#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /!< 0dBm. /
vcoubard	551:ab7a8de3ff10	5220	#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /!< -4dBm. /
vcoubard	551:ab7a8de3ff10	5221	#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /!< -8dBm. /
vcoubard	551:ab7a8de3ff10	5222	#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /!< -12dBm. /
vcoubard	551:ab7a8de3ff10	5223	#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /!< -16dBm. /
vcoubard	551:ab7a8de3ff10	5224	#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /!< -20dBm. /
vcoubard	551:ab7a8de3ff10	5225	#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /!< -30dBm. /
vcoubard	551:ab7a8de3ff10	5226
vcoubard	551:ab7a8de3ff10	5227	/* Register: RADIO_MODE */
vcoubard	551:ab7a8de3ff10	5228	/* Description: Data rate and modulation. */
vcoubard	551:ab7a8de3ff10	5229
vcoubard	551:ab7a8de3ff10	5230	/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
vcoubard	551:ab7a8de3ff10	5231	#define RADIO_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
vcoubard	551:ab7a8de3ff10	5232	#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /!< Bit mask of MODE field. /
vcoubard	551:ab7a8de3ff10	5233	#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /!< 1Mbit/s Nordic propietary radio mode. /
vcoubard	551:ab7a8de3ff10	5234	#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /!< 2Mbit/s Nordic propietary radio mode. /
vcoubard	551:ab7a8de3ff10	5235	#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /!< 250kbit/s Nordic propietary radio mode. /
vcoubard	551:ab7a8de3ff10	5236	#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /!< 1Mbit/s Bluetooth Low Energy /
vcoubard	551:ab7a8de3ff10	5237
vcoubard	551:ab7a8de3ff10	5238	/* Register: RADIO_PCNF0 */
vcoubard	551:ab7a8de3ff10	5239	/* Description: Packet configuration 0. */
vcoubard	551:ab7a8de3ff10	5240
vcoubard	551:ab7a8de3ff10	5241	/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5242	#define RADIO_PCNF0_S1LEN_Pos (16UL) /!< Position of S1LEN field. /
vcoubard	551:ab7a8de3ff10	5243	#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /!< Bit mask of S1LEN field. /
vcoubard	551:ab7a8de3ff10	5244
vcoubard	551:ab7a8de3ff10	5245	/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5246	#define RADIO_PCNF0_S0LEN_Pos (8UL) /!< Position of S0LEN field. /
vcoubard	551:ab7a8de3ff10	5247	#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /!< Bit mask of S0LEN field. /
vcoubard	551:ab7a8de3ff10	5248
vcoubard	551:ab7a8de3ff10	5249	/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5250	#define RADIO_PCNF0_LFLEN_Pos (0UL) /!< Position of LFLEN field. /
vcoubard	551:ab7a8de3ff10	5251	#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /!< Bit mask of LFLEN field. /
vcoubard	551:ab7a8de3ff10	5252
vcoubard	551:ab7a8de3ff10	5253	/* Register: RADIO_PCNF1 */
vcoubard	551:ab7a8de3ff10	5254	/* Description: Packet configuration 1. */
vcoubard	551:ab7a8de3ff10	5255
vcoubard	551:ab7a8de3ff10	5256	/* Bit 25 : Packet whitening enable. */
vcoubard	551:ab7a8de3ff10	5257	#define RADIO_PCNF1_WHITEEN_Pos (25UL) /!< Position of WHITEEN field. /
vcoubard	551:ab7a8de3ff10	5258	#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /!< Bit mask of WHITEEN field. /
vcoubard	551:ab7a8de3ff10	5259	#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /!< Whitening disabled. /
vcoubard	551:ab7a8de3ff10	5260	#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /!< Whitening enabled. /
vcoubard	551:ab7a8de3ff10	5261
vcoubard	551:ab7a8de3ff10	5262	/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5263	#define RADIO_PCNF1_ENDIAN_Pos (24UL) /!< Position of ENDIAN field. /
vcoubard	551:ab7a8de3ff10	5264	#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /!< Bit mask of ENDIAN field. /
vcoubard	551:ab7a8de3ff10	5265	#define RADIO_PCNF1_ENDIAN_Little (0UL) /!< Least significant bit on air first /
vcoubard	551:ab7a8de3ff10	5266	#define RADIO_PCNF1_ENDIAN_Big (1UL) /!< Most significant bit on air first /
vcoubard	551:ab7a8de3ff10	5267
vcoubard	551:ab7a8de3ff10	5268	/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5269	#define RADIO_PCNF1_BALEN_Pos (16UL) /!< Position of BALEN field. /
vcoubard	551:ab7a8de3ff10	5270	#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /!< Bit mask of BALEN field. /
vcoubard	551:ab7a8de3ff10	5271
vcoubard	551:ab7a8de3ff10	5272	/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5273	#define RADIO_PCNF1_STATLEN_Pos (8UL) /!< Position of STATLEN field. /
vcoubard	551:ab7a8de3ff10	5274	#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /!< Bit mask of STATLEN field. /
vcoubard	551:ab7a8de3ff10	5275
vcoubard	551:ab7a8de3ff10	5276	/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
vcoubard	551:ab7a8de3ff10	5277	#define RADIO_PCNF1_MAXLEN_Pos (0UL) /!< Position of MAXLEN field. /
vcoubard	551:ab7a8de3ff10	5278	#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /!< Bit mask of MAXLEN field. /
vcoubard	551:ab7a8de3ff10	5279
vcoubard	551:ab7a8de3ff10	5280	/* Register: RADIO_PREFIX0 */
vcoubard	551:ab7a8de3ff10	5281	/* Description: Prefixes bytes for logical addresses 0 to 3. */
vcoubard	551:ab7a8de3ff10	5282
vcoubard	551:ab7a8de3ff10	5283	/* Bits 31..24 : Address prefix 3. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5284	#define RADIO_PREFIX0_AP3_Pos (24UL) /!< Position of AP3 field. /
vcoubard	551:ab7a8de3ff10	5285	#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /!< Bit mask of AP3 field. /
vcoubard	551:ab7a8de3ff10	5286
vcoubard	551:ab7a8de3ff10	5287	/* Bits 23..16 : Address prefix 2. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5288	#define RADIO_PREFIX0_AP2_Pos (16UL) /!< Position of AP2 field. /
vcoubard	551:ab7a8de3ff10	5289	#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /!< Bit mask of AP2 field. /
vcoubard	551:ab7a8de3ff10	5290
vcoubard	551:ab7a8de3ff10	5291	/* Bits 15..8 : Address prefix 1. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5292	#define RADIO_PREFIX0_AP1_Pos (8UL) /!< Position of AP1 field. /
vcoubard	551:ab7a8de3ff10	5293	#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /!< Bit mask of AP1 field. /
vcoubard	551:ab7a8de3ff10	5294
vcoubard	551:ab7a8de3ff10	5295	/* Bits 7..0 : Address prefix 0. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5296	#define RADIO_PREFIX0_AP0_Pos (0UL) /!< Position of AP0 field. /
vcoubard	551:ab7a8de3ff10	5297	#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /!< Bit mask of AP0 field. /
vcoubard	551:ab7a8de3ff10	5298
vcoubard	551:ab7a8de3ff10	5299	/* Register: RADIO_PREFIX1 */
vcoubard	551:ab7a8de3ff10	5300	/* Description: Prefixes bytes for logical addresses 4 to 7. */
vcoubard	551:ab7a8de3ff10	5301
vcoubard	551:ab7a8de3ff10	5302	/* Bits 31..24 : Address prefix 7. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5303	#define RADIO_PREFIX1_AP7_Pos (24UL) /!< Position of AP7 field. /
vcoubard	551:ab7a8de3ff10	5304	#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /!< Bit mask of AP7 field. /
vcoubard	551:ab7a8de3ff10	5305
vcoubard	551:ab7a8de3ff10	5306	/* Bits 23..16 : Address prefix 6. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5307	#define RADIO_PREFIX1_AP6_Pos (16UL) /!< Position of AP6 field. /
vcoubard	551:ab7a8de3ff10	5308	#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /!< Bit mask of AP6 field. /
vcoubard	551:ab7a8de3ff10	5309
vcoubard	551:ab7a8de3ff10	5310	/* Bits 15..8 : Address prefix 5. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5311	#define RADIO_PREFIX1_AP5_Pos (8UL) /!< Position of AP5 field. /
vcoubard	551:ab7a8de3ff10	5312	#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /!< Bit mask of AP5 field. /
vcoubard	551:ab7a8de3ff10	5313
vcoubard	551:ab7a8de3ff10	5314	/* Bits 7..0 : Address prefix 4. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5315	#define RADIO_PREFIX1_AP4_Pos (0UL) /!< Position of AP4 field. /
vcoubard	551:ab7a8de3ff10	5316	#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /!< Bit mask of AP4 field. /
vcoubard	551:ab7a8de3ff10	5317
vcoubard	551:ab7a8de3ff10	5318	/* Register: RADIO_TXADDRESS */
vcoubard	551:ab7a8de3ff10	5319	/* Description: Transmit address select. */
vcoubard	551:ab7a8de3ff10	5320
vcoubard	551:ab7a8de3ff10	5321	/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5322	#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /!< Position of TXADDRESS field. /
vcoubard	551:ab7a8de3ff10	5323	#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /!< Bit mask of TXADDRESS field. /
vcoubard	551:ab7a8de3ff10	5324
vcoubard	551:ab7a8de3ff10	5325	/* Register: RADIO_RXADDRESSES */
vcoubard	551:ab7a8de3ff10	5326	/* Description: Receive address select. */
vcoubard	551:ab7a8de3ff10	5327
vcoubard	551:ab7a8de3ff10	5328	/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5329	#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /!< Position of ADDR7 field. /
vcoubard	551:ab7a8de3ff10	5330	#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /!< Bit mask of ADDR7 field. /
vcoubard	551:ab7a8de3ff10	5331	#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /!< Reception disabled. /
vcoubard	551:ab7a8de3ff10	5332	#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /!< Reception enabled. /
vcoubard	551:ab7a8de3ff10	5333
vcoubard	551:ab7a8de3ff10	5334	/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5335	#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /!< Position of ADDR6 field. /
vcoubard	551:ab7a8de3ff10	5336	#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /!< Bit mask of ADDR6 field. /
vcoubard	551:ab7a8de3ff10	5337	#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /!< Reception disabled. /
vcoubard	551:ab7a8de3ff10	5338	#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /!< Reception enabled. /
vcoubard	551:ab7a8de3ff10	5339
vcoubard	551:ab7a8de3ff10	5340	/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5341	#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /!< Position of ADDR5 field. /
vcoubard	551:ab7a8de3ff10	5342	#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /!< Bit mask of ADDR5 field. /
vcoubard	551:ab7a8de3ff10	5343	#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /!< Reception disabled. /
vcoubard	551:ab7a8de3ff10	5344	#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /!< Reception enabled. /
vcoubard	551:ab7a8de3ff10	5345
vcoubard	551:ab7a8de3ff10	5346	/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5347	#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /!< Position of ADDR4 field. /
vcoubard	551:ab7a8de3ff10	5348	#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /!< Bit mask of ADDR4 field. /
vcoubard	551:ab7a8de3ff10	5349	#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /!< Reception disabled. /
vcoubard	551:ab7a8de3ff10	5350	#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /!< Reception enabled. /
vcoubard	551:ab7a8de3ff10	5351
vcoubard	551:ab7a8de3ff10	5352	/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5353	#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /!< Position of ADDR3 field. /
vcoubard	551:ab7a8de3ff10	5354	#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /!< Bit mask of ADDR3 field. /
vcoubard	551:ab7a8de3ff10	5355	#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /!< Reception disabled. /
vcoubard	551:ab7a8de3ff10	5356	#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /!< Reception enabled. /
vcoubard	551:ab7a8de3ff10	5357
vcoubard	551:ab7a8de3ff10	5358	/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5359	#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /!< Position of ADDR2 field. /
vcoubard	551:ab7a8de3ff10	5360	#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /!< Bit mask of ADDR2 field. /
vcoubard	551:ab7a8de3ff10	5361	#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /!< Reception disabled. /
vcoubard	551:ab7a8de3ff10	5362	#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /!< Reception enabled. /
vcoubard	551:ab7a8de3ff10	5363
vcoubard	551:ab7a8de3ff10	5364	/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5365	#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /!< Position of ADDR1 field. /
vcoubard	551:ab7a8de3ff10	5366	#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /!< Bit mask of ADDR1 field. /
vcoubard	551:ab7a8de3ff10	5367	#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /!< Reception disabled. /
vcoubard	551:ab7a8de3ff10	5368	#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /!< Reception enabled. /
vcoubard	551:ab7a8de3ff10	5369
vcoubard	551:ab7a8de3ff10	5370	/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5371	#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /!< Position of ADDR0 field. /
vcoubard	551:ab7a8de3ff10	5372	#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /!< Bit mask of ADDR0 field. /
vcoubard	551:ab7a8de3ff10	5373	#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /!< Reception disabled. /
vcoubard	551:ab7a8de3ff10	5374	#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /!< Reception enabled. /
vcoubard	551:ab7a8de3ff10	5375
vcoubard	551:ab7a8de3ff10	5376	/* Register: RADIO_CRCCNF */
vcoubard	551:ab7a8de3ff10	5377	/* Description: CRC configuration. */
vcoubard	551:ab7a8de3ff10	5378
vcoubard	551:ab7a8de3ff10	5379	/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5380	#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /!< Position of SKIPADDR field. /
vcoubard	551:ab7a8de3ff10	5381	#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /!< Bit mask of SKIPADDR field. /
vcoubard	551:ab7a8de3ff10	5382	#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /!< Include packet address in CRC calculation. /
vcoubard	551:ab7a8de3ff10	5383	#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. /
vcoubard	551:ab7a8de3ff10	5384
vcoubard	551:ab7a8de3ff10	5385	/* Bits 1..0 : CRC length. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5386	#define RADIO_CRCCNF_LEN_Pos (0UL) /!< Position of LEN field. /
vcoubard	551:ab7a8de3ff10	5387	#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /!< Bit mask of LEN field. /
vcoubard	551:ab7a8de3ff10	5388	#define RADIO_CRCCNF_LEN_Disabled (0UL) /!< CRC calculation disabled. /
vcoubard	551:ab7a8de3ff10	5389	#define RADIO_CRCCNF_LEN_One (1UL) /!< One byte long CRC. /
vcoubard	551:ab7a8de3ff10	5390	#define RADIO_CRCCNF_LEN_Two (2UL) /!< Two bytes long CRC. /
vcoubard	551:ab7a8de3ff10	5391	#define RADIO_CRCCNF_LEN_Three (3UL) /!< Three bytes long CRC. /
vcoubard	551:ab7a8de3ff10	5392
vcoubard	551:ab7a8de3ff10	5393	/* Register: RADIO_CRCPOLY */
vcoubard	551:ab7a8de3ff10	5394	/* Description: CRC polynomial. */
vcoubard	551:ab7a8de3ff10	5395
vcoubard	551:ab7a8de3ff10	5396	/* Bits 23..0 : CRC polynomial. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5397	#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /!< Position of CRCPOLY field. /
vcoubard	551:ab7a8de3ff10	5398	#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /!< Bit mask of CRCPOLY field. /
vcoubard	551:ab7a8de3ff10	5399
vcoubard	551:ab7a8de3ff10	5400	/* Register: RADIO_CRCINIT */
vcoubard	551:ab7a8de3ff10	5401	/* Description: CRC initial value. */
vcoubard	551:ab7a8de3ff10	5402
vcoubard	551:ab7a8de3ff10	5403	/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
vcoubard	551:ab7a8de3ff10	5404	#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /!< Position of CRCINIT field. /
vcoubard	551:ab7a8de3ff10	5405	#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /!< Bit mask of CRCINIT field. /
vcoubard	551:ab7a8de3ff10	5406
vcoubard	551:ab7a8de3ff10	5407	/* Register: RADIO_TEST */
vcoubard	551:ab7a8de3ff10	5408	/* Description: Test features enable register. */
vcoubard	551:ab7a8de3ff10	5409
vcoubard	551:ab7a8de3ff10	5410	/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
vcoubard	551:ab7a8de3ff10	5411	#define RADIO_TEST_PLLLOCK_Pos (1UL) /!< Position of PLLLOCK field. /
vcoubard	551:ab7a8de3ff10	5412	#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /!< Bit mask of PLLLOCK field. /
vcoubard	551:ab7a8de3ff10	5413	#define RADIO_TEST_PLLLOCK_Disabled (0UL) /!< PLL lock disabled. /
vcoubard	551:ab7a8de3ff10	5414	#define RADIO_TEST_PLLLOCK_Enabled (1UL) /!< PLL lock enabled. /
vcoubard	551:ab7a8de3ff10	5415
vcoubard	551:ab7a8de3ff10	5416	/* Bit 0 : Constant carrier. Decision point: TXEN task. */
vcoubard	551:ab7a8de3ff10	5417	#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /!< Position of CONSTCARRIER field. /
vcoubard	551:ab7a8de3ff10	5418	#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /!< Bit mask of CONSTCARRIER field. /
vcoubard	551:ab7a8de3ff10	5419	#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /!< Constant carrier disabled. /
vcoubard	551:ab7a8de3ff10	5420	#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /!< Constant carrier enabled. /
vcoubard	551:ab7a8de3ff10	5421
vcoubard	551:ab7a8de3ff10	5422	/* Register: RADIO_TIFS */
vcoubard	551:ab7a8de3ff10	5423	/* Description: Inter Frame Spacing in microseconds. */
vcoubard	551:ab7a8de3ff10	5424
vcoubard	551:ab7a8de3ff10	5425	/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
vcoubard	551:ab7a8de3ff10	5426	#define RADIO_TIFS_TIFS_Pos (0UL) /!< Position of TIFS field. /
vcoubard	551:ab7a8de3ff10	5427	#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /!< Bit mask of TIFS field. /
vcoubard	551:ab7a8de3ff10	5428
vcoubard	551:ab7a8de3ff10	5429	/* Register: RADIO_RSSISAMPLE */
vcoubard	551:ab7a8de3ff10	5430	/* Description: RSSI sample. */
vcoubard	551:ab7a8de3ff10	5431
vcoubard	551:ab7a8de3ff10	5432	/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
vcoubard	551:ab7a8de3ff10	5433	#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /!< Position of RSSISAMPLE field. /
vcoubard	551:ab7a8de3ff10	5434	#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /!< Bit mask of RSSISAMPLE field. /
vcoubard	551:ab7a8de3ff10	5435
vcoubard	551:ab7a8de3ff10	5436	/* Register: RADIO_STATE */
vcoubard	551:ab7a8de3ff10	5437	/* Description: Current radio state. */
vcoubard	551:ab7a8de3ff10	5438
vcoubard	551:ab7a8de3ff10	5439	/* Bits 3..0 : Current radio state. */
vcoubard	551:ab7a8de3ff10	5440	#define RADIO_STATE_STATE_Pos (0UL) /!< Position of STATE field. /
vcoubard	551:ab7a8de3ff10	5441	#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /!< Bit mask of STATE field. /
vcoubard	551:ab7a8de3ff10	5442	#define RADIO_STATE_STATE_Disabled (0x00UL) /!< Radio is in the Disabled state. /
vcoubard	551:ab7a8de3ff10	5443	#define RADIO_STATE_STATE_RxRu (0x01UL) /!< Radio is in the Rx Ramp Up state. /
vcoubard	551:ab7a8de3ff10	5444	#define RADIO_STATE_STATE_RxIdle (0x02UL) /!< Radio is in the Rx Idle state. /
vcoubard	551:ab7a8de3ff10	5445	#define RADIO_STATE_STATE_Rx (0x03UL) /!< Radio is in the Rx state. /
vcoubard	551:ab7a8de3ff10	5446	#define RADIO_STATE_STATE_RxDisable (0x04UL) /!< Radio is in the Rx Disable state. /
vcoubard	551:ab7a8de3ff10	5447	#define RADIO_STATE_STATE_TxRu (0x09UL) /!< Radio is in the Tx Ramp Up state. /
vcoubard	551:ab7a8de3ff10	5448	#define RADIO_STATE_STATE_TxIdle (0x0AUL) /!< Radio is in the Tx Idle state. /
vcoubard	551:ab7a8de3ff10	5449	#define RADIO_STATE_STATE_Tx (0x0BUL) /!< Radio is in the Tx state. /
vcoubard	551:ab7a8de3ff10	5450	#define RADIO_STATE_STATE_TxDisable (0x0CUL) /!< Radio is in the Tx Disable state. /
vcoubard	551:ab7a8de3ff10	5451
vcoubard	551:ab7a8de3ff10	5452	/* Register: RADIO_DATAWHITEIV */
vcoubard	551:ab7a8de3ff10	5453	/* Description: Data whitening initial value. */
vcoubard	551:ab7a8de3ff10	5454
vcoubard	551:ab7a8de3ff10	5455	/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
vcoubard	551:ab7a8de3ff10	5456	#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /!< Position of DATAWHITEIV field. /
vcoubard	551:ab7a8de3ff10	5457	#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /!< Bit mask of DATAWHITEIV field. /
vcoubard	551:ab7a8de3ff10	5458
vcoubard	551:ab7a8de3ff10	5459	/* Register: RADIO_DAP */
vcoubard	551:ab7a8de3ff10	5460	/* Description: Device address prefix. */
vcoubard	551:ab7a8de3ff10	5461
vcoubard	551:ab7a8de3ff10	5462	/* Bits 15..0 : Device address prefix. */
vcoubard	551:ab7a8de3ff10	5463	#define RADIO_DAP_DAP_Pos (0UL) /!< Position of DAP field. /
vcoubard	551:ab7a8de3ff10	5464	#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /!< Bit mask of DAP field. /
vcoubard	551:ab7a8de3ff10	5465
vcoubard	551:ab7a8de3ff10	5466	/* Register: RADIO_DACNF */
vcoubard	551:ab7a8de3ff10	5467	/* Description: Device address match configuration. */
vcoubard	551:ab7a8de3ff10	5468
vcoubard	551:ab7a8de3ff10	5469	/* Bit 15 : TxAdd for device address 7. */
vcoubard	551:ab7a8de3ff10	5470	#define RADIO_DACNF_TXADD7_Pos (15UL) /!< Position of TXADD7 field. /
vcoubard	551:ab7a8de3ff10	5471	#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /!< Bit mask of TXADD7 field. /
vcoubard	551:ab7a8de3ff10	5472
vcoubard	551:ab7a8de3ff10	5473	/* Bit 14 : TxAdd for device address 6. */
vcoubard	551:ab7a8de3ff10	5474	#define RADIO_DACNF_TXADD6_Pos (14UL) /!< Position of TXADD6 field. /
vcoubard	551:ab7a8de3ff10	5475	#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /!< Bit mask of TXADD6 field. /
vcoubard	551:ab7a8de3ff10	5476
vcoubard	551:ab7a8de3ff10	5477	/* Bit 13 : TxAdd for device address 5. */
vcoubard	551:ab7a8de3ff10	5478	#define RADIO_DACNF_TXADD5_Pos (13UL) /!< Position of TXADD5 field. /
vcoubard	551:ab7a8de3ff10	5479	#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /!< Bit mask of TXADD5 field. /
vcoubard	551:ab7a8de3ff10	5480
vcoubard	551:ab7a8de3ff10	5481	/* Bit 12 : TxAdd for device address 4. */
vcoubard	551:ab7a8de3ff10	5482	#define RADIO_DACNF_TXADD4_Pos (12UL) /!< Position of TXADD4 field. /
vcoubard	551:ab7a8de3ff10	5483	#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /!< Bit mask of TXADD4 field. /
vcoubard	551:ab7a8de3ff10	5484
vcoubard	551:ab7a8de3ff10	5485	/* Bit 11 : TxAdd for device address 3. */
vcoubard	551:ab7a8de3ff10	5486	#define RADIO_DACNF_TXADD3_Pos (11UL) /!< Position of TXADD3 field. /
vcoubard	551:ab7a8de3ff10	5487	#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /!< Bit mask of TXADD3 field. /
vcoubard	551:ab7a8de3ff10	5488
vcoubard	551:ab7a8de3ff10	5489	/* Bit 10 : TxAdd for device address 2. */
vcoubard	551:ab7a8de3ff10	5490	#define RADIO_DACNF_TXADD2_Pos (10UL) /!< Position of TXADD2 field. /
vcoubard	551:ab7a8de3ff10	5491	#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /!< Bit mask of TXADD2 field. /
vcoubard	551:ab7a8de3ff10	5492
vcoubard	551:ab7a8de3ff10	5493	/* Bit 9 : TxAdd for device address 1. */
vcoubard	551:ab7a8de3ff10	5494	#define RADIO_DACNF_TXADD1_Pos (9UL) /!< Position of TXADD1 field. /
vcoubard	551:ab7a8de3ff10	5495	#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /!< Bit mask of TXADD1 field. /
vcoubard	551:ab7a8de3ff10	5496
vcoubard	551:ab7a8de3ff10	5497	/* Bit 8 : TxAdd for device address 0. */
vcoubard	551:ab7a8de3ff10	5498	#define RADIO_DACNF_TXADD0_Pos (8UL) /!< Position of TXADD0 field. /
vcoubard	551:ab7a8de3ff10	5499	#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /!< Bit mask of TXADD0 field. /
vcoubard	551:ab7a8de3ff10	5500
vcoubard	551:ab7a8de3ff10	5501	/* Bit 7 : Enable or disable device address matching using device address 7. */
vcoubard	551:ab7a8de3ff10	5502	#define RADIO_DACNF_ENA7_Pos (7UL) /!< Position of ENA7 field. /
vcoubard	551:ab7a8de3ff10	5503	#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /!< Bit mask of ENA7 field. /
vcoubard	551:ab7a8de3ff10	5504	#define RADIO_DACNF_ENA7_Disabled (0UL) /!< Disabled. /
vcoubard	551:ab7a8de3ff10	5505	#define RADIO_DACNF_ENA7_Enabled (1UL) /!< Enabled. /
vcoubard	551:ab7a8de3ff10	5506
vcoubard	551:ab7a8de3ff10	5507	/* Bit 6 : Enable or disable device address matching using device address 6. */
vcoubard	551:ab7a8de3ff10	5508	#define RADIO_DACNF_ENA6_Pos (6UL) /!< Position of ENA6 field. /
vcoubard	551:ab7a8de3ff10	5509	#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /!< Bit mask of ENA6 field. /
vcoubard	551:ab7a8de3ff10	5510	#define RADIO_DACNF_ENA6_Disabled (0UL) /!< Disabled. /
vcoubard	551:ab7a8de3ff10	5511	#define RADIO_DACNF_ENA6_Enabled (1UL) /!< Enabled. /
vcoubard	551:ab7a8de3ff10	5512
vcoubard	551:ab7a8de3ff10	5513	/* Bit 5 : Enable or disable device address matching using device address 5. */
vcoubard	551:ab7a8de3ff10	5514	#define RADIO_DACNF_ENA5_Pos (5UL) /!< Position of ENA5 field. /
vcoubard	551:ab7a8de3ff10	5515	#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /!< Bit mask of ENA5 field. /
vcoubard	551:ab7a8de3ff10	5516	#define RADIO_DACNF_ENA5_Disabled (0UL) /!< Disabled. /
vcoubard	551:ab7a8de3ff10	5517	#define RADIO_DACNF_ENA5_Enabled (1UL) /!< Enabled. /
vcoubard	551:ab7a8de3ff10	5518
vcoubard	551:ab7a8de3ff10	5519	/* Bit 4 : Enable or disable device address matching using device address 4. */
vcoubard	551:ab7a8de3ff10	5520	#define RADIO_DACNF_ENA4_Pos (4UL) /!< Position of ENA4 field. /
vcoubard	551:ab7a8de3ff10	5521	#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /!< Bit mask of ENA4 field. /
vcoubard	551:ab7a8de3ff10	5522	#define RADIO_DACNF_ENA4_Disabled (0UL) /!< Disabled. /
vcoubard	551:ab7a8de3ff10	5523	#define RADIO_DACNF_ENA4_Enabled (1UL) /!< Enabled. /
vcoubard	551:ab7a8de3ff10	5524
vcoubard	551:ab7a8de3ff10	5525	/* Bit 3 : Enable or disable device address matching using device address 3. */
vcoubard	551:ab7a8de3ff10	5526	#define RADIO_DACNF_ENA3_Pos (3UL) /!< Position of ENA3 field. /
vcoubard	551:ab7a8de3ff10	5527	#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /!< Bit mask of ENA3 field. /
vcoubard	551:ab7a8de3ff10	5528	#define RADIO_DACNF_ENA3_Disabled (0UL) /!< Disabled. /
vcoubard	551:ab7a8de3ff10	5529	#define RADIO_DACNF_ENA3_Enabled (1UL) /!< Enabled. /
vcoubard	551:ab7a8de3ff10	5530
vcoubard	551:ab7a8de3ff10	5531	/* Bit 2 : Enable or disable device address matching using device address 2. */
vcoubard	551:ab7a8de3ff10	5532	#define RADIO_DACNF_ENA2_Pos (2UL) /!< Position of ENA2 field. /
vcoubard	551:ab7a8de3ff10	5533	#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /!< Bit mask of ENA2 field. /
vcoubard	551:ab7a8de3ff10	5534	#define RADIO_DACNF_ENA2_Disabled (0UL) /!< Disabled. /
vcoubard	551:ab7a8de3ff10	5535	#define RADIO_DACNF_ENA2_Enabled (1UL) /!< Enabled. /
vcoubard	551:ab7a8de3ff10	5536
vcoubard	551:ab7a8de3ff10	5537	/* Bit 1 : Enable or disable device address matching using device address 1. */
vcoubard	551:ab7a8de3ff10	5538	#define RADIO_DACNF_ENA1_Pos (1UL) /!< Position of ENA1 field. /
vcoubard	551:ab7a8de3ff10	5539	#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /!< Bit mask of ENA1 field. /
vcoubard	551:ab7a8de3ff10	5540	#define RADIO_DACNF_ENA1_Disabled (0UL) /!< Disabled. /
vcoubard	551:ab7a8de3ff10	5541	#define RADIO_DACNF_ENA1_Enabled (1UL) /!< Enabled. /
vcoubard	551:ab7a8de3ff10	5542
vcoubard	551:ab7a8de3ff10	5543	/* Bit 0 : Enable or disable device address matching using device address 0. */
vcoubard	551:ab7a8de3ff10	5544	#define RADIO_DACNF_ENA0_Pos (0UL) /!< Position of ENA0 field. /
vcoubard	551:ab7a8de3ff10	5545	#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /!< Bit mask of ENA0 field. /
vcoubard	551:ab7a8de3ff10	5546	#define RADIO_DACNF_ENA0_Disabled (0UL) /!< Disabled. /
vcoubard	551:ab7a8de3ff10	5547	#define RADIO_DACNF_ENA0_Enabled (1UL) /!< Enabled. /
vcoubard	551:ab7a8de3ff10	5548
vcoubard	551:ab7a8de3ff10	5549	/* Register: RADIO_OVERRIDE0 */
vcoubard	551:ab7a8de3ff10	5550	/* Description: Trim value override register 0. */
vcoubard	551:ab7a8de3ff10	5551
vcoubard	551:ab7a8de3ff10	5552	/* Bits 31..0 : Trim value override 0. */
vcoubard	551:ab7a8de3ff10	5553	#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /!< Position of OVERRIDE0 field. /
vcoubard	551:ab7a8de3ff10	5554	#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /!< Bit mask of OVERRIDE0 field. /
vcoubard	551:ab7a8de3ff10	5555
vcoubard	551:ab7a8de3ff10	5556	/* Register: RADIO_OVERRIDE1 */
vcoubard	551:ab7a8de3ff10	5557	/* Description: Trim value override register 1. */
vcoubard	551:ab7a8de3ff10	5558
vcoubard	551:ab7a8de3ff10	5559	/* Bits 31..0 : Trim value override 1. */
vcoubard	551:ab7a8de3ff10	5560	#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /!< Position of OVERRIDE1 field. /
vcoubard	551:ab7a8de3ff10	5561	#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /!< Bit mask of OVERRIDE1 field. /
vcoubard	551:ab7a8de3ff10	5562
vcoubard	551:ab7a8de3ff10	5563	/* Register: RADIO_OVERRIDE2 */
vcoubard	551:ab7a8de3ff10	5564	/* Description: Trim value override register 2. */
vcoubard	551:ab7a8de3ff10	5565
vcoubard	551:ab7a8de3ff10	5566	/* Bits 31..0 : Trim value override 2. */
vcoubard	551:ab7a8de3ff10	5567	#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /!< Position of OVERRIDE2 field. /
vcoubard	551:ab7a8de3ff10	5568	#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /!< Bit mask of OVERRIDE2 field. /
vcoubard	551:ab7a8de3ff10	5569
vcoubard	551:ab7a8de3ff10	5570	/* Register: RADIO_OVERRIDE3 */
vcoubard	551:ab7a8de3ff10	5571	/* Description: Trim value override register 3. */
vcoubard	551:ab7a8de3ff10	5572
vcoubard	551:ab7a8de3ff10	5573	/* Bits 31..0 : Trim value override 3. */
vcoubard	551:ab7a8de3ff10	5574	#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /!< Position of OVERRIDE3 field. /
vcoubard	551:ab7a8de3ff10	5575	#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /!< Bit mask of OVERRIDE3 field. /
vcoubard	551:ab7a8de3ff10	5576
vcoubard	551:ab7a8de3ff10	5577	/* Register: RADIO_OVERRIDE4 */
vcoubard	551:ab7a8de3ff10	5578	/* Description: Trim value override register 4. */
vcoubard	551:ab7a8de3ff10	5579
vcoubard	551:ab7a8de3ff10	5580	/* Bit 31 : Enable or disable override of default trim values. */
vcoubard	551:ab7a8de3ff10	5581	#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /!< Position of ENABLE field. /
vcoubard	551:ab7a8de3ff10	5582	#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	551:ab7a8de3ff10	5583	#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /!< Override trim values disabled. /
vcoubard	551:ab7a8de3ff10	5584	#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /!< Override trim values enabled. /
vcoubard	551:ab7a8de3ff10	5585
vcoubard	551:ab7a8de3ff10	5586	/* Bits 27..0 : Trim value override 4. */
vcoubard	551:ab7a8de3ff10	5587	#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /!< Position of OVERRIDE4 field. /
vcoubard	551:ab7a8de3ff10	5588	#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /!< Bit mask of OVERRIDE4 field. /
vcoubard	551:ab7a8de3ff10	5589
vcoubard	551:ab7a8de3ff10	5590	/* Register: RADIO_POWER */
vcoubard	551:ab7a8de3ff10	5591	/* Description: Peripheral power control. */
vcoubard	551:ab7a8de3ff10	5592
vcoubard	551:ab7a8de3ff10	5593	/* Bit 0 : Peripheral power control. */
vcoubard	551:ab7a8de3ff10	5594	#define RADIO_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	551:ab7a8de3ff10	5595	#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	551:ab7a8de3ff10	5596	#define RADIO_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	551:ab7a8de3ff10	5597	#define RADIO_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	551:ab7a8de3ff10	5598
vcoubard	551:ab7a8de3ff10	5599
vcoubard	551:ab7a8de3ff10	5600	/* Peripheral: RNG */
vcoubard	551:ab7a8de3ff10	5601	/* Description: Random Number Generator. */
vcoubard	551:ab7a8de3ff10	5602
vcoubard	551:ab7a8de3ff10	5603	/* Register: RNG_SHORTS */
vcoubard	551:ab7a8de3ff10	5604	/* Description: Shortcuts for the RNG. */
vcoubard	551:ab7a8de3ff10	5605
vcoubard	551:ab7a8de3ff10	5606	/* Bit 0 : Shortcut between VALRDY event and STOP task. */
vcoubard	551:ab7a8de3ff10	5607	#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /!< Position of VALRDY_STOP field. /
vcoubard	551:ab7a8de3ff10	5608	#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /!< Bit mask of VALRDY_STOP field. /
vcoubard	551:ab7a8de3ff10	5609	#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	5610	#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	5611
vcoubard	551:ab7a8de3ff10	5612	/* Register: RNG_INTENSET */
vcoubard	551:ab7a8de3ff10	5613	/* Description: Interrupt enable set register */
vcoubard	551:ab7a8de3ff10	5614
vcoubard	551:ab7a8de3ff10	5615	/* Bit 0 : Enable interrupt on VALRDY event. */
vcoubard	551:ab7a8de3ff10	5616	#define RNG_INTENSET_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
vcoubard	551:ab7a8de3ff10	5617	#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /!< Bit mask of VALRDY field. /
vcoubard	551:ab7a8de3ff10	5618	#define RNG_INTENSET_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5619	#define RNG_INTENSET_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5620	#define RNG_INTENSET_VALRDY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5621
vcoubard	551:ab7a8de3ff10	5622	/* Register: RNG_INTENCLR */
vcoubard	551:ab7a8de3ff10	5623	/* Description: Interrupt enable clear register */
vcoubard	551:ab7a8de3ff10	5624
vcoubard	551:ab7a8de3ff10	5625	/* Bit 0 : Disable interrupt on VALRDY event. */
vcoubard	551:ab7a8de3ff10	5626	#define RNG_INTENCLR_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
vcoubard	551:ab7a8de3ff10	5627	#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /!< Bit mask of VALRDY field. /
vcoubard	551:ab7a8de3ff10	5628	#define RNG_INTENCLR_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5629	#define RNG_INTENCLR_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5630	#define RNG_INTENCLR_VALRDY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5631
vcoubard	551:ab7a8de3ff10	5632	/* Register: RNG_CONFIG */
vcoubard	551:ab7a8de3ff10	5633	/* Description: Configuration register. */
vcoubard	551:ab7a8de3ff10	5634
vcoubard	551:ab7a8de3ff10	5635	/* Bit 0 : Digital error correction enable. */
vcoubard	551:ab7a8de3ff10	5636	#define RNG_CONFIG_DERCEN_Pos (0UL) /!< Position of DERCEN field. /
vcoubard	551:ab7a8de3ff10	5637	#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /!< Bit mask of DERCEN field. /
vcoubard	551:ab7a8de3ff10	5638	#define RNG_CONFIG_DERCEN_Disabled (0UL) /!< Digital error correction disabled. /
vcoubard	551:ab7a8de3ff10	5639	#define RNG_CONFIG_DERCEN_Enabled (1UL) /!< Digital error correction enabled. /
vcoubard	551:ab7a8de3ff10	5640
vcoubard	551:ab7a8de3ff10	5641	/* Register: RNG_VALUE */
vcoubard	551:ab7a8de3ff10	5642	/* Description: RNG random number. */
vcoubard	551:ab7a8de3ff10	5643
vcoubard	551:ab7a8de3ff10	5644	/* Bits 7..0 : Generated random number. */
vcoubard	551:ab7a8de3ff10	5645	#define RNG_VALUE_VALUE_Pos (0UL) /!< Position of VALUE field. /
vcoubard	551:ab7a8de3ff10	5646	#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /!< Bit mask of VALUE field. /
vcoubard	551:ab7a8de3ff10	5647
vcoubard	551:ab7a8de3ff10	5648	/* Register: RNG_POWER */
vcoubard	551:ab7a8de3ff10	5649	/* Description: Peripheral power control. */
vcoubard	551:ab7a8de3ff10	5650
vcoubard	551:ab7a8de3ff10	5651	/* Bit 0 : Peripheral power control. */
vcoubard	551:ab7a8de3ff10	5652	#define RNG_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	551:ab7a8de3ff10	5653	#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	551:ab7a8de3ff10	5654	#define RNG_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	551:ab7a8de3ff10	5655	#define RNG_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	551:ab7a8de3ff10	5656
vcoubard	551:ab7a8de3ff10	5657
vcoubard	551:ab7a8de3ff10	5658	/* Peripheral: RTC */
vcoubard	551:ab7a8de3ff10	5659	/* Description: Real time counter 0. */
vcoubard	551:ab7a8de3ff10	5660
vcoubard	551:ab7a8de3ff10	5661	/* Register: RTC_INTENSET */
vcoubard	551:ab7a8de3ff10	5662	/* Description: Interrupt enable set register. */
vcoubard	551:ab7a8de3ff10	5663
vcoubard	551:ab7a8de3ff10	5664	/* Bit 19 : Enable interrupt on COMPARE[3] event. */
vcoubard	551:ab7a8de3ff10	5665	#define RTC_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	551:ab7a8de3ff10	5666	#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	551:ab7a8de3ff10	5667	#define RTC_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5668	#define RTC_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5669	#define RTC_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5670
vcoubard	551:ab7a8de3ff10	5671	/* Bit 18 : Enable interrupt on COMPARE[2] event. */
vcoubard	551:ab7a8de3ff10	5672	#define RTC_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	551:ab7a8de3ff10	5673	#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	551:ab7a8de3ff10	5674	#define RTC_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5675	#define RTC_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5676	#define RTC_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5677
vcoubard	551:ab7a8de3ff10	5678	/* Bit 17 : Enable interrupt on COMPARE[1] event. */
vcoubard	551:ab7a8de3ff10	5679	#define RTC_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	551:ab7a8de3ff10	5680	#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	551:ab7a8de3ff10	5681	#define RTC_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5682	#define RTC_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5683	#define RTC_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5684
vcoubard	551:ab7a8de3ff10	5685	/* Bit 16 : Enable interrupt on COMPARE[0] event. */
vcoubard	551:ab7a8de3ff10	5686	#define RTC_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	551:ab7a8de3ff10	5687	#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	551:ab7a8de3ff10	5688	#define RTC_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5689	#define RTC_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5690	#define RTC_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5691
vcoubard	551:ab7a8de3ff10	5692	/* Bit 1 : Enable interrupt on OVRFLW event. */
vcoubard	551:ab7a8de3ff10	5693	#define RTC_INTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
vcoubard	551:ab7a8de3ff10	5694	#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
vcoubard	551:ab7a8de3ff10	5695	#define RTC_INTENSET_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5696	#define RTC_INTENSET_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5697	#define RTC_INTENSET_OVRFLW_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5698
vcoubard	551:ab7a8de3ff10	5699	/* Bit 0 : Enable interrupt on TICK event. */
vcoubard	551:ab7a8de3ff10	5700	#define RTC_INTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
vcoubard	551:ab7a8de3ff10	5701	#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /!< Bit mask of TICK field. /
vcoubard	551:ab7a8de3ff10	5702	#define RTC_INTENSET_TICK_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5703	#define RTC_INTENSET_TICK_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5704	#define RTC_INTENSET_TICK_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5705
vcoubard	551:ab7a8de3ff10	5706	/* Register: RTC_INTENCLR */
vcoubard	551:ab7a8de3ff10	5707	/* Description: Interrupt enable clear register. */
vcoubard	551:ab7a8de3ff10	5708
vcoubard	551:ab7a8de3ff10	5709	/* Bit 19 : Disable interrupt on COMPARE[3] event. */
vcoubard	551:ab7a8de3ff10	5710	#define RTC_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	551:ab7a8de3ff10	5711	#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	551:ab7a8de3ff10	5712	#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5713	#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5714	#define RTC_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5715
vcoubard	551:ab7a8de3ff10	5716	/* Bit 18 : Disable interrupt on COMPARE[2] event. */
vcoubard	551:ab7a8de3ff10	5717	#define RTC_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	551:ab7a8de3ff10	5718	#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	551:ab7a8de3ff10	5719	#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5720	#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5721	#define RTC_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5722
vcoubard	551:ab7a8de3ff10	5723	/* Bit 17 : Disable interrupt on COMPARE[1] event. */
vcoubard	551:ab7a8de3ff10	5724	#define RTC_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	551:ab7a8de3ff10	5725	#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	551:ab7a8de3ff10	5726	#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5727	#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5728	#define RTC_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5729
vcoubard	551:ab7a8de3ff10	5730	/* Bit 16 : Disable interrupt on COMPARE[0] event. */
vcoubard	551:ab7a8de3ff10	5731	#define RTC_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	551:ab7a8de3ff10	5732	#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	551:ab7a8de3ff10	5733	#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5734	#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5735	#define RTC_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5736
vcoubard	551:ab7a8de3ff10	5737	/* Bit 1 : Disable interrupt on OVRFLW event. */
vcoubard	551:ab7a8de3ff10	5738	#define RTC_INTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
vcoubard	551:ab7a8de3ff10	5739	#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
vcoubard	551:ab7a8de3ff10	5740	#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5741	#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5742	#define RTC_INTENCLR_OVRFLW_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5743
vcoubard	551:ab7a8de3ff10	5744	/* Bit 0 : Disable interrupt on TICK event. */
vcoubard	551:ab7a8de3ff10	5745	#define RTC_INTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
vcoubard	551:ab7a8de3ff10	5746	#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
vcoubard	551:ab7a8de3ff10	5747	#define RTC_INTENCLR_TICK_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5748	#define RTC_INTENCLR_TICK_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5749	#define RTC_INTENCLR_TICK_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5750
vcoubard	551:ab7a8de3ff10	5751	/* Register: RTC_EVTEN */
vcoubard	551:ab7a8de3ff10	5752	/* Description: Configures event enable routing to PPI for each RTC event. */
vcoubard	551:ab7a8de3ff10	5753
vcoubard	551:ab7a8de3ff10	5754	/* Bit 19 : COMPARE[3] event enable. */
vcoubard	551:ab7a8de3ff10	5755	#define RTC_EVTEN_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	551:ab7a8de3ff10	5756	#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	551:ab7a8de3ff10	5757	#define RTC_EVTEN_COMPARE3_Disabled (0UL) /!< Event disabled. /
vcoubard	551:ab7a8de3ff10	5758	#define RTC_EVTEN_COMPARE3_Enabled (1UL) /!< Event enabled. /
vcoubard	551:ab7a8de3ff10	5759
vcoubard	551:ab7a8de3ff10	5760	/* Bit 18 : COMPARE[2] event enable. */
vcoubard	551:ab7a8de3ff10	5761	#define RTC_EVTEN_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	551:ab7a8de3ff10	5762	#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	551:ab7a8de3ff10	5763	#define RTC_EVTEN_COMPARE2_Disabled (0UL) /!< Event disabled. /
vcoubard	551:ab7a8de3ff10	5764	#define RTC_EVTEN_COMPARE2_Enabled (1UL) /!< Event enabled. /
vcoubard	551:ab7a8de3ff10	5765
vcoubard	551:ab7a8de3ff10	5766	/* Bit 17 : COMPARE[1] event enable. */
vcoubard	551:ab7a8de3ff10	5767	#define RTC_EVTEN_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	551:ab7a8de3ff10	5768	#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	551:ab7a8de3ff10	5769	#define RTC_EVTEN_COMPARE1_Disabled (0UL) /!< Event disabled. /
vcoubard	551:ab7a8de3ff10	5770	#define RTC_EVTEN_COMPARE1_Enabled (1UL) /!< Event enabled. /
vcoubard	551:ab7a8de3ff10	5771
vcoubard	551:ab7a8de3ff10	5772	/* Bit 16 : COMPARE[0] event enable. */
vcoubard	551:ab7a8de3ff10	5773	#define RTC_EVTEN_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	551:ab7a8de3ff10	5774	#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	551:ab7a8de3ff10	5775	#define RTC_EVTEN_COMPARE0_Disabled (0UL) /!< Event disabled. /
vcoubard	551:ab7a8de3ff10	5776	#define RTC_EVTEN_COMPARE0_Enabled (1UL) /!< Event enabled. /
vcoubard	551:ab7a8de3ff10	5777
vcoubard	551:ab7a8de3ff10	5778	/* Bit 1 : OVRFLW event enable. */
vcoubard	551:ab7a8de3ff10	5779	#define RTC_EVTEN_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
vcoubard	551:ab7a8de3ff10	5780	#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
vcoubard	551:ab7a8de3ff10	5781	#define RTC_EVTEN_OVRFLW_Disabled (0UL) /!< Event disabled. /
vcoubard	551:ab7a8de3ff10	5782	#define RTC_EVTEN_OVRFLW_Enabled (1UL) /!< Event enabled. /
vcoubard	551:ab7a8de3ff10	5783
vcoubard	551:ab7a8de3ff10	5784	/* Bit 0 : TICK event enable. */
vcoubard	551:ab7a8de3ff10	5785	#define RTC_EVTEN_TICK_Pos (0UL) /!< Position of TICK field. /
vcoubard	551:ab7a8de3ff10	5786	#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /!< Bit mask of TICK field. /
vcoubard	551:ab7a8de3ff10	5787	#define RTC_EVTEN_TICK_Disabled (0UL) /!< Event disabled. /
vcoubard	551:ab7a8de3ff10	5788	#define RTC_EVTEN_TICK_Enabled (1UL) /!< Event enabled. /
vcoubard	551:ab7a8de3ff10	5789
vcoubard	551:ab7a8de3ff10	5790	/* Register: RTC_EVTENSET */
vcoubard	551:ab7a8de3ff10	5791	/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
vcoubard	551:ab7a8de3ff10	5792
vcoubard	551:ab7a8de3ff10	5793	/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
vcoubard	551:ab7a8de3ff10	5794	#define RTC_EVTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	551:ab7a8de3ff10	5795	#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	551:ab7a8de3ff10	5796	#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /!< Event disabled. /
vcoubard	551:ab7a8de3ff10	5797	#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /!< Event enabled. /
vcoubard	551:ab7a8de3ff10	5798	#define RTC_EVTENSET_COMPARE3_Set (1UL) /!< Enable event on write. /
vcoubard	551:ab7a8de3ff10	5799
vcoubard	551:ab7a8de3ff10	5800	/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
vcoubard	551:ab7a8de3ff10	5801	#define RTC_EVTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	551:ab7a8de3ff10	5802	#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	551:ab7a8de3ff10	5803	#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /!< Event disabled. /
vcoubard	551:ab7a8de3ff10	5804	#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /!< Event enabled. /
vcoubard	551:ab7a8de3ff10	5805	#define RTC_EVTENSET_COMPARE2_Set (1UL) /!< Enable event on write. /
vcoubard	551:ab7a8de3ff10	5806
vcoubard	551:ab7a8de3ff10	5807	/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
vcoubard	551:ab7a8de3ff10	5808	#define RTC_EVTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	551:ab7a8de3ff10	5809	#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	551:ab7a8de3ff10	5810	#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /!< Event disabled. /
vcoubard	551:ab7a8de3ff10	5811	#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /!< Event enabled. /
vcoubard	551:ab7a8de3ff10	5812	#define RTC_EVTENSET_COMPARE1_Set (1UL) /!< Enable event on write. /
vcoubard	551:ab7a8de3ff10	5813
vcoubard	551:ab7a8de3ff10	5814	/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
vcoubard	551:ab7a8de3ff10	5815	#define RTC_EVTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	551:ab7a8de3ff10	5816	#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	551:ab7a8de3ff10	5817	#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /!< Event disabled. /
vcoubard	551:ab7a8de3ff10	5818	#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /!< Event enabled. /
vcoubard	551:ab7a8de3ff10	5819	#define RTC_EVTENSET_COMPARE0_Set (1UL) /!< Enable event on write. /
vcoubard	551:ab7a8de3ff10	5820
vcoubard	551:ab7a8de3ff10	5821	/* Bit 1 : Enable routing to PPI of OVRFLW event. */
vcoubard	551:ab7a8de3ff10	5822	#define RTC_EVTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
vcoubard	551:ab7a8de3ff10	5823	#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
vcoubard	551:ab7a8de3ff10	5824	#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /!< Event disabled. /
vcoubard	551:ab7a8de3ff10	5825	#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /!< Event enabled. /
vcoubard	551:ab7a8de3ff10	5826	#define RTC_EVTENSET_OVRFLW_Set (1UL) /!< Enable event on write. /
vcoubard	551:ab7a8de3ff10	5827
vcoubard	551:ab7a8de3ff10	5828	/* Bit 0 : Enable routing to PPI of TICK event. */
vcoubard	551:ab7a8de3ff10	5829	#define RTC_EVTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
vcoubard	551:ab7a8de3ff10	5830	#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /!< Bit mask of TICK field. /
vcoubard	551:ab7a8de3ff10	5831	#define RTC_EVTENSET_TICK_Disabled (0UL) /!< Event disabled. /
vcoubard	551:ab7a8de3ff10	5832	#define RTC_EVTENSET_TICK_Enabled (1UL) /!< Event enabled. /
vcoubard	551:ab7a8de3ff10	5833	#define RTC_EVTENSET_TICK_Set (1UL) /!< Enable event on write. /
vcoubard	551:ab7a8de3ff10	5834
vcoubard	551:ab7a8de3ff10	5835	/* Register: RTC_EVTENCLR */
vcoubard	551:ab7a8de3ff10	5836	/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
vcoubard	551:ab7a8de3ff10	5837
vcoubard	551:ab7a8de3ff10	5838	/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
vcoubard	551:ab7a8de3ff10	5839	#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	551:ab7a8de3ff10	5840	#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	551:ab7a8de3ff10	5841	#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /!< Event disabled. /
vcoubard	551:ab7a8de3ff10	5842	#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /!< Event enabled. /
vcoubard	551:ab7a8de3ff10	5843	#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /!< Disable event on write. /
vcoubard	551:ab7a8de3ff10	5844
vcoubard	551:ab7a8de3ff10	5845	/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
vcoubard	551:ab7a8de3ff10	5846	#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	551:ab7a8de3ff10	5847	#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	551:ab7a8de3ff10	5848	#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /!< Event disabled. /
vcoubard	551:ab7a8de3ff10	5849	#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /!< Event enabled. /
vcoubard	551:ab7a8de3ff10	5850	#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /!< Disable event on write. /
vcoubard	551:ab7a8de3ff10	5851
vcoubard	551:ab7a8de3ff10	5852	/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
vcoubard	551:ab7a8de3ff10	5853	#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	551:ab7a8de3ff10	5854	#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	551:ab7a8de3ff10	5855	#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /!< Event disabled. /
vcoubard	551:ab7a8de3ff10	5856	#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /!< Event enabled. /
vcoubard	551:ab7a8de3ff10	5857	#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /!< Disable event on write. /
vcoubard	551:ab7a8de3ff10	5858
vcoubard	551:ab7a8de3ff10	5859	/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
vcoubard	551:ab7a8de3ff10	5860	#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	551:ab7a8de3ff10	5861	#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	551:ab7a8de3ff10	5862	#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /!< Event disabled. /
vcoubard	551:ab7a8de3ff10	5863	#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /!< Event enabled. /
vcoubard	551:ab7a8de3ff10	5864	#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /!< Disable event on write. /
vcoubard	551:ab7a8de3ff10	5865
vcoubard	551:ab7a8de3ff10	5866	/* Bit 1 : Disable routing to PPI of OVRFLW event. */
vcoubard	551:ab7a8de3ff10	5867	#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
vcoubard	551:ab7a8de3ff10	5868	#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
vcoubard	551:ab7a8de3ff10	5869	#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /!< Event disabled. /
vcoubard	551:ab7a8de3ff10	5870	#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /!< Event enabled. /
vcoubard	551:ab7a8de3ff10	5871	#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /!< Disable event on write. /
vcoubard	551:ab7a8de3ff10	5872
vcoubard	551:ab7a8de3ff10	5873	/* Bit 0 : Disable routing to PPI of TICK event. */
vcoubard	551:ab7a8de3ff10	5874	#define RTC_EVTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
vcoubard	551:ab7a8de3ff10	5875	#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
vcoubard	551:ab7a8de3ff10	5876	#define RTC_EVTENCLR_TICK_Disabled (0UL) /!< Event disabled. /
vcoubard	551:ab7a8de3ff10	5877	#define RTC_EVTENCLR_TICK_Enabled (1UL) /!< Event enabled. /
vcoubard	551:ab7a8de3ff10	5878	#define RTC_EVTENCLR_TICK_Clear (1UL) /!< Disable event on write. /
vcoubard	551:ab7a8de3ff10	5879
vcoubard	551:ab7a8de3ff10	5880	/* Register: RTC_COUNTER */
vcoubard	551:ab7a8de3ff10	5881	/* Description: Current COUNTER value. */
vcoubard	551:ab7a8de3ff10	5882
vcoubard	551:ab7a8de3ff10	5883	/* Bits 23..0 : Counter value. */
vcoubard	551:ab7a8de3ff10	5884	#define RTC_COUNTER_COUNTER_Pos (0UL) /!< Position of COUNTER field. /
vcoubard	551:ab7a8de3ff10	5885	#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /!< Bit mask of COUNTER field. /
vcoubard	551:ab7a8de3ff10	5886
vcoubard	551:ab7a8de3ff10	5887	/* Register: RTC_PRESCALER */
vcoubard	551:ab7a8de3ff10	5888	/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
vcoubard	551:ab7a8de3ff10	5889
vcoubard	551:ab7a8de3ff10	5890	/* Bits 11..0 : RTC PRESCALER value. */
vcoubard	551:ab7a8de3ff10	5891	#define RTC_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
vcoubard	551:ab7a8de3ff10	5892	#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
vcoubard	551:ab7a8de3ff10	5893
vcoubard	551:ab7a8de3ff10	5894	/* Register: RTC_CC */
vcoubard	551:ab7a8de3ff10	5895	/* Description: Capture/compare registers. */
vcoubard	551:ab7a8de3ff10	5896
vcoubard	551:ab7a8de3ff10	5897	/* Bits 23..0 : Compare value. */
vcoubard	551:ab7a8de3ff10	5898	#define RTC_CC_COMPARE_Pos (0UL) /!< Position of COMPARE field. /
vcoubard	551:ab7a8de3ff10	5899	#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /!< Bit mask of COMPARE field. /
vcoubard	551:ab7a8de3ff10	5900
vcoubard	551:ab7a8de3ff10	5901	/* Register: RTC_POWER */
vcoubard	551:ab7a8de3ff10	5902	/* Description: Peripheral power control. */
vcoubard	551:ab7a8de3ff10	5903
vcoubard	551:ab7a8de3ff10	5904	/* Bit 0 : Peripheral power control. */
vcoubard	551:ab7a8de3ff10	5905	#define RTC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	551:ab7a8de3ff10	5906	#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	551:ab7a8de3ff10	5907	#define RTC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	551:ab7a8de3ff10	5908	#define RTC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	551:ab7a8de3ff10	5909
vcoubard	551:ab7a8de3ff10	5910
vcoubard	551:ab7a8de3ff10	5911	/* Peripheral: SPI */
vcoubard	551:ab7a8de3ff10	5912	/* Description: SPI master 0. */
vcoubard	551:ab7a8de3ff10	5913
vcoubard	551:ab7a8de3ff10	5914	/* Register: SPI_INTENSET */
vcoubard	551:ab7a8de3ff10	5915	/* Description: Interrupt enable set register. */
vcoubard	551:ab7a8de3ff10	5916
vcoubard	551:ab7a8de3ff10	5917	/* Bit 2 : Enable interrupt on READY event. */
vcoubard	551:ab7a8de3ff10	5918	#define SPI_INTENSET_READY_Pos (2UL) /!< Position of READY field. /
vcoubard	551:ab7a8de3ff10	5919	#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /!< Bit mask of READY field. /
vcoubard	551:ab7a8de3ff10	5920	#define SPI_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5921	#define SPI_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5922	#define SPI_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5923
vcoubard	551:ab7a8de3ff10	5924	/* Register: SPI_INTENCLR */
vcoubard	551:ab7a8de3ff10	5925	/* Description: Interrupt enable clear register. */
vcoubard	551:ab7a8de3ff10	5926
vcoubard	551:ab7a8de3ff10	5927	/* Bit 2 : Disable interrupt on READY event. */
vcoubard	551:ab7a8de3ff10	5928	#define SPI_INTENCLR_READY_Pos (2UL) /!< Position of READY field. /
vcoubard	551:ab7a8de3ff10	5929	#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
vcoubard	551:ab7a8de3ff10	5930	#define SPI_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	5931	#define SPI_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	5932	#define SPI_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	5933
vcoubard	551:ab7a8de3ff10	5934	/* Register: SPI_ENABLE */
vcoubard	551:ab7a8de3ff10	5935	/* Description: Enable SPI. */
vcoubard	551:ab7a8de3ff10	5936
vcoubard	551:ab7a8de3ff10	5937	/* Bits 2..0 : Enable or disable SPI. */
vcoubard	551:ab7a8de3ff10	5938	#define SPI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	551:ab7a8de3ff10	5939	#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	551:ab7a8de3ff10	5940	#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPI. /
vcoubard	551:ab7a8de3ff10	5941	#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable SPI. /
vcoubard	551:ab7a8de3ff10	5942
vcoubard	551:ab7a8de3ff10	5943	/* Register: SPI_RXD */
vcoubard	551:ab7a8de3ff10	5944	/* Description: RX data. */
vcoubard	551:ab7a8de3ff10	5945
vcoubard	551:ab7a8de3ff10	5946	/* Bits 7..0 : RX data from last transfer. */
vcoubard	551:ab7a8de3ff10	5947	#define SPI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
vcoubard	551:ab7a8de3ff10	5948	#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
vcoubard	551:ab7a8de3ff10	5949
vcoubard	551:ab7a8de3ff10	5950	/* Register: SPI_TXD */
vcoubard	551:ab7a8de3ff10	5951	/* Description: TX data. */
vcoubard	551:ab7a8de3ff10	5952
vcoubard	551:ab7a8de3ff10	5953	/* Bits 7..0 : TX data for next transfer. */
vcoubard	551:ab7a8de3ff10	5954	#define SPI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
vcoubard	551:ab7a8de3ff10	5955	#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
vcoubard	551:ab7a8de3ff10	5956
vcoubard	551:ab7a8de3ff10	5957	/* Register: SPI_FREQUENCY */
vcoubard	551:ab7a8de3ff10	5958	/* Description: SPI frequency */
vcoubard	551:ab7a8de3ff10	5959
vcoubard	551:ab7a8de3ff10	5960	/* Bits 31..0 : SPI data rate. */
vcoubard	551:ab7a8de3ff10	5961	#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
vcoubard	551:ab7a8de3ff10	5962	#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
vcoubard	551:ab7a8de3ff10	5963	#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125kbps. /
vcoubard	551:ab7a8de3ff10	5964	#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250kbps. /
vcoubard	551:ab7a8de3ff10	5965	#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500kbps. /
vcoubard	551:ab7a8de3ff10	5966	#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1Mbps. /
vcoubard	551:ab7a8de3ff10	5967	#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2Mbps. /
vcoubard	551:ab7a8de3ff10	5968	#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4Mbps. /
vcoubard	551:ab7a8de3ff10	5969	#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8Mbps. /
vcoubard	551:ab7a8de3ff10	5970
vcoubard	551:ab7a8de3ff10	5971	/* Register: SPI_CONFIG */
vcoubard	551:ab7a8de3ff10	5972	/* Description: Configuration register. */
vcoubard	551:ab7a8de3ff10	5973
vcoubard	551:ab7a8de3ff10	5974	/* Bit 2 : Serial clock (SCK) polarity. */
vcoubard	551:ab7a8de3ff10	5975	#define SPI_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
vcoubard	551:ab7a8de3ff10	5976	#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
vcoubard	551:ab7a8de3ff10	5977	#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
vcoubard	551:ab7a8de3ff10	5978	#define SPI_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
vcoubard	551:ab7a8de3ff10	5979
vcoubard	551:ab7a8de3ff10	5980	/* Bit 1 : Serial clock (SCK) phase. */
vcoubard	551:ab7a8de3ff10	5981	#define SPI_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
vcoubard	551:ab7a8de3ff10	5982	#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
vcoubard	551:ab7a8de3ff10	5983	#define SPI_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
vcoubard	551:ab7a8de3ff10	5984	#define SPI_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
vcoubard	551:ab7a8de3ff10	5985
vcoubard	551:ab7a8de3ff10	5986	/* Bit 0 : Bit order. */
vcoubard	551:ab7a8de3ff10	5987	#define SPI_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
vcoubard	551:ab7a8de3ff10	5988	#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
vcoubard	551:ab7a8de3ff10	5989	#define SPI_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
vcoubard	551:ab7a8de3ff10	5990	#define SPI_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
vcoubard	551:ab7a8de3ff10	5991
vcoubard	551:ab7a8de3ff10	5992	/* Register: SPI_POWER */
vcoubard	551:ab7a8de3ff10	5993	/* Description: Peripheral power control. */
vcoubard	551:ab7a8de3ff10	5994
vcoubard	551:ab7a8de3ff10	5995	/* Bit 0 : Peripheral power control. */
vcoubard	551:ab7a8de3ff10	5996	#define SPI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	551:ab7a8de3ff10	5997	#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	551:ab7a8de3ff10	5998	#define SPI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	551:ab7a8de3ff10	5999	#define SPI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	551:ab7a8de3ff10	6000
vcoubard	551:ab7a8de3ff10	6001
vcoubard	551:ab7a8de3ff10	6002	/* Peripheral: SPIM */
vcoubard	551:ab7a8de3ff10	6003	/* Description: SPI master with easyDMA 1. */
vcoubard	551:ab7a8de3ff10	6004
vcoubard	551:ab7a8de3ff10	6005	/* Register: SPIM_SHORTS */
vcoubard	551:ab7a8de3ff10	6006	/* Description: Shortcuts for SPIM. */
vcoubard	551:ab7a8de3ff10	6007
vcoubard	551:ab7a8de3ff10	6008	/* Bit 17 : Shortcut between END event and START task. */
vcoubard	551:ab7a8de3ff10	6009	#define SPIM_SHORTS_END_START_Pos (17UL) /!< Position of END_START field. /
vcoubard	551:ab7a8de3ff10	6010	#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /!< Bit mask of END_START field. /
vcoubard	551:ab7a8de3ff10	6011	#define SPIM_SHORTS_END_START_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	6012	#define SPIM_SHORTS_END_START_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	6013
vcoubard	551:ab7a8de3ff10	6014	/* Register: SPIM_INTENSET */
vcoubard	551:ab7a8de3ff10	6015	/* Description: Interrupt enable set register. */
vcoubard	551:ab7a8de3ff10	6016
vcoubard	551:ab7a8de3ff10	6017	/* Bit 19 : Enable interrupt on STARTED event. */
vcoubard	551:ab7a8de3ff10	6018	#define SPIM_INTENSET_STARTED_Pos (19UL) /!< Position of STARTED field. /
vcoubard	551:ab7a8de3ff10	6019	#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /!< Bit mask of STARTED field. /
vcoubard	551:ab7a8de3ff10	6020	#define SPIM_INTENSET_STARTED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6021	#define SPIM_INTENSET_STARTED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6022	#define SPIM_INTENSET_STARTED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6023
vcoubard	551:ab7a8de3ff10	6024	/* Bit 8 : Enable interrupt on ENDTX event. */
vcoubard	551:ab7a8de3ff10	6025	#define SPIM_INTENSET_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
vcoubard	551:ab7a8de3ff10	6026	#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /!< Bit mask of ENDTX field. /
vcoubard	551:ab7a8de3ff10	6027	#define SPIM_INTENSET_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6028	#define SPIM_INTENSET_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6029	#define SPIM_INTENSET_ENDTX_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6030
vcoubard	551:ab7a8de3ff10	6031	/* Bit 6 : Enable interrupt on END event. */
vcoubard	551:ab7a8de3ff10	6032	#define SPIM_INTENSET_END_Pos (6UL) /!< Position of END field. /
vcoubard	551:ab7a8de3ff10	6033	#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /!< Bit mask of END field. /
vcoubard	551:ab7a8de3ff10	6034	#define SPIM_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6035	#define SPIM_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6036	#define SPIM_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6037
vcoubard	551:ab7a8de3ff10	6038	/* Bit 4 : Enable interrupt on ENDRX event. */
vcoubard	551:ab7a8de3ff10	6039	#define SPIM_INTENSET_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
vcoubard	551:ab7a8de3ff10	6040	#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /!< Bit mask of ENDRX field. /
vcoubard	551:ab7a8de3ff10	6041	#define SPIM_INTENSET_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6042	#define SPIM_INTENSET_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6043	#define SPIM_INTENSET_ENDRX_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6044
vcoubard	551:ab7a8de3ff10	6045	/* Bit 1 : Enable interrupt on STOPPED event. */
vcoubard	551:ab7a8de3ff10	6046	#define SPIM_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
vcoubard	551:ab7a8de3ff10	6047	#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
vcoubard	551:ab7a8de3ff10	6048	#define SPIM_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6049	#define SPIM_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6050	#define SPIM_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6051
vcoubard	551:ab7a8de3ff10	6052	/* Register: SPIM_INTENCLR */
vcoubard	551:ab7a8de3ff10	6053	/* Description: Interrupt enable clear register. */
vcoubard	551:ab7a8de3ff10	6054
vcoubard	551:ab7a8de3ff10	6055	/* Bit 19 : Disable interrupt on STARTED event. */
vcoubard	551:ab7a8de3ff10	6056	#define SPIM_INTENCLR_STARTED_Pos (19UL) /!< Position of STARTED field. /
vcoubard	551:ab7a8de3ff10	6057	#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /!< Bit mask of STARTED field. /
vcoubard	551:ab7a8de3ff10	6058	#define SPIM_INTENCLR_STARTED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6059	#define SPIM_INTENCLR_STARTED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6060	#define SPIM_INTENCLR_STARTED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6061
vcoubard	551:ab7a8de3ff10	6062	/* Bit 8 : Disable interrupt on ENDTX event. */
vcoubard	551:ab7a8de3ff10	6063	#define SPIM_INTENCLR_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
vcoubard	551:ab7a8de3ff10	6064	#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /!< Bit mask of ENDTX field. /
vcoubard	551:ab7a8de3ff10	6065	#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6066	#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6067	#define SPIM_INTENCLR_ENDTX_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6068
vcoubard	551:ab7a8de3ff10	6069	/* Bit 6 : Disable interrupt on END event. */
vcoubard	551:ab7a8de3ff10	6070	#define SPIM_INTENCLR_END_Pos (6UL) /!< Position of END field. /
vcoubard	551:ab7a8de3ff10	6071	#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /!< Bit mask of END field. /
vcoubard	551:ab7a8de3ff10	6072	#define SPIM_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6073	#define SPIM_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6074	#define SPIM_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6075
vcoubard	551:ab7a8de3ff10	6076	/* Bit 4 : Disable interrupt on ENDRX event. */
vcoubard	551:ab7a8de3ff10	6077	#define SPIM_INTENCLR_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
vcoubard	551:ab7a8de3ff10	6078	#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /!< Bit mask of ENDRX field. /
vcoubard	551:ab7a8de3ff10	6079	#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6080	#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6081	#define SPIM_INTENCLR_ENDRX_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6082
vcoubard	551:ab7a8de3ff10	6083	/* Bit 1 : Disable interrupt on STOPPED event. */
vcoubard	551:ab7a8de3ff10	6084	#define SPIM_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
vcoubard	551:ab7a8de3ff10	6085	#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
vcoubard	551:ab7a8de3ff10	6086	#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6087	#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6088	#define SPIM_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6089
vcoubard	551:ab7a8de3ff10	6090	/* Register: SPIM_ENABLE */
vcoubard	551:ab7a8de3ff10	6091	/* Description: Enable SPIM. */
vcoubard	551:ab7a8de3ff10	6092
vcoubard	551:ab7a8de3ff10	6093	/* Bits 3..0 : Enable or disable SPIM. */
vcoubard	551:ab7a8de3ff10	6094	#define SPIM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	551:ab7a8de3ff10	6095	#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	551:ab7a8de3ff10	6096	#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIM. /
vcoubard	551:ab7a8de3ff10	6097	#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /!< Enable SPIM. /
vcoubard	551:ab7a8de3ff10	6098
vcoubard	551:ab7a8de3ff10	6099	/* Register: SPIM_RXDDATA */
vcoubard	551:ab7a8de3ff10	6100	/* Description: RXD register. */
vcoubard	551:ab7a8de3ff10	6101
vcoubard	551:ab7a8de3ff10	6102	/* Bits 7..0 : RX data received. Double buffered. */
vcoubard	551:ab7a8de3ff10	6103	#define SPIM_RXDDATA_RXD_Pos (0UL) /!< Position of RXD field. /
vcoubard	551:ab7a8de3ff10	6104	#define SPIM_RXDDATA_RXD_Msk (0xFFUL << SPIM_RXDDATA_RXD_Pos) /!< Bit mask of RXD field. /
vcoubard	551:ab7a8de3ff10	6105
vcoubard	551:ab7a8de3ff10	6106	/* Register: SPIM_TXDDATA */
vcoubard	551:ab7a8de3ff10	6107	/* Description: TXD register. */
vcoubard	551:ab7a8de3ff10	6108
vcoubard	551:ab7a8de3ff10	6109	/* Bits 7..0 : TX data to send. Double buffered. */
vcoubard	551:ab7a8de3ff10	6110	#define SPIM_TXDDATA_TXD_Pos (0UL) /!< Position of TXD field. /
vcoubard	551:ab7a8de3ff10	6111	#define SPIM_TXDDATA_TXD_Msk (0xFFUL << SPIM_TXDDATA_TXD_Pos) /!< Bit mask of TXD field. /
vcoubard	551:ab7a8de3ff10	6112
vcoubard	551:ab7a8de3ff10	6113	/* Register: SPIM_FREQUENCY */
vcoubard	551:ab7a8de3ff10	6114	/* Description: SPI frequency. */
vcoubard	551:ab7a8de3ff10	6115
vcoubard	551:ab7a8de3ff10	6116	/* Bits 31..0 : SPI master data rate. */
vcoubard	551:ab7a8de3ff10	6117	#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
vcoubard	551:ab7a8de3ff10	6118	#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
vcoubard	551:ab7a8de3ff10	6119	#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125 kbps. /
vcoubard	551:ab7a8de3ff10	6120	#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
vcoubard	551:ab7a8de3ff10	6121	#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500 kbps. /
vcoubard	551:ab7a8de3ff10	6122	#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1 Mbps. /
vcoubard	551:ab7a8de3ff10	6123	#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2 Mbps. /
vcoubard	551:ab7a8de3ff10	6124	#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4 Mbps. /
vcoubard	551:ab7a8de3ff10	6125	#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8 Mbps. /
vcoubard	551:ab7a8de3ff10	6126
vcoubard	551:ab7a8de3ff10	6127	/* Register: SPIM_CONFIG */
vcoubard	551:ab7a8de3ff10	6128	/* Description: Configuration register. */
vcoubard	551:ab7a8de3ff10	6129
vcoubard	551:ab7a8de3ff10	6130	/* Bit 2 : Serial clock (SCK) polarity. */
vcoubard	551:ab7a8de3ff10	6131	#define SPIM_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
vcoubard	551:ab7a8de3ff10	6132	#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
vcoubard	551:ab7a8de3ff10	6133	#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
vcoubard	551:ab7a8de3ff10	6134	#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
vcoubard	551:ab7a8de3ff10	6135
vcoubard	551:ab7a8de3ff10	6136	/* Bit 1 : Serial clock (SCK) phase. */
vcoubard	551:ab7a8de3ff10	6137	#define SPIM_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
vcoubard	551:ab7a8de3ff10	6138	#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
vcoubard	551:ab7a8de3ff10	6139	#define SPIM_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
vcoubard	551:ab7a8de3ff10	6140	#define SPIM_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
vcoubard	551:ab7a8de3ff10	6141
vcoubard	551:ab7a8de3ff10	6142	/* Bit 0 : Bit order. */
vcoubard	551:ab7a8de3ff10	6143	#define SPIM_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
vcoubard	551:ab7a8de3ff10	6144	#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
vcoubard	551:ab7a8de3ff10	6145	#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
vcoubard	551:ab7a8de3ff10	6146	#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
vcoubard	551:ab7a8de3ff10	6147
vcoubard	551:ab7a8de3ff10	6148	/* Register: SPIM_ORC */
vcoubard	551:ab7a8de3ff10	6149	/* Description: Over-read character. */
vcoubard	551:ab7a8de3ff10	6150
vcoubard	551:ab7a8de3ff10	6151	/* Bits 7..0 : Over-read character. */
vcoubard	551:ab7a8de3ff10	6152	#define SPIM_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
vcoubard	551:ab7a8de3ff10	6153	#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /!< Bit mask of ORC field. /
vcoubard	551:ab7a8de3ff10	6154
vcoubard	551:ab7a8de3ff10	6155	/* Register: SPIM_POWER */
vcoubard	551:ab7a8de3ff10	6156	/* Description: Peripheral power control. */
vcoubard	551:ab7a8de3ff10	6157
vcoubard	551:ab7a8de3ff10	6158	/* Bit 0 : Peripheral power control. */
vcoubard	551:ab7a8de3ff10	6159	#define SPIM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	551:ab7a8de3ff10	6160	#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	551:ab7a8de3ff10	6161	#define SPIM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	551:ab7a8de3ff10	6162	#define SPIM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	551:ab7a8de3ff10	6163
vcoubard	551:ab7a8de3ff10	6164	/* Register: SPIM_RXD_PTR */
vcoubard	551:ab7a8de3ff10	6165	/* Description: Data pointer. */
vcoubard	551:ab7a8de3ff10	6166
vcoubard	551:ab7a8de3ff10	6167	/* Bits 31..0 : Data pointer. */
vcoubard	551:ab7a8de3ff10	6168	#define SPIM_RXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
vcoubard	551:ab7a8de3ff10	6169	#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
vcoubard	551:ab7a8de3ff10	6170
vcoubard	551:ab7a8de3ff10	6171	/* Register: SPIM_RXD_MAXCNT */
vcoubard	551:ab7a8de3ff10	6172	/* Description: Maximum number of buffer bytes to receive. */
vcoubard	551:ab7a8de3ff10	6173
vcoubard	551:ab7a8de3ff10	6174	/* Bits 7..0 : Maximum number of buffer bytes to receive. */
vcoubard	551:ab7a8de3ff10	6175	#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
vcoubard	551:ab7a8de3ff10	6176	#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
vcoubard	551:ab7a8de3ff10	6177
vcoubard	551:ab7a8de3ff10	6178	/* Register: SPIM_RXD_AMOUNT */
vcoubard	551:ab7a8de3ff10	6179	/* Description: Number of bytes received in the last transaction. */
vcoubard	551:ab7a8de3ff10	6180
vcoubard	551:ab7a8de3ff10	6181	/* Bits 7..0 : Number of bytes received in the last transaction. */
vcoubard	551:ab7a8de3ff10	6182	#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
vcoubard	551:ab7a8de3ff10	6183	#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
vcoubard	551:ab7a8de3ff10	6184
vcoubard	551:ab7a8de3ff10	6185	/* Register: SPIM_TXD_PTR */
vcoubard	551:ab7a8de3ff10	6186	/* Description: Data pointer. */
vcoubard	551:ab7a8de3ff10	6187
vcoubard	551:ab7a8de3ff10	6188	/* Bits 31..0 : Data pointer. */
vcoubard	551:ab7a8de3ff10	6189	#define SPIM_TXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
vcoubard	551:ab7a8de3ff10	6190	#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
vcoubard	551:ab7a8de3ff10	6191
vcoubard	551:ab7a8de3ff10	6192	/* Register: SPIM_TXD_MAXCNT */
vcoubard	551:ab7a8de3ff10	6193	/* Description: Maximum number of buffer bytes to send. */
vcoubard	551:ab7a8de3ff10	6194
vcoubard	551:ab7a8de3ff10	6195	/* Bits 7..0 : Maximum number of buffer bytes to send. */
vcoubard	551:ab7a8de3ff10	6196	#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
vcoubard	551:ab7a8de3ff10	6197	#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
vcoubard	551:ab7a8de3ff10	6198
vcoubard	551:ab7a8de3ff10	6199	/* Register: SPIM_TXD_AMOUNT */
vcoubard	551:ab7a8de3ff10	6200	/* Description: Number of bytes sent in the last transaction. */
vcoubard	551:ab7a8de3ff10	6201
vcoubard	551:ab7a8de3ff10	6202	/* Bits 7..0 : Number of bytes sent in the last transaction. */
vcoubard	551:ab7a8de3ff10	6203	#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
vcoubard	551:ab7a8de3ff10	6204	#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
vcoubard	551:ab7a8de3ff10	6205
vcoubard	551:ab7a8de3ff10	6206
vcoubard	551:ab7a8de3ff10	6207	/* Peripheral: SPIS */
vcoubard	551:ab7a8de3ff10	6208	/* Description: SPI slave 1. */
vcoubard	551:ab7a8de3ff10	6209
vcoubard	551:ab7a8de3ff10	6210	/* Register: SPIS_SHORTS */
vcoubard	551:ab7a8de3ff10	6211	/* Description: Shortcuts for SPIS. */
vcoubard	551:ab7a8de3ff10	6212
vcoubard	551:ab7a8de3ff10	6213	/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
vcoubard	551:ab7a8de3ff10	6214	#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /!< Position of END_ACQUIRE field. /
vcoubard	551:ab7a8de3ff10	6215	#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /!< Bit mask of END_ACQUIRE field. /
vcoubard	551:ab7a8de3ff10	6216	#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	6217	#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	6218
vcoubard	551:ab7a8de3ff10	6219	/* Register: SPIS_INTENSET */
vcoubard	551:ab7a8de3ff10	6220	/* Description: Interrupt enable set register. */
vcoubard	551:ab7a8de3ff10	6221
vcoubard	551:ab7a8de3ff10	6222	/* Bit 10 : Enable interrupt on ACQUIRED event. */
vcoubard	551:ab7a8de3ff10	6223	#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
vcoubard	551:ab7a8de3ff10	6224	#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
vcoubard	551:ab7a8de3ff10	6225	#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6226	#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6227	#define SPIS_INTENSET_ACQUIRED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6228
vcoubard	551:ab7a8de3ff10	6229	/* Bit 1 : Enable interrupt on END event. */
vcoubard	551:ab7a8de3ff10	6230	#define SPIS_INTENSET_END_Pos (1UL) /!< Position of END field. /
vcoubard	551:ab7a8de3ff10	6231	#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /!< Bit mask of END field. /
vcoubard	551:ab7a8de3ff10	6232	#define SPIS_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6233	#define SPIS_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6234	#define SPIS_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6235
vcoubard	551:ab7a8de3ff10	6236	/* Register: SPIS_INTENCLR */
vcoubard	551:ab7a8de3ff10	6237	/* Description: Interrupt enable clear register. */
vcoubard	551:ab7a8de3ff10	6238
vcoubard	551:ab7a8de3ff10	6239	/* Bit 10 : Disable interrupt on ACQUIRED event. */
vcoubard	551:ab7a8de3ff10	6240	#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
vcoubard	551:ab7a8de3ff10	6241	#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
vcoubard	551:ab7a8de3ff10	6242	#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6243	#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6244	#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6245
vcoubard	551:ab7a8de3ff10	6246	/* Bit 1 : Disable interrupt on END event. */
vcoubard	551:ab7a8de3ff10	6247	#define SPIS_INTENCLR_END_Pos (1UL) /!< Position of END field. /
vcoubard	551:ab7a8de3ff10	6248	#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /!< Bit mask of END field. /
vcoubard	551:ab7a8de3ff10	6249	#define SPIS_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6250	#define SPIS_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6251	#define SPIS_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6252
vcoubard	551:ab7a8de3ff10	6253	/* Register: SPIS_SEMSTAT */
vcoubard	551:ab7a8de3ff10	6254	/* Description: Semaphore status. */
vcoubard	551:ab7a8de3ff10	6255
vcoubard	551:ab7a8de3ff10	6256	/* Bits 1..0 : Semaphore status. */
vcoubard	551:ab7a8de3ff10	6257	#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /!< Position of SEMSTAT field. /
vcoubard	551:ab7a8de3ff10	6258	#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /!< Bit mask of SEMSTAT field. /
vcoubard	551:ab7a8de3ff10	6259	#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /!< Semaphore is free. /
vcoubard	551:ab7a8de3ff10	6260	#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /!< Semaphore is assigned to the CPU. /
vcoubard	551:ab7a8de3ff10	6261	#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /!< Semaphore is assigned to the SPIS. /
vcoubard	551:ab7a8de3ff10	6262	#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. /
vcoubard	551:ab7a8de3ff10	6263
vcoubard	551:ab7a8de3ff10	6264	/* Register: SPIS_STATUS */
vcoubard	551:ab7a8de3ff10	6265	/* Description: Status from last transaction. */
vcoubard	551:ab7a8de3ff10	6266
vcoubard	551:ab7a8de3ff10	6267	/* Bit 1 : RX buffer overflow detected, and prevented. */
vcoubard	551:ab7a8de3ff10	6268	#define SPIS_STATUS_OVERFLOW_Pos (1UL) /!< Position of OVERFLOW field. /
vcoubard	551:ab7a8de3ff10	6269	#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /!< Bit mask of OVERFLOW field. /
vcoubard	551:ab7a8de3ff10	6270	#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /!< Error not present. /
vcoubard	551:ab7a8de3ff10	6271	#define SPIS_STATUS_OVERFLOW_Present (1UL) /!< Error present. /
vcoubard	551:ab7a8de3ff10	6272	#define SPIS_STATUS_OVERFLOW_Clear (1UL) /!< Clear on write. /
vcoubard	551:ab7a8de3ff10	6273
vcoubard	551:ab7a8de3ff10	6274	/* Bit 0 : TX buffer overread detected, and prevented. */
vcoubard	551:ab7a8de3ff10	6275	#define SPIS_STATUS_OVERREAD_Pos (0UL) /!< Position of OVERREAD field. /
vcoubard	551:ab7a8de3ff10	6276	#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /!< Bit mask of OVERREAD field. /
vcoubard	551:ab7a8de3ff10	6277	#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /!< Error not present. /
vcoubard	551:ab7a8de3ff10	6278	#define SPIS_STATUS_OVERREAD_Present (1UL) /!< Error present. /
vcoubard	551:ab7a8de3ff10	6279	#define SPIS_STATUS_OVERREAD_Clear (1UL) /!< Clear on write. /
vcoubard	551:ab7a8de3ff10	6280
vcoubard	551:ab7a8de3ff10	6281	/* Register: SPIS_ENABLE */
vcoubard	551:ab7a8de3ff10	6282	/* Description: Enable SPIS. */
vcoubard	551:ab7a8de3ff10	6283
vcoubard	551:ab7a8de3ff10	6284	/* Bits 2..0 : Enable or disable SPIS. */
vcoubard	551:ab7a8de3ff10	6285	#define SPIS_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	551:ab7a8de3ff10	6286	#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	551:ab7a8de3ff10	6287	#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIS. /
vcoubard	551:ab7a8de3ff10	6288	#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /!< Enable SPIS. /
vcoubard	551:ab7a8de3ff10	6289
vcoubard	551:ab7a8de3ff10	6290	/* Register: SPIS_MAXRX */
vcoubard	551:ab7a8de3ff10	6291	/* Description: Maximum number of bytes in the receive buffer. */
vcoubard	551:ab7a8de3ff10	6292
vcoubard	551:ab7a8de3ff10	6293	/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
vcoubard	551:ab7a8de3ff10	6294	#define SPIS_MAXRX_MAXRX_Pos (0UL) /!< Position of MAXRX field. /
vcoubard	551:ab7a8de3ff10	6295	#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /!< Bit mask of MAXRX field. /
vcoubard	551:ab7a8de3ff10	6296
vcoubard	551:ab7a8de3ff10	6297	/* Register: SPIS_AMOUNTRX */
vcoubard	551:ab7a8de3ff10	6298	/* Description: Number of bytes received in last granted transaction. */
vcoubard	551:ab7a8de3ff10	6299
vcoubard	551:ab7a8de3ff10	6300	/* Bits 7..0 : Number of bytes received in last granted transaction. */
vcoubard	551:ab7a8de3ff10	6301	#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /!< Position of AMOUNTRX field. /
vcoubard	551:ab7a8de3ff10	6302	#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /!< Bit mask of AMOUNTRX field. /
vcoubard	551:ab7a8de3ff10	6303
vcoubard	551:ab7a8de3ff10	6304	/* Register: SPIS_MAXTX */
vcoubard	551:ab7a8de3ff10	6305	/* Description: Maximum number of bytes in the transmit buffer. */
vcoubard	551:ab7a8de3ff10	6306
vcoubard	551:ab7a8de3ff10	6307	/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
vcoubard	551:ab7a8de3ff10	6308	#define SPIS_MAXTX_MAXTX_Pos (0UL) /!< Position of MAXTX field. /
vcoubard	551:ab7a8de3ff10	6309	#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /!< Bit mask of MAXTX field. /
vcoubard	551:ab7a8de3ff10	6310
vcoubard	551:ab7a8de3ff10	6311	/* Register: SPIS_AMOUNTTX */
vcoubard	551:ab7a8de3ff10	6312	/* Description: Number of bytes transmitted in last granted transaction. */
vcoubard	551:ab7a8de3ff10	6313
vcoubard	551:ab7a8de3ff10	6314	/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
vcoubard	551:ab7a8de3ff10	6315	#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /!< Position of AMOUNTTX field. /
vcoubard	551:ab7a8de3ff10	6316	#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /!< Bit mask of AMOUNTTX field. /
vcoubard	551:ab7a8de3ff10	6317
vcoubard	551:ab7a8de3ff10	6318	/* Register: SPIS_CONFIG */
vcoubard	551:ab7a8de3ff10	6319	/* Description: Configuration register. */
vcoubard	551:ab7a8de3ff10	6320
vcoubard	551:ab7a8de3ff10	6321	/* Bit 2 : Serial clock (SCK) polarity. */
vcoubard	551:ab7a8de3ff10	6322	#define SPIS_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
vcoubard	551:ab7a8de3ff10	6323	#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
vcoubard	551:ab7a8de3ff10	6324	#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
vcoubard	551:ab7a8de3ff10	6325	#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
vcoubard	551:ab7a8de3ff10	6326
vcoubard	551:ab7a8de3ff10	6327	/* Bit 1 : Serial clock (SCK) phase. */
vcoubard	551:ab7a8de3ff10	6328	#define SPIS_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
vcoubard	551:ab7a8de3ff10	6329	#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
vcoubard	551:ab7a8de3ff10	6330	#define SPIS_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
vcoubard	551:ab7a8de3ff10	6331	#define SPIS_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
vcoubard	551:ab7a8de3ff10	6332
vcoubard	551:ab7a8de3ff10	6333	/* Bit 0 : Bit order. */
vcoubard	551:ab7a8de3ff10	6334	#define SPIS_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
vcoubard	551:ab7a8de3ff10	6335	#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
vcoubard	551:ab7a8de3ff10	6336	#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
vcoubard	551:ab7a8de3ff10	6337	#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
vcoubard	551:ab7a8de3ff10	6338
vcoubard	551:ab7a8de3ff10	6339	/* Register: SPIS_DEF */
vcoubard	551:ab7a8de3ff10	6340	/* Description: Default character. */
vcoubard	551:ab7a8de3ff10	6341
vcoubard	551:ab7a8de3ff10	6342	/* Bits 7..0 : Default character. */
vcoubard	551:ab7a8de3ff10	6343	#define SPIS_DEF_DEF_Pos (0UL) /!< Position of DEF field. /
vcoubard	551:ab7a8de3ff10	6344	#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /!< Bit mask of DEF field. /
vcoubard	551:ab7a8de3ff10	6345
vcoubard	551:ab7a8de3ff10	6346	/* Register: SPIS_ORC */
vcoubard	551:ab7a8de3ff10	6347	/* Description: Over-read character. */
vcoubard	551:ab7a8de3ff10	6348
vcoubard	551:ab7a8de3ff10	6349	/* Bits 7..0 : Over-read character. */
vcoubard	551:ab7a8de3ff10	6350	#define SPIS_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
vcoubard	551:ab7a8de3ff10	6351	#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /!< Bit mask of ORC field. /
vcoubard	551:ab7a8de3ff10	6352
vcoubard	551:ab7a8de3ff10	6353	/* Register: SPIS_POWER */
vcoubard	551:ab7a8de3ff10	6354	/* Description: Peripheral power control. */
vcoubard	551:ab7a8de3ff10	6355
vcoubard	551:ab7a8de3ff10	6356	/* Bit 0 : Peripheral power control. */
vcoubard	551:ab7a8de3ff10	6357	#define SPIS_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	551:ab7a8de3ff10	6358	#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	551:ab7a8de3ff10	6359	#define SPIS_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	551:ab7a8de3ff10	6360	#define SPIS_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	551:ab7a8de3ff10	6361
vcoubard	551:ab7a8de3ff10	6362
vcoubard	551:ab7a8de3ff10	6363	/* Peripheral: TEMP */
vcoubard	551:ab7a8de3ff10	6364	/* Description: Temperature Sensor. */
vcoubard	551:ab7a8de3ff10	6365
vcoubard	551:ab7a8de3ff10	6366	/* Register: TEMP_INTENSET */
vcoubard	551:ab7a8de3ff10	6367	/* Description: Interrupt enable set register. */
vcoubard	551:ab7a8de3ff10	6368
vcoubard	551:ab7a8de3ff10	6369	/* Bit 0 : Enable interrupt on DATARDY event. */
vcoubard	551:ab7a8de3ff10	6370	#define TEMP_INTENSET_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
vcoubard	551:ab7a8de3ff10	6371	#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /!< Bit mask of DATARDY field. /
vcoubard	551:ab7a8de3ff10	6372	#define TEMP_INTENSET_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6373	#define TEMP_INTENSET_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6374	#define TEMP_INTENSET_DATARDY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6375
vcoubard	551:ab7a8de3ff10	6376	/* Register: TEMP_INTENCLR */
vcoubard	551:ab7a8de3ff10	6377	/* Description: Interrupt enable clear register. */
vcoubard	551:ab7a8de3ff10	6378
vcoubard	551:ab7a8de3ff10	6379	/* Bit 0 : Disable interrupt on DATARDY event. */
vcoubard	551:ab7a8de3ff10	6380	#define TEMP_INTENCLR_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
vcoubard	551:ab7a8de3ff10	6381	#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /!< Bit mask of DATARDY field. /
vcoubard	551:ab7a8de3ff10	6382	#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6383	#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6384	#define TEMP_INTENCLR_DATARDY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6385
vcoubard	551:ab7a8de3ff10	6386	/* Register: TEMP_POWER */
vcoubard	551:ab7a8de3ff10	6387	/* Description: Peripheral power control. */
vcoubard	551:ab7a8de3ff10	6388
vcoubard	551:ab7a8de3ff10	6389	/* Bit 0 : Peripheral power control. */
vcoubard	551:ab7a8de3ff10	6390	#define TEMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	551:ab7a8de3ff10	6391	#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	551:ab7a8de3ff10	6392	#define TEMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	551:ab7a8de3ff10	6393	#define TEMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	551:ab7a8de3ff10	6394
vcoubard	551:ab7a8de3ff10	6395
vcoubard	551:ab7a8de3ff10	6396	/* Peripheral: TIMER */
vcoubard	551:ab7a8de3ff10	6397	/* Description: Timer 0. */
vcoubard	551:ab7a8de3ff10	6398
vcoubard	551:ab7a8de3ff10	6399	/* Register: TIMER_SHORTS */
vcoubard	551:ab7a8de3ff10	6400	/* Description: Shortcuts for Timer. */
vcoubard	551:ab7a8de3ff10	6401
vcoubard	551:ab7a8de3ff10	6402	/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
vcoubard	551:ab7a8de3ff10	6403	#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /!< Position of COMPARE3_STOP field. /
vcoubard	551:ab7a8de3ff10	6404	#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /!< Bit mask of COMPARE3_STOP field. /
vcoubard	551:ab7a8de3ff10	6405	#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	6406	#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	6407
vcoubard	551:ab7a8de3ff10	6408	/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
vcoubard	551:ab7a8de3ff10	6409	#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /!< Position of COMPARE2_STOP field. /
vcoubard	551:ab7a8de3ff10	6410	#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /!< Bit mask of COMPARE2_STOP field. /
vcoubard	551:ab7a8de3ff10	6411	#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	6412	#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	6413
vcoubard	551:ab7a8de3ff10	6414	/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
vcoubard	551:ab7a8de3ff10	6415	#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /!< Position of COMPARE1_STOP field. /
vcoubard	551:ab7a8de3ff10	6416	#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /!< Bit mask of COMPARE1_STOP field. /
vcoubard	551:ab7a8de3ff10	6417	#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	6418	#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	6419
vcoubard	551:ab7a8de3ff10	6420	/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
vcoubard	551:ab7a8de3ff10	6421	#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /!< Position of COMPARE0_STOP field. /
vcoubard	551:ab7a8de3ff10	6422	#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /!< Bit mask of COMPARE0_STOP field. /
vcoubard	551:ab7a8de3ff10	6423	#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	6424	#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	6425
vcoubard	551:ab7a8de3ff10	6426	/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
vcoubard	551:ab7a8de3ff10	6427	#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /!< Position of COMPARE3_CLEAR field. /
vcoubard	551:ab7a8de3ff10	6428	#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /!< Bit mask of COMPARE3_CLEAR field. /
vcoubard	551:ab7a8de3ff10	6429	#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	6430	#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	6431
vcoubard	551:ab7a8de3ff10	6432	/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
vcoubard	551:ab7a8de3ff10	6433	#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /!< Position of COMPARE2_CLEAR field. /
vcoubard	551:ab7a8de3ff10	6434	#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /!< Bit mask of COMPARE2_CLEAR field. /
vcoubard	551:ab7a8de3ff10	6435	#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	6436	#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	6437
vcoubard	551:ab7a8de3ff10	6438	/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
vcoubard	551:ab7a8de3ff10	6439	#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /!< Position of COMPARE1_CLEAR field. /
vcoubard	551:ab7a8de3ff10	6440	#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /!< Bit mask of COMPARE1_CLEAR field. /
vcoubard	551:ab7a8de3ff10	6441	#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	6442	#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	6443
vcoubard	551:ab7a8de3ff10	6444	/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
vcoubard	551:ab7a8de3ff10	6445	#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /!< Position of COMPARE0_CLEAR field. /
vcoubard	551:ab7a8de3ff10	6446	#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /!< Bit mask of COMPARE0_CLEAR field. /
vcoubard	551:ab7a8de3ff10	6447	#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	6448	#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	6449
vcoubard	551:ab7a8de3ff10	6450	/* Register: TIMER_INTENSET */
vcoubard	551:ab7a8de3ff10	6451	/* Description: Interrupt enable set register. */
vcoubard	551:ab7a8de3ff10	6452
vcoubard	551:ab7a8de3ff10	6453	/* Bit 19 : Enable interrupt on COMPARE[3] */
vcoubard	551:ab7a8de3ff10	6454	#define TIMER_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	551:ab7a8de3ff10	6455	#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	551:ab7a8de3ff10	6456	#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6457	#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6458	#define TIMER_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6459
vcoubard	551:ab7a8de3ff10	6460	/* Bit 18 : Enable interrupt on COMPARE[2] */
vcoubard	551:ab7a8de3ff10	6461	#define TIMER_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	551:ab7a8de3ff10	6462	#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	551:ab7a8de3ff10	6463	#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6464	#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6465	#define TIMER_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6466
vcoubard	551:ab7a8de3ff10	6467	/* Bit 17 : Enable interrupt on COMPARE[1] */
vcoubard	551:ab7a8de3ff10	6468	#define TIMER_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	551:ab7a8de3ff10	6469	#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	551:ab7a8de3ff10	6470	#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6471	#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6472	#define TIMER_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6473
vcoubard	551:ab7a8de3ff10	6474	/* Bit 16 : Enable interrupt on COMPARE[0] */
vcoubard	551:ab7a8de3ff10	6475	#define TIMER_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	551:ab7a8de3ff10	6476	#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	551:ab7a8de3ff10	6477	#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6478	#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6479	#define TIMER_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6480
vcoubard	551:ab7a8de3ff10	6481	/* Register: TIMER_INTENCLR */
vcoubard	551:ab7a8de3ff10	6482	/* Description: Interrupt enable clear register. */
vcoubard	551:ab7a8de3ff10	6483
vcoubard	551:ab7a8de3ff10	6484	/* Bit 19 : Disable interrupt on COMPARE[3] */
vcoubard	551:ab7a8de3ff10	6485	#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
vcoubard	551:ab7a8de3ff10	6486	#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
vcoubard	551:ab7a8de3ff10	6487	#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6488	#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6489	#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6490
vcoubard	551:ab7a8de3ff10	6491	/* Bit 18 : Disable interrupt on COMPARE[2] */
vcoubard	551:ab7a8de3ff10	6492	#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
vcoubard	551:ab7a8de3ff10	6493	#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
vcoubard	551:ab7a8de3ff10	6494	#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6495	#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6496	#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6497
vcoubard	551:ab7a8de3ff10	6498	/* Bit 17 : Disable interrupt on COMPARE[1] */
vcoubard	551:ab7a8de3ff10	6499	#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
vcoubard	551:ab7a8de3ff10	6500	#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
vcoubard	551:ab7a8de3ff10	6501	#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6502	#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6503	#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6504
vcoubard	551:ab7a8de3ff10	6505	/* Bit 16 : Disable interrupt on COMPARE[0] */
vcoubard	551:ab7a8de3ff10	6506	#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
vcoubard	551:ab7a8de3ff10	6507	#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
vcoubard	551:ab7a8de3ff10	6508	#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6509	#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6510	#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6511
vcoubard	551:ab7a8de3ff10	6512	/* Register: TIMER_MODE */
vcoubard	551:ab7a8de3ff10	6513	/* Description: Timer Mode selection. */
vcoubard	551:ab7a8de3ff10	6514
vcoubard	551:ab7a8de3ff10	6515	/* Bit 0 : Select Normal or Counter mode. */
vcoubard	551:ab7a8de3ff10	6516	#define TIMER_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
vcoubard	551:ab7a8de3ff10	6517	#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /!< Bit mask of MODE field. /
vcoubard	551:ab7a8de3ff10	6518	#define TIMER_MODE_MODE_Timer (0UL) /!< Timer in Normal mode. /
vcoubard	551:ab7a8de3ff10	6519	#define TIMER_MODE_MODE_Counter (1UL) /!< Timer in Counter mode. /
vcoubard	551:ab7a8de3ff10	6520
vcoubard	551:ab7a8de3ff10	6521	/* Register: TIMER_BITMODE */
vcoubard	551:ab7a8de3ff10	6522	/* Description: Sets timer behaviour. */
vcoubard	551:ab7a8de3ff10	6523
vcoubard	551:ab7a8de3ff10	6524	/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
vcoubard	551:ab7a8de3ff10	6525	#define TIMER_BITMODE_BITMODE_Pos (0UL) /!< Position of BITMODE field. /
vcoubard	551:ab7a8de3ff10	6526	#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /!< Bit mask of BITMODE field. /
vcoubard	551:ab7a8de3ff10	6527	#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /!< 16-bit timer behaviour. /
vcoubard	551:ab7a8de3ff10	6528	#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /!< 8-bit timer behaviour. /
vcoubard	551:ab7a8de3ff10	6529	#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /!< 24-bit timer behaviour. /
vcoubard	551:ab7a8de3ff10	6530	#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /!< 32-bit timer behaviour. /
vcoubard	551:ab7a8de3ff10	6531
vcoubard	551:ab7a8de3ff10	6532	/* Register: TIMER_PRESCALER */
vcoubard	551:ab7a8de3ff10	6533	/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
vcoubard	551:ab7a8de3ff10	6534
vcoubard	551:ab7a8de3ff10	6535	/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
vcoubard	551:ab7a8de3ff10	6536	#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
vcoubard	551:ab7a8de3ff10	6537	#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
vcoubard	551:ab7a8de3ff10	6538
vcoubard	551:ab7a8de3ff10	6539	/* Register: TIMER_POWER */
vcoubard	551:ab7a8de3ff10	6540	/* Description: Peripheral power control. */
vcoubard	551:ab7a8de3ff10	6541
vcoubard	551:ab7a8de3ff10	6542	/* Bit 0 : Peripheral power control. */
vcoubard	551:ab7a8de3ff10	6543	#define TIMER_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	551:ab7a8de3ff10	6544	#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	551:ab7a8de3ff10	6545	#define TIMER_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	551:ab7a8de3ff10	6546	#define TIMER_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	551:ab7a8de3ff10	6547
vcoubard	551:ab7a8de3ff10	6548
vcoubard	551:ab7a8de3ff10	6549	/* Peripheral: TWI */
vcoubard	551:ab7a8de3ff10	6550	/* Description: Two-wire interface master 0. */
vcoubard	551:ab7a8de3ff10	6551
vcoubard	551:ab7a8de3ff10	6552	/* Register: TWI_SHORTS */
vcoubard	551:ab7a8de3ff10	6553	/* Description: Shortcuts for TWI. */
vcoubard	551:ab7a8de3ff10	6554
vcoubard	551:ab7a8de3ff10	6555	/* Bit 1 : Shortcut between BB event and the STOP task. */
vcoubard	551:ab7a8de3ff10	6556	#define TWI_SHORTS_BB_STOP_Pos (1UL) /!< Position of BB_STOP field. /
vcoubard	551:ab7a8de3ff10	6557	#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /!< Bit mask of BB_STOP field. /
vcoubard	551:ab7a8de3ff10	6558	#define TWI_SHORTS_BB_STOP_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	6559	#define TWI_SHORTS_BB_STOP_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	6560
vcoubard	551:ab7a8de3ff10	6561	/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
vcoubard	551:ab7a8de3ff10	6562	#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /!< Position of BB_SUSPEND field. /
vcoubard	551:ab7a8de3ff10	6563	#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /!< Bit mask of BB_SUSPEND field. /
vcoubard	551:ab7a8de3ff10	6564	#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	6565	#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	6566
vcoubard	551:ab7a8de3ff10	6567	/* Register: TWI_INTENSET */
vcoubard	551:ab7a8de3ff10	6568	/* Description: Interrupt enable set register. */
vcoubard	551:ab7a8de3ff10	6569
vcoubard	551:ab7a8de3ff10	6570	/* Bit 18 : Enable interrupt on SUSPENDED event. */
vcoubard	551:ab7a8de3ff10	6571	#define TWI_INTENSET_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
vcoubard	551:ab7a8de3ff10	6572	#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
vcoubard	551:ab7a8de3ff10	6573	#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6574	#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6575	#define TWI_INTENSET_SUSPENDED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6576
vcoubard	551:ab7a8de3ff10	6577	/* Bit 14 : Enable interrupt on BB event. */
vcoubard	551:ab7a8de3ff10	6578	#define TWI_INTENSET_BB_Pos (14UL) /!< Position of BB field. /
vcoubard	551:ab7a8de3ff10	6579	#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /!< Bit mask of BB field. /
vcoubard	551:ab7a8de3ff10	6580	#define TWI_INTENSET_BB_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6581	#define TWI_INTENSET_BB_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6582	#define TWI_INTENSET_BB_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6583
vcoubard	551:ab7a8de3ff10	6584	/* Bit 9 : Enable interrupt on ERROR event. */
vcoubard	551:ab7a8de3ff10	6585	#define TWI_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
vcoubard	551:ab7a8de3ff10	6586	#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
vcoubard	551:ab7a8de3ff10	6587	#define TWI_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6588	#define TWI_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6589	#define TWI_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6590
vcoubard	551:ab7a8de3ff10	6591	/* Bit 7 : Enable interrupt on TXDSENT event. */
vcoubard	551:ab7a8de3ff10	6592	#define TWI_INTENSET_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
vcoubard	551:ab7a8de3ff10	6593	#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
vcoubard	551:ab7a8de3ff10	6594	#define TWI_INTENSET_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6595	#define TWI_INTENSET_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6596	#define TWI_INTENSET_TXDSENT_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6597
vcoubard	551:ab7a8de3ff10	6598	/* Bit 2 : Enable interrupt on READY event. */
vcoubard	551:ab7a8de3ff10	6599	#define TWI_INTENSET_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
vcoubard	551:ab7a8de3ff10	6600	#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
vcoubard	551:ab7a8de3ff10	6601	#define TWI_INTENSET_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6602	#define TWI_INTENSET_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6603	#define TWI_INTENSET_RXDREADY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6604
vcoubard	551:ab7a8de3ff10	6605	/* Bit 1 : Enable interrupt on STOPPED event. */
vcoubard	551:ab7a8de3ff10	6606	#define TWI_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
vcoubard	551:ab7a8de3ff10	6607	#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
vcoubard	551:ab7a8de3ff10	6608	#define TWI_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6609	#define TWI_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6610	#define TWI_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6611
vcoubard	551:ab7a8de3ff10	6612	/* Register: TWI_INTENCLR */
vcoubard	551:ab7a8de3ff10	6613	/* Description: Interrupt enable clear register. */
vcoubard	551:ab7a8de3ff10	6614
vcoubard	551:ab7a8de3ff10	6615	/* Bit 18 : Disable interrupt on SUSPENDED event. */
vcoubard	551:ab7a8de3ff10	6616	#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
vcoubard	551:ab7a8de3ff10	6617	#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
vcoubard	551:ab7a8de3ff10	6618	#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6619	#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6620	#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6621
vcoubard	551:ab7a8de3ff10	6622	/* Bit 14 : Disable interrupt on BB event. */
vcoubard	551:ab7a8de3ff10	6623	#define TWI_INTENCLR_BB_Pos (14UL) /!< Position of BB field. /
vcoubard	551:ab7a8de3ff10	6624	#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /!< Bit mask of BB field. /
vcoubard	551:ab7a8de3ff10	6625	#define TWI_INTENCLR_BB_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6626	#define TWI_INTENCLR_BB_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6627	#define TWI_INTENCLR_BB_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6628
vcoubard	551:ab7a8de3ff10	6629	/* Bit 9 : Disable interrupt on ERROR event. */
vcoubard	551:ab7a8de3ff10	6630	#define TWI_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
vcoubard	551:ab7a8de3ff10	6631	#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
vcoubard	551:ab7a8de3ff10	6632	#define TWI_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6633	#define TWI_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6634	#define TWI_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6635
vcoubard	551:ab7a8de3ff10	6636	/* Bit 7 : Disable interrupt on TXDSENT event. */
vcoubard	551:ab7a8de3ff10	6637	#define TWI_INTENCLR_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
vcoubard	551:ab7a8de3ff10	6638	#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
vcoubard	551:ab7a8de3ff10	6639	#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6640	#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6641	#define TWI_INTENCLR_TXDSENT_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6642
vcoubard	551:ab7a8de3ff10	6643	/* Bit 2 : Disable interrupt on RXDREADY event. */
vcoubard	551:ab7a8de3ff10	6644	#define TWI_INTENCLR_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
vcoubard	551:ab7a8de3ff10	6645	#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
vcoubard	551:ab7a8de3ff10	6646	#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6647	#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6648	#define TWI_INTENCLR_RXDREADY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6649
vcoubard	551:ab7a8de3ff10	6650	/* Bit 1 : Disable interrupt on STOPPED event. */
vcoubard	551:ab7a8de3ff10	6651	#define TWI_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
vcoubard	551:ab7a8de3ff10	6652	#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
vcoubard	551:ab7a8de3ff10	6653	#define TWI_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6654	#define TWI_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6655	#define TWI_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6656
vcoubard	551:ab7a8de3ff10	6657	/* Register: TWI_ERRORSRC */
vcoubard	551:ab7a8de3ff10	6658	/* Description: Two-wire error source. Write error field to 1 to clear error. */
vcoubard	551:ab7a8de3ff10	6659
vcoubard	551:ab7a8de3ff10	6660	/* Bit 2 : NACK received after sending a data byte. */
vcoubard	551:ab7a8de3ff10	6661	#define TWI_ERRORSRC_DNACK_Pos (2UL) /!< Position of DNACK field. /
vcoubard	551:ab7a8de3ff10	6662	#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /!< Bit mask of DNACK field. /
vcoubard	551:ab7a8de3ff10	6663	#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /!< Error not present. /
vcoubard	551:ab7a8de3ff10	6664	#define TWI_ERRORSRC_DNACK_Present (1UL) /!< Error present. /
vcoubard	551:ab7a8de3ff10	6665	#define TWI_ERRORSRC_DNACK_Clear (1UL) /!< Clear error on write. /
vcoubard	551:ab7a8de3ff10	6666
vcoubard	551:ab7a8de3ff10	6667	/* Bit 1 : NACK received after sending the address. */
vcoubard	551:ab7a8de3ff10	6668	#define TWI_ERRORSRC_ANACK_Pos (1UL) /!< Position of ANACK field. /
vcoubard	551:ab7a8de3ff10	6669	#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /!< Bit mask of ANACK field. /
vcoubard	551:ab7a8de3ff10	6670	#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /!< Error not present. /
vcoubard	551:ab7a8de3ff10	6671	#define TWI_ERRORSRC_ANACK_Present (1UL) /!< Error present. /
vcoubard	551:ab7a8de3ff10	6672	#define TWI_ERRORSRC_ANACK_Clear (1UL) /!< Clear error on write. /
vcoubard	551:ab7a8de3ff10	6673
vcoubard	551:ab7a8de3ff10	6674	/* Register: TWI_ENABLE */
vcoubard	551:ab7a8de3ff10	6675	/* Description: Enable two-wire master. */
vcoubard	551:ab7a8de3ff10	6676
vcoubard	551:ab7a8de3ff10	6677	/* Bits 2..0 : Enable or disable W2M */
vcoubard	551:ab7a8de3ff10	6678	#define TWI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	551:ab7a8de3ff10	6679	#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	551:ab7a8de3ff10	6680	#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled. /
vcoubard	551:ab7a8de3ff10	6681	#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /!< Enabled. /
vcoubard	551:ab7a8de3ff10	6682
vcoubard	551:ab7a8de3ff10	6683	/* Register: TWI_RXD */
vcoubard	551:ab7a8de3ff10	6684	/* Description: RX data register. */
vcoubard	551:ab7a8de3ff10	6685
vcoubard	551:ab7a8de3ff10	6686	/* Bits 7..0 : RX data from last transfer. */
vcoubard	551:ab7a8de3ff10	6687	#define TWI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
vcoubard	551:ab7a8de3ff10	6688	#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
vcoubard	551:ab7a8de3ff10	6689
vcoubard	551:ab7a8de3ff10	6690	/* Register: TWI_TXD */
vcoubard	551:ab7a8de3ff10	6691	/* Description: TX data register. */
vcoubard	551:ab7a8de3ff10	6692
vcoubard	551:ab7a8de3ff10	6693	/* Bits 7..0 : TX data for next transfer. */
vcoubard	551:ab7a8de3ff10	6694	#define TWI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
vcoubard	551:ab7a8de3ff10	6695	#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
vcoubard	551:ab7a8de3ff10	6696
vcoubard	551:ab7a8de3ff10	6697	/* Register: TWI_FREQUENCY */
vcoubard	551:ab7a8de3ff10	6698	/* Description: Two-wire frequency. */
vcoubard	551:ab7a8de3ff10	6699
vcoubard	551:ab7a8de3ff10	6700	/* Bits 31..0 : Two-wire master clock frequency. */
vcoubard	551:ab7a8de3ff10	6701	#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
vcoubard	551:ab7a8de3ff10	6702	#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
vcoubard	551:ab7a8de3ff10	6703	#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /!< 100 kbps. /
vcoubard	551:ab7a8de3ff10	6704	#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
vcoubard	551:ab7a8de3ff10	6705	#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /!< 400 kbps. /
vcoubard	551:ab7a8de3ff10	6706
vcoubard	551:ab7a8de3ff10	6707	/* Register: TWI_ADDRESS */
vcoubard	551:ab7a8de3ff10	6708	/* Description: Address used in the two-wire transfer. */
vcoubard	551:ab7a8de3ff10	6709
vcoubard	551:ab7a8de3ff10	6710	/* Bits 6..0 : Two-wire address. */
vcoubard	551:ab7a8de3ff10	6711	#define TWI_ADDRESS_ADDRESS_Pos (0UL) /!< Position of ADDRESS field. /
vcoubard	551:ab7a8de3ff10	6712	#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
vcoubard	551:ab7a8de3ff10	6713
vcoubard	551:ab7a8de3ff10	6714	/* Register: TWI_POWER */
vcoubard	551:ab7a8de3ff10	6715	/* Description: Peripheral power control. */
vcoubard	551:ab7a8de3ff10	6716
vcoubard	551:ab7a8de3ff10	6717	/* Bit 0 : Peripheral power control. */
vcoubard	551:ab7a8de3ff10	6718	#define TWI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	551:ab7a8de3ff10	6719	#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	551:ab7a8de3ff10	6720	#define TWI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	551:ab7a8de3ff10	6721	#define TWI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	551:ab7a8de3ff10	6722
vcoubard	551:ab7a8de3ff10	6723
vcoubard	551:ab7a8de3ff10	6724	/* Peripheral: UART */
vcoubard	551:ab7a8de3ff10	6725	/* Description: Universal Asynchronous Receiver/Transmitter. */
vcoubard	551:ab7a8de3ff10	6726
vcoubard	551:ab7a8de3ff10	6727	/* Register: UART_SHORTS */
vcoubard	551:ab7a8de3ff10	6728	/* Description: Shortcuts for UART. */
vcoubard	551:ab7a8de3ff10	6729
vcoubard	551:ab7a8de3ff10	6730	/* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
vcoubard	551:ab7a8de3ff10	6731	#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /!< Position of NCTS_STOPRX field. /
vcoubard	551:ab7a8de3ff10	6732	#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /!< Bit mask of NCTS_STOPRX field. /
vcoubard	551:ab7a8de3ff10	6733	#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	6734	#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	6735
vcoubard	551:ab7a8de3ff10	6736	/* Bit 3 : Shortcut between CTS event and the STARTRX task. */
vcoubard	551:ab7a8de3ff10	6737	#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /!< Position of CTS_STARTRX field. /
vcoubard	551:ab7a8de3ff10	6738	#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /!< Bit mask of CTS_STARTRX field. /
vcoubard	551:ab7a8de3ff10	6739	#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /!< Shortcut disabled. /
vcoubard	551:ab7a8de3ff10	6740	#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /!< Shortcut enabled. /
vcoubard	551:ab7a8de3ff10	6741
vcoubard	551:ab7a8de3ff10	6742	/* Register: UART_INTENSET */
vcoubard	551:ab7a8de3ff10	6743	/* Description: Interrupt enable set register. */
vcoubard	551:ab7a8de3ff10	6744
vcoubard	551:ab7a8de3ff10	6745	/* Bit 17 : Enable interrupt on RXTO event. */
vcoubard	551:ab7a8de3ff10	6746	#define UART_INTENSET_RXTO_Pos (17UL) /!< Position of RXTO field. /
vcoubard	551:ab7a8de3ff10	6747	#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /!< Bit mask of RXTO field. /
vcoubard	551:ab7a8de3ff10	6748	#define UART_INTENSET_RXTO_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6749	#define UART_INTENSET_RXTO_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6750	#define UART_INTENSET_RXTO_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6751
vcoubard	551:ab7a8de3ff10	6752	/* Bit 9 : Enable interrupt on ERROR event. */
vcoubard	551:ab7a8de3ff10	6753	#define UART_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
vcoubard	551:ab7a8de3ff10	6754	#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
vcoubard	551:ab7a8de3ff10	6755	#define UART_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6756	#define UART_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6757	#define UART_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6758
vcoubard	551:ab7a8de3ff10	6759	/* Bit 7 : Enable interrupt on TXRDY event. */
vcoubard	551:ab7a8de3ff10	6760	#define UART_INTENSET_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
vcoubard	551:ab7a8de3ff10	6761	#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
vcoubard	551:ab7a8de3ff10	6762	#define UART_INTENSET_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6763	#define UART_INTENSET_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6764	#define UART_INTENSET_TXDRDY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6765
vcoubard	551:ab7a8de3ff10	6766	/* Bit 2 : Enable interrupt on RXRDY event. */
vcoubard	551:ab7a8de3ff10	6767	#define UART_INTENSET_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
vcoubard	551:ab7a8de3ff10	6768	#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
vcoubard	551:ab7a8de3ff10	6769	#define UART_INTENSET_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6770	#define UART_INTENSET_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6771	#define UART_INTENSET_RXDRDY_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6772
vcoubard	551:ab7a8de3ff10	6773	/* Bit 1 : Enable interrupt on NCTS event. */
vcoubard	551:ab7a8de3ff10	6774	#define UART_INTENSET_NCTS_Pos (1UL) /!< Position of NCTS field. /
vcoubard	551:ab7a8de3ff10	6775	#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /!< Bit mask of NCTS field. /
vcoubard	551:ab7a8de3ff10	6776	#define UART_INTENSET_NCTS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6777	#define UART_INTENSET_NCTS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6778	#define UART_INTENSET_NCTS_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6779
vcoubard	551:ab7a8de3ff10	6780	/* Bit 0 : Enable interrupt on CTS event. */
vcoubard	551:ab7a8de3ff10	6781	#define UART_INTENSET_CTS_Pos (0UL) /!< Position of CTS field. /
vcoubard	551:ab7a8de3ff10	6782	#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /!< Bit mask of CTS field. /
vcoubard	551:ab7a8de3ff10	6783	#define UART_INTENSET_CTS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6784	#define UART_INTENSET_CTS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6785	#define UART_INTENSET_CTS_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6786
vcoubard	551:ab7a8de3ff10	6787	/* Register: UART_INTENCLR */
vcoubard	551:ab7a8de3ff10	6788	/* Description: Interrupt enable clear register. */
vcoubard	551:ab7a8de3ff10	6789
vcoubard	551:ab7a8de3ff10	6790	/* Bit 17 : Disable interrupt on RXTO event. */
vcoubard	551:ab7a8de3ff10	6791	#define UART_INTENCLR_RXTO_Pos (17UL) /!< Position of RXTO field. /
vcoubard	551:ab7a8de3ff10	6792	#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /!< Bit mask of RXTO field. /
vcoubard	551:ab7a8de3ff10	6793	#define UART_INTENCLR_RXTO_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6794	#define UART_INTENCLR_RXTO_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6795	#define UART_INTENCLR_RXTO_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6796
vcoubard	551:ab7a8de3ff10	6797	/* Bit 9 : Disable interrupt on ERROR event. */
vcoubard	551:ab7a8de3ff10	6798	#define UART_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
vcoubard	551:ab7a8de3ff10	6799	#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
vcoubard	551:ab7a8de3ff10	6800	#define UART_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6801	#define UART_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6802	#define UART_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6803
vcoubard	551:ab7a8de3ff10	6804	/* Bit 7 : Disable interrupt on TXRDY event. */
vcoubard	551:ab7a8de3ff10	6805	#define UART_INTENCLR_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
vcoubard	551:ab7a8de3ff10	6806	#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
vcoubard	551:ab7a8de3ff10	6807	#define UART_INTENCLR_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6808	#define UART_INTENCLR_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6809	#define UART_INTENCLR_TXDRDY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6810
vcoubard	551:ab7a8de3ff10	6811	/* Bit 2 : Disable interrupt on RXRDY event. */
vcoubard	551:ab7a8de3ff10	6812	#define UART_INTENCLR_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
vcoubard	551:ab7a8de3ff10	6813	#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
vcoubard	551:ab7a8de3ff10	6814	#define UART_INTENCLR_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6815	#define UART_INTENCLR_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6816	#define UART_INTENCLR_RXDRDY_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6817
vcoubard	551:ab7a8de3ff10	6818	/* Bit 1 : Disable interrupt on NCTS event. */
vcoubard	551:ab7a8de3ff10	6819	#define UART_INTENCLR_NCTS_Pos (1UL) /!< Position of NCTS field. /
vcoubard	551:ab7a8de3ff10	6820	#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /!< Bit mask of NCTS field. /
vcoubard	551:ab7a8de3ff10	6821	#define UART_INTENCLR_NCTS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6822	#define UART_INTENCLR_NCTS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6823	#define UART_INTENCLR_NCTS_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6824
vcoubard	551:ab7a8de3ff10	6825	/* Bit 0 : Disable interrupt on CTS event. */
vcoubard	551:ab7a8de3ff10	6826	#define UART_INTENCLR_CTS_Pos (0UL) /!< Position of CTS field. /
vcoubard	551:ab7a8de3ff10	6827	#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /!< Bit mask of CTS field. /
vcoubard	551:ab7a8de3ff10	6828	#define UART_INTENCLR_CTS_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6829	#define UART_INTENCLR_CTS_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6830	#define UART_INTENCLR_CTS_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6831
vcoubard	551:ab7a8de3ff10	6832	/* Register: UART_ERRORSRC */
vcoubard	551:ab7a8de3ff10	6833	/* Description: Error source. Write error field to 1 to clear error. */
vcoubard	551:ab7a8de3ff10	6834
vcoubard	551:ab7a8de3ff10	6835	/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
vcoubard	551:ab7a8de3ff10	6836	#define UART_ERRORSRC_BREAK_Pos (3UL) /!< Position of BREAK field. /
vcoubard	551:ab7a8de3ff10	6837	#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /!< Bit mask of BREAK field. /
vcoubard	551:ab7a8de3ff10	6838	#define UART_ERRORSRC_BREAK_NotPresent (0UL) /!< Error not present. /
vcoubard	551:ab7a8de3ff10	6839	#define UART_ERRORSRC_BREAK_Present (1UL) /!< Error present. /
vcoubard	551:ab7a8de3ff10	6840	#define UART_ERRORSRC_BREAK_Clear (1UL) /!< Clear error on write. /
vcoubard	551:ab7a8de3ff10	6841
vcoubard	551:ab7a8de3ff10	6842	/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
vcoubard	551:ab7a8de3ff10	6843	#define UART_ERRORSRC_FRAMING_Pos (2UL) /!< Position of FRAMING field. /
vcoubard	551:ab7a8de3ff10	6844	#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /!< Bit mask of FRAMING field. /
vcoubard	551:ab7a8de3ff10	6845	#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /!< Error not present. /
vcoubard	551:ab7a8de3ff10	6846	#define UART_ERRORSRC_FRAMING_Present (1UL) /!< Error present. /
vcoubard	551:ab7a8de3ff10	6847	#define UART_ERRORSRC_FRAMING_Clear (1UL) /!< Clear error on write. /
vcoubard	551:ab7a8de3ff10	6848
vcoubard	551:ab7a8de3ff10	6849	/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
vcoubard	551:ab7a8de3ff10	6850	#define UART_ERRORSRC_PARITY_Pos (1UL) /!< Position of PARITY field. /
vcoubard	551:ab7a8de3ff10	6851	#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /!< Bit mask of PARITY field. /
vcoubard	551:ab7a8de3ff10	6852	#define UART_ERRORSRC_PARITY_NotPresent (0UL) /!< Error not present. /
vcoubard	551:ab7a8de3ff10	6853	#define UART_ERRORSRC_PARITY_Present (1UL) /!< Error present. /
vcoubard	551:ab7a8de3ff10	6854	#define UART_ERRORSRC_PARITY_Clear (1UL) /!< Clear error on write. /
vcoubard	551:ab7a8de3ff10	6855
vcoubard	551:ab7a8de3ff10	6856	/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
vcoubard	551:ab7a8de3ff10	6857	#define UART_ERRORSRC_OVERRUN_Pos (0UL) /!< Position of OVERRUN field. /
vcoubard	551:ab7a8de3ff10	6858	#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /!< Bit mask of OVERRUN field. /
vcoubard	551:ab7a8de3ff10	6859	#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /!< Error not present. /
vcoubard	551:ab7a8de3ff10	6860	#define UART_ERRORSRC_OVERRUN_Present (1UL) /!< Error present. /
vcoubard	551:ab7a8de3ff10	6861	#define UART_ERRORSRC_OVERRUN_Clear (1UL) /!< Clear error on write. /
vcoubard	551:ab7a8de3ff10	6862
vcoubard	551:ab7a8de3ff10	6863	/* Register: UART_ENABLE */
vcoubard	551:ab7a8de3ff10	6864	/* Description: Enable UART and acquire IOs. */
vcoubard	551:ab7a8de3ff10	6865
vcoubard	551:ab7a8de3ff10	6866	/* Bits 2..0 : Enable or disable UART and acquire IOs. */
vcoubard	551:ab7a8de3ff10	6867	#define UART_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
vcoubard	551:ab7a8de3ff10	6868	#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
vcoubard	551:ab7a8de3ff10	6869	#define UART_ENABLE_ENABLE_Disabled (0x00UL) /!< UART disabled. /
vcoubard	551:ab7a8de3ff10	6870	#define UART_ENABLE_ENABLE_Enabled (0x04UL) /!< UART enabled. /
vcoubard	551:ab7a8de3ff10	6871
vcoubard	551:ab7a8de3ff10	6872	/* Register: UART_RXD */
vcoubard	551:ab7a8de3ff10	6873	/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
vcoubard	551:ab7a8de3ff10	6874
vcoubard	551:ab7a8de3ff10	6875	/* Bits 7..0 : RX data from previous transfer. Double buffered. */
vcoubard	551:ab7a8de3ff10	6876	#define UART_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
vcoubard	551:ab7a8de3ff10	6877	#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /!< Bit mask of RXD field. /
vcoubard	551:ab7a8de3ff10	6878
vcoubard	551:ab7a8de3ff10	6879	/* Register: UART_TXD */
vcoubard	551:ab7a8de3ff10	6880	/* Description: TXD register. */
vcoubard	551:ab7a8de3ff10	6881
vcoubard	551:ab7a8de3ff10	6882	/* Bits 7..0 : TX data for transfer. */
vcoubard	551:ab7a8de3ff10	6883	#define UART_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
vcoubard	551:ab7a8de3ff10	6884	#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /!< Bit mask of TXD field. /
vcoubard	551:ab7a8de3ff10	6885
vcoubard	551:ab7a8de3ff10	6886	/* Register: UART_BAUDRATE */
vcoubard	551:ab7a8de3ff10	6887	/* Description: UART Baudrate. */
vcoubard	551:ab7a8de3ff10	6888
vcoubard	551:ab7a8de3ff10	6889	/* Bits 31..0 : UART baudrate. */
vcoubard	551:ab7a8de3ff10	6890	#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /!< Position of BAUDRATE field. /
vcoubard	551:ab7a8de3ff10	6891	#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /!< Bit mask of BAUDRATE field. /
vcoubard	551:ab7a8de3ff10	6892	#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /!< 1200 baud. /
vcoubard	551:ab7a8de3ff10	6893	#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /!< 2400 baud. /
vcoubard	551:ab7a8de3ff10	6894	#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /!< 4800 baud. /
vcoubard	551:ab7a8de3ff10	6895	#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /!< 9600 baud. /
vcoubard	551:ab7a8de3ff10	6896	#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /!< 14400 baud. /
vcoubard	551:ab7a8de3ff10	6897	#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /!< 19200 baud. /
vcoubard	551:ab7a8de3ff10	6898	#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /!< 28800 baud. /
vcoubard	551:ab7a8de3ff10	6899	#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /!< 38400 baud. /
vcoubard	551:ab7a8de3ff10	6900	#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /!< 57600 baud. /
vcoubard	551:ab7a8de3ff10	6901	#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /!< 76800 baud. /
vcoubard	551:ab7a8de3ff10	6902	#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /!< 115200 baud. /
vcoubard	551:ab7a8de3ff10	6903	#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /!< 230400 baud. /
vcoubard	551:ab7a8de3ff10	6904	#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /!< 250000 baud. /
vcoubard	551:ab7a8de3ff10	6905	#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /!< 460800 baud. /
vcoubard	551:ab7a8de3ff10	6906	#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /!< 921600 baud. /
vcoubard	551:ab7a8de3ff10	6907	#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /!< 1M baud. /
vcoubard	551:ab7a8de3ff10	6908
vcoubard	551:ab7a8de3ff10	6909	/* Register: UART_CONFIG */
vcoubard	551:ab7a8de3ff10	6910	/* Description: Configuration of parity and hardware flow control register. */
vcoubard	551:ab7a8de3ff10	6911
vcoubard	551:ab7a8de3ff10	6912	/* Bits 3..1 : Include parity bit. */
vcoubard	551:ab7a8de3ff10	6913	#define UART_CONFIG_PARITY_Pos (1UL) /!< Position of PARITY field. /
vcoubard	551:ab7a8de3ff10	6914	#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /!< Bit mask of PARITY field. /
vcoubard	551:ab7a8de3ff10	6915	#define UART_CONFIG_PARITY_Excluded (0UL) /!< Parity bit excluded. /
vcoubard	551:ab7a8de3ff10	6916	#define UART_CONFIG_PARITY_Included (7UL) /!< Parity bit included. /
vcoubard	551:ab7a8de3ff10	6917
vcoubard	551:ab7a8de3ff10	6918	/* Bit 0 : Hardware flow control. */
vcoubard	551:ab7a8de3ff10	6919	#define UART_CONFIG_HWFC_Pos (0UL) /!< Position of HWFC field. /
vcoubard	551:ab7a8de3ff10	6920	#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /!< Bit mask of HWFC field. /
vcoubard	551:ab7a8de3ff10	6921	#define UART_CONFIG_HWFC_Disabled (0UL) /!< Hardware flow control disabled. /
vcoubard	551:ab7a8de3ff10	6922	#define UART_CONFIG_HWFC_Enabled (1UL) /!< Hardware flow control enabled. /
vcoubard	551:ab7a8de3ff10	6923
vcoubard	551:ab7a8de3ff10	6924	/* Register: UART_POWER */
vcoubard	551:ab7a8de3ff10	6925	/* Description: Peripheral power control. */
vcoubard	551:ab7a8de3ff10	6926
vcoubard	551:ab7a8de3ff10	6927	/* Bit 0 : Peripheral power control. */
vcoubard	551:ab7a8de3ff10	6928	#define UART_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	551:ab7a8de3ff10	6929	#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	551:ab7a8de3ff10	6930	#define UART_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	551:ab7a8de3ff10	6931	#define UART_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	551:ab7a8de3ff10	6932
vcoubard	551:ab7a8de3ff10	6933
vcoubard	551:ab7a8de3ff10	6934	/* Peripheral: UICR */
vcoubard	551:ab7a8de3ff10	6935	/* Description: User Information Configuration. */
vcoubard	551:ab7a8de3ff10	6936
vcoubard	551:ab7a8de3ff10	6937	/* Register: UICR_RBPCONF */
vcoubard	551:ab7a8de3ff10	6938	/* Description: Readback protection configuration. */
vcoubard	551:ab7a8de3ff10	6939
vcoubard	551:ab7a8de3ff10	6940	/* Bits 15..8 : Readback protect all code in the device. */
vcoubard	551:ab7a8de3ff10	6941	#define UICR_RBPCONF_PALL_Pos (8UL) /!< Position of PALL field. /
vcoubard	551:ab7a8de3ff10	6942	#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /!< Bit mask of PALL field. /
vcoubard	551:ab7a8de3ff10	6943	#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /!< Disabled. /
vcoubard	551:ab7a8de3ff10	6944	#define UICR_RBPCONF_PALL_Enabled (0x00UL) /!< Enabled. /
vcoubard	551:ab7a8de3ff10	6945
vcoubard	551:ab7a8de3ff10	6946	/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
vcoubard	551:ab7a8de3ff10	6947	#define UICR_RBPCONF_PR0_Pos (0UL) /!< Position of PR0 field. /
vcoubard	551:ab7a8de3ff10	6948	#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /!< Bit mask of PR0 field. /
vcoubard	551:ab7a8de3ff10	6949	#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /!< Disabled. /
vcoubard	551:ab7a8de3ff10	6950	#define UICR_RBPCONF_PR0_Enabled (0x00UL) /!< Enabled. /
vcoubard	551:ab7a8de3ff10	6951
vcoubard	551:ab7a8de3ff10	6952	/* Register: UICR_XTALFREQ */
vcoubard	551:ab7a8de3ff10	6953	/* Description: Reset value for CLOCK XTALFREQ register. */
vcoubard	551:ab7a8de3ff10	6954
vcoubard	551:ab7a8de3ff10	6955	/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
vcoubard	551:ab7a8de3ff10	6956	#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
vcoubard	551:ab7a8de3ff10	6957	#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
vcoubard	551:ab7a8de3ff10	6958	#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz Xtal is used. /
vcoubard	551:ab7a8de3ff10	6959	#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz Xtal is used. /
vcoubard	551:ab7a8de3ff10	6960
vcoubard	551:ab7a8de3ff10	6961	/* Register: UICR_FWID */
vcoubard	551:ab7a8de3ff10	6962	/* Description: Firmware ID. */
vcoubard	551:ab7a8de3ff10	6963
vcoubard	551:ab7a8de3ff10	6964	/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
vcoubard	551:ab7a8de3ff10	6965	#define UICR_FWID_FWID_Pos (0UL) /!< Position of FWID field. /
vcoubard	551:ab7a8de3ff10	6966	#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /!< Bit mask of FWID field. /
vcoubard	551:ab7a8de3ff10	6967
vcoubard	551:ab7a8de3ff10	6968
vcoubard	551:ab7a8de3ff10	6969	/* Peripheral: WDT */
vcoubard	551:ab7a8de3ff10	6970	/* Description: Watchdog Timer. */
vcoubard	551:ab7a8de3ff10	6971
vcoubard	551:ab7a8de3ff10	6972	/* Register: WDT_INTENSET */
vcoubard	551:ab7a8de3ff10	6973	/* Description: Interrupt enable set register. */
vcoubard	551:ab7a8de3ff10	6974
vcoubard	551:ab7a8de3ff10	6975	/* Bit 0 : Enable interrupt on TIMEOUT event. */
vcoubard	551:ab7a8de3ff10	6976	#define WDT_INTENSET_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
vcoubard	551:ab7a8de3ff10	6977	#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
vcoubard	551:ab7a8de3ff10	6978	#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6979	#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6980	#define WDT_INTENSET_TIMEOUT_Set (1UL) /!< Enable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6981
vcoubard	551:ab7a8de3ff10	6982	/* Register: WDT_INTENCLR */
vcoubard	551:ab7a8de3ff10	6983	/* Description: Interrupt enable clear register. */
vcoubard	551:ab7a8de3ff10	6984
vcoubard	551:ab7a8de3ff10	6985	/* Bit 0 : Disable interrupt on TIMEOUT event. */
vcoubard	551:ab7a8de3ff10	6986	#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
vcoubard	551:ab7a8de3ff10	6987	#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
vcoubard	551:ab7a8de3ff10	6988	#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
vcoubard	551:ab7a8de3ff10	6989	#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
vcoubard	551:ab7a8de3ff10	6990	#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /!< Disable interrupt on write. /
vcoubard	551:ab7a8de3ff10	6991
vcoubard	551:ab7a8de3ff10	6992	/* Register: WDT_RUNSTATUS */
vcoubard	551:ab7a8de3ff10	6993	/* Description: Watchdog running status. */
vcoubard	551:ab7a8de3ff10	6994
vcoubard	551:ab7a8de3ff10	6995	/* Bit 0 : Watchdog running status. */
vcoubard	551:ab7a8de3ff10	6996	#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /!< Position of RUNSTATUS field. /
vcoubard	551:ab7a8de3ff10	6997	#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /!< Bit mask of RUNSTATUS field. /
vcoubard	551:ab7a8de3ff10	6998	#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /!< Watchdog timer is not running. /
vcoubard	551:ab7a8de3ff10	6999	#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /!< Watchdog timer is running. /
vcoubard	551:ab7a8de3ff10	7000
vcoubard	551:ab7a8de3ff10	7001	/* Register: WDT_REQSTATUS */
vcoubard	551:ab7a8de3ff10	7002	/* Description: Request status. */
vcoubard	551:ab7a8de3ff10	7003
vcoubard	551:ab7a8de3ff10	7004	/* Bit 7 : Request status for RR[7]. */
vcoubard	551:ab7a8de3ff10	7005	#define WDT_REQSTATUS_RR7_Pos (7UL) /!< Position of RR7 field. /
vcoubard	551:ab7a8de3ff10	7006	#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /!< Bit mask of RR7 field. /
vcoubard	551:ab7a8de3ff10	7007	#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /!< RR[7] register is not enabled or has already requested reload. /
vcoubard	551:ab7a8de3ff10	7008	#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /!< RR[7] register is enabled and has not jet requested. /
vcoubard	551:ab7a8de3ff10	7009
vcoubard	551:ab7a8de3ff10	7010	/* Bit 6 : Request status for RR[6]. */
vcoubard	551:ab7a8de3ff10	7011	#define WDT_REQSTATUS_RR6_Pos (6UL) /!< Position of RR6 field. /
vcoubard	551:ab7a8de3ff10	7012	#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /!< Bit mask of RR6 field. /
vcoubard	551:ab7a8de3ff10	7013	#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /!< RR[6] register is not enabled or has already requested reload. /
vcoubard	551:ab7a8de3ff10	7014	#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /!< RR[6] register is enabled and has not jet requested. /
vcoubard	551:ab7a8de3ff10	7015
vcoubard	551:ab7a8de3ff10	7016	/* Bit 5 : Request status for RR[5]. */
vcoubard	551:ab7a8de3ff10	7017	#define WDT_REQSTATUS_RR5_Pos (5UL) /!< Position of RR5 field. /
vcoubard	551:ab7a8de3ff10	7018	#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /!< Bit mask of RR5 field. /
vcoubard	551:ab7a8de3ff10	7019	#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /!< RR[5] register is not enabled or has already requested reload. /
vcoubard	551:ab7a8de3ff10	7020	#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /!< RR[5] register is enabled and has not jet requested. /
vcoubard	551:ab7a8de3ff10	7021
vcoubard	551:ab7a8de3ff10	7022	/* Bit 4 : Request status for RR[4]. */
vcoubard	551:ab7a8de3ff10	7023	#define WDT_REQSTATUS_RR4_Pos (4UL) /!< Position of RR4 field. /
vcoubard	551:ab7a8de3ff10	7024	#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /!< Bit mask of RR4 field. /
vcoubard	551:ab7a8de3ff10	7025	#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /!< RR[4] register is not enabled or has already requested reload. /
vcoubard	551:ab7a8de3ff10	7026	#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /!< RR[4] register is enabled and has not jet requested. /
vcoubard	551:ab7a8de3ff10	7027
vcoubard	551:ab7a8de3ff10	7028	/* Bit 3 : Request status for RR[3]. */
vcoubard	551:ab7a8de3ff10	7029	#define WDT_REQSTATUS_RR3_Pos (3UL) /!< Position of RR3 field. /
vcoubard	551:ab7a8de3ff10	7030	#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /!< Bit mask of RR3 field. /
vcoubard	551:ab7a8de3ff10	7031	#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /!< RR[3] register is not enabled or has already requested reload. /
vcoubard	551:ab7a8de3ff10	7032	#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /!< RR[3] register is enabled and has not jet requested. /
vcoubard	551:ab7a8de3ff10	7033
vcoubard	551:ab7a8de3ff10	7034	/* Bit 2 : Request status for RR[2]. */
vcoubard	551:ab7a8de3ff10	7035	#define WDT_REQSTATUS_RR2_Pos (2UL) /!< Position of RR2 field. /
vcoubard	551:ab7a8de3ff10	7036	#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /!< Bit mask of RR2 field. /
vcoubard	551:ab7a8de3ff10	7037	#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /!< RR[2] register is not enabled or has already requested reload. /
vcoubard	551:ab7a8de3ff10	7038	#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /!< RR[2] register is enabled and has not jet requested. /
vcoubard	551:ab7a8de3ff10	7039
vcoubard	551:ab7a8de3ff10	7040	/* Bit 1 : Request status for RR[1]. */
vcoubard	551:ab7a8de3ff10	7041	#define WDT_REQSTATUS_RR1_Pos (1UL) /!< Position of RR1 field. /
vcoubard	551:ab7a8de3ff10	7042	#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /!< Bit mask of RR1 field. /
vcoubard	551:ab7a8de3ff10	7043	#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /!< RR[1] register is not enabled or has already requested reload. /
vcoubard	551:ab7a8de3ff10	7044	#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /!< RR[1] register is enabled and has not jet requested. /
vcoubard	551:ab7a8de3ff10	7045
vcoubard	551:ab7a8de3ff10	7046	/* Bit 0 : Request status for RR[0]. */
vcoubard	551:ab7a8de3ff10	7047	#define WDT_REQSTATUS_RR0_Pos (0UL) /!< Position of RR0 field. /
vcoubard	551:ab7a8de3ff10	7048	#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /!< Bit mask of RR0 field. /
vcoubard	551:ab7a8de3ff10	7049	#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /!< RR[0] register is not enabled or has already requested reload. /
vcoubard	551:ab7a8de3ff10	7050	#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /!< RR[0] register is enabled and has not jet requested. /
vcoubard	551:ab7a8de3ff10	7051
vcoubard	551:ab7a8de3ff10	7052	/* Register: WDT_RREN */
vcoubard	551:ab7a8de3ff10	7053	/* Description: Reload request enable. */
vcoubard	551:ab7a8de3ff10	7054
vcoubard	551:ab7a8de3ff10	7055	/* Bit 7 : Enable or disable RR[7] register. */
vcoubard	551:ab7a8de3ff10	7056	#define WDT_RREN_RR7_Pos (7UL) /!< Position of RR7 field. /
vcoubard	551:ab7a8de3ff10	7057	#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /!< Bit mask of RR7 field. /
vcoubard	551:ab7a8de3ff10	7058	#define WDT_RREN_RR7_Disabled (0UL) /!< RR[7] register is disabled. /
vcoubard	551:ab7a8de3ff10	7059	#define WDT_RREN_RR7_Enabled (1UL) /!< RR[7] register is enabled. /
vcoubard	551:ab7a8de3ff10	7060
vcoubard	551:ab7a8de3ff10	7061	/* Bit 6 : Enable or disable RR[6] register. */
vcoubard	551:ab7a8de3ff10	7062	#define WDT_RREN_RR6_Pos (6UL) /!< Position of RR6 field. /
vcoubard	551:ab7a8de3ff10	7063	#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /!< Bit mask of RR6 field. /
vcoubard	551:ab7a8de3ff10	7064	#define WDT_RREN_RR6_Disabled (0UL) /!< RR[6] register is disabled. /
vcoubard	551:ab7a8de3ff10	7065	#define WDT_RREN_RR6_Enabled (1UL) /!< RR[6] register is enabled. /
vcoubard	551:ab7a8de3ff10	7066
vcoubard	551:ab7a8de3ff10	7067	/* Bit 5 : Enable or disable RR[5] register. */
vcoubard	551:ab7a8de3ff10	7068	#define WDT_RREN_RR5_Pos (5UL) /!< Position of RR5 field. /
vcoubard	551:ab7a8de3ff10	7069	#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /!< Bit mask of RR5 field. /
vcoubard	551:ab7a8de3ff10	7070	#define WDT_RREN_RR5_Disabled (0UL) /!< RR[5] register is disabled. /
vcoubard	551:ab7a8de3ff10	7071	#define WDT_RREN_RR5_Enabled (1UL) /!< RR[5] register is enabled. /
vcoubard	551:ab7a8de3ff10	7072
vcoubard	551:ab7a8de3ff10	7073	/* Bit 4 : Enable or disable RR[4] register. */
vcoubard	551:ab7a8de3ff10	7074	#define WDT_RREN_RR4_Pos (4UL) /!< Position of RR4 field. /
vcoubard	551:ab7a8de3ff10	7075	#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /!< Bit mask of RR4 field. /
vcoubard	551:ab7a8de3ff10	7076	#define WDT_RREN_RR4_Disabled (0UL) /!< RR[4] register is disabled. /
vcoubard	551:ab7a8de3ff10	7077	#define WDT_RREN_RR4_Enabled (1UL) /!< RR[4] register is enabled. /
vcoubard	551:ab7a8de3ff10	7078
vcoubard	551:ab7a8de3ff10	7079	/* Bit 3 : Enable or disable RR[3] register. */
vcoubard	551:ab7a8de3ff10	7080	#define WDT_RREN_RR3_Pos (3UL) /!< Position of RR3 field. /
vcoubard	551:ab7a8de3ff10	7081	#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /!< Bit mask of RR3 field. /
vcoubard	551:ab7a8de3ff10	7082	#define WDT_RREN_RR3_Disabled (0UL) /!< RR[3] register is disabled. /
vcoubard	551:ab7a8de3ff10	7083	#define WDT_RREN_RR3_Enabled (1UL) /!< RR[3] register is enabled. /
vcoubard	551:ab7a8de3ff10	7084
vcoubard	551:ab7a8de3ff10	7085	/* Bit 2 : Enable or disable RR[2] register. */
vcoubard	551:ab7a8de3ff10	7086	#define WDT_RREN_RR2_Pos (2UL) /!< Position of RR2 field. /
vcoubard	551:ab7a8de3ff10	7087	#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /!< Bit mask of RR2 field. /
vcoubard	551:ab7a8de3ff10	7088	#define WDT_RREN_RR2_Disabled (0UL) /!< RR[2] register is disabled. /
vcoubard	551:ab7a8de3ff10	7089	#define WDT_RREN_RR2_Enabled (1UL) /!< RR[2] register is enabled. /
vcoubard	551:ab7a8de3ff10	7090
vcoubard	551:ab7a8de3ff10	7091	/* Bit 1 : Enable or disable RR[1] register. */
vcoubard	551:ab7a8de3ff10	7092	#define WDT_RREN_RR1_Pos (1UL) /!< Position of RR1 field. /
vcoubard	551:ab7a8de3ff10	7093	#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /!< Bit mask of RR1 field. /
vcoubard	551:ab7a8de3ff10	7094	#define WDT_RREN_RR1_Disabled (0UL) /!< RR[1] register is disabled. /
vcoubard	551:ab7a8de3ff10	7095	#define WDT_RREN_RR1_Enabled (1UL) /!< RR[1] register is enabled. /
vcoubard	551:ab7a8de3ff10	7096
vcoubard	551:ab7a8de3ff10	7097	/* Bit 0 : Enable or disable RR[0] register. */
vcoubard	551:ab7a8de3ff10	7098	#define WDT_RREN_RR0_Pos (0UL) /!< Position of RR0 field. /
vcoubard	551:ab7a8de3ff10	7099	#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /!< Bit mask of RR0 field. /
vcoubard	551:ab7a8de3ff10	7100	#define WDT_RREN_RR0_Disabled (0UL) /!< RR[0] register is disabled. /
vcoubard	551:ab7a8de3ff10	7101	#define WDT_RREN_RR0_Enabled (1UL) /!< RR[0] register is enabled. /
vcoubard	551:ab7a8de3ff10	7102
vcoubard	551:ab7a8de3ff10	7103	/* Register: WDT_CONFIG */
vcoubard	551:ab7a8de3ff10	7104	/* Description: Configuration register. */
vcoubard	551:ab7a8de3ff10	7105
vcoubard	551:ab7a8de3ff10	7106	/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
vcoubard	551:ab7a8de3ff10	7107	#define WDT_CONFIG_HALT_Pos (3UL) /!< Position of HALT field. /
vcoubard	551:ab7a8de3ff10	7108	#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /!< Bit mask of HALT field. /
vcoubard	551:ab7a8de3ff10	7109	#define WDT_CONFIG_HALT_Pause (0UL) /!< Pause watchdog while the CPU is halted by the debugger. /
vcoubard	551:ab7a8de3ff10	7110	#define WDT_CONFIG_HALT_Run (1UL) /!< Do not pause watchdog while the CPU is halted by the debugger. /
vcoubard	551:ab7a8de3ff10	7111
vcoubard	551:ab7a8de3ff10	7112	/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
vcoubard	551:ab7a8de3ff10	7113	#define WDT_CONFIG_SLEEP_Pos (0UL) /!< Position of SLEEP field. /
vcoubard	551:ab7a8de3ff10	7114	#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /!< Bit mask of SLEEP field. /
vcoubard	551:ab7a8de3ff10	7115	#define WDT_CONFIG_SLEEP_Pause (0UL) /!< Pause watchdog while the CPU is asleep. /
vcoubard	551:ab7a8de3ff10	7116	#define WDT_CONFIG_SLEEP_Run (1UL) /!< Do not pause watchdog while the CPU is asleep. /
vcoubard	551:ab7a8de3ff10	7117
vcoubard	551:ab7a8de3ff10	7118	/* Register: WDT_RR */
vcoubard	551:ab7a8de3ff10	7119	/* Description: Reload requests registers. */
vcoubard	551:ab7a8de3ff10	7120
vcoubard	551:ab7a8de3ff10	7121	/* Bits 31..0 : Reload register. */
vcoubard	551:ab7a8de3ff10	7122	#define WDT_RR_RR_Pos (0UL) /!< Position of RR field. /
vcoubard	551:ab7a8de3ff10	7123	#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /!< Bit mask of RR field. /
vcoubard	551:ab7a8de3ff10	7124	#define WDT_RR_RR_Reload (0x6E524635UL) /!< Value to request a reload of the watchdog timer. /
vcoubard	551:ab7a8de3ff10	7125
vcoubard	551:ab7a8de3ff10	7126	/* Register: WDT_POWER */
vcoubard	551:ab7a8de3ff10	7127	/* Description: Peripheral power control. */
vcoubard	551:ab7a8de3ff10	7128
vcoubard	551:ab7a8de3ff10	7129	/* Bit 0 : Peripheral power control. */
vcoubard	551:ab7a8de3ff10	7130	#define WDT_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
vcoubard	551:ab7a8de3ff10	7131	#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /!< Bit mask of POWER field. /
vcoubard	551:ab7a8de3ff10	7132	#define WDT_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
vcoubard	551:ab7a8de3ff10	7133	#define WDT_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
vcoubard	551:ab7a8de3ff10	7134
vcoubard	551:ab7a8de3ff10	7135
vcoubard	551:ab7a8de3ff10	7136	/lint --flb "Leave library region" /
rgrover1	504:2179e57ad950	7137	#endif

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Type:	Library
Created:	01 Jun 2016
Imports:	6
Forks:	0
Commits:	625
Dependents:	1
Dependencies:	1
Followers:	1

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source/nordic-sdk/components/device/nrf51_bitfields.h@551:ab7a8de3ff10, 2016-01-11 (annotated)

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