Marco Graf / Mbed 2 deprecated 20MHz_PWM_on_80MHz_cclk

Fast 20MHz PWM, with double edge controlled PWMs (90° Phase shifted). CPU clock had to be adjusted to 80MHz (PLL-controlled). Done by accessing the registers directrly.

Dependencies:   mbed

main.cpp@0:8bd0ebc5cbb0, 2010-06-09 (annotated)

Committer:
cedes
Date:
Wed Jun 09 07:47:00 2010 +0000
Revision:
0:8bd0ebc5cbb0

        

        
Who changed what in which revision?

        

            
                
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#include "mbed.h"





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DigitalOut myled1(LED1);





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DigitalOut myled2(LED2);





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DigitalOut myled3(LED3);





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DigitalOut myled4(LED4);





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DigitalOut  outGND1(p21);





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PwmOut      fmclck6(p22);





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PwmOut      fmclck5(p23);





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DigitalOut  outGND2(p24);





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PwmOut      fmclck4(p25);





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#define PLL0CFG_Val     0x00027





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#define PLL1_SETUP      0





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#define CCLKCFG_Val     5





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#define WAIT_SEC_BEFORE_START   5.0





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int main() {





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    // Wait a bit before changing the clock. Who knows, perhaps





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    // it is needed to connect to the device





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    myled1 = 1;





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    wait(WAIT_SEC_BEFORE_START/4.0);





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    myled1 = 0;





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    myled2 = 1;





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    wait(WAIT_SEC_BEFORE_START/4.0);





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    myled2 = 0;





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    myled3 = 1;





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    wait(WAIT_SEC_BEFORE_START/4.0);





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    myled3 = 0;





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    myled4 = 1;





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    wait(WAIT_SEC_BEFORE_START/4.0);





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    myled1 = 1;





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    myled2 = 1;





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    myled3 = 1;





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    myled4 = 1;





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    // The following sequence must be followed step by step in order to have PLL0 initialized





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    // and running:





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    // 1. Disconnect PLL0 with one feed sequence if PLL0 is already connected.





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    LPC_SC->PLL0CON  &= ~0x02;              /* PLL0 Disconnect */





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    LPC_SC->PLL0FEED  = 0xAA;





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    LPC_SC->PLL0FEED  = 0x55;





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    // 2. Disable PLL0 with one feed sequence.





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    LPC_SC->PLL0CON  &= ~0x01;              /* PLL0 Disable */





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    LPC_SC->PLL0FEED  = 0xAA;





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    LPC_SC->PLL0FEED  = 0x55;





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    // 3. Change the CPU Clock Divider setting to speed up operation without PLL0, if desired.





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//    LPC_SC->CCLKCFG   = 2;                /* Setup Clock Divider "2 + 1 = 3 DIVIDER"  */





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    // 4. Write to the Clock Source Selection Control register to change the clock source if





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    // needed.





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    LPC_SC->CLKSRCSEL = 0x00000001;         /* Select Clock Source for PLL0       */





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    // 5. Write to the PLL0CFG and make it effective with one feed sequence. The PLL0CFG





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    // can only be updated when PLL0 is disabled.





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    LPC_SC->PLL0CFG   = 0x00000013;         /* configure PLL0, N = 1, M = 20 (0x13 + 1) */





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    LPC_SC->PLL0FEED  = 0xAA;





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    LPC_SC->PLL0FEED  = 0x55;





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    // 6. Enable PLL0 with one feed sequence.





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    LPC_SC->PLL0CON  |= 0x01;               /* PLL0 Enable */





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    LPC_SC->PLL0FEED  = 0xAA;





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    LPC_SC->PLL0FEED  = 0x55;





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    // 7. Change the CPU Clock Divider setting for the operation with PLL0. It is critical to do





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    // this before connecting PLL0.





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    LPC_SC->CCLKCFG   = 5;                  /* Setup Clock Divider "5 + 1 = 6 DIVIDER"  */





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    // 8. Wait for PLL0 to achieve lock by monitoring the PLOCK0 bit in the PLL0STAT register,





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    // or using the PLOCK0 interrupt, or wait for a fixed time when the input clock to PLL0 is





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    // slow (i.e. 32 kHz). The value of PLOCK0 may not be stable when the PLL reference





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    // frequency (FREF, the frequency of REFCLK, which is equal to the PLL input





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    // frequency divided by the pre-divider value) is less than 100 kHz or greater than





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    // 20 MHz. In these cases, the PLL may be assumed to be stable after a start-up time





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    // has passed. This time is 500 μs when FREF is greater than 400 kHz and 200 / FREF





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    // seconds when FREF is less than 400 kHz.





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    while (!(LPC_SC->PLL0STAT & (1<<26)));  /* Wait for PLOCK0 */





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    // 9. Connect PLL0 with one feed sequence.





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    LPC_SC->PLL0CON  |= 0x02;               /* PLL0 Connect */





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    LPC_SC->PLL0FEED  = 0xAA;





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    LPC_SC->PLL0FEED  = 0x55;





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    // It is very important not to merge any steps above. For example, do not update the





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    // PLL0CFG and enable PLL0 simultaneously with the same feed sequence.





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    // set PWM





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    outGND1 = 0;                            // Just to have a GND near to the PWMs





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    outGND2 = 0;                            // Just to have a GND near to the PWMs





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    LPC_PWM1->TCR = (1 << 1);               // Reset counter, disable PWM





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    LPC_SC->PCLKSEL0 &= ~(0x3 << 12);





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    LPC_SC->PCLKSEL0 |= (1 << 12);          // Set peripheral clock divider to /1, i.e. system clock





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    LPC_PWM1->PCR |= 0x002C;                // Double edge PWM for PWM2,3,5





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    LPC_PWM1->MR0 = 3;                      // Match Register 0 is shared period counter for all PWM1





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    LPC_PWM1->MR1 = 0;                      // so Match Register 0





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    LPC_PWM1->MR2 = 2;                      // so Match Register 1





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    LPC_PWM1->MR3 = 0;                      // so Match Register 2





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    LPC_PWM1->MR4 = 1;                      // so Match Register 3





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    LPC_PWM1->MR5 = 3;                      // so Match Register 3





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    LPC_PWM1->LER |= 1;                     // Start updating at next period start





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    LPC_PWM1->TCR = (1 << 0) || (1 << 3);   // Enable counter and PWM





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    while(1);





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}