Christopher De Bank / SX1276Lib

pcb changes

Fork of SingleFrequencyLora by Christopher De Bank

sx1276/sx1276-hal.cpp@28:7cd527a4f931, 2017-12-01 (annotated)

Committer:
cdebank
Date:
Fri Dec 01 18:07:14 2017 +0000
Revision:
28:7cd527a4f931
Parent:
27:69b1750b2096 
pcb changes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 22:7f3aab69cca9 7 (C) 2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: -
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276-hal.h"
GregCr 0:e6ceb13d2d05 16
mluis 22:7f3aab69cca9 17 const RadioRegisters_t SX1276MB1xAS::RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE;
GregCr 0:e6ceb13d2d05 18
mluis 21:2e496deb7858 19 SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events,
GregCr 0:e6ceb13d2d05 20 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 21 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5,
GregCr 0:e6ceb13d2d05 22 PinName antSwitch )
mluis 21:2e496deb7858 23 : SX1276( events, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5 ),
mluis 26:d09a8ef807e2 24 AntSwitch( antSwitch ),
GregCr 12:aa5b3bf7fdf4 25 #if( defined ( TARGET_NUCLEO_L152RE ) )
mluis 26:d09a8ef807e2 26 Fake( D8 )
GregCr 12:aa5b3bf7fdf4 27 #else
mluis 26:d09a8ef807e2 28 Fake( A3 )
GregCr 0:e6ceb13d2d05 29 #endif
GregCr 0:e6ceb13d2d05 30 {
mluis 21:2e496deb7858 31 this->RadioEvents = events;
mluis 21:2e496deb7858 32
GregCr 0:e6ceb13d2d05 33 Reset( );
mluis 26:d09a8ef807e2 34
GregCr 0:e6ceb13d2d05 35 RxChainCalibration( );
mluis 26:d09a8ef807e2 36
GregCr 0:e6ceb13d2d05 37 IoInit( );
mluis 26:d09a8ef807e2 38
GregCr 0:e6ceb13d2d05 39 SetOpMode( RF_OPMODE_SLEEP );
mluis 26:d09a8ef807e2 40
GregCr 0:e6ceb13d2d05 41 IoIrqInit( dioIrq );
mluis 26:d09a8ef807e2 42
GregCr 0:e6ceb13d2d05 43 RadioRegistersInit( );
GregCr 0:e6ceb13d2d05 44
GregCr 0:e6ceb13d2d05 45 SetModem( MODEM_FSK );
GregCr 0:e6ceb13d2d05 46
mluis 21:2e496deb7858 47 this->settings.State = RF_IDLE ;
GregCr 0:e6ceb13d2d05 48 }
GregCr 0:e6ceb13d2d05 49
mluis 26:d09a8ef807e2 50 SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events )
GregCr 12:aa5b3bf7fdf4 51 #if defined ( TARGET_NUCLEO_L152RE )
mluis 21:2e496deb7858 52 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, A3, D9 ), // For NUCLEO L152RE dio4 is on port A3
mluis 26:d09a8ef807e2 53 AntSwitch( A4 ),
mluis 26:d09a8ef807e2 54 Fake( D8 )
mluis 20:e05596ba4166 55 #elif defined( TARGET_LPC11U6X )
mluis 21:2e496deb7858 56 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
mluis 26:d09a8ef807e2 57 AntSwitch( P0_23 ),
mluis 26:d09a8ef807e2 58 Fake( A3 )
GregCr 0:e6ceb13d2d05 59 #else
cdebank 28:7cd527a4f931 60 : SX1276( events, PB_5, PB_4, PB_3, PA_15, PB_6, PC_10, PB_8, PC_12, PC_11, PC_9, PC_8 ),
mluis 26:d09a8ef807e2 61 AntSwitch( A4 ),
mluis 26:d09a8ef807e2 62 Fake( A3 )
GregCr 0:e6ceb13d2d05 63 #endif
GregCr 0:e6ceb13d2d05 64 {
mluis 21:2e496deb7858 65 this->RadioEvents = events;
mluis 21:2e496deb7858 66
GregCr 0:e6ceb13d2d05 67 Reset( );
mluis 26:d09a8ef807e2 68
GregCr 5:11ec8a6ba4f0 69 boardConnected = UNKNOWN;
mluis 26:d09a8ef807e2 70
GregCr 1:f979673946c0 71 DetectBoardType( );
mluis 26:d09a8ef807e2 72
GregCr 0:e6ceb13d2d05 73 RxChainCalibration( );
mluis 26:d09a8ef807e2 74
GregCr 0:e6ceb13d2d05 75 IoInit( );
mluis 26:d09a8ef807e2 76
GregCr 0:e6ceb13d2d05 77 SetOpMode( RF_OPMODE_SLEEP );
GregCr 0:e6ceb13d2d05 78 IoIrqInit( dioIrq );
mluis 26:d09a8ef807e2 79
GregCr 0:e6ceb13d2d05 80 RadioRegistersInit( );
GregCr 0:e6ceb13d2d05 81
GregCr 0:e6ceb13d2d05 82 SetModem( MODEM_FSK );
GregCr 0:e6ceb13d2d05 83
mluis 21:2e496deb7858 84 this->settings.State = RF_IDLE ;
GregCr 0:e6ceb13d2d05 85 }
GregCr 0:e6ceb13d2d05 86
GregCr 0:e6ceb13d2d05 87 //-------------------------------------------------------------------------
GregCr 0:e6ceb13d2d05 88 // Board relative functions
GregCr 0:e6ceb13d2d05 89 //-------------------------------------------------------------------------
GregCr 2:5eb3066446dd 90 uint8_t SX1276MB1xAS::DetectBoardType( void )
GregCr 1:f979673946c0 91 {
GregCr 5:11ec8a6ba4f0 92 if( boardConnected == UNKNOWN )
GregCr 1:f979673946c0 93 {
mluis 26:d09a8ef807e2 94 this->AntSwitch.input( );
GregCr 5:11ec8a6ba4f0 95 wait_ms( 1 );
mluis 26:d09a8ef807e2 96 if( this->AntSwitch == 1 )
GregCr 5:11ec8a6ba4f0 97 {
GregCr 5:11ec8a6ba4f0 98 boardConnected = SX1276MB1LAS;
GregCr 5:11ec8a6ba4f0 99 }
GregCr 5:11ec8a6ba4f0 100 else
GregCr 5:11ec8a6ba4f0 101 {
GregCr 5:11ec8a6ba4f0 102 boardConnected = SX1276MB1MAS;
GregCr 5:11ec8a6ba4f0 103 }
mluis 26:d09a8ef807e2 104 this->AntSwitch.output( );
GregCr 5:11ec8a6ba4f0 105 wait_ms( 1 );
GregCr 1:f979673946c0 106 }
GregCr 2:5eb3066446dd 107 return ( boardConnected );
GregCr 1:f979673946c0 108 }
GregCr 0:e6ceb13d2d05 109
GregCr 0:e6ceb13d2d05 110 void SX1276MB1xAS::IoInit( void )
GregCr 0:e6ceb13d2d05 111 {
GregCr 0:e6ceb13d2d05 112 AntSwInit( );
GregCr 0:e6ceb13d2d05 113 SpiInit( );
GregCr 0:e6ceb13d2d05 114 }
GregCr 0:e6ceb13d2d05 115
mluis 22:7f3aab69cca9 116 void SX1276MB1xAS::RadioRegistersInit( )
mluis 22:7f3aab69cca9 117 {
GregCr 0:e6ceb13d2d05 118 uint8_t i = 0;
GregCr 0:e6ceb13d2d05 119 for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
GregCr 0:e6ceb13d2d05 120 {
GregCr 0:e6ceb13d2d05 121 SetModem( RadioRegsInit[i].Modem );
GregCr 0:e6ceb13d2d05 122 Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
GregCr 0:e6ceb13d2d05 123 }
GregCr 0:e6ceb13d2d05 124 }
GregCr 0:e6ceb13d2d05 125
GregCr 0:e6ceb13d2d05 126 void SX1276MB1xAS::SpiInit( void )
GregCr 0:e6ceb13d2d05 127 {
GregCr 0:e6ceb13d2d05 128 nss = 1;
GregCr 0:e6ceb13d2d05 129 spi.format( 8,0 );
GregCr 0:e6ceb13d2d05 130 uint32_t frequencyToSet = 8000000;
mluis 26:d09a8ef807e2 131 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) )
GregCr 0:e6ceb13d2d05 132 spi.frequency( frequencyToSet );
GregCr 0:e6ceb13d2d05 133 #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate
GregCr 0:e6ceb13d2d05 134 spi.frequency( frequencyToSet * 2 );
GregCr 0:e6ceb13d2d05 135 #else
GregCr 0:e6ceb13d2d05 136 #warning "Check the board's SPI frequency"
GregCr 0:e6ceb13d2d05 137 #endif
GregCr 0:e6ceb13d2d05 138 wait(0.1);
GregCr 0:e6ceb13d2d05 139 }
GregCr 0:e6ceb13d2d05 140
GregCr 0:e6ceb13d2d05 141 void SX1276MB1xAS::IoIrqInit( DioIrqHandler *irqHandlers )
GregCr 0:e6ceb13d2d05 142 {
mluis 26:d09a8ef807e2 143 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) )
mluis 26:d09a8ef807e2 144 dio0.mode( PullDown );
mluis 26:d09a8ef807e2 145 dio1.mode( PullDown );
mluis 26:d09a8ef807e2 146 dio2.mode( PullDown );
mluis 26:d09a8ef807e2 147 dio3.mode( PullDown );
mluis 26:d09a8ef807e2 148 dio4.mode( PullDown );
mluis 22:7f3aab69cca9 149 #endif
mluis 26:d09a8ef807e2 150 dio0.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[0] ) ) );
mluis 26:d09a8ef807e2 151 dio1.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[1] ) ) );
mluis 26:d09a8ef807e2 152 dio2.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[2] ) ) );
mluis 26:d09a8ef807e2 153 dio3.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[3] ) ) );
mluis 26:d09a8ef807e2 154 dio4.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[4] ) ) );
GregCr 0:e6ceb13d2d05 155 }
GregCr 0:e6ceb13d2d05 156
GregCr 0:e6ceb13d2d05 157 void SX1276MB1xAS::IoDeInit( void )
GregCr 0:e6ceb13d2d05 158 {
GregCr 0:e6ceb13d2d05 159 //nothing
GregCr 0:e6ceb13d2d05 160 }
GregCr 0:e6ceb13d2d05 161
mluis 26:d09a8ef807e2 162 void SX1276MB1xAS::SetRfTxPower( int8_t power )
mluis 26:d09a8ef807e2 163 {
mluis 26:d09a8ef807e2 164 uint8_t paConfig = 0;
mluis 26:d09a8ef807e2 165 uint8_t paDac = 0;
mluis 26:d09a8ef807e2 166
mluis 26:d09a8ef807e2 167 paConfig = Read( REG_PACONFIG );
mluis 26:d09a8ef807e2 168 paDac = Read( REG_PADAC );
mluis 26:d09a8ef807e2 169
mluis 26:d09a8ef807e2 170 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
mluis 26:d09a8ef807e2 171 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
mluis 26:d09a8ef807e2 172
mluis 26:d09a8ef807e2 173 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
mluis 26:d09a8ef807e2 174 {
mluis 26:d09a8ef807e2 175 if( power > 17 )
mluis 26:d09a8ef807e2 176 {
mluis 26:d09a8ef807e2 177 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
mluis 26:d09a8ef807e2 178 }
mluis 26:d09a8ef807e2 179 else
mluis 26:d09a8ef807e2 180 {
mluis 26:d09a8ef807e2 181 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
mluis 26:d09a8ef807e2 182 }
mluis 26:d09a8ef807e2 183 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
mluis 26:d09a8ef807e2 184 {
mluis 26:d09a8ef807e2 185 if( power < 5 )
mluis 26:d09a8ef807e2 186 {
mluis 26:d09a8ef807e2 187 power = 5;
mluis 26:d09a8ef807e2 188 }
mluis 26:d09a8ef807e2 189 if( power > 20 )
mluis 26:d09a8ef807e2 190 {
mluis 26:d09a8ef807e2 191 power = 20;
mluis 26:d09a8ef807e2 192 }
mluis 26:d09a8ef807e2 193 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
mluis 26:d09a8ef807e2 194 }
mluis 26:d09a8ef807e2 195 else
mluis 26:d09a8ef807e2 196 {
mluis 26:d09a8ef807e2 197 if( power < 2 )
mluis 26:d09a8ef807e2 198 {
mluis 26:d09a8ef807e2 199 power = 2;
mluis 26:d09a8ef807e2 200 }
mluis 26:d09a8ef807e2 201 if( power > 17 )
mluis 26:d09a8ef807e2 202 {
mluis 26:d09a8ef807e2 203 power = 17;
mluis 26:d09a8ef807e2 204 }
mluis 26:d09a8ef807e2 205 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
mluis 26:d09a8ef807e2 206 }
mluis 26:d09a8ef807e2 207 }
mluis 26:d09a8ef807e2 208 else
mluis 26:d09a8ef807e2 209 {
mluis 26:d09a8ef807e2 210 if( power < -1 )
mluis 26:d09a8ef807e2 211 {
mluis 26:d09a8ef807e2 212 power = -1;
mluis 26:d09a8ef807e2 213 }
mluis 26:d09a8ef807e2 214 if( power > 14 )
mluis 26:d09a8ef807e2 215 {
mluis 26:d09a8ef807e2 216 power = 14;
mluis 26:d09a8ef807e2 217 }
mluis 26:d09a8ef807e2 218 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
mluis 26:d09a8ef807e2 219 }
mluis 26:d09a8ef807e2 220 Write( REG_PACONFIG, paConfig );
mluis 26:d09a8ef807e2 221 Write( REG_PADAC, paDac );
mluis 26:d09a8ef807e2 222 }
mluis 26:d09a8ef807e2 223
GregCr 0:e6ceb13d2d05 224 uint8_t SX1276MB1xAS::GetPaSelect( uint32_t channel )
GregCr 0:e6ceb13d2d05 225 {
GregCr 0:e6ceb13d2d05 226 if( channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 227 {
GregCr 3:ca84be1f3fac 228 if( boardConnected == SX1276MB1LAS )
GregCr 1:f979673946c0 229 {
GregCr 1:f979673946c0 230 return RF_PACONFIG_PASELECT_PABOOST;
GregCr 1:f979673946c0 231 }
GregCr 1:f979673946c0 232 else
GregCr 1:f979673946c0 233 {
GregCr 1:f979673946c0 234 return RF_PACONFIG_PASELECT_RFO;
GregCr 1:f979673946c0 235 }
GregCr 0:e6ceb13d2d05 236 }
GregCr 0:e6ceb13d2d05 237 else
GregCr 0:e6ceb13d2d05 238 {
GregCr 0:e6ceb13d2d05 239 return RF_PACONFIG_PASELECT_RFO;
GregCr 0:e6ceb13d2d05 240 }
GregCr 0:e6ceb13d2d05 241 }
GregCr 0:e6ceb13d2d05 242
GregCr 0:e6ceb13d2d05 243 void SX1276MB1xAS::SetAntSwLowPower( bool status )
GregCr 0:e6ceb13d2d05 244 {
GregCr 0:e6ceb13d2d05 245 if( isRadioActive != status )
GregCr 0:e6ceb13d2d05 246 {
GregCr 0:e6ceb13d2d05 247 isRadioActive = status;
GregCr 0:e6ceb13d2d05 248
GregCr 0:e6ceb13d2d05 249 if( status == false )
GregCr 0:e6ceb13d2d05 250 {
GregCr 0:e6ceb13d2d05 251 AntSwInit( );
GregCr 0:e6ceb13d2d05 252 }
GregCr 0:e6ceb13d2d05 253 else
GregCr 0:e6ceb13d2d05 254 {
GregCr 0:e6ceb13d2d05 255 AntSwDeInit( );
GregCr 0:e6ceb13d2d05 256 }
GregCr 0:e6ceb13d2d05 257 }
GregCr 0:e6ceb13d2d05 258 }
GregCr 0:e6ceb13d2d05 259
GregCr 0:e6ceb13d2d05 260 void SX1276MB1xAS::AntSwInit( void )
GregCr 0:e6ceb13d2d05 261 {
mluis 26:d09a8ef807e2 262 this->AntSwitch = 0;
GregCr 0:e6ceb13d2d05 263 }
GregCr 0:e6ceb13d2d05 264
GregCr 0:e6ceb13d2d05 265 void SX1276MB1xAS::AntSwDeInit( void )
GregCr 0:e6ceb13d2d05 266 {
mluis 26:d09a8ef807e2 267 this->AntSwitch = 0;
GregCr 0:e6ceb13d2d05 268 }
GregCr 0:e6ceb13d2d05 269
mluis 26:d09a8ef807e2 270 void SX1276MB1xAS::SetAntSw( uint8_t opMode )
GregCr 0:e6ceb13d2d05 271 {
mluis 26:d09a8ef807e2 272 switch( opMode )
GregCr 0:e6ceb13d2d05 273 {
mluis 26:d09a8ef807e2 274 case RFLR_OPMODE_TRANSMITTER:
mluis 26:d09a8ef807e2 275 this->AntSwitch = 1;
mluis 26:d09a8ef807e2 276 break;
mluis 26:d09a8ef807e2 277 case RFLR_OPMODE_RECEIVER:
mluis 26:d09a8ef807e2 278 case RFLR_OPMODE_RECEIVER_SINGLE:
mluis 26:d09a8ef807e2 279 case RFLR_OPMODE_CAD:
mluis 26:d09a8ef807e2 280 this->AntSwitch = 0;
mluis 26:d09a8ef807e2 281 break;
mluis 26:d09a8ef807e2 282 default:
mluis 26:d09a8ef807e2 283 this->AntSwitch = 0;
mluis 26:d09a8ef807e2 284 break;
GregCr 0:e6ceb13d2d05 285 }
GregCr 0:e6ceb13d2d05 286 }
GregCr 0:e6ceb13d2d05 287
GregCr 0:e6ceb13d2d05 288 bool SX1276MB1xAS::CheckRfFrequency( uint32_t frequency )
GregCr 0:e6ceb13d2d05 289 {
mluis 26:d09a8ef807e2 290 // Implement check. Currently all frequencies are supported
GregCr 0:e6ceb13d2d05 291 return true;
GregCr 0:e6ceb13d2d05 292 }
GregCr 0:e6ceb13d2d05 293
GregCr 0:e6ceb13d2d05 294 void SX1276MB1xAS::Reset( void )
GregCr 0:e6ceb13d2d05 295 {
mluis 26:d09a8ef807e2 296 reset.output( );
GregCr 0:e6ceb13d2d05 297 reset = 0;
GregCr 0:e6ceb13d2d05 298 wait_ms( 1 );
mluis 26:d09a8ef807e2 299 reset.input( );
GregCr 0:e6ceb13d2d05 300 wait_ms( 6 );
GregCr 0:e6ceb13d2d05 301 }
mluis 26:d09a8ef807e2 302
GregCr 0:e6ceb13d2d05 303 void SX1276MB1xAS::Write( uint8_t addr, uint8_t data )
GregCr 0:e6ceb13d2d05 304 {
GregCr 0:e6ceb13d2d05 305 Write( addr, &data, 1 );
GregCr 0:e6ceb13d2d05 306 }
GregCr 0:e6ceb13d2d05 307
GregCr 0:e6ceb13d2d05 308 uint8_t SX1276MB1xAS::Read( uint8_t addr )
GregCr 0:e6ceb13d2d05 309 {
GregCr 0:e6ceb13d2d05 310 uint8_t data;
GregCr 0:e6ceb13d2d05 311 Read( addr, &data, 1 );
GregCr 0:e6ceb13d2d05 312 return data;
GregCr 0:e6ceb13d2d05 313 }
GregCr 0:e6ceb13d2d05 314
GregCr 0:e6ceb13d2d05 315 void SX1276MB1xAS::Write( uint8_t addr, uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 316 {
GregCr 0:e6ceb13d2d05 317 uint8_t i;
GregCr 0:e6ceb13d2d05 318
GregCr 0:e6ceb13d2d05 319 nss = 0;
GregCr 0:e6ceb13d2d05 320 spi.write( addr | 0x80 );
GregCr 0:e6ceb13d2d05 321 for( i = 0; i < size; i++ )
GregCr 0:e6ceb13d2d05 322 {
GregCr 0:e6ceb13d2d05 323 spi.write( buffer[i] );
GregCr 0:e6ceb13d2d05 324 }
GregCr 0:e6ceb13d2d05 325 nss = 1;
GregCr 0:e6ceb13d2d05 326 }
GregCr 0:e6ceb13d2d05 327
GregCr 0:e6ceb13d2d05 328 void SX1276MB1xAS::Read( uint8_t addr, uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 329 {
GregCr 0:e6ceb13d2d05 330 uint8_t i;
GregCr 0:e6ceb13d2d05 331
GregCr 0:e6ceb13d2d05 332 nss = 0;
GregCr 0:e6ceb13d2d05 333 spi.write( addr & 0x7F );
GregCr 0:e6ceb13d2d05 334 for( i = 0; i < size; i++ )
GregCr 0:e6ceb13d2d05 335 {
GregCr 0:e6ceb13d2d05 336 buffer[i] = spi.write( 0 );
GregCr 0:e6ceb13d2d05 337 }
GregCr 0:e6ceb13d2d05 338 nss = 1;
GregCr 0:e6ceb13d2d05 339 }
GregCr 0:e6ceb13d2d05 340
GregCr 0:e6ceb13d2d05 341 void SX1276MB1xAS::WriteFifo( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 342 {
GregCr 0:e6ceb13d2d05 343 Write( 0, buffer, size );
GregCr 0:e6ceb13d2d05 344 }
GregCr 0:e6ceb13d2d05 345
GregCr 0:e6ceb13d2d05 346 void SX1276MB1xAS::ReadFifo( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 347 {
GregCr 0:e6ceb13d2d05 348 Read( 0, buffer, size );
GregCr 0:e6ceb13d2d05 349 }