pcb changes

Fork of SingleFrequencyLora by Christopher De Bank

Committer:
cdebank
Date:
Fri Dec 01 18:07:14 2017 +0000
Revision:
28:7cd527a4f931
Parent:
26:d09a8ef807e2
pcb changes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 22:7f3aab69cca9 7 (C) 2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: SX1276 FSK modem registers and bits definitions
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainer: Miguel Luis and Gregory Cristian
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #ifndef __SX1276_REGS_FSK_H__
GregCr 0:e6ceb13d2d05 16 #define __SX1276_REGS_FSK_H__
GregCr 0:e6ceb13d2d05 17
GregCr 0:e6ceb13d2d05 18 /*!
GregCr 0:e6ceb13d2d05 19 * ============================================================================
GregCr 0:e6ceb13d2d05 20 * SX1276 Internal registers Address
GregCr 0:e6ceb13d2d05 21 * ============================================================================
GregCr 0:e6ceb13d2d05 22 */
GregCr 0:e6ceb13d2d05 23 #define REG_FIFO 0x00
GregCr 0:e6ceb13d2d05 24 // Common settings
GregCr 0:e6ceb13d2d05 25 #define REG_OPMODE 0x01
GregCr 0:e6ceb13d2d05 26 #define REG_BITRATEMSB 0x02
GregCr 0:e6ceb13d2d05 27 #define REG_BITRATELSB 0x03
GregCr 0:e6ceb13d2d05 28 #define REG_FDEVMSB 0x04
GregCr 0:e6ceb13d2d05 29 #define REG_FDEVLSB 0x05
GregCr 0:e6ceb13d2d05 30 #define REG_FRFMSB 0x06
GregCr 0:e6ceb13d2d05 31 #define REG_FRFMID 0x07
GregCr 0:e6ceb13d2d05 32 #define REG_FRFLSB 0x08
GregCr 0:e6ceb13d2d05 33 // Tx settings
GregCr 0:e6ceb13d2d05 34 #define REG_PACONFIG 0x09
GregCr 0:e6ceb13d2d05 35 #define REG_PARAMP 0x0A
GregCr 0:e6ceb13d2d05 36 #define REG_OCP 0x0B
GregCr 0:e6ceb13d2d05 37 // Rx settings
GregCr 0:e6ceb13d2d05 38 #define REG_LNA 0x0C
GregCr 0:e6ceb13d2d05 39 #define REG_RXCONFIG 0x0D
GregCr 0:e6ceb13d2d05 40 #define REG_RSSICONFIG 0x0E
GregCr 0:e6ceb13d2d05 41 #define REG_RSSICOLLISION 0x0F
GregCr 0:e6ceb13d2d05 42 #define REG_RSSITHRESH 0x10
GregCr 0:e6ceb13d2d05 43 #define REG_RSSIVALUE 0x11
GregCr 0:e6ceb13d2d05 44 #define REG_RXBW 0x12
GregCr 0:e6ceb13d2d05 45 #define REG_AFCBW 0x13
GregCr 0:e6ceb13d2d05 46 #define REG_OOKPEAK 0x14
GregCr 0:e6ceb13d2d05 47 #define REG_OOKFIX 0x15
GregCr 0:e6ceb13d2d05 48 #define REG_OOKAVG 0x16
GregCr 0:e6ceb13d2d05 49 #define REG_RES17 0x17
GregCr 0:e6ceb13d2d05 50 #define REG_RES18 0x18
GregCr 0:e6ceb13d2d05 51 #define REG_RES19 0x19
GregCr 0:e6ceb13d2d05 52 #define REG_AFCFEI 0x1A
GregCr 0:e6ceb13d2d05 53 #define REG_AFCMSB 0x1B
GregCr 0:e6ceb13d2d05 54 #define REG_AFCLSB 0x1C
GregCr 0:e6ceb13d2d05 55 #define REG_FEIMSB 0x1D
GregCr 0:e6ceb13d2d05 56 #define REG_FEILSB 0x1E
GregCr 0:e6ceb13d2d05 57 #define REG_PREAMBLEDETECT 0x1F
GregCr 0:e6ceb13d2d05 58 #define REG_RXTIMEOUT1 0x20
GregCr 0:e6ceb13d2d05 59 #define REG_RXTIMEOUT2 0x21
GregCr 0:e6ceb13d2d05 60 #define REG_RXTIMEOUT3 0x22
GregCr 0:e6ceb13d2d05 61 #define REG_RXDELAY 0x23
GregCr 0:e6ceb13d2d05 62 // Oscillator settings
GregCr 0:e6ceb13d2d05 63 #define REG_OSC 0x24
GregCr 0:e6ceb13d2d05 64 // Packet handler settings
GregCr 0:e6ceb13d2d05 65 #define REG_PREAMBLEMSB 0x25
GregCr 0:e6ceb13d2d05 66 #define REG_PREAMBLELSB 0x26
GregCr 0:e6ceb13d2d05 67 #define REG_SYNCCONFIG 0x27
GregCr 0:e6ceb13d2d05 68 #define REG_SYNCVALUE1 0x28
GregCr 0:e6ceb13d2d05 69 #define REG_SYNCVALUE2 0x29
GregCr 0:e6ceb13d2d05 70 #define REG_SYNCVALUE3 0x2A
GregCr 0:e6ceb13d2d05 71 #define REG_SYNCVALUE4 0x2B
GregCr 0:e6ceb13d2d05 72 #define REG_SYNCVALUE5 0x2C
GregCr 0:e6ceb13d2d05 73 #define REG_SYNCVALUE6 0x2D
GregCr 0:e6ceb13d2d05 74 #define REG_SYNCVALUE7 0x2E
GregCr 0:e6ceb13d2d05 75 #define REG_SYNCVALUE8 0x2F
GregCr 0:e6ceb13d2d05 76 #define REG_PACKETCONFIG1 0x30
GregCr 0:e6ceb13d2d05 77 #define REG_PACKETCONFIG2 0x31
GregCr 0:e6ceb13d2d05 78 #define REG_PAYLOADLENGTH 0x32
GregCr 0:e6ceb13d2d05 79 #define REG_NODEADRS 0x33
GregCr 0:e6ceb13d2d05 80 #define REG_BROADCASTADRS 0x34
GregCr 0:e6ceb13d2d05 81 #define REG_FIFOTHRESH 0x35
GregCr 0:e6ceb13d2d05 82 // SM settings
GregCr 0:e6ceb13d2d05 83 #define REG_SEQCONFIG1 0x36
GregCr 0:e6ceb13d2d05 84 #define REG_SEQCONFIG2 0x37
GregCr 0:e6ceb13d2d05 85 #define REG_TIMERRESOL 0x38
GregCr 0:e6ceb13d2d05 86 #define REG_TIMER1COEF 0x39
GregCr 0:e6ceb13d2d05 87 #define REG_TIMER2COEF 0x3A
GregCr 0:e6ceb13d2d05 88 // Service settings
GregCr 0:e6ceb13d2d05 89 #define REG_IMAGECAL 0x3B
GregCr 0:e6ceb13d2d05 90 #define REG_TEMP 0x3C
GregCr 0:e6ceb13d2d05 91 #define REG_LOWBAT 0x3D
GregCr 0:e6ceb13d2d05 92 // Status
GregCr 0:e6ceb13d2d05 93 #define REG_IRQFLAGS1 0x3E
GregCr 0:e6ceb13d2d05 94 #define REG_IRQFLAGS2 0x3F
GregCr 0:e6ceb13d2d05 95 // I/O settings
GregCr 0:e6ceb13d2d05 96 #define REG_DIOMAPPING1 0x40
GregCr 0:e6ceb13d2d05 97 #define REG_DIOMAPPING2 0x41
GregCr 0:e6ceb13d2d05 98 // Version
GregCr 0:e6ceb13d2d05 99 #define REG_VERSION 0x42
GregCr 0:e6ceb13d2d05 100 // Additional settings
GregCr 0:e6ceb13d2d05 101 #define REG_PLLHOP 0x44
GregCr 0:e6ceb13d2d05 102 #define REG_TCXO 0x4B
GregCr 0:e6ceb13d2d05 103 #define REG_PADAC 0x4D
GregCr 0:e6ceb13d2d05 104 #define REG_FORMERTEMP 0x5B
GregCr 0:e6ceb13d2d05 105 #define REG_BITRATEFRAC 0x5D
GregCr 0:e6ceb13d2d05 106 #define REG_AGCREF 0x61
GregCr 0:e6ceb13d2d05 107 #define REG_AGCTHRESH1 0x62
GregCr 0:e6ceb13d2d05 108 #define REG_AGCTHRESH2 0x63
GregCr 0:e6ceb13d2d05 109 #define REG_AGCTHRESH3 0x64
GregCr 0:e6ceb13d2d05 110 #define REG_PLL 0x70
GregCr 0:e6ceb13d2d05 111
GregCr 0:e6ceb13d2d05 112 /*!
GregCr 0:e6ceb13d2d05 113 * ============================================================================
GregCr 0:e6ceb13d2d05 114 * SX1276 FSK bits control definition
GregCr 0:e6ceb13d2d05 115 * ============================================================================
GregCr 0:e6ceb13d2d05 116 */
GregCr 0:e6ceb13d2d05 117
GregCr 0:e6ceb13d2d05 118 /*!
GregCr 0:e6ceb13d2d05 119 * RegFifo
GregCr 0:e6ceb13d2d05 120 */
GregCr 0:e6ceb13d2d05 121
GregCr 0:e6ceb13d2d05 122 /*!
GregCr 0:e6ceb13d2d05 123 * RegOpMode
GregCr 0:e6ceb13d2d05 124 */
GregCr 0:e6ceb13d2d05 125 #define RF_OPMODE_LONGRANGEMODE_MASK 0x7F
GregCr 0:e6ceb13d2d05 126 #define RF_OPMODE_LONGRANGEMODE_OFF 0x00
GregCr 0:e6ceb13d2d05 127 #define RF_OPMODE_LONGRANGEMODE_ON 0x80
GregCr 0:e6ceb13d2d05 128
GregCr 0:e6ceb13d2d05 129 #define RF_OPMODE_MODULATIONTYPE_MASK 0x9F
GregCr 0:e6ceb13d2d05 130 #define RF_OPMODE_MODULATIONTYPE_FSK 0x00 // Default
GregCr 0:e6ceb13d2d05 131 #define RF_OPMODE_MODULATIONTYPE_OOK 0x20
GregCr 0:e6ceb13d2d05 132
GregCr 0:e6ceb13d2d05 133 #define RF_OPMODE_MODULATIONSHAPING_MASK 0xE7
GregCr 0:e6ceb13d2d05 134 #define RF_OPMODE_MODULATIONSHAPING_00 0x00 // Default
GregCr 0:e6ceb13d2d05 135 #define RF_OPMODE_MODULATIONSHAPING_01 0x08
GregCr 0:e6ceb13d2d05 136 #define RF_OPMODE_MODULATIONSHAPING_10 0x10
GregCr 0:e6ceb13d2d05 137 #define RF_OPMODE_MODULATIONSHAPING_11 0x18
GregCr 0:e6ceb13d2d05 138
GregCr 0:e6ceb13d2d05 139 #define RF_OPMODE_MASK 0xF8
GregCr 0:e6ceb13d2d05 140 #define RF_OPMODE_SLEEP 0x00
GregCr 0:e6ceb13d2d05 141 #define RF_OPMODE_STANDBY 0x01 // Default
GregCr 0:e6ceb13d2d05 142 #define RF_OPMODE_SYNTHESIZER_TX 0x02
GregCr 0:e6ceb13d2d05 143 #define RF_OPMODE_TRANSMITTER 0x03
GregCr 0:e6ceb13d2d05 144 #define RF_OPMODE_SYNTHESIZER_RX 0x04
GregCr 0:e6ceb13d2d05 145 #define RF_OPMODE_RECEIVER 0x05
GregCr 0:e6ceb13d2d05 146
GregCr 0:e6ceb13d2d05 147 /*!
mluis 22:7f3aab69cca9 148 * RegBitRate (bits/sec)
GregCr 0:e6ceb13d2d05 149 */
GregCr 0:e6ceb13d2d05 150 #define RF_BITRATEMSB_1200_BPS 0x68
GregCr 0:e6ceb13d2d05 151 #define RF_BITRATELSB_1200_BPS 0x2B
GregCr 0:e6ceb13d2d05 152 #define RF_BITRATEMSB_2400_BPS 0x34
GregCr 0:e6ceb13d2d05 153 #define RF_BITRATELSB_2400_BPS 0x15
GregCr 0:e6ceb13d2d05 154 #define RF_BITRATEMSB_4800_BPS 0x1A // Default
GregCr 0:e6ceb13d2d05 155 #define RF_BITRATELSB_4800_BPS 0x0B // Default
GregCr 0:e6ceb13d2d05 156 #define RF_BITRATEMSB_9600_BPS 0x0D
GregCr 0:e6ceb13d2d05 157 #define RF_BITRATELSB_9600_BPS 0x05
GregCr 0:e6ceb13d2d05 158 #define RF_BITRATEMSB_15000_BPS 0x08
GregCr 0:e6ceb13d2d05 159 #define RF_BITRATELSB_15000_BPS 0x55
GregCr 0:e6ceb13d2d05 160 #define RF_BITRATEMSB_19200_BPS 0x06
GregCr 0:e6ceb13d2d05 161 #define RF_BITRATELSB_19200_BPS 0x83
GregCr 0:e6ceb13d2d05 162 #define RF_BITRATEMSB_38400_BPS 0x03
GregCr 0:e6ceb13d2d05 163 #define RF_BITRATELSB_38400_BPS 0x41
GregCr 0:e6ceb13d2d05 164 #define RF_BITRATEMSB_76800_BPS 0x01
GregCr 0:e6ceb13d2d05 165 #define RF_BITRATELSB_76800_BPS 0xA1
GregCr 0:e6ceb13d2d05 166 #define RF_BITRATEMSB_153600_BPS 0x00
GregCr 0:e6ceb13d2d05 167 #define RF_BITRATELSB_153600_BPS 0xD0
GregCr 0:e6ceb13d2d05 168 #define RF_BITRATEMSB_57600_BPS 0x02
GregCr 0:e6ceb13d2d05 169 #define RF_BITRATELSB_57600_BPS 0x2C
GregCr 0:e6ceb13d2d05 170 #define RF_BITRATEMSB_115200_BPS 0x01
GregCr 0:e6ceb13d2d05 171 #define RF_BITRATELSB_115200_BPS 0x16
GregCr 0:e6ceb13d2d05 172 #define RF_BITRATEMSB_12500_BPS 0x0A
GregCr 0:e6ceb13d2d05 173 #define RF_BITRATELSB_12500_BPS 0x00
GregCr 0:e6ceb13d2d05 174 #define RF_BITRATEMSB_25000_BPS 0x05
GregCr 0:e6ceb13d2d05 175 #define RF_BITRATELSB_25000_BPS 0x00
GregCr 0:e6ceb13d2d05 176 #define RF_BITRATEMSB_50000_BPS 0x02
GregCr 0:e6ceb13d2d05 177 #define RF_BITRATELSB_50000_BPS 0x80
GregCr 0:e6ceb13d2d05 178 #define RF_BITRATEMSB_100000_BPS 0x01
GregCr 0:e6ceb13d2d05 179 #define RF_BITRATELSB_100000_BPS 0x40
GregCr 0:e6ceb13d2d05 180 #define RF_BITRATEMSB_150000_BPS 0x00
GregCr 0:e6ceb13d2d05 181 #define RF_BITRATELSB_150000_BPS 0xD5
GregCr 0:e6ceb13d2d05 182 #define RF_BITRATEMSB_200000_BPS 0x00
GregCr 0:e6ceb13d2d05 183 #define RF_BITRATELSB_200000_BPS 0xA0
GregCr 0:e6ceb13d2d05 184 #define RF_BITRATEMSB_250000_BPS 0x00
GregCr 0:e6ceb13d2d05 185 #define RF_BITRATELSB_250000_BPS 0x80
GregCr 0:e6ceb13d2d05 186 #define RF_BITRATEMSB_32768_BPS 0x03
GregCr 0:e6ceb13d2d05 187 #define RF_BITRATELSB_32768_BPS 0xD1
GregCr 0:e6ceb13d2d05 188
GregCr 0:e6ceb13d2d05 189 /*!
mluis 22:7f3aab69cca9 190 * RegFdev (Hz)
GregCr 0:e6ceb13d2d05 191 */
GregCr 0:e6ceb13d2d05 192 #define RF_FDEVMSB_2000_HZ 0x00
GregCr 0:e6ceb13d2d05 193 #define RF_FDEVLSB_2000_HZ 0x21
GregCr 0:e6ceb13d2d05 194 #define RF_FDEVMSB_5000_HZ 0x00 // Default
GregCr 0:e6ceb13d2d05 195 #define RF_FDEVLSB_5000_HZ 0x52 // Default
GregCr 0:e6ceb13d2d05 196 #define RF_FDEVMSB_10000_HZ 0x00
GregCr 0:e6ceb13d2d05 197 #define RF_FDEVLSB_10000_HZ 0xA4
GregCr 0:e6ceb13d2d05 198 #define RF_FDEVMSB_15000_HZ 0x00
GregCr 0:e6ceb13d2d05 199 #define RF_FDEVLSB_15000_HZ 0xF6
GregCr 0:e6ceb13d2d05 200 #define RF_FDEVMSB_20000_HZ 0x01
GregCr 0:e6ceb13d2d05 201 #define RF_FDEVLSB_20000_HZ 0x48
GregCr 0:e6ceb13d2d05 202 #define RF_FDEVMSB_25000_HZ 0x01
GregCr 0:e6ceb13d2d05 203 #define RF_FDEVLSB_25000_HZ 0x9A
GregCr 0:e6ceb13d2d05 204 #define RF_FDEVMSB_30000_HZ 0x01
GregCr 0:e6ceb13d2d05 205 #define RF_FDEVLSB_30000_HZ 0xEC
GregCr 0:e6ceb13d2d05 206 #define RF_FDEVMSB_35000_HZ 0x02
GregCr 0:e6ceb13d2d05 207 #define RF_FDEVLSB_35000_HZ 0x3D
GregCr 0:e6ceb13d2d05 208 #define RF_FDEVMSB_40000_HZ 0x02
GregCr 0:e6ceb13d2d05 209 #define RF_FDEVLSB_40000_HZ 0x8F
GregCr 0:e6ceb13d2d05 210 #define RF_FDEVMSB_45000_HZ 0x02
GregCr 0:e6ceb13d2d05 211 #define RF_FDEVLSB_45000_HZ 0xE1
GregCr 0:e6ceb13d2d05 212 #define RF_FDEVMSB_50000_HZ 0x03
GregCr 0:e6ceb13d2d05 213 #define RF_FDEVLSB_50000_HZ 0x33
GregCr 0:e6ceb13d2d05 214 #define RF_FDEVMSB_55000_HZ 0x03
GregCr 0:e6ceb13d2d05 215 #define RF_FDEVLSB_55000_HZ 0x85
GregCr 0:e6ceb13d2d05 216 #define RF_FDEVMSB_60000_HZ 0x03
GregCr 0:e6ceb13d2d05 217 #define RF_FDEVLSB_60000_HZ 0xD7
GregCr 0:e6ceb13d2d05 218 #define RF_FDEVMSB_65000_HZ 0x04
GregCr 0:e6ceb13d2d05 219 #define RF_FDEVLSB_65000_HZ 0x29
GregCr 0:e6ceb13d2d05 220 #define RF_FDEVMSB_70000_HZ 0x04
GregCr 0:e6ceb13d2d05 221 #define RF_FDEVLSB_70000_HZ 0x7B
GregCr 0:e6ceb13d2d05 222 #define RF_FDEVMSB_75000_HZ 0x04
GregCr 0:e6ceb13d2d05 223 #define RF_FDEVLSB_75000_HZ 0xCD
GregCr 0:e6ceb13d2d05 224 #define RF_FDEVMSB_80000_HZ 0x05
GregCr 0:e6ceb13d2d05 225 #define RF_FDEVLSB_80000_HZ 0x1F
GregCr 0:e6ceb13d2d05 226 #define RF_FDEVMSB_85000_HZ 0x05
GregCr 0:e6ceb13d2d05 227 #define RF_FDEVLSB_85000_HZ 0x71
GregCr 0:e6ceb13d2d05 228 #define RF_FDEVMSB_90000_HZ 0x05
GregCr 0:e6ceb13d2d05 229 #define RF_FDEVLSB_90000_HZ 0xC3
GregCr 0:e6ceb13d2d05 230 #define RF_FDEVMSB_95000_HZ 0x06
GregCr 0:e6ceb13d2d05 231 #define RF_FDEVLSB_95000_HZ 0x14
GregCr 0:e6ceb13d2d05 232 #define RF_FDEVMSB_100000_HZ 0x06
GregCr 0:e6ceb13d2d05 233 #define RF_FDEVLSB_100000_HZ 0x66
GregCr 0:e6ceb13d2d05 234 #define RF_FDEVMSB_110000_HZ 0x07
GregCr 0:e6ceb13d2d05 235 #define RF_FDEVLSB_110000_HZ 0x0A
GregCr 0:e6ceb13d2d05 236 #define RF_FDEVMSB_120000_HZ 0x07
GregCr 0:e6ceb13d2d05 237 #define RF_FDEVLSB_120000_HZ 0xAE
GregCr 0:e6ceb13d2d05 238 #define RF_FDEVMSB_130000_HZ 0x08
GregCr 0:e6ceb13d2d05 239 #define RF_FDEVLSB_130000_HZ 0x52
GregCr 0:e6ceb13d2d05 240 #define RF_FDEVMSB_140000_HZ 0x08
GregCr 0:e6ceb13d2d05 241 #define RF_FDEVLSB_140000_HZ 0xF6
GregCr 0:e6ceb13d2d05 242 #define RF_FDEVMSB_150000_HZ 0x09
GregCr 0:e6ceb13d2d05 243 #define RF_FDEVLSB_150000_HZ 0x9A
GregCr 0:e6ceb13d2d05 244 #define RF_FDEVMSB_160000_HZ 0x0A
GregCr 0:e6ceb13d2d05 245 #define RF_FDEVLSB_160000_HZ 0x3D
GregCr 0:e6ceb13d2d05 246 #define RF_FDEVMSB_170000_HZ 0x0A
GregCr 0:e6ceb13d2d05 247 #define RF_FDEVLSB_170000_HZ 0xE1
GregCr 0:e6ceb13d2d05 248 #define RF_FDEVMSB_180000_HZ 0x0B
GregCr 0:e6ceb13d2d05 249 #define RF_FDEVLSB_180000_HZ 0x85
GregCr 0:e6ceb13d2d05 250 #define RF_FDEVMSB_190000_HZ 0x0C
GregCr 0:e6ceb13d2d05 251 #define RF_FDEVLSB_190000_HZ 0x29
GregCr 0:e6ceb13d2d05 252 #define RF_FDEVMSB_200000_HZ 0x0C
GregCr 0:e6ceb13d2d05 253 #define RF_FDEVLSB_200000_HZ 0xCD
GregCr 0:e6ceb13d2d05 254
GregCr 0:e6ceb13d2d05 255 /*!
mluis 22:7f3aab69cca9 256 * RegFrf (MHz)
GregCr 0:e6ceb13d2d05 257 */
GregCr 0:e6ceb13d2d05 258 #define RF_FRFMSB_863_MHZ 0xD7
GregCr 0:e6ceb13d2d05 259 #define RF_FRFMID_863_MHZ 0xC0
GregCr 0:e6ceb13d2d05 260 #define RF_FRFLSB_863_MHZ 0x00
GregCr 0:e6ceb13d2d05 261 #define RF_FRFMSB_864_MHZ 0xD8
GregCr 0:e6ceb13d2d05 262 #define RF_FRFMID_864_MHZ 0x00
GregCr 0:e6ceb13d2d05 263 #define RF_FRFLSB_864_MHZ 0x00
GregCr 0:e6ceb13d2d05 264 #define RF_FRFMSB_865_MHZ 0xD8
GregCr 0:e6ceb13d2d05 265 #define RF_FRFMID_865_MHZ 0x40
GregCr 0:e6ceb13d2d05 266 #define RF_FRFLSB_865_MHZ 0x00
GregCr 0:e6ceb13d2d05 267 #define RF_FRFMSB_866_MHZ 0xD8
GregCr 0:e6ceb13d2d05 268 #define RF_FRFMID_866_MHZ 0x80
GregCr 0:e6ceb13d2d05 269 #define RF_FRFLSB_866_MHZ 0x00
GregCr 0:e6ceb13d2d05 270 #define RF_FRFMSB_867_MHZ 0xD8
GregCr 0:e6ceb13d2d05 271 #define RF_FRFMID_867_MHZ 0xC0
GregCr 0:e6ceb13d2d05 272 #define RF_FRFLSB_867_MHZ 0x00
GregCr 0:e6ceb13d2d05 273 #define RF_FRFMSB_868_MHZ 0xD9
GregCr 0:e6ceb13d2d05 274 #define RF_FRFMID_868_MHZ 0x00
GregCr 0:e6ceb13d2d05 275 #define RF_FRFLSB_868_MHZ 0x00
GregCr 0:e6ceb13d2d05 276 #define RF_FRFMSB_869_MHZ 0xD9
GregCr 0:e6ceb13d2d05 277 #define RF_FRFMID_869_MHZ 0x40
GregCr 0:e6ceb13d2d05 278 #define RF_FRFLSB_869_MHZ 0x00
GregCr 0:e6ceb13d2d05 279 #define RF_FRFMSB_870_MHZ 0xD9
GregCr 0:e6ceb13d2d05 280 #define RF_FRFMID_870_MHZ 0x80
GregCr 0:e6ceb13d2d05 281 #define RF_FRFLSB_870_MHZ 0x00
GregCr 0:e6ceb13d2d05 282
GregCr 0:e6ceb13d2d05 283 #define RF_FRFMSB_902_MHZ 0xE1
GregCr 0:e6ceb13d2d05 284 #define RF_FRFMID_902_MHZ 0x80
GregCr 0:e6ceb13d2d05 285 #define RF_FRFLSB_902_MHZ 0x00
GregCr 0:e6ceb13d2d05 286 #define RF_FRFMSB_903_MHZ 0xE1
GregCr 0:e6ceb13d2d05 287 #define RF_FRFMID_903_MHZ 0xC0
GregCr 0:e6ceb13d2d05 288 #define RF_FRFLSB_903_MHZ 0x00
GregCr 0:e6ceb13d2d05 289 #define RF_FRFMSB_904_MHZ 0xE2
GregCr 0:e6ceb13d2d05 290 #define RF_FRFMID_904_MHZ 0x00
GregCr 0:e6ceb13d2d05 291 #define RF_FRFLSB_904_MHZ 0x00
GregCr 0:e6ceb13d2d05 292 #define RF_FRFMSB_905_MHZ 0xE2
GregCr 0:e6ceb13d2d05 293 #define RF_FRFMID_905_MHZ 0x40
GregCr 0:e6ceb13d2d05 294 #define RF_FRFLSB_905_MHZ 0x00
GregCr 0:e6ceb13d2d05 295 #define RF_FRFMSB_906_MHZ 0xE2
GregCr 0:e6ceb13d2d05 296 #define RF_FRFMID_906_MHZ 0x80
GregCr 0:e6ceb13d2d05 297 #define RF_FRFLSB_906_MHZ 0x00
GregCr 0:e6ceb13d2d05 298 #define RF_FRFMSB_907_MHZ 0xE2
GregCr 0:e6ceb13d2d05 299 #define RF_FRFMID_907_MHZ 0xC0
GregCr 0:e6ceb13d2d05 300 #define RF_FRFLSB_907_MHZ 0x00
GregCr 0:e6ceb13d2d05 301 #define RF_FRFMSB_908_MHZ 0xE3
GregCr 0:e6ceb13d2d05 302 #define RF_FRFMID_908_MHZ 0x00
GregCr 0:e6ceb13d2d05 303 #define RF_FRFLSB_908_MHZ 0x00
GregCr 0:e6ceb13d2d05 304 #define RF_FRFMSB_909_MHZ 0xE3
GregCr 0:e6ceb13d2d05 305 #define RF_FRFMID_909_MHZ 0x40
GregCr 0:e6ceb13d2d05 306 #define RF_FRFLSB_909_MHZ 0x00
GregCr 0:e6ceb13d2d05 307 #define RF_FRFMSB_910_MHZ 0xE3
GregCr 0:e6ceb13d2d05 308 #define RF_FRFMID_910_MHZ 0x80
GregCr 0:e6ceb13d2d05 309 #define RF_FRFLSB_910_MHZ 0x00
GregCr 0:e6ceb13d2d05 310 #define RF_FRFMSB_911_MHZ 0xE3
GregCr 0:e6ceb13d2d05 311 #define RF_FRFMID_911_MHZ 0xC0
GregCr 0:e6ceb13d2d05 312 #define RF_FRFLSB_911_MHZ 0x00
GregCr 0:e6ceb13d2d05 313 #define RF_FRFMSB_912_MHZ 0xE4
GregCr 0:e6ceb13d2d05 314 #define RF_FRFMID_912_MHZ 0x00
GregCr 0:e6ceb13d2d05 315 #define RF_FRFLSB_912_MHZ 0x00
GregCr 0:e6ceb13d2d05 316 #define RF_FRFMSB_913_MHZ 0xE4
GregCr 0:e6ceb13d2d05 317 #define RF_FRFMID_913_MHZ 0x40
GregCr 0:e6ceb13d2d05 318 #define RF_FRFLSB_913_MHZ 0x00
GregCr 0:e6ceb13d2d05 319 #define RF_FRFMSB_914_MHZ 0xE4
GregCr 0:e6ceb13d2d05 320 #define RF_FRFMID_914_MHZ 0x80
GregCr 0:e6ceb13d2d05 321 #define RF_FRFLSB_914_MHZ 0x00
GregCr 0:e6ceb13d2d05 322 #define RF_FRFMSB_915_MHZ 0xE4 // Default
GregCr 0:e6ceb13d2d05 323 #define RF_FRFMID_915_MHZ 0xC0 // Default
GregCr 0:e6ceb13d2d05 324 #define RF_FRFLSB_915_MHZ 0x00 // Default
GregCr 0:e6ceb13d2d05 325 #define RF_FRFMSB_916_MHZ 0xE5
GregCr 0:e6ceb13d2d05 326 #define RF_FRFMID_916_MHZ 0x00
GregCr 0:e6ceb13d2d05 327 #define RF_FRFLSB_916_MHZ 0x00
GregCr 0:e6ceb13d2d05 328 #define RF_FRFMSB_917_MHZ 0xE5
GregCr 0:e6ceb13d2d05 329 #define RF_FRFMID_917_MHZ 0x40
GregCr 0:e6ceb13d2d05 330 #define RF_FRFLSB_917_MHZ 0x00
GregCr 0:e6ceb13d2d05 331 #define RF_FRFMSB_918_MHZ 0xE5
GregCr 0:e6ceb13d2d05 332 #define RF_FRFMID_918_MHZ 0x80
GregCr 0:e6ceb13d2d05 333 #define RF_FRFLSB_918_MHZ 0x00
GregCr 0:e6ceb13d2d05 334 #define RF_FRFMSB_919_MHZ 0xE5
GregCr 0:e6ceb13d2d05 335 #define RF_FRFMID_919_MHZ 0xC0
GregCr 0:e6ceb13d2d05 336 #define RF_FRFLSB_919_MHZ 0x00
GregCr 0:e6ceb13d2d05 337 #define RF_FRFMSB_920_MHZ 0xE6
GregCr 0:e6ceb13d2d05 338 #define RF_FRFMID_920_MHZ 0x00
GregCr 0:e6ceb13d2d05 339 #define RF_FRFLSB_920_MHZ 0x00
GregCr 0:e6ceb13d2d05 340 #define RF_FRFMSB_921_MHZ 0xE6
GregCr 0:e6ceb13d2d05 341 #define RF_FRFMID_921_MHZ 0x40
GregCr 0:e6ceb13d2d05 342 #define RF_FRFLSB_921_MHZ 0x00
GregCr 0:e6ceb13d2d05 343 #define RF_FRFMSB_922_MHZ 0xE6
GregCr 0:e6ceb13d2d05 344 #define RF_FRFMID_922_MHZ 0x80
GregCr 0:e6ceb13d2d05 345 #define RF_FRFLSB_922_MHZ 0x00
GregCr 0:e6ceb13d2d05 346 #define RF_FRFMSB_923_MHZ 0xE6
GregCr 0:e6ceb13d2d05 347 #define RF_FRFMID_923_MHZ 0xC0
GregCr 0:e6ceb13d2d05 348 #define RF_FRFLSB_923_MHZ 0x00
GregCr 0:e6ceb13d2d05 349 #define RF_FRFMSB_924_MHZ 0xE7
GregCr 0:e6ceb13d2d05 350 #define RF_FRFMID_924_MHZ 0x00
GregCr 0:e6ceb13d2d05 351 #define RF_FRFLSB_924_MHZ 0x00
GregCr 0:e6ceb13d2d05 352 #define RF_FRFMSB_925_MHZ 0xE7
GregCr 0:e6ceb13d2d05 353 #define RF_FRFMID_925_MHZ 0x40
GregCr 0:e6ceb13d2d05 354 #define RF_FRFLSB_925_MHZ 0x00
GregCr 0:e6ceb13d2d05 355 #define RF_FRFMSB_926_MHZ 0xE7
GregCr 0:e6ceb13d2d05 356 #define RF_FRFMID_926_MHZ 0x80
GregCr 0:e6ceb13d2d05 357 #define RF_FRFLSB_926_MHZ 0x00
GregCr 0:e6ceb13d2d05 358 #define RF_FRFMSB_927_MHZ 0xE7
GregCr 0:e6ceb13d2d05 359 #define RF_FRFMID_927_MHZ 0xC0
GregCr 0:e6ceb13d2d05 360 #define RF_FRFLSB_927_MHZ 0x00
GregCr 0:e6ceb13d2d05 361 #define RF_FRFMSB_928_MHZ 0xE8
GregCr 0:e6ceb13d2d05 362 #define RF_FRFMID_928_MHZ 0x00
GregCr 0:e6ceb13d2d05 363 #define RF_FRFLSB_928_MHZ 0x00
GregCr 0:e6ceb13d2d05 364
GregCr 0:e6ceb13d2d05 365 /*!
GregCr 0:e6ceb13d2d05 366 * RegPaConfig
GregCr 0:e6ceb13d2d05 367 */
GregCr 0:e6ceb13d2d05 368 #define RF_PACONFIG_PASELECT_MASK 0x7F
GregCr 0:e6ceb13d2d05 369 #define RF_PACONFIG_PASELECT_PABOOST 0x80
GregCr 0:e6ceb13d2d05 370 #define RF_PACONFIG_PASELECT_RFO 0x00 // Default
GregCr 0:e6ceb13d2d05 371
GregCr 0:e6ceb13d2d05 372 #define RF_PACONFIG_MAX_POWER_MASK 0x8F
GregCr 0:e6ceb13d2d05 373
GregCr 0:e6ceb13d2d05 374 #define RF_PACONFIG_OUTPUTPOWER_MASK 0xF0
GregCr 0:e6ceb13d2d05 375
GregCr 0:e6ceb13d2d05 376 /*!
GregCr 0:e6ceb13d2d05 377 * RegPaRamp
GregCr 0:e6ceb13d2d05 378 */
mluis 26:d09a8ef807e2 379 #define RF_PARAMP_MODULATIONSHAPING_MASK 0x9F
mluis 26:d09a8ef807e2 380 #define RF_PARAMP_MODULATIONSHAPING_00 0x00 // Default
mluis 26:d09a8ef807e2 381 #define RF_PARAMP_MODULATIONSHAPING_01 0x20
mluis 26:d09a8ef807e2 382 #define RF_PARAMP_MODULATIONSHAPING_10 0x40
mluis 26:d09a8ef807e2 383 #define RF_PARAMP_MODULATIONSHAPING_11 0x60
mluis 26:d09a8ef807e2 384
mluis 26:d09a8ef807e2 385 #define RF_PARAMP_LOWPNTXPLL_MASK 0xEF
mluis 26:d09a8ef807e2 386 #define RF_PARAMP_LOWPNTXPLL_OFF 0x10
mluis 26:d09a8ef807e2 387 #define RF_PARAMP_LOWPNTXPLL_ON 0x00 // Default
GregCr 0:e6ceb13d2d05 388
GregCr 0:e6ceb13d2d05 389 #define RF_PARAMP_MASK 0xF0
GregCr 0:e6ceb13d2d05 390 #define RF_PARAMP_3400_US 0x00
GregCr 0:e6ceb13d2d05 391 #define RF_PARAMP_2000_US 0x01
GregCr 0:e6ceb13d2d05 392 #define RF_PARAMP_1000_US 0x02
GregCr 0:e6ceb13d2d05 393 #define RF_PARAMP_0500_US 0x03
GregCr 0:e6ceb13d2d05 394 #define RF_PARAMP_0250_US 0x04
GregCr 0:e6ceb13d2d05 395 #define RF_PARAMP_0125_US 0x05
GregCr 0:e6ceb13d2d05 396 #define RF_PARAMP_0100_US 0x06
GregCr 0:e6ceb13d2d05 397 #define RF_PARAMP_0062_US 0x07
GregCr 0:e6ceb13d2d05 398 #define RF_PARAMP_0050_US 0x08
GregCr 0:e6ceb13d2d05 399 #define RF_PARAMP_0040_US 0x09 // Default
GregCr 0:e6ceb13d2d05 400 #define RF_PARAMP_0031_US 0x0A
GregCr 0:e6ceb13d2d05 401 #define RF_PARAMP_0025_US 0x0B
GregCr 0:e6ceb13d2d05 402 #define RF_PARAMP_0020_US 0x0C
GregCr 0:e6ceb13d2d05 403 #define RF_PARAMP_0015_US 0x0D
GregCr 0:e6ceb13d2d05 404 #define RF_PARAMP_0012_US 0x0E
GregCr 0:e6ceb13d2d05 405 #define RF_PARAMP_0010_US 0x0F
GregCr 0:e6ceb13d2d05 406
GregCr 0:e6ceb13d2d05 407 /*!
GregCr 0:e6ceb13d2d05 408 * RegOcp
GregCr 0:e6ceb13d2d05 409 */
GregCr 0:e6ceb13d2d05 410 #define RF_OCP_MASK 0xDF
GregCr 0:e6ceb13d2d05 411 #define RF_OCP_ON 0x20 // Default
GregCr 0:e6ceb13d2d05 412 #define RF_OCP_OFF 0x00
GregCr 0:e6ceb13d2d05 413
GregCr 0:e6ceb13d2d05 414 #define RF_OCP_TRIM_MASK 0xE0
GregCr 0:e6ceb13d2d05 415 #define RF_OCP_TRIM_045_MA 0x00
GregCr 0:e6ceb13d2d05 416 #define RF_OCP_TRIM_050_MA 0x01
GregCr 0:e6ceb13d2d05 417 #define RF_OCP_TRIM_055_MA 0x02
GregCr 0:e6ceb13d2d05 418 #define RF_OCP_TRIM_060_MA 0x03
GregCr 0:e6ceb13d2d05 419 #define RF_OCP_TRIM_065_MA 0x04
GregCr 0:e6ceb13d2d05 420 #define RF_OCP_TRIM_070_MA 0x05
GregCr 0:e6ceb13d2d05 421 #define RF_OCP_TRIM_075_MA 0x06
GregCr 0:e6ceb13d2d05 422 #define RF_OCP_TRIM_080_MA 0x07
GregCr 0:e6ceb13d2d05 423 #define RF_OCP_TRIM_085_MA 0x08
GregCr 0:e6ceb13d2d05 424 #define RF_OCP_TRIM_090_MA 0x09
GregCr 0:e6ceb13d2d05 425 #define RF_OCP_TRIM_095_MA 0x0A
GregCr 0:e6ceb13d2d05 426 #define RF_OCP_TRIM_100_MA 0x0B // Default
GregCr 0:e6ceb13d2d05 427 #define RF_OCP_TRIM_105_MA 0x0C
GregCr 0:e6ceb13d2d05 428 #define RF_OCP_TRIM_110_MA 0x0D
GregCr 0:e6ceb13d2d05 429 #define RF_OCP_TRIM_115_MA 0x0E
GregCr 0:e6ceb13d2d05 430 #define RF_OCP_TRIM_120_MA 0x0F
GregCr 0:e6ceb13d2d05 431 #define RF_OCP_TRIM_130_MA 0x10
GregCr 0:e6ceb13d2d05 432 #define RF_OCP_TRIM_140_MA 0x11
GregCr 0:e6ceb13d2d05 433 #define RF_OCP_TRIM_150_MA 0x12
GregCr 0:e6ceb13d2d05 434 #define RF_OCP_TRIM_160_MA 0x13
GregCr 0:e6ceb13d2d05 435 #define RF_OCP_TRIM_170_MA 0x14
GregCr 0:e6ceb13d2d05 436 #define RF_OCP_TRIM_180_MA 0x15
GregCr 0:e6ceb13d2d05 437 #define RF_OCP_TRIM_190_MA 0x16
GregCr 0:e6ceb13d2d05 438 #define RF_OCP_TRIM_200_MA 0x17
GregCr 0:e6ceb13d2d05 439 #define RF_OCP_TRIM_210_MA 0x18
GregCr 0:e6ceb13d2d05 440 #define RF_OCP_TRIM_220_MA 0x19
GregCr 0:e6ceb13d2d05 441 #define RF_OCP_TRIM_230_MA 0x1A
GregCr 0:e6ceb13d2d05 442 #define RF_OCP_TRIM_240_MA 0x1B
GregCr 0:e6ceb13d2d05 443
GregCr 0:e6ceb13d2d05 444 /*!
GregCr 0:e6ceb13d2d05 445 * RegLna
GregCr 0:e6ceb13d2d05 446 */
GregCr 0:e6ceb13d2d05 447 #define RF_LNA_GAIN_MASK 0x1F
GregCr 0:e6ceb13d2d05 448 #define RF_LNA_GAIN_G1 0x20 // Default
GregCr 0:e6ceb13d2d05 449 #define RF_LNA_GAIN_G2 0x40
GregCr 0:e6ceb13d2d05 450 #define RF_LNA_GAIN_G3 0x60
GregCr 0:e6ceb13d2d05 451 #define RF_LNA_GAIN_G4 0x80
GregCr 0:e6ceb13d2d05 452 #define RF_LNA_GAIN_G5 0xA0
GregCr 0:e6ceb13d2d05 453 #define RF_LNA_GAIN_G6 0xC0
GregCr 0:e6ceb13d2d05 454
GregCr 0:e6ceb13d2d05 455 #define RF_LNA_BOOST_MASK 0xFC
GregCr 0:e6ceb13d2d05 456 #define RF_LNA_BOOST_OFF 0x00 // Default
GregCr 0:e6ceb13d2d05 457 #define RF_LNA_BOOST_ON 0x03
GregCr 0:e6ceb13d2d05 458
GregCr 0:e6ceb13d2d05 459 /*!
GregCr 0:e6ceb13d2d05 460 * RegRxConfig
GregCr 0:e6ceb13d2d05 461 */
GregCr 0:e6ceb13d2d05 462 #define RF_RXCONFIG_RESTARTRXONCOLLISION_MASK 0x7F
GregCr 0:e6ceb13d2d05 463 #define RF_RXCONFIG_RESTARTRXONCOLLISION_ON 0x80
GregCr 0:e6ceb13d2d05 464 #define RF_RXCONFIG_RESTARTRXONCOLLISION_OFF 0x00 // Default
GregCr 0:e6ceb13d2d05 465
GregCr 0:e6ceb13d2d05 466 #define RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK 0x40 // Write only
GregCr 0:e6ceb13d2d05 467
GregCr 0:e6ceb13d2d05 468 #define RF_RXCONFIG_RESTARTRXWITHPLLLOCK 0x20 // Write only
GregCr 0:e6ceb13d2d05 469
GregCr 0:e6ceb13d2d05 470 #define RF_RXCONFIG_AFCAUTO_MASK 0xEF
GregCr 0:e6ceb13d2d05 471 #define RF_RXCONFIG_AFCAUTO_ON 0x10
GregCr 0:e6ceb13d2d05 472 #define RF_RXCONFIG_AFCAUTO_OFF 0x00 // Default
GregCr 0:e6ceb13d2d05 473
GregCr 0:e6ceb13d2d05 474 #define RF_RXCONFIG_AGCAUTO_MASK 0xF7
GregCr 0:e6ceb13d2d05 475 #define RF_RXCONFIG_AGCAUTO_ON 0x08 // Default
GregCr 0:e6ceb13d2d05 476 #define RF_RXCONFIG_AGCAUTO_OFF 0x00
GregCr 0:e6ceb13d2d05 477
GregCr 0:e6ceb13d2d05 478 #define RF_RXCONFIG_RXTRIGER_MASK 0xF8
GregCr 0:e6ceb13d2d05 479 #define RF_RXCONFIG_RXTRIGER_OFF 0x00
GregCr 0:e6ceb13d2d05 480 #define RF_RXCONFIG_RXTRIGER_RSSI 0x01
GregCr 0:e6ceb13d2d05 481 #define RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT 0x06 // Default
GregCr 0:e6ceb13d2d05 482 #define RF_RXCONFIG_RXTRIGER_RSSI_PREAMBLEDETECT 0x07
GregCr 0:e6ceb13d2d05 483
GregCr 0:e6ceb13d2d05 484 /*!
GregCr 0:e6ceb13d2d05 485 * RegRssiConfig
GregCr 0:e6ceb13d2d05 486 */
GregCr 0:e6ceb13d2d05 487 #define RF_RSSICONFIG_OFFSET_MASK 0x07
GregCr 0:e6ceb13d2d05 488 #define RF_RSSICONFIG_OFFSET_P_00_DB 0x00 // Default
GregCr 0:e6ceb13d2d05 489 #define RF_RSSICONFIG_OFFSET_P_01_DB 0x08
GregCr 0:e6ceb13d2d05 490 #define RF_RSSICONFIG_OFFSET_P_02_DB 0x10
GregCr 0:e6ceb13d2d05 491 #define RF_RSSICONFIG_OFFSET_P_03_DB 0x18
GregCr 0:e6ceb13d2d05 492 #define RF_RSSICONFIG_OFFSET_P_04_DB 0x20
GregCr 0:e6ceb13d2d05 493 #define RF_RSSICONFIG_OFFSET_P_05_DB 0x28
GregCr 0:e6ceb13d2d05 494 #define RF_RSSICONFIG_OFFSET_P_06_DB 0x30
GregCr 0:e6ceb13d2d05 495 #define RF_RSSICONFIG_OFFSET_P_07_DB 0x38
GregCr 0:e6ceb13d2d05 496 #define RF_RSSICONFIG_OFFSET_P_08_DB 0x40
GregCr 0:e6ceb13d2d05 497 #define RF_RSSICONFIG_OFFSET_P_09_DB 0x48
GregCr 0:e6ceb13d2d05 498 #define RF_RSSICONFIG_OFFSET_P_10_DB 0x50
GregCr 0:e6ceb13d2d05 499 #define RF_RSSICONFIG_OFFSET_P_11_DB 0x58
GregCr 0:e6ceb13d2d05 500 #define RF_RSSICONFIG_OFFSET_P_12_DB 0x60
GregCr 0:e6ceb13d2d05 501 #define RF_RSSICONFIG_OFFSET_P_13_DB 0x68
GregCr 0:e6ceb13d2d05 502 #define RF_RSSICONFIG_OFFSET_P_14_DB 0x70
GregCr 0:e6ceb13d2d05 503 #define RF_RSSICONFIG_OFFSET_P_15_DB 0x78
GregCr 0:e6ceb13d2d05 504 #define RF_RSSICONFIG_OFFSET_M_16_DB 0x80
GregCr 0:e6ceb13d2d05 505 #define RF_RSSICONFIG_OFFSET_M_15_DB 0x88
GregCr 0:e6ceb13d2d05 506 #define RF_RSSICONFIG_OFFSET_M_14_DB 0x90
GregCr 0:e6ceb13d2d05 507 #define RF_RSSICONFIG_OFFSET_M_13_DB 0x98
GregCr 0:e6ceb13d2d05 508 #define RF_RSSICONFIG_OFFSET_M_12_DB 0xA0
GregCr 0:e6ceb13d2d05 509 #define RF_RSSICONFIG_OFFSET_M_11_DB 0xA8
GregCr 0:e6ceb13d2d05 510 #define RF_RSSICONFIG_OFFSET_M_10_DB 0xB0
GregCr 0:e6ceb13d2d05 511 #define RF_RSSICONFIG_OFFSET_M_09_DB 0xB8
GregCr 0:e6ceb13d2d05 512 #define RF_RSSICONFIG_OFFSET_M_08_DB 0xC0
GregCr 0:e6ceb13d2d05 513 #define RF_RSSICONFIG_OFFSET_M_07_DB 0xC8
GregCr 0:e6ceb13d2d05 514 #define RF_RSSICONFIG_OFFSET_M_06_DB 0xD0
GregCr 0:e6ceb13d2d05 515 #define RF_RSSICONFIG_OFFSET_M_05_DB 0xD8
GregCr 0:e6ceb13d2d05 516 #define RF_RSSICONFIG_OFFSET_M_04_DB 0xE0
GregCr 0:e6ceb13d2d05 517 #define RF_RSSICONFIG_OFFSET_M_03_DB 0xE8
GregCr 0:e6ceb13d2d05 518 #define RF_RSSICONFIG_OFFSET_M_02_DB 0xF0
GregCr 0:e6ceb13d2d05 519 #define RF_RSSICONFIG_OFFSET_M_01_DB 0xF8
GregCr 0:e6ceb13d2d05 520
GregCr 0:e6ceb13d2d05 521 #define RF_RSSICONFIG_SMOOTHING_MASK 0xF8
GregCr 0:e6ceb13d2d05 522 #define RF_RSSICONFIG_SMOOTHING_2 0x00
GregCr 0:e6ceb13d2d05 523 #define RF_RSSICONFIG_SMOOTHING_4 0x01
GregCr 0:e6ceb13d2d05 524 #define RF_RSSICONFIG_SMOOTHING_8 0x02 // Default
GregCr 0:e6ceb13d2d05 525 #define RF_RSSICONFIG_SMOOTHING_16 0x03
GregCr 0:e6ceb13d2d05 526 #define RF_RSSICONFIG_SMOOTHING_32 0x04
GregCr 0:e6ceb13d2d05 527 #define RF_RSSICONFIG_SMOOTHING_64 0x05
GregCr 0:e6ceb13d2d05 528 #define RF_RSSICONFIG_SMOOTHING_128 0x06
GregCr 0:e6ceb13d2d05 529 #define RF_RSSICONFIG_SMOOTHING_256 0x07
GregCr 0:e6ceb13d2d05 530
GregCr 0:e6ceb13d2d05 531 /*!
GregCr 0:e6ceb13d2d05 532 * RegRssiCollision
GregCr 0:e6ceb13d2d05 533 */
GregCr 0:e6ceb13d2d05 534 #define RF_RSSICOLISION_THRESHOLD 0x0A // Default
GregCr 0:e6ceb13d2d05 535
GregCr 0:e6ceb13d2d05 536 /*!
GregCr 0:e6ceb13d2d05 537 * RegRssiThresh
GregCr 0:e6ceb13d2d05 538 */
GregCr 0:e6ceb13d2d05 539 #define RF_RSSITHRESH_THRESHOLD 0xFF // Default
GregCr 0:e6ceb13d2d05 540
GregCr 0:e6ceb13d2d05 541 /*!
mluis 22:7f3aab69cca9 542 * RegRssiValue (Read Only)
GregCr 0:e6ceb13d2d05 543 */
GregCr 0:e6ceb13d2d05 544
GregCr 0:e6ceb13d2d05 545 /*!
GregCr 0:e6ceb13d2d05 546 * RegRxBw
GregCr 0:e6ceb13d2d05 547 */
GregCr 0:e6ceb13d2d05 548 #define RF_RXBW_MANT_MASK 0xE7
GregCr 0:e6ceb13d2d05 549 #define RF_RXBW_MANT_16 0x00
GregCr 0:e6ceb13d2d05 550 #define RF_RXBW_MANT_20 0x08
GregCr 0:e6ceb13d2d05 551 #define RF_RXBW_MANT_24 0x10 // Default
GregCr 0:e6ceb13d2d05 552
GregCr 0:e6ceb13d2d05 553 #define RF_RXBW_EXP_MASK 0xF8
GregCr 0:e6ceb13d2d05 554 #define RF_RXBW_EXP_0 0x00
GregCr 0:e6ceb13d2d05 555 #define RF_RXBW_EXP_1 0x01
GregCr 0:e6ceb13d2d05 556 #define RF_RXBW_EXP_2 0x02
GregCr 0:e6ceb13d2d05 557 #define RF_RXBW_EXP_3 0x03
GregCr 0:e6ceb13d2d05 558 #define RF_RXBW_EXP_4 0x04
GregCr 0:e6ceb13d2d05 559 #define RF_RXBW_EXP_5 0x05 // Default
GregCr 0:e6ceb13d2d05 560 #define RF_RXBW_EXP_6 0x06
GregCr 0:e6ceb13d2d05 561 #define RF_RXBW_EXP_7 0x07
GregCr 0:e6ceb13d2d05 562
GregCr 0:e6ceb13d2d05 563 /*!
GregCr 0:e6ceb13d2d05 564 * RegAfcBw
GregCr 0:e6ceb13d2d05 565 */
GregCr 0:e6ceb13d2d05 566 #define RF_AFCBW_MANTAFC_MASK 0xE7
GregCr 0:e6ceb13d2d05 567 #define RF_AFCBW_MANTAFC_16 0x00
GregCr 0:e6ceb13d2d05 568 #define RF_AFCBW_MANTAFC_20 0x08 // Default
GregCr 0:e6ceb13d2d05 569 #define RF_AFCBW_MANTAFC_24 0x10
GregCr 0:e6ceb13d2d05 570
GregCr 0:e6ceb13d2d05 571 #define RF_AFCBW_EXPAFC_MASK 0xF8
GregCr 0:e6ceb13d2d05 572 #define RF_AFCBW_EXPAFC_0 0x00
GregCr 0:e6ceb13d2d05 573 #define RF_AFCBW_EXPAFC_1 0x01
GregCr 0:e6ceb13d2d05 574 #define RF_AFCBW_EXPAFC_2 0x02
GregCr 0:e6ceb13d2d05 575 #define RF_AFCBW_EXPAFC_3 0x03 // Default
GregCr 0:e6ceb13d2d05 576 #define RF_AFCBW_EXPAFC_4 0x04
GregCr 0:e6ceb13d2d05 577 #define RF_AFCBW_EXPAFC_5 0x05
GregCr 0:e6ceb13d2d05 578 #define RF_AFCBW_EXPAFC_6 0x06
GregCr 0:e6ceb13d2d05 579 #define RF_AFCBW_EXPAFC_7 0x07
GregCr 0:e6ceb13d2d05 580
GregCr 0:e6ceb13d2d05 581 /*!
GregCr 0:e6ceb13d2d05 582 * RegOokPeak
GregCr 0:e6ceb13d2d05 583 */
GregCr 0:e6ceb13d2d05 584 #define RF_OOKPEAK_BITSYNC_MASK 0xDF // Default
GregCr 0:e6ceb13d2d05 585 #define RF_OOKPEAK_BITSYNC_ON 0x20 // Default
GregCr 0:e6ceb13d2d05 586 #define RF_OOKPEAK_BITSYNC_OFF 0x00
GregCr 0:e6ceb13d2d05 587
GregCr 0:e6ceb13d2d05 588 #define RF_OOKPEAK_OOKTHRESHTYPE_MASK 0xE7
GregCr 0:e6ceb13d2d05 589 #define RF_OOKPEAK_OOKTHRESHTYPE_FIXED 0x00
GregCr 0:e6ceb13d2d05 590 #define RF_OOKPEAK_OOKTHRESHTYPE_PEAK 0x08 // Default
GregCr 0:e6ceb13d2d05 591 #define RF_OOKPEAK_OOKTHRESHTYPE_AVERAGE 0x10
GregCr 0:e6ceb13d2d05 592
GregCr 0:e6ceb13d2d05 593 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_MASK 0xF8
GregCr 0:e6ceb13d2d05 594 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_0_5_DB 0x00 // Default
GregCr 0:e6ceb13d2d05 595 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_0_DB 0x01
GregCr 0:e6ceb13d2d05 596 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_5_DB 0x02
GregCr 0:e6ceb13d2d05 597 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_2_0_DB 0x03
GregCr 0:e6ceb13d2d05 598 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_3_0_DB 0x04
GregCr 0:e6ceb13d2d05 599 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_4_0_DB 0x05
GregCr 0:e6ceb13d2d05 600 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_5_0_DB 0x06
GregCr 0:e6ceb13d2d05 601 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_6_0_DB 0x07
GregCr 0:e6ceb13d2d05 602
GregCr 0:e6ceb13d2d05 603 /*!
GregCr 0:e6ceb13d2d05 604 * RegOokFix
GregCr 0:e6ceb13d2d05 605 */
GregCr 0:e6ceb13d2d05 606 #define RF_OOKFIX_OOKFIXEDTHRESHOLD 0x0C // Default
GregCr 0:e6ceb13d2d05 607
GregCr 0:e6ceb13d2d05 608 /*!
GregCr 0:e6ceb13d2d05 609 * RegOokAvg
GregCr 0:e6ceb13d2d05 610 */
GregCr 0:e6ceb13d2d05 611 #define RF_OOKAVG_OOKPEAKTHRESHDEC_MASK 0x1F
GregCr 0:e6ceb13d2d05 612 #define RF_OOKAVG_OOKPEAKTHRESHDEC_000 0x00 // Default
GregCr 0:e6ceb13d2d05 613 #define RF_OOKAVG_OOKPEAKTHRESHDEC_001 0x20
GregCr 0:e6ceb13d2d05 614 #define RF_OOKAVG_OOKPEAKTHRESHDEC_010 0x40
GregCr 0:e6ceb13d2d05 615 #define RF_OOKAVG_OOKPEAKTHRESHDEC_011 0x60
GregCr 0:e6ceb13d2d05 616 #define RF_OOKAVG_OOKPEAKTHRESHDEC_100 0x80
GregCr 0:e6ceb13d2d05 617 #define RF_OOKAVG_OOKPEAKTHRESHDEC_101 0xA0
GregCr 0:e6ceb13d2d05 618 #define RF_OOKAVG_OOKPEAKTHRESHDEC_110 0xC0
GregCr 0:e6ceb13d2d05 619 #define RF_OOKAVG_OOKPEAKTHRESHDEC_111 0xE0
GregCr 0:e6ceb13d2d05 620
GregCr 0:e6ceb13d2d05 621 #define RF_OOKAVG_AVERAGEOFFSET_MASK 0xF3
GregCr 0:e6ceb13d2d05 622 #define RF_OOKAVG_AVERAGEOFFSET_0_DB 0x00 // Default
GregCr 0:e6ceb13d2d05 623 #define RF_OOKAVG_AVERAGEOFFSET_2_DB 0x04
GregCr 0:e6ceb13d2d05 624 #define RF_OOKAVG_AVERAGEOFFSET_4_DB 0x08
GregCr 0:e6ceb13d2d05 625 #define RF_OOKAVG_AVERAGEOFFSET_6_DB 0x0C
GregCr 0:e6ceb13d2d05 626
GregCr 0:e6ceb13d2d05 627 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_MASK 0xFC
GregCr 0:e6ceb13d2d05 628 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_00 0x00
GregCr 0:e6ceb13d2d05 629 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_01 0x01
GregCr 0:e6ceb13d2d05 630 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_10 0x02 // Default
GregCr 0:e6ceb13d2d05 631 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_11 0x03
GregCr 0:e6ceb13d2d05 632
GregCr 0:e6ceb13d2d05 633 /*!
GregCr 0:e6ceb13d2d05 634 * RegAfcFei
GregCr 0:e6ceb13d2d05 635 */
GregCr 0:e6ceb13d2d05 636 #define RF_AFCFEI_AGCSTART 0x10
GregCr 0:e6ceb13d2d05 637
GregCr 0:e6ceb13d2d05 638 #define RF_AFCFEI_AFCCLEAR 0x02
GregCr 0:e6ceb13d2d05 639
GregCr 0:e6ceb13d2d05 640 #define RF_AFCFEI_AFCAUTOCLEAR_MASK 0xFE
GregCr 0:e6ceb13d2d05 641 #define RF_AFCFEI_AFCAUTOCLEAR_ON 0x01
GregCr 0:e6ceb13d2d05 642 #define RF_AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default
GregCr 0:e6ceb13d2d05 643
GregCr 0:e6ceb13d2d05 644 /*!
mluis 22:7f3aab69cca9 645 * RegAfcMsb (Read Only)
GregCr 0:e6ceb13d2d05 646 */
GregCr 0:e6ceb13d2d05 647
GregCr 0:e6ceb13d2d05 648 /*!
mluis 22:7f3aab69cca9 649 * RegAfcLsb (Read Only)
GregCr 0:e6ceb13d2d05 650 */
GregCr 0:e6ceb13d2d05 651
GregCr 0:e6ceb13d2d05 652 /*!
mluis 22:7f3aab69cca9 653 * RegFeiMsb (Read Only)
GregCr 0:e6ceb13d2d05 654 */
GregCr 0:e6ceb13d2d05 655
GregCr 0:e6ceb13d2d05 656 /*!
mluis 22:7f3aab69cca9 657 * RegFeiLsb (Read Only)
GregCr 0:e6ceb13d2d05 658 */
GregCr 0:e6ceb13d2d05 659
GregCr 0:e6ceb13d2d05 660 /*!
GregCr 0:e6ceb13d2d05 661 * RegPreambleDetect
GregCr 0:e6ceb13d2d05 662 */
GregCr 0:e6ceb13d2d05 663 #define RF_PREAMBLEDETECT_DETECTOR_MASK 0x7F
GregCr 0:e6ceb13d2d05 664 #define RF_PREAMBLEDETECT_DETECTOR_ON 0x80 // Default
GregCr 0:e6ceb13d2d05 665 #define RF_PREAMBLEDETECT_DETECTOR_OFF 0x00
GregCr 0:e6ceb13d2d05 666
GregCr 0:e6ceb13d2d05 667 #define RF_PREAMBLEDETECT_DETECTORSIZE_MASK 0x9F
GregCr 0:e6ceb13d2d05 668 #define RF_PREAMBLEDETECT_DETECTORSIZE_1 0x00
GregCr 0:e6ceb13d2d05 669 #define RF_PREAMBLEDETECT_DETECTORSIZE_2 0x20 // Default
GregCr 0:e6ceb13d2d05 670 #define RF_PREAMBLEDETECT_DETECTORSIZE_3 0x40
GregCr 0:e6ceb13d2d05 671 #define RF_PREAMBLEDETECT_DETECTORSIZE_4 0x60
GregCr 0:e6ceb13d2d05 672
GregCr 0:e6ceb13d2d05 673 #define RF_PREAMBLEDETECT_DETECTORTOL_MASK 0xE0
GregCr 0:e6ceb13d2d05 674 #define RF_PREAMBLEDETECT_DETECTORTOL_0 0x00
GregCr 0:e6ceb13d2d05 675 #define RF_PREAMBLEDETECT_DETECTORTOL_1 0x01
GregCr 0:e6ceb13d2d05 676 #define RF_PREAMBLEDETECT_DETECTORTOL_2 0x02
GregCr 0:e6ceb13d2d05 677 #define RF_PREAMBLEDETECT_DETECTORTOL_3 0x03
GregCr 0:e6ceb13d2d05 678 #define RF_PREAMBLEDETECT_DETECTORTOL_4 0x04
GregCr 0:e6ceb13d2d05 679 #define RF_PREAMBLEDETECT_DETECTORTOL_5 0x05
GregCr 0:e6ceb13d2d05 680 #define RF_PREAMBLEDETECT_DETECTORTOL_6 0x06
GregCr 0:e6ceb13d2d05 681 #define RF_PREAMBLEDETECT_DETECTORTOL_7 0x07
GregCr 0:e6ceb13d2d05 682 #define RF_PREAMBLEDETECT_DETECTORTOL_8 0x08
GregCr 0:e6ceb13d2d05 683 #define RF_PREAMBLEDETECT_DETECTORTOL_9 0x09
GregCr 0:e6ceb13d2d05 684 #define RF_PREAMBLEDETECT_DETECTORTOL_10 0x0A // Default
GregCr 0:e6ceb13d2d05 685 #define RF_PREAMBLEDETECT_DETECTORTOL_11 0x0B
GregCr 0:e6ceb13d2d05 686 #define RF_PREAMBLEDETECT_DETECTORTOL_12 0x0C
GregCr 0:e6ceb13d2d05 687 #define RF_PREAMBLEDETECT_DETECTORTOL_13 0x0D
GregCr 0:e6ceb13d2d05 688 #define RF_PREAMBLEDETECT_DETECTORTOL_14 0x0E
GregCr 0:e6ceb13d2d05 689 #define RF_PREAMBLEDETECT_DETECTORTOL_15 0x0F
GregCr 0:e6ceb13d2d05 690 #define RF_PREAMBLEDETECT_DETECTORTOL_16 0x10
GregCr 0:e6ceb13d2d05 691 #define RF_PREAMBLEDETECT_DETECTORTOL_17 0x11
GregCr 0:e6ceb13d2d05 692 #define RF_PREAMBLEDETECT_DETECTORTOL_18 0x12
GregCr 0:e6ceb13d2d05 693 #define RF_PREAMBLEDETECT_DETECTORTOL_19 0x13
GregCr 0:e6ceb13d2d05 694 #define RF_PREAMBLEDETECT_DETECTORTOL_20 0x14
GregCr 0:e6ceb13d2d05 695 #define RF_PREAMBLEDETECT_DETECTORTOL_21 0x15
GregCr 0:e6ceb13d2d05 696 #define RF_PREAMBLEDETECT_DETECTORTOL_22 0x16
GregCr 0:e6ceb13d2d05 697 #define RF_PREAMBLEDETECT_DETECTORTOL_23 0x17
GregCr 0:e6ceb13d2d05 698 #define RF_PREAMBLEDETECT_DETECTORTOL_24 0x18
GregCr 0:e6ceb13d2d05 699 #define RF_PREAMBLEDETECT_DETECTORTOL_25 0x19
GregCr 0:e6ceb13d2d05 700 #define RF_PREAMBLEDETECT_DETECTORTOL_26 0x1A
GregCr 0:e6ceb13d2d05 701 #define RF_PREAMBLEDETECT_DETECTORTOL_27 0x1B
GregCr 0:e6ceb13d2d05 702 #define RF_PREAMBLEDETECT_DETECTORTOL_28 0x1C
GregCr 0:e6ceb13d2d05 703 #define RF_PREAMBLEDETECT_DETECTORTOL_29 0x1D
GregCr 0:e6ceb13d2d05 704 #define RF_PREAMBLEDETECT_DETECTORTOL_30 0x1E
GregCr 0:e6ceb13d2d05 705 #define RF_PREAMBLEDETECT_DETECTORTOL_31 0x1F
GregCr 0:e6ceb13d2d05 706
GregCr 0:e6ceb13d2d05 707 /*!
GregCr 0:e6ceb13d2d05 708 * RegRxTimeout1
GregCr 0:e6ceb13d2d05 709 */
GregCr 0:e6ceb13d2d05 710 #define RF_RXTIMEOUT1_TIMEOUTRXRSSI 0x00 // Default
GregCr 0:e6ceb13d2d05 711
GregCr 0:e6ceb13d2d05 712 /*!
GregCr 0:e6ceb13d2d05 713 * RegRxTimeout2
GregCr 0:e6ceb13d2d05 714 */
GregCr 0:e6ceb13d2d05 715 #define RF_RXTIMEOUT2_TIMEOUTRXPREAMBLE 0x00 // Default
GregCr 0:e6ceb13d2d05 716
GregCr 0:e6ceb13d2d05 717 /*!
GregCr 0:e6ceb13d2d05 718 * RegRxTimeout3
GregCr 0:e6ceb13d2d05 719 */
GregCr 0:e6ceb13d2d05 720 #define RF_RXTIMEOUT3_TIMEOUTSIGNALSYNC 0x00 // Default
GregCr 0:e6ceb13d2d05 721
GregCr 0:e6ceb13d2d05 722 /*!
GregCr 0:e6ceb13d2d05 723 * RegRxDelay
GregCr 0:e6ceb13d2d05 724 */
GregCr 0:e6ceb13d2d05 725 #define RF_RXDELAY_INTERPACKETRXDELAY 0x00 // Default
GregCr 0:e6ceb13d2d05 726
GregCr 0:e6ceb13d2d05 727 /*!
GregCr 0:e6ceb13d2d05 728 * RegOsc
GregCr 0:e6ceb13d2d05 729 */
GregCr 0:e6ceb13d2d05 730 #define RF_OSC_RCCALSTART 0x08
GregCr 0:e6ceb13d2d05 731
GregCr 0:e6ceb13d2d05 732 #define RF_OSC_CLKOUT_MASK 0xF8
GregCr 0:e6ceb13d2d05 733 #define RF_OSC_CLKOUT_32_MHZ 0x00
GregCr 0:e6ceb13d2d05 734 #define RF_OSC_CLKOUT_16_MHZ 0x01
GregCr 0:e6ceb13d2d05 735 #define RF_OSC_CLKOUT_8_MHZ 0x02
GregCr 0:e6ceb13d2d05 736 #define RF_OSC_CLKOUT_4_MHZ 0x03
GregCr 0:e6ceb13d2d05 737 #define RF_OSC_CLKOUT_2_MHZ 0x04
GregCr 0:e6ceb13d2d05 738 #define RF_OSC_CLKOUT_1_MHZ 0x05 // Default
GregCr 0:e6ceb13d2d05 739 #define RF_OSC_CLKOUT_RC 0x06
GregCr 0:e6ceb13d2d05 740 #define RF_OSC_CLKOUT_OFF 0x07
GregCr 0:e6ceb13d2d05 741
GregCr 0:e6ceb13d2d05 742 /*!
GregCr 0:e6ceb13d2d05 743 * RegPreambleMsb/RegPreambleLsb
GregCr 0:e6ceb13d2d05 744 */
GregCr 0:e6ceb13d2d05 745 #define RF_PREAMBLEMSB_SIZE 0x00 // Default
GregCr 0:e6ceb13d2d05 746 #define RF_PREAMBLELSB_SIZE 0x03 // Default
GregCr 0:e6ceb13d2d05 747
GregCr 0:e6ceb13d2d05 748 /*!
GregCr 0:e6ceb13d2d05 749 * RegSyncConfig
GregCr 0:e6ceb13d2d05 750 */
GregCr 0:e6ceb13d2d05 751 #define RF_SYNCCONFIG_AUTORESTARTRXMODE_MASK 0x3F
GregCr 0:e6ceb13d2d05 752 #define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_ON 0x80 // Default
GregCr 0:e6ceb13d2d05 753 #define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_OFF 0x40
GregCr 0:e6ceb13d2d05 754 #define RF_SYNCCONFIG_AUTORESTARTRXMODE_OFF 0x00
GregCr 0:e6ceb13d2d05 755
GregCr 0:e6ceb13d2d05 756
GregCr 0:e6ceb13d2d05 757 #define RF_SYNCCONFIG_PREAMBLEPOLARITY_MASK 0xDF
GregCr 0:e6ceb13d2d05 758 #define RF_SYNCCONFIG_PREAMBLEPOLARITY_55 0x20
GregCr 0:e6ceb13d2d05 759 #define RF_SYNCCONFIG_PREAMBLEPOLARITY_AA 0x00 // Default
GregCr 0:e6ceb13d2d05 760
GregCr 0:e6ceb13d2d05 761 #define RF_SYNCCONFIG_SYNC_MASK 0xEF
GregCr 0:e6ceb13d2d05 762 #define RF_SYNCCONFIG_SYNC_ON 0x10 // Default
GregCr 0:e6ceb13d2d05 763 #define RF_SYNCCONFIG_SYNC_OFF 0x00
GregCr 0:e6ceb13d2d05 764
GregCr 0:e6ceb13d2d05 765
GregCr 0:e6ceb13d2d05 766 #define RF_SYNCCONFIG_SYNCSIZE_MASK 0xF8
GregCr 0:e6ceb13d2d05 767 #define RF_SYNCCONFIG_SYNCSIZE_1 0x00
GregCr 0:e6ceb13d2d05 768 #define RF_SYNCCONFIG_SYNCSIZE_2 0x01
GregCr 0:e6ceb13d2d05 769 #define RF_SYNCCONFIG_SYNCSIZE_3 0x02
GregCr 0:e6ceb13d2d05 770 #define RF_SYNCCONFIG_SYNCSIZE_4 0x03 // Default
GregCr 0:e6ceb13d2d05 771 #define RF_SYNCCONFIG_SYNCSIZE_5 0x04
GregCr 0:e6ceb13d2d05 772 #define RF_SYNCCONFIG_SYNCSIZE_6 0x05
GregCr 0:e6ceb13d2d05 773 #define RF_SYNCCONFIG_SYNCSIZE_7 0x06
GregCr 0:e6ceb13d2d05 774 #define RF_SYNCCONFIG_SYNCSIZE_8 0x07
GregCr 0:e6ceb13d2d05 775
GregCr 0:e6ceb13d2d05 776 /*!
GregCr 0:e6ceb13d2d05 777 * RegSyncValue1-8
GregCr 0:e6ceb13d2d05 778 */
GregCr 0:e6ceb13d2d05 779 #define RF_SYNCVALUE1_SYNCVALUE 0x01 // Default
GregCr 0:e6ceb13d2d05 780 #define RF_SYNCVALUE2_SYNCVALUE 0x01 // Default
GregCr 0:e6ceb13d2d05 781 #define RF_SYNCVALUE3_SYNCVALUE 0x01 // Default
GregCr 0:e6ceb13d2d05 782 #define RF_SYNCVALUE4_SYNCVALUE 0x01 // Default
GregCr 0:e6ceb13d2d05 783 #define RF_SYNCVALUE5_SYNCVALUE 0x01 // Default
GregCr 0:e6ceb13d2d05 784 #define RF_SYNCVALUE6_SYNCVALUE 0x01 // Default
GregCr 0:e6ceb13d2d05 785 #define RF_SYNCVALUE7_SYNCVALUE 0x01 // Default
GregCr 0:e6ceb13d2d05 786 #define RF_SYNCVALUE8_SYNCVALUE 0x01 // Default
GregCr 0:e6ceb13d2d05 787
GregCr 0:e6ceb13d2d05 788 /*!
GregCr 0:e6ceb13d2d05 789 * RegPacketConfig1
GregCr 0:e6ceb13d2d05 790 */
GregCr 0:e6ceb13d2d05 791 #define RF_PACKETCONFIG1_PACKETFORMAT_MASK 0x7F
GregCr 0:e6ceb13d2d05 792 #define RF_PACKETCONFIG1_PACKETFORMAT_FIXED 0x00
GregCr 0:e6ceb13d2d05 793 #define RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE 0x80 // Default
GregCr 0:e6ceb13d2d05 794
GregCr 0:e6ceb13d2d05 795 #define RF_PACKETCONFIG1_DCFREE_MASK 0x9F
GregCr 0:e6ceb13d2d05 796 #define RF_PACKETCONFIG1_DCFREE_OFF 0x00 // Default
GregCr 0:e6ceb13d2d05 797 #define RF_PACKETCONFIG1_DCFREE_MANCHESTER 0x20
GregCr 0:e6ceb13d2d05 798 #define RF_PACKETCONFIG1_DCFREE_WHITENING 0x40
GregCr 0:e6ceb13d2d05 799
GregCr 0:e6ceb13d2d05 800 #define RF_PACKETCONFIG1_CRC_MASK 0xEF
GregCr 0:e6ceb13d2d05 801 #define RF_PACKETCONFIG1_CRC_ON 0x10 // Default
GregCr 0:e6ceb13d2d05 802 #define RF_PACKETCONFIG1_CRC_OFF 0x00
GregCr 0:e6ceb13d2d05 803
GregCr 0:e6ceb13d2d05 804 #define RF_PACKETCONFIG1_CRCAUTOCLEAR_MASK 0xF7
GregCr 0:e6ceb13d2d05 805 #define RF_PACKETCONFIG1_CRCAUTOCLEAR_ON 0x00 // Default
GregCr 0:e6ceb13d2d05 806 #define RF_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08
GregCr 0:e6ceb13d2d05 807
GregCr 0:e6ceb13d2d05 808 #define RF_PACKETCONFIG1_ADDRSFILTERING_MASK 0xF9
GregCr 0:e6ceb13d2d05 809 #define RF_PACKETCONFIG1_ADDRSFILTERING_OFF 0x00 // Default
GregCr 0:e6ceb13d2d05 810 #define RF_PACKETCONFIG1_ADDRSFILTERING_NODE 0x02
GregCr 0:e6ceb13d2d05 811 #define RF_PACKETCONFIG1_ADDRSFILTERING_NODEBROADCAST 0x04
GregCr 0:e6ceb13d2d05 812
GregCr 0:e6ceb13d2d05 813 #define RF_PACKETCONFIG1_CRCWHITENINGTYPE_MASK 0xFE
GregCr 0:e6ceb13d2d05 814 #define RF_PACKETCONFIG1_CRCWHITENINGTYPE_CCITT 0x00 // Default
GregCr 0:e6ceb13d2d05 815 #define RF_PACKETCONFIG1_CRCWHITENINGTYPE_IBM 0x01
GregCr 0:e6ceb13d2d05 816
GregCr 0:e6ceb13d2d05 817 /*!
GregCr 0:e6ceb13d2d05 818 * RegPacketConfig2
GregCr 0:e6ceb13d2d05 819 */
GregCr 0:e6ceb13d2d05 820
GregCr 0:e6ceb13d2d05 821 #define RF_PACKETCONFIG2_WMBUS_CRC_ENABLE_MASK 0x7F
GregCr 0:e6ceb13d2d05 822 #define RF_PACKETCONFIG2_WMBUS_CRC_ENABLE 0x80
GregCr 0:e6ceb13d2d05 823 #define RF_PACKETCONFIG2_WMBUS_CRC_DISABLE 0x00 // Default
GregCr 0:e6ceb13d2d05 824
GregCr 0:e6ceb13d2d05 825 #define RF_PACKETCONFIG2_DATAMODE_MASK 0xBF
GregCr 0:e6ceb13d2d05 826 #define RF_PACKETCONFIG2_DATAMODE_CONTINUOUS 0x00
GregCr 0:e6ceb13d2d05 827 #define RF_PACKETCONFIG2_DATAMODE_PACKET 0x40 // Default
GregCr 0:e6ceb13d2d05 828
GregCr 0:e6ceb13d2d05 829 #define RF_PACKETCONFIG2_IOHOME_MASK 0xDF
GregCr 0:e6ceb13d2d05 830 #define RF_PACKETCONFIG2_IOHOME_ON 0x20
GregCr 0:e6ceb13d2d05 831 #define RF_PACKETCONFIG2_IOHOME_OFF 0x00 // Default
GregCr 0:e6ceb13d2d05 832
GregCr 0:e6ceb13d2d05 833 #define RF_PACKETCONFIG2_BEACON_MASK 0xF7
GregCr 0:e6ceb13d2d05 834 #define RF_PACKETCONFIG2_BEACON_ON 0x08
GregCr 0:e6ceb13d2d05 835 #define RF_PACKETCONFIG2_BEACON_OFF 0x00 // Default
GregCr 0:e6ceb13d2d05 836
GregCr 0:e6ceb13d2d05 837 #define RF_PACKETCONFIG2_PAYLOADLENGTH_MSB_MASK 0xF8
GregCr 0:e6ceb13d2d05 838
GregCr 0:e6ceb13d2d05 839 /*!
GregCr 0:e6ceb13d2d05 840 * RegPayloadLength
GregCr 0:e6ceb13d2d05 841 */
GregCr 0:e6ceb13d2d05 842 #define RF_PAYLOADLENGTH_LENGTH 0x40 // Default
GregCr 0:e6ceb13d2d05 843
GregCr 0:e6ceb13d2d05 844 /*!
GregCr 0:e6ceb13d2d05 845 * RegNodeAdrs
GregCr 0:e6ceb13d2d05 846 */
GregCr 0:e6ceb13d2d05 847 #define RF_NODEADDRESS_ADDRESS 0x00
GregCr 0:e6ceb13d2d05 848
GregCr 0:e6ceb13d2d05 849 /*!
GregCr 0:e6ceb13d2d05 850 * RegBroadcastAdrs
GregCr 0:e6ceb13d2d05 851 */
GregCr 0:e6ceb13d2d05 852 #define RF_BROADCASTADDRESS_ADDRESS 0x00
GregCr 0:e6ceb13d2d05 853
GregCr 0:e6ceb13d2d05 854 /*!
GregCr 0:e6ceb13d2d05 855 * RegFifoThresh
GregCr 0:e6ceb13d2d05 856 */
GregCr 0:e6ceb13d2d05 857 #define RF_FIFOTHRESH_TXSTARTCONDITION_MASK 0x7F
GregCr 0:e6ceb13d2d05 858 #define RF_FIFOTHRESH_TXSTARTCONDITION_FIFOTHRESH 0x00 // Default
GregCr 0:e6ceb13d2d05 859 #define RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY 0x80
GregCr 0:e6ceb13d2d05 860
GregCr 0:e6ceb13d2d05 861 #define RF_FIFOTHRESH_FIFOTHRESHOLD_MASK 0xC0
GregCr 0:e6ceb13d2d05 862 #define RF_FIFOTHRESH_FIFOTHRESHOLD_THRESHOLD 0x0F // Default
GregCr 0:e6ceb13d2d05 863
GregCr 0:e6ceb13d2d05 864 /*!
GregCr 0:e6ceb13d2d05 865 * RegSeqConfig1
GregCr 0:e6ceb13d2d05 866 */
GregCr 0:e6ceb13d2d05 867 #define RF_SEQCONFIG1_SEQUENCER_START 0x80
GregCr 0:e6ceb13d2d05 868
GregCr 0:e6ceb13d2d05 869 #define RF_SEQCONFIG1_SEQUENCER_STOP 0x40
GregCr 0:e6ceb13d2d05 870
GregCr 0:e6ceb13d2d05 871 #define RF_SEQCONFIG1_IDLEMODE_MASK 0xDF
GregCr 0:e6ceb13d2d05 872 #define RF_SEQCONFIG1_IDLEMODE_SLEEP 0x20
GregCr 0:e6ceb13d2d05 873 #define RF_SEQCONFIG1_IDLEMODE_STANDBY 0x00 // Default
GregCr 0:e6ceb13d2d05 874
GregCr 0:e6ceb13d2d05 875 #define RF_SEQCONFIG1_FROMSTART_MASK 0xE7
GregCr 0:e6ceb13d2d05 876 #define RF_SEQCONFIG1_FROMSTART_TOLPS 0x00 // Default
GregCr 0:e6ceb13d2d05 877 #define RF_SEQCONFIG1_FROMSTART_TORX 0x08
GregCr 0:e6ceb13d2d05 878 #define RF_SEQCONFIG1_FROMSTART_TOTX 0x10
GregCr 0:e6ceb13d2d05 879 #define RF_SEQCONFIG1_FROMSTART_TOTX_ONFIFOLEVEL 0x18
GregCr 0:e6ceb13d2d05 880
GregCr 0:e6ceb13d2d05 881 #define RF_SEQCONFIG1_LPS_MASK 0xFB
GregCr 0:e6ceb13d2d05 882 #define RF_SEQCONFIG1_LPS_SEQUENCER_OFF 0x00 // Default
GregCr 0:e6ceb13d2d05 883 #define RF_SEQCONFIG1_LPS_IDLE 0x04
GregCr 0:e6ceb13d2d05 884
GregCr 0:e6ceb13d2d05 885 #define RF_SEQCONFIG1_FROMIDLE_MASK 0xFD
GregCr 0:e6ceb13d2d05 886 #define RF_SEQCONFIG1_FROMIDLE_TOTX 0x00 // Default
GregCr 0:e6ceb13d2d05 887 #define RF_SEQCONFIG1_FROMIDLE_TORX 0x02
GregCr 0:e6ceb13d2d05 888
GregCr 0:e6ceb13d2d05 889 #define RF_SEQCONFIG1_FROMTX_MASK 0xFE
GregCr 0:e6ceb13d2d05 890 #define RF_SEQCONFIG1_FROMTX_TOLPS 0x00 // Default
GregCr 0:e6ceb13d2d05 891 #define RF_SEQCONFIG1_FROMTX_TORX 0x01
GregCr 0:e6ceb13d2d05 892
GregCr 0:e6ceb13d2d05 893 /*!
GregCr 0:e6ceb13d2d05 894 * RegSeqConfig2
GregCr 0:e6ceb13d2d05 895 */
GregCr 0:e6ceb13d2d05 896 #define RF_SEQCONFIG2_FROMRX_MASK 0x1F
GregCr 0:e6ceb13d2d05 897 #define RF_SEQCONFIG2_FROMRX_TOUNUSED_000 0x00 // Default
GregCr 0:e6ceb13d2d05 898 #define RF_SEQCONFIG2_FROMRX_TORXPKT_ONPLDRDY 0x20
GregCr 0:e6ceb13d2d05 899 #define RF_SEQCONFIG2_FROMRX_TOLPS_ONPLDRDY 0x40
GregCr 0:e6ceb13d2d05 900 #define RF_SEQCONFIG2_FROMRX_TORXPKT_ONCRCOK 0x60
GregCr 0:e6ceb13d2d05 901 #define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONRSSI 0x80
GregCr 0:e6ceb13d2d05 902 #define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONSYNC 0xA0
GregCr 0:e6ceb13d2d05 903 #define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONPREAMBLE 0xC0
GregCr 0:e6ceb13d2d05 904 #define RF_SEQCONFIG2_FROMRX_TOUNUSED_111 0xE0
GregCr 0:e6ceb13d2d05 905
GregCr 0:e6ceb13d2d05 906 #define RF_SEQCONFIG2_FROMRXTIMEOUT_MASK 0xE7
GregCr 0:e6ceb13d2d05 907 #define RF_SEQCONFIG2_FROMRXTIMEOUT_TORXRESTART 0x00 // Default
GregCr 0:e6ceb13d2d05 908 #define RF_SEQCONFIG2_FROMRXTIMEOUT_TOTX 0x08
GregCr 0:e6ceb13d2d05 909 #define RF_SEQCONFIG2_FROMRXTIMEOUT_TOLPS 0x10
GregCr 0:e6ceb13d2d05 910 #define RF_SEQCONFIG2_FROMRXTIMEOUT_TOSEQUENCEROFF 0x18
GregCr 0:e6ceb13d2d05 911
GregCr 0:e6ceb13d2d05 912 #define RF_SEQCONFIG2_FROMRXPKT_MASK 0xF8
GregCr 0:e6ceb13d2d05 913 #define RF_SEQCONFIG2_FROMRXPKT_TOSEQUENCEROFF 0x00 // Default
GregCr 0:e6ceb13d2d05 914 #define RF_SEQCONFIG2_FROMRXPKT_TOTX_ONFIFOEMPTY 0x01
GregCr 0:e6ceb13d2d05 915 #define RF_SEQCONFIG2_FROMRXPKT_TOLPS 0x02
GregCr 0:e6ceb13d2d05 916 #define RF_SEQCONFIG2_FROMRXPKT_TOSYNTHESIZERRX 0x03
GregCr 0:e6ceb13d2d05 917 #define RF_SEQCONFIG2_FROMRXPKT_TORX 0x04
GregCr 0:e6ceb13d2d05 918
GregCr 0:e6ceb13d2d05 919 /*!
GregCr 0:e6ceb13d2d05 920 * RegTimerResol
GregCr 0:e6ceb13d2d05 921 */
GregCr 0:e6ceb13d2d05 922 #define RF_TIMERRESOL_TIMER1RESOL_MASK 0xF3
GregCr 0:e6ceb13d2d05 923 #define RF_TIMERRESOL_TIMER1RESOL_OFF 0x00 // Default
GregCr 0:e6ceb13d2d05 924 #define RF_TIMERRESOL_TIMER1RESOL_000064_US 0x04
GregCr 0:e6ceb13d2d05 925 #define RF_TIMERRESOL_TIMER1RESOL_004100_US 0x08
GregCr 0:e6ceb13d2d05 926 #define RF_TIMERRESOL_TIMER1RESOL_262000_US 0x0C
GregCr 0:e6ceb13d2d05 927
GregCr 0:e6ceb13d2d05 928 #define RF_TIMERRESOL_TIMER2RESOL_MASK 0xFC
GregCr 0:e6ceb13d2d05 929 #define RF_TIMERRESOL_TIMER2RESOL_OFF 0x00 // Default
GregCr 0:e6ceb13d2d05 930 #define RF_TIMERRESOL_TIMER2RESOL_000064_US 0x01
GregCr 0:e6ceb13d2d05 931 #define RF_TIMERRESOL_TIMER2RESOL_004100_US 0x02
GregCr 0:e6ceb13d2d05 932 #define RF_TIMERRESOL_TIMER2RESOL_262000_US 0x03
GregCr 0:e6ceb13d2d05 933
GregCr 0:e6ceb13d2d05 934 /*!
GregCr 0:e6ceb13d2d05 935 * RegTimer1Coef
GregCr 0:e6ceb13d2d05 936 */
GregCr 0:e6ceb13d2d05 937 #define RF_TIMER1COEF_TIMER1COEFFICIENT 0xF5 // Default
GregCr 0:e6ceb13d2d05 938
GregCr 0:e6ceb13d2d05 939 /*!
GregCr 0:e6ceb13d2d05 940 * RegTimer2Coef
GregCr 0:e6ceb13d2d05 941 */
GregCr 0:e6ceb13d2d05 942 #define RF_TIMER2COEF_TIMER2COEFFICIENT 0x20 // Default
GregCr 0:e6ceb13d2d05 943
GregCr 0:e6ceb13d2d05 944 /*!
GregCr 0:e6ceb13d2d05 945 * RegImageCal
GregCr 0:e6ceb13d2d05 946 */
GregCr 0:e6ceb13d2d05 947 #define RF_IMAGECAL_AUTOIMAGECAL_MASK 0x7F
GregCr 0:e6ceb13d2d05 948 #define RF_IMAGECAL_AUTOIMAGECAL_ON 0x80
GregCr 0:e6ceb13d2d05 949 #define RF_IMAGECAL_AUTOIMAGECAL_OFF 0x00 // Default
GregCr 0:e6ceb13d2d05 950
GregCr 0:e6ceb13d2d05 951 #define RF_IMAGECAL_IMAGECAL_MASK 0xBF
GregCr 0:e6ceb13d2d05 952 #define RF_IMAGECAL_IMAGECAL_START 0x40
GregCr 0:e6ceb13d2d05 953
GregCr 0:e6ceb13d2d05 954 #define RF_IMAGECAL_IMAGECAL_RUNNING 0x20
GregCr 0:e6ceb13d2d05 955 #define RF_IMAGECAL_IMAGECAL_DONE 0x00 // Default
GregCr 0:e6ceb13d2d05 956
GregCr 0:e6ceb13d2d05 957 #define RF_IMAGECAL_TEMPCHANGE_HIGHER 0x08
GregCr 0:e6ceb13d2d05 958 #define RF_IMAGECAL_TEMPCHANGE_LOWER 0x00
GregCr 0:e6ceb13d2d05 959
GregCr 0:e6ceb13d2d05 960 #define RF_IMAGECAL_TEMPTHRESHOLD_MASK 0xF9
GregCr 0:e6ceb13d2d05 961 #define RF_IMAGECAL_TEMPTHRESHOLD_05 0x00
GregCr 0:e6ceb13d2d05 962 #define RF_IMAGECAL_TEMPTHRESHOLD_10 0x02 // Default
GregCr 0:e6ceb13d2d05 963 #define RF_IMAGECAL_TEMPTHRESHOLD_15 0x04
GregCr 0:e6ceb13d2d05 964 #define RF_IMAGECAL_TEMPTHRESHOLD_20 0x06
GregCr 0:e6ceb13d2d05 965
GregCr 0:e6ceb13d2d05 966 #define RF_IMAGECAL_TEMPMONITOR_MASK 0xFE
GregCr 0:e6ceb13d2d05 967 #define RF_IMAGECAL_TEMPMONITOR_ON 0x00 // Default
GregCr 0:e6ceb13d2d05 968 #define RF_IMAGECAL_TEMPMONITOR_OFF 0x01
GregCr 0:e6ceb13d2d05 969
GregCr 0:e6ceb13d2d05 970 /*!
mluis 22:7f3aab69cca9 971 * RegTemp (Read Only)
GregCr 0:e6ceb13d2d05 972 */
GregCr 0:e6ceb13d2d05 973
GregCr 0:e6ceb13d2d05 974 /*!
GregCr 0:e6ceb13d2d05 975 * RegLowBat
GregCr 0:e6ceb13d2d05 976 */
GregCr 0:e6ceb13d2d05 977 #define RF_LOWBAT_MASK 0xF7
GregCr 0:e6ceb13d2d05 978 #define RF_LOWBAT_ON 0x08
GregCr 0:e6ceb13d2d05 979 #define RF_LOWBAT_OFF 0x00 // Default
GregCr 0:e6ceb13d2d05 980
GregCr 0:e6ceb13d2d05 981 #define RF_LOWBAT_TRIM_MASK 0xF8
GregCr 0:e6ceb13d2d05 982 #define RF_LOWBAT_TRIM_1695 0x00
GregCr 0:e6ceb13d2d05 983 #define RF_LOWBAT_TRIM_1764 0x01
GregCr 0:e6ceb13d2d05 984 #define RF_LOWBAT_TRIM_1835 0x02 // Default
GregCr 0:e6ceb13d2d05 985 #define RF_LOWBAT_TRIM_1905 0x03
GregCr 0:e6ceb13d2d05 986 #define RF_LOWBAT_TRIM_1976 0x04
GregCr 0:e6ceb13d2d05 987 #define RF_LOWBAT_TRIM_2045 0x05
GregCr 0:e6ceb13d2d05 988 #define RF_LOWBAT_TRIM_2116 0x06
GregCr 0:e6ceb13d2d05 989 #define RF_LOWBAT_TRIM_2185 0x07
GregCr 0:e6ceb13d2d05 990
GregCr 0:e6ceb13d2d05 991 /*!
GregCr 0:e6ceb13d2d05 992 * RegIrqFlags1
GregCr 0:e6ceb13d2d05 993 */
GregCr 0:e6ceb13d2d05 994 #define RF_IRQFLAGS1_MODEREADY 0x80
GregCr 0:e6ceb13d2d05 995
GregCr 0:e6ceb13d2d05 996 #define RF_IRQFLAGS1_RXREADY 0x40
GregCr 0:e6ceb13d2d05 997
GregCr 0:e6ceb13d2d05 998 #define RF_IRQFLAGS1_TXREADY 0x20
GregCr 0:e6ceb13d2d05 999
GregCr 0:e6ceb13d2d05 1000 #define RF_IRQFLAGS1_PLLLOCK 0x10
GregCr 0:e6ceb13d2d05 1001
GregCr 0:e6ceb13d2d05 1002 #define RF_IRQFLAGS1_RSSI 0x08
GregCr 0:e6ceb13d2d05 1003
GregCr 0:e6ceb13d2d05 1004 #define RF_IRQFLAGS1_TIMEOUT 0x04
GregCr 0:e6ceb13d2d05 1005
GregCr 0:e6ceb13d2d05 1006 #define RF_IRQFLAGS1_PREAMBLEDETECT 0x02
GregCr 0:e6ceb13d2d05 1007
GregCr 0:e6ceb13d2d05 1008 #define RF_IRQFLAGS1_SYNCADDRESSMATCH 0x01
GregCr 0:e6ceb13d2d05 1009
GregCr 0:e6ceb13d2d05 1010 /*!
GregCr 0:e6ceb13d2d05 1011 * RegIrqFlags2
GregCr 0:e6ceb13d2d05 1012 */
GregCr 0:e6ceb13d2d05 1013 #define RF_IRQFLAGS2_FIFOFULL 0x80
GregCr 0:e6ceb13d2d05 1014
GregCr 0:e6ceb13d2d05 1015 #define RF_IRQFLAGS2_FIFOEMPTY 0x40
GregCr 0:e6ceb13d2d05 1016
GregCr 0:e6ceb13d2d05 1017 #define RF_IRQFLAGS2_FIFOLEVEL 0x20
GregCr 0:e6ceb13d2d05 1018
GregCr 0:e6ceb13d2d05 1019 #define RF_IRQFLAGS2_FIFOOVERRUN 0x10
GregCr 0:e6ceb13d2d05 1020
GregCr 0:e6ceb13d2d05 1021 #define RF_IRQFLAGS2_PACKETSENT 0x08
GregCr 0:e6ceb13d2d05 1022
GregCr 0:e6ceb13d2d05 1023 #define RF_IRQFLAGS2_PAYLOADREADY 0x04
GregCr 0:e6ceb13d2d05 1024
GregCr 0:e6ceb13d2d05 1025 #define RF_IRQFLAGS2_CRCOK 0x02
GregCr 0:e6ceb13d2d05 1026
GregCr 0:e6ceb13d2d05 1027 #define RF_IRQFLAGS2_LOWBAT 0x01
GregCr 0:e6ceb13d2d05 1028
GregCr 0:e6ceb13d2d05 1029 /*!
GregCr 0:e6ceb13d2d05 1030 * RegDioMapping1
GregCr 0:e6ceb13d2d05 1031 */
GregCr 0:e6ceb13d2d05 1032 #define RF_DIOMAPPING1_DIO0_MASK 0x3F
GregCr 0:e6ceb13d2d05 1033 #define RF_DIOMAPPING1_DIO0_00 0x00 // Default
GregCr 0:e6ceb13d2d05 1034 #define RF_DIOMAPPING1_DIO0_01 0x40
GregCr 0:e6ceb13d2d05 1035 #define RF_DIOMAPPING1_DIO0_10 0x80
GregCr 0:e6ceb13d2d05 1036 #define RF_DIOMAPPING1_DIO0_11 0xC0
GregCr 0:e6ceb13d2d05 1037
GregCr 0:e6ceb13d2d05 1038 #define RF_DIOMAPPING1_DIO1_MASK 0xCF
GregCr 0:e6ceb13d2d05 1039 #define RF_DIOMAPPING1_DIO1_00 0x00 // Default
GregCr 0:e6ceb13d2d05 1040 #define RF_DIOMAPPING1_DIO1_01 0x10
GregCr 0:e6ceb13d2d05 1041 #define RF_DIOMAPPING1_DIO1_10 0x20
GregCr 0:e6ceb13d2d05 1042 #define RF_DIOMAPPING1_DIO1_11 0x30
GregCr 0:e6ceb13d2d05 1043
GregCr 0:e6ceb13d2d05 1044 #define RF_DIOMAPPING1_DIO2_MASK 0xF3
GregCr 0:e6ceb13d2d05 1045 #define RF_DIOMAPPING1_DIO2_00 0x00 // Default
GregCr 0:e6ceb13d2d05 1046 #define RF_DIOMAPPING1_DIO2_01 0x04
GregCr 0:e6ceb13d2d05 1047 #define RF_DIOMAPPING1_DIO2_10 0x08
GregCr 0:e6ceb13d2d05 1048 #define RF_DIOMAPPING1_DIO2_11 0x0C
GregCr 0:e6ceb13d2d05 1049
GregCr 0:e6ceb13d2d05 1050 #define RF_DIOMAPPING1_DIO3_MASK 0xFC
GregCr 0:e6ceb13d2d05 1051 #define RF_DIOMAPPING1_DIO3_00 0x00 // Default
GregCr 0:e6ceb13d2d05 1052 #define RF_DIOMAPPING1_DIO3_01 0x01
GregCr 0:e6ceb13d2d05 1053 #define RF_DIOMAPPING1_DIO3_10 0x02
GregCr 0:e6ceb13d2d05 1054 #define RF_DIOMAPPING1_DIO3_11 0x03
GregCr 0:e6ceb13d2d05 1055
GregCr 0:e6ceb13d2d05 1056 /*!
GregCr 0:e6ceb13d2d05 1057 * RegDioMapping2
GregCr 0:e6ceb13d2d05 1058 */
GregCr 0:e6ceb13d2d05 1059 #define RF_DIOMAPPING2_DIO4_MASK 0x3F
GregCr 0:e6ceb13d2d05 1060 #define RF_DIOMAPPING2_DIO4_00 0x00 // Default
GregCr 0:e6ceb13d2d05 1061 #define RF_DIOMAPPING2_DIO4_01 0x40
GregCr 0:e6ceb13d2d05 1062 #define RF_DIOMAPPING2_DIO4_10 0x80
GregCr 0:e6ceb13d2d05 1063 #define RF_DIOMAPPING2_DIO4_11 0xC0
GregCr 0:e6ceb13d2d05 1064
GregCr 0:e6ceb13d2d05 1065 #define RF_DIOMAPPING2_DIO5_MASK 0xCF
GregCr 0:e6ceb13d2d05 1066 #define RF_DIOMAPPING2_DIO5_00 0x00 // Default
GregCr 0:e6ceb13d2d05 1067 #define RF_DIOMAPPING2_DIO5_01 0x10
GregCr 0:e6ceb13d2d05 1068 #define RF_DIOMAPPING2_DIO5_10 0x20
GregCr 0:e6ceb13d2d05 1069 #define RF_DIOMAPPING2_DIO5_11 0x30
GregCr 0:e6ceb13d2d05 1070
GregCr 0:e6ceb13d2d05 1071 #define RF_DIOMAPPING2_MAP_MASK 0xFE
GregCr 0:e6ceb13d2d05 1072 #define RF_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01
GregCr 0:e6ceb13d2d05 1073 #define RF_DIOMAPPING2_MAP_RSSI 0x00 // Default
GregCr 0:e6ceb13d2d05 1074
GregCr 0:e6ceb13d2d05 1075 /*!
mluis 22:7f3aab69cca9 1076 * RegVersion (Read Only)
GregCr 0:e6ceb13d2d05 1077 */
GregCr 0:e6ceb13d2d05 1078
GregCr 0:e6ceb13d2d05 1079 /*!
GregCr 0:e6ceb13d2d05 1080 * RegPllHop
GregCr 0:e6ceb13d2d05 1081 */
GregCr 0:e6ceb13d2d05 1082 #define RF_PLLHOP_FASTHOP_MASK 0x7F
GregCr 0:e6ceb13d2d05 1083 #define RF_PLLHOP_FASTHOP_ON 0x80
GregCr 0:e6ceb13d2d05 1084 #define RF_PLLHOP_FASTHOP_OFF 0x00 // Default
GregCr 0:e6ceb13d2d05 1085
GregCr 0:e6ceb13d2d05 1086 /*!
GregCr 0:e6ceb13d2d05 1087 * RegTcxo
GregCr 0:e6ceb13d2d05 1088 */
GregCr 0:e6ceb13d2d05 1089 #define RF_TCXO_TCXOINPUT_MASK 0xEF
GregCr 0:e6ceb13d2d05 1090 #define RF_TCXO_TCXOINPUT_ON 0x10
GregCr 0:e6ceb13d2d05 1091 #define RF_TCXO_TCXOINPUT_OFF 0x00 // Default
GregCr 0:e6ceb13d2d05 1092
GregCr 0:e6ceb13d2d05 1093 /*!
GregCr 0:e6ceb13d2d05 1094 * RegPaDac
GregCr 0:e6ceb13d2d05 1095 */
GregCr 0:e6ceb13d2d05 1096 #define RF_PADAC_20DBM_MASK 0xF8
GregCr 0:e6ceb13d2d05 1097 #define RF_PADAC_20DBM_ON 0x07
GregCr 0:e6ceb13d2d05 1098 #define RF_PADAC_20DBM_OFF 0x04 // Default
GregCr 0:e6ceb13d2d05 1099
GregCr 0:e6ceb13d2d05 1100 /*!
GregCr 0:e6ceb13d2d05 1101 * RegFormerTemp
GregCr 0:e6ceb13d2d05 1102 */
GregCr 0:e6ceb13d2d05 1103
GregCr 0:e6ceb13d2d05 1104 /*!
GregCr 0:e6ceb13d2d05 1105 * RegBitrateFrac
GregCr 0:e6ceb13d2d05 1106 */
GregCr 0:e6ceb13d2d05 1107 #define RF_BITRATEFRAC_MASK 0xF0
GregCr 0:e6ceb13d2d05 1108
GregCr 0:e6ceb13d2d05 1109 /*!
GregCr 0:e6ceb13d2d05 1110 * RegAgcRef
GregCr 0:e6ceb13d2d05 1111 */
GregCr 0:e6ceb13d2d05 1112
GregCr 0:e6ceb13d2d05 1113 /*!
GregCr 0:e6ceb13d2d05 1114 * RegAgcThresh1
GregCr 0:e6ceb13d2d05 1115 */
GregCr 0:e6ceb13d2d05 1116
GregCr 0:e6ceb13d2d05 1117 /*!
GregCr 0:e6ceb13d2d05 1118 * RegAgcThresh2
GregCr 0:e6ceb13d2d05 1119 */
GregCr 0:e6ceb13d2d05 1120
GregCr 0:e6ceb13d2d05 1121 /*!
GregCr 0:e6ceb13d2d05 1122 * RegAgcThresh3
GregCr 0:e6ceb13d2d05 1123 */
GregCr 0:e6ceb13d2d05 1124
GregCr 0:e6ceb13d2d05 1125 /*!
GregCr 0:e6ceb13d2d05 1126 * RegPll
GregCr 0:e6ceb13d2d05 1127 */
GregCr 0:e6ceb13d2d05 1128 #define RF_PLL_BANDWIDTH_MASK 0x3F
GregCr 0:e6ceb13d2d05 1129 #define RF_PLL_BANDWIDTH_75 0x00
GregCr 0:e6ceb13d2d05 1130 #define RF_PLL_BANDWIDTH_150 0x40
GregCr 0:e6ceb13d2d05 1131 #define RF_PLL_BANDWIDTH_225 0x80
GregCr 0:e6ceb13d2d05 1132 #define RF_PLL_BANDWIDTH_300 0xC0 // Default
GregCr 0:e6ceb13d2d05 1133
GregCr 0:e6ceb13d2d05 1134 #endif // __SX1276_REGS_FSK_H__