Calmantara Sumpono Putra / encoder_hal

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encoderHAL.cpp@0:1c05321d03a4, 2019-04-10 (annotated)

Committer:
calmantara186
Date:
Wed Apr 10 19:48:18 2019 +0000
Revision:
0:1c05321d03a4
external encoder;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
calmantara186 0:1c05321d03a4 1 #include "encoderHAL.h"
calmantara186 0:1c05321d03a4 2
calmantara186 0:1c05321d03a4 3 namespace mbed
calmantara186 0:1c05321d03a4 4 {
calmantara186 0:1c05321d03a4 5
calmantara186 0:1c05321d03a4 6 encoderHAL::encoderHAL(TIM_TypeDef * _TIM)
calmantara186 0:1c05321d03a4 7 {
calmantara186 0:1c05321d03a4 8 TIM = _TIM;
calmantara186 0:1c05321d03a4 9 // Initialisation of the TIM module as an encoder counter
calmantara186 0:1c05321d03a4 10 EncoderInit(&encoder, &timer, _TIM, 0xffff, TIM_ENCODERMODE_TI12);
calmantara186 0:1c05321d03a4 11
calmantara186 0:1c05321d03a4 12 // Update (aka over- and underflow) interrupt enabled
calmantara186 0:1c05321d03a4 13 TIM->DIER |= 0x0001;
calmantara186 0:1c05321d03a4 14 // The initialisation process generates an update interrupt, so we'll have to clear the update flag before anything else
calmantara186 0:1c05321d03a4 15 TIM->SR &= 0xfffe;
calmantara186 0:1c05321d03a4 16 //generate update event
calmantara186 0:1c05321d03a4 17 TIM->EGR = 1;
calmantara186 0:1c05321d03a4 18 //enable counter
calmantara186 0:1c05321d03a4 19 TIM->CR1 = 1;
calmantara186 0:1c05321d03a4 20
calmantara186 0:1c05321d03a4 21 }
calmantara186 0:1c05321d03a4 22
calmantara186 0:1c05321d03a4 23 encoderHAL::encoderHAL(TIM_TypeDef * _TIM, uint32_t _maxcount, uint32_t _encmode)
calmantara186 0:1c05321d03a4 24 {
calmantara186 0:1c05321d03a4 25 TIM = _TIM;
calmantara186 0:1c05321d03a4 26 // Initialisation of the TIM module as an encoder counter
calmantara186 0:1c05321d03a4 27 EncoderInit(&encoder, &timer, _TIM, _maxcount, _encmode);
calmantara186 0:1c05321d03a4 28
calmantara186 0:1c05321d03a4 29 // Update (aka over- and underflow) interrupt enabled
calmantara186 0:1c05321d03a4 30 TIM->DIER |= 0x0001;
calmantara186 0:1c05321d03a4 31 // The initialisation process generates an update interrupt, so we'll have to clear the update flag before anything else
calmantara186 0:1c05321d03a4 32 TIM->SR &= 0xfffe;
calmantara186 0:1c05321d03a4 33 }
calmantara186 0:1c05321d03a4 34
calmantara186 0:1c05321d03a4 35 encoderHAL::encoderHAL(TIM_Encoder_InitTypeDef * _encoder, TIM_HandleTypeDef * _timer, TIM_TypeDef * _TIM, uint32_t _maxcount, uint32_t _encmode)
calmantara186 0:1c05321d03a4 36 {
calmantara186 0:1c05321d03a4 37 timer = *_timer;
calmantara186 0:1c05321d03a4 38 encoder = *_encoder;
calmantara186 0:1c05321d03a4 39 TIM = _TIM;
calmantara186 0:1c05321d03a4 40 // Initialisation of the TIM module as an encoder counter
calmantara186 0:1c05321d03a4 41 EncoderInit(&encoder, &timer, _TIM, _maxcount, _encmode);
calmantara186 0:1c05321d03a4 42
calmantara186 0:1c05321d03a4 43 // Update (aka over- and underflow) interrupt enabled
calmantara186 0:1c05321d03a4 44 TIM->DIER |= 0x0001;
calmantara186 0:1c05321d03a4 45 // The initialisation process generates an update interrupt, so we'll have to clear the update flag before anything else
calmantara186 0:1c05321d03a4 46 TIM->SR &= 0xfffe;
calmantara186 0:1c05321d03a4 47 }
calmantara186 0:1c05321d03a4 48
calmantara186 0:1c05321d03a4 49
calmantara186 0:1c05321d03a4 50 int32_t encoderHAL::getPulses(bool reset)
calmantara186 0:1c05321d03a4 51 {
calmantara186 0:1c05321d03a4 52 int16_t count = TIM->CNT;
calmantara186 0:1c05321d03a4 53 if(reset){
calmantara186 0:1c05321d03a4 54 switch((uint32_t)TIM){
calmantara186 0:1c05321d03a4 55 case TIM1_BASE :
calmantara186 0:1c05321d03a4 56 TIM1->CNT = 0;
calmantara186 0:1c05321d03a4 57 break;
calmantara186 0:1c05321d03a4 58
calmantara186 0:1c05321d03a4 59 case TIM2_BASE :
calmantara186 0:1c05321d03a4 60 TIM2->CNT = 0;
calmantara186 0:1c05321d03a4 61 break;
calmantara186 0:1c05321d03a4 62
calmantara186 0:1c05321d03a4 63 case TIM3_BASE :
calmantara186 0:1c05321d03a4 64 TIM3->CNT = 0;
calmantara186 0:1c05321d03a4 65 break;
calmantara186 0:1c05321d03a4 66
calmantara186 0:1c05321d03a4 67 case TIM4_BASE :
calmantara186 0:1c05321d03a4 68 TIM4->CNT = 0;
calmantara186 0:1c05321d03a4 69 break;
calmantara186 0:1c05321d03a4 70
calmantara186 0:1c05321d03a4 71 case TIM5_BASE :
calmantara186 0:1c05321d03a4 72 TIM5->CNT = 0;
calmantara186 0:1c05321d03a4 73 break;
calmantara186 0:1c05321d03a4 74
calmantara186 0:1c05321d03a4 75 case TIM8_BASE :
calmantara186 0:1c05321d03a4 76 TIM8->CNT = 0;
calmantara186 0:1c05321d03a4 77 break;
calmantara186 0:1c05321d03a4 78 }
calmantara186 0:1c05321d03a4 79 }
calmantara186 0:1c05321d03a4 80 else{
calmantara186 0:1c05321d03a4 81 switch((uint32_t)TIM)
calmantara186 0:1c05321d03a4 82 {
calmantara186 0:1c05321d03a4 83 case TIM1_BASE :
calmantara186 0:1c05321d03a4 84 return (int32_t)count;
calmantara186 0:1c05321d03a4 85
calmantara186 0:1c05321d03a4 86 case TIM2_BASE :
calmantara186 0:1c05321d03a4 87 return (int32_t)count;
calmantara186 0:1c05321d03a4 88
calmantara186 0:1c05321d03a4 89 case TIM3_BASE :
calmantara186 0:1c05321d03a4 90 return (int32_t)count;
calmantara186 0:1c05321d03a4 91
calmantara186 0:1c05321d03a4 92 case TIM4_BASE :
calmantara186 0:1c05321d03a4 93 return (int32_t)count;
calmantara186 0:1c05321d03a4 94
calmantara186 0:1c05321d03a4 95 case TIM5_BASE :
calmantara186 0:1c05321d03a4 96 return (int32_t)count;
calmantara186 0:1c05321d03a4 97
calmantara186 0:1c05321d03a4 98 case TIM8_BASE :
calmantara186 0:1c05321d03a4 99 return (int32_t)count;
calmantara186 0:1c05321d03a4 100 }
calmantara186 0:1c05321d03a4 101 }
calmantara186 0:1c05321d03a4 102
calmantara186 0:1c05321d03a4 103 return (int32_t)count;
calmantara186 0:1c05321d03a4 104 }
calmantara186 0:1c05321d03a4 105
calmantara186 0:1c05321d03a4 106
calmantara186 0:1c05321d03a4 107 TIM_HandleTypeDef* encoderHAL::GetTimer()
calmantara186 0:1c05321d03a4 108 {
calmantara186 0:1c05321d03a4 109 return &timer;
calmantara186 0:1c05321d03a4 110 }
calmantara186 0:1c05321d03a4 111
calmantara186 0:1c05321d03a4 112 }