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Serial_test_010_1/system_stm32l0xx.c@10:a1e81afb27ef, 2021-11-23 (annotated)

Committer:
caa45040
Date:
Tue Nov 23 21:43:04 2021 +0000
Revision:
10:a1e81afb27ef
Serial_test_010_1

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caa45040 10:a1e81afb27ef 1 /**
caa45040 10:a1e81afb27ef 2 ******************************************************************************
caa45040 10:a1e81afb27ef 3 * @file system_stm32l0xx.c
caa45040 10:a1e81afb27ef 4 * @author MCD Application Team
caa45040 10:a1e81afb27ef 5 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
caa45040 10:a1e81afb27ef 6 *
caa45040 10:a1e81afb27ef 7 * This file provides two functions and one global variable to be called from
caa45040 10:a1e81afb27ef 8 * user application:
caa45040 10:a1e81afb27ef 9 * - SystemInit(): This function is called at startup just after reset and
caa45040 10:a1e81afb27ef 10 * before branch to main program. This call is made inside
caa45040 10:a1e81afb27ef 11 * the "startup_stm32l0xx.s" file.
caa45040 10:a1e81afb27ef 12 *
caa45040 10:a1e81afb27ef 13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
caa45040 10:a1e81afb27ef 14 * by the user application to setup the SysTick
caa45040 10:a1e81afb27ef 15 * timer or configure other parameters.
caa45040 10:a1e81afb27ef 16 *
caa45040 10:a1e81afb27ef 17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
caa45040 10:a1e81afb27ef 18 * be called whenever the core clock is changed
caa45040 10:a1e81afb27ef 19 * during program execution.
caa45040 10:a1e81afb27ef 20 *
caa45040 10:a1e81afb27ef 21 *
caa45040 10:a1e81afb27ef 22 ******************************************************************************
caa45040 10:a1e81afb27ef 23 * @attention
caa45040 10:a1e81afb27ef 24 *
caa45040 10:a1e81afb27ef 25 * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
caa45040 10:a1e81afb27ef 26 * All rights reserved.</center></h2>
caa45040 10:a1e81afb27ef 27 *
caa45040 10:a1e81afb27ef 28 * This software component is licensed by ST under BSD 3-Clause license,
caa45040 10:a1e81afb27ef 29 * the "License"; You may not use this file except in compliance with the
caa45040 10:a1e81afb27ef 30 * License. You may obtain a copy of the License at:
caa45040 10:a1e81afb27ef 31 * opensource.org/licenses/BSD-3-Clause
caa45040 10:a1e81afb27ef 32 *
caa45040 10:a1e81afb27ef 33 ******************************************************************************
caa45040 10:a1e81afb27ef 34 */
caa45040 10:a1e81afb27ef 35
caa45040 10:a1e81afb27ef 36 /** @addtogroup CMSIS
caa45040 10:a1e81afb27ef 37 * @{
caa45040 10:a1e81afb27ef 38 */
caa45040 10:a1e81afb27ef 39
caa45040 10:a1e81afb27ef 40 /** @addtogroup stm32l0xx_system
caa45040 10:a1e81afb27ef 41 * @{
caa45040 10:a1e81afb27ef 42 */
caa45040 10:a1e81afb27ef 43
caa45040 10:a1e81afb27ef 44 /** @addtogroup STM32L0xx_System_Private_Includes
caa45040 10:a1e81afb27ef 45 * @{
caa45040 10:a1e81afb27ef 46 */
caa45040 10:a1e81afb27ef 47
caa45040 10:a1e81afb27ef 48 #include "stm32l0xx.h"
caa45040 10:a1e81afb27ef 49
caa45040 10:a1e81afb27ef 50 #if !defined (HSE_VALUE)
caa45040 10:a1e81afb27ef 51 #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
caa45040 10:a1e81afb27ef 52 #endif /* HSE_VALUE */
caa45040 10:a1e81afb27ef 53
caa45040 10:a1e81afb27ef 54 #if !defined (MSI_VALUE)
caa45040 10:a1e81afb27ef 55 #define MSI_VALUE ((uint32_t)2097152U) /*!< Value of the Internal oscillator in Hz*/
caa45040 10:a1e81afb27ef 56 #endif /* MSI_VALUE */
caa45040 10:a1e81afb27ef 57
caa45040 10:a1e81afb27ef 58 #if !defined (HSI_VALUE)
caa45040 10:a1e81afb27ef 59 #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
caa45040 10:a1e81afb27ef 60 #endif /* HSI_VALUE */
caa45040 10:a1e81afb27ef 61
caa45040 10:a1e81afb27ef 62
caa45040 10:a1e81afb27ef 63 /**
caa45040 10:a1e81afb27ef 64 * @}
caa45040 10:a1e81afb27ef 65 */
caa45040 10:a1e81afb27ef 66
caa45040 10:a1e81afb27ef 67 /** @addtogroup STM32L0xx_System_Private_TypesDefinitions
caa45040 10:a1e81afb27ef 68 * @{
caa45040 10:a1e81afb27ef 69 */
caa45040 10:a1e81afb27ef 70
caa45040 10:a1e81afb27ef 71 /**
caa45040 10:a1e81afb27ef 72 * @}
caa45040 10:a1e81afb27ef 73 */
caa45040 10:a1e81afb27ef 74
caa45040 10:a1e81afb27ef 75 /** @addtogroup STM32L0xx_System_Private_Defines
caa45040 10:a1e81afb27ef 76 * @{
caa45040 10:a1e81afb27ef 77 */
caa45040 10:a1e81afb27ef 78 /************************* Miscellaneous Configuration ************************/
caa45040 10:a1e81afb27ef 79
caa45040 10:a1e81afb27ef 80 /* Note: Following vector table addresses must be defined in line with linker
caa45040 10:a1e81afb27ef 81 configuration. */
caa45040 10:a1e81afb27ef 82 /*!< Uncomment the following line if you need to relocate the vector table
caa45040 10:a1e81afb27ef 83 anywhere in Flash or Sram, else the vector table is kept at the automatic
caa45040 10:a1e81afb27ef 84 remap of boot address selected */
caa45040 10:a1e81afb27ef 85 /* #define USER_VECT_TAB_ADDRESS */
caa45040 10:a1e81afb27ef 86
caa45040 10:a1e81afb27ef 87 #if defined(USER_VECT_TAB_ADDRESS)
caa45040 10:a1e81afb27ef 88 /*!< Uncomment the following line if you need to relocate your vector Table
caa45040 10:a1e81afb27ef 89 in Sram else user remap will be done in Flash. */
caa45040 10:a1e81afb27ef 90 /* #define VECT_TAB_SRAM */
caa45040 10:a1e81afb27ef 91 #if defined(VECT_TAB_SRAM)
caa45040 10:a1e81afb27ef 92 #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
caa45040 10:a1e81afb27ef 93 This value must be a multiple of 0x200. */
caa45040 10:a1e81afb27ef 94 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
caa45040 10:a1e81afb27ef 95 This value must be a multiple of 0x200. */
caa45040 10:a1e81afb27ef 96 #else
caa45040 10:a1e81afb27ef 97 #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
caa45040 10:a1e81afb27ef 98 This value must be a multiple of 0x200. */
caa45040 10:a1e81afb27ef 99 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
caa45040 10:a1e81afb27ef 100 This value must be a multiple of 0x200. */
caa45040 10:a1e81afb27ef 101 #endif /* VECT_TAB_SRAM */
caa45040 10:a1e81afb27ef 102 #endif /* USER_VECT_TAB_ADDRESS */
caa45040 10:a1e81afb27ef 103
caa45040 10:a1e81afb27ef 104 /******************************************************************************/
caa45040 10:a1e81afb27ef 105 /**
caa45040 10:a1e81afb27ef 106 * @}
caa45040 10:a1e81afb27ef 107 */
caa45040 10:a1e81afb27ef 108
caa45040 10:a1e81afb27ef 109 /** @addtogroup STM32L0xx_System_Private_Macros
caa45040 10:a1e81afb27ef 110 * @{
caa45040 10:a1e81afb27ef 111 */
caa45040 10:a1e81afb27ef 112
caa45040 10:a1e81afb27ef 113 /**
caa45040 10:a1e81afb27ef 114 * @}
caa45040 10:a1e81afb27ef 115 */
caa45040 10:a1e81afb27ef 116
caa45040 10:a1e81afb27ef 117 /** @addtogroup STM32L0xx_System_Private_Variables
caa45040 10:a1e81afb27ef 118 * @{
caa45040 10:a1e81afb27ef 119 */
caa45040 10:a1e81afb27ef 120 /* This variable is updated in three ways:
caa45040 10:a1e81afb27ef 121 1) by calling CMSIS function SystemCoreClockUpdate()
caa45040 10:a1e81afb27ef 122 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
caa45040 10:a1e81afb27ef 123 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
caa45040 10:a1e81afb27ef 124 Note: If you use this function to configure the system clock; then there
caa45040 10:a1e81afb27ef 125 is no need to call the 2 first functions listed above, since SystemCoreClock
caa45040 10:a1e81afb27ef 126 variable is updated automatically.
caa45040 10:a1e81afb27ef 127 */
caa45040 10:a1e81afb27ef 128 uint32_t SystemCoreClock = 2097152U; /* 32.768 kHz * 2^6 */
caa45040 10:a1e81afb27ef 129 const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
caa45040 10:a1e81afb27ef 130 const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
caa45040 10:a1e81afb27ef 131 const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
caa45040 10:a1e81afb27ef 132
caa45040 10:a1e81afb27ef 133 /**
caa45040 10:a1e81afb27ef 134 * @}
caa45040 10:a1e81afb27ef 135 */
caa45040 10:a1e81afb27ef 136
caa45040 10:a1e81afb27ef 137 /** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
caa45040 10:a1e81afb27ef 138 * @{
caa45040 10:a1e81afb27ef 139 */
caa45040 10:a1e81afb27ef 140
caa45040 10:a1e81afb27ef 141 /**
caa45040 10:a1e81afb27ef 142 * @}
caa45040 10:a1e81afb27ef 143 */
caa45040 10:a1e81afb27ef 144
caa45040 10:a1e81afb27ef 145 /** @addtogroup STM32L0xx_System_Private_Functions
caa45040 10:a1e81afb27ef 146 * @{
caa45040 10:a1e81afb27ef 147 */
caa45040 10:a1e81afb27ef 148
caa45040 10:a1e81afb27ef 149 /**
caa45040 10:a1e81afb27ef 150 * @brief Setup the microcontroller system.
caa45040 10:a1e81afb27ef 151 * @param None
caa45040 10:a1e81afb27ef 152 * @retval None
caa45040 10:a1e81afb27ef 153 */
caa45040 10:a1e81afb27ef 154 void SystemInit (void)
caa45040 10:a1e81afb27ef 155 {
caa45040 10:a1e81afb27ef 156 /* Configure the Vector Table location add offset address ------------------*/
caa45040 10:a1e81afb27ef 157 #if defined (USER_VECT_TAB_ADDRESS)
caa45040 10:a1e81afb27ef 158 SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
caa45040 10:a1e81afb27ef 159 #endif /* USER_VECT_TAB_ADDRESS */
caa45040 10:a1e81afb27ef 160 }
caa45040 10:a1e81afb27ef 161
caa45040 10:a1e81afb27ef 162 /**
caa45040 10:a1e81afb27ef 163 * @brief Update SystemCoreClock variable according to Clock Register Values.
caa45040 10:a1e81afb27ef 164 * The SystemCoreClock variable contains the core clock (HCLK), it can
caa45040 10:a1e81afb27ef 165 * be used by the user application to setup the SysTick timer or configure
caa45040 10:a1e81afb27ef 166 * other parameters.
caa45040 10:a1e81afb27ef 167 *
caa45040 10:a1e81afb27ef 168 * @note Each time the core clock (HCLK) changes, this function must be called
caa45040 10:a1e81afb27ef 169 * to update SystemCoreClock variable value. Otherwise, any configuration
caa45040 10:a1e81afb27ef 170 * based on this variable will be incorrect.
caa45040 10:a1e81afb27ef 171 *
caa45040 10:a1e81afb27ef 172 * @note - The system frequency computed by this function is not the real
caa45040 10:a1e81afb27ef 173 * frequency in the chip. It is calculated based on the predefined
caa45040 10:a1e81afb27ef 174 * constant and the selected clock source:
caa45040 10:a1e81afb27ef 175 *
caa45040 10:a1e81afb27ef 176 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
caa45040 10:a1e81afb27ef 177 * value as defined by the MSI range.
caa45040 10:a1e81afb27ef 178 *
caa45040 10:a1e81afb27ef 179 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
caa45040 10:a1e81afb27ef 180 *
caa45040 10:a1e81afb27ef 181 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
caa45040 10:a1e81afb27ef 182 *
caa45040 10:a1e81afb27ef 183 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
caa45040 10:a1e81afb27ef 184 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
caa45040 10:a1e81afb27ef 185 *
caa45040 10:a1e81afb27ef 186 * (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
caa45040 10:a1e81afb27ef 187 * 16 MHz) but the real value may vary depending on the variations
caa45040 10:a1e81afb27ef 188 * in voltage and temperature.
caa45040 10:a1e81afb27ef 189 *
caa45040 10:a1e81afb27ef 190 * (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
caa45040 10:a1e81afb27ef 191 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
caa45040 10:a1e81afb27ef 192 * frequency of the crystal used. Otherwise, this function may
caa45040 10:a1e81afb27ef 193 * have wrong result.
caa45040 10:a1e81afb27ef 194 *
caa45040 10:a1e81afb27ef 195 * - The result of this function could be not correct when using fractional
caa45040 10:a1e81afb27ef 196 * value for HSE crystal.
caa45040 10:a1e81afb27ef 197 * @param None
caa45040 10:a1e81afb27ef 198 * @retval None
caa45040 10:a1e81afb27ef 199 */
caa45040 10:a1e81afb27ef 200 void SystemCoreClockUpdate (void)
caa45040 10:a1e81afb27ef 201 {
caa45040 10:a1e81afb27ef 202 uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
caa45040 10:a1e81afb27ef 203
caa45040 10:a1e81afb27ef 204 /* Get SYSCLK source -------------------------------------------------------*/
caa45040 10:a1e81afb27ef 205 tmp = RCC->CFGR & RCC_CFGR_SWS;
caa45040 10:a1e81afb27ef 206
caa45040 10:a1e81afb27ef 207 switch (tmp)
caa45040 10:a1e81afb27ef 208 {
caa45040 10:a1e81afb27ef 209 case 0x00U: /* MSI used as system clock */
caa45040 10:a1e81afb27ef 210 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> RCC_ICSCR_MSIRANGE_Pos;
caa45040 10:a1e81afb27ef 211 SystemCoreClock = (32768U * (1U << (msirange + 1U)));
caa45040 10:a1e81afb27ef 212 break;
caa45040 10:a1e81afb27ef 213 case 0x04U: /* HSI used as system clock */
caa45040 10:a1e81afb27ef 214 if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
caa45040 10:a1e81afb27ef 215 {
caa45040 10:a1e81afb27ef 216 SystemCoreClock = HSI_VALUE / 4U;
caa45040 10:a1e81afb27ef 217 }
caa45040 10:a1e81afb27ef 218 else
caa45040 10:a1e81afb27ef 219 {
caa45040 10:a1e81afb27ef 220 SystemCoreClock = HSI_VALUE;
caa45040 10:a1e81afb27ef 221 }
caa45040 10:a1e81afb27ef 222 break;
caa45040 10:a1e81afb27ef 223 case 0x08U: /* HSE used as system clock */
caa45040 10:a1e81afb27ef 224 SystemCoreClock = HSE_VALUE;
caa45040 10:a1e81afb27ef 225 break;
caa45040 10:a1e81afb27ef 226 default: /* PLL used as system clock */
caa45040 10:a1e81afb27ef 227 /* Get PLL clock source and multiplication factor ----------------------*/
caa45040 10:a1e81afb27ef 228 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
caa45040 10:a1e81afb27ef 229 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
caa45040 10:a1e81afb27ef 230 pllmul = PLLMulTable[(pllmul >> RCC_CFGR_PLLMUL_Pos)];
caa45040 10:a1e81afb27ef 231 plldiv = (plldiv >> RCC_CFGR_PLLDIV_Pos) + 1U;
caa45040 10:a1e81afb27ef 232
caa45040 10:a1e81afb27ef 233 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
caa45040 10:a1e81afb27ef 234
caa45040 10:a1e81afb27ef 235 if (pllsource == 0x00U)
caa45040 10:a1e81afb27ef 236 {
caa45040 10:a1e81afb27ef 237 /* HSI oscillator clock selected as PLL clock entry */
caa45040 10:a1e81afb27ef 238 if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
caa45040 10:a1e81afb27ef 239 {
caa45040 10:a1e81afb27ef 240 SystemCoreClock = (((HSI_VALUE / 4U) * pllmul) / plldiv);
caa45040 10:a1e81afb27ef 241 }
caa45040 10:a1e81afb27ef 242 else
caa45040 10:a1e81afb27ef 243 {
caa45040 10:a1e81afb27ef 244 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
caa45040 10:a1e81afb27ef 245 }
caa45040 10:a1e81afb27ef 246 }
caa45040 10:a1e81afb27ef 247 else
caa45040 10:a1e81afb27ef 248 {
caa45040 10:a1e81afb27ef 249 /* HSE selected as PLL clock entry */
caa45040 10:a1e81afb27ef 250 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
caa45040 10:a1e81afb27ef 251 }
caa45040 10:a1e81afb27ef 252 break;
caa45040 10:a1e81afb27ef 253 }
caa45040 10:a1e81afb27ef 254 /* Compute HCLK clock frequency --------------------------------------------*/
caa45040 10:a1e81afb27ef 255 /* Get HCLK prescaler */
caa45040 10:a1e81afb27ef 256 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
caa45040 10:a1e81afb27ef 257 /* HCLK clock frequency */
caa45040 10:a1e81afb27ef 258 SystemCoreClock >>= tmp;
caa45040 10:a1e81afb27ef 259 }
caa45040 10:a1e81afb27ef 260
caa45040 10:a1e81afb27ef 261
caa45040 10:a1e81afb27ef 262
caa45040 10:a1e81afb27ef 263 /**
caa45040 10:a1e81afb27ef 264 * @}
caa45040 10:a1e81afb27ef 265 */
caa45040 10:a1e81afb27ef 266
caa45040 10:a1e81afb27ef 267 /**
caa45040 10:a1e81afb27ef 268 * @}
caa45040 10:a1e81afb27ef 269 */
caa45040 10:a1e81afb27ef 270
caa45040 10:a1e81afb27ef 271 /**
caa45040 10:a1e81afb27ef 272 * @}
caa45040 10:a1e81afb27ef 273 */
caa45040 10:a1e81afb27ef 274
caa45040 10:a1e81afb27ef 275 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
caa45040 10:a1e81afb27ef 276