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stm32f303_l_tika2/system_stm32f3xx.c@1:bad45e3ee8ec, 2021-11-17 (annotated)
- Committer:
- caa45040
- Date:
- Wed Nov 17 21:55:57 2021 +0000
- Revision:
- 1:bad45e3ee8ec
stm32f303k8 l_tika
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
caa45040 | 1:bad45e3ee8ec | 1 | /** |
caa45040 | 1:bad45e3ee8ec | 2 | ****************************************************************************** |
caa45040 | 1:bad45e3ee8ec | 3 | * @file system_stm32f3xx.c |
caa45040 | 1:bad45e3ee8ec | 4 | * @author MCD Application Team |
caa45040 | 1:bad45e3ee8ec | 5 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. |
caa45040 | 1:bad45e3ee8ec | 6 | * |
caa45040 | 1:bad45e3ee8ec | 7 | * 1. This file provides two functions and one global variable to be called from |
caa45040 | 1:bad45e3ee8ec | 8 | * user application: |
caa45040 | 1:bad45e3ee8ec | 9 | * - SystemInit(): This function is called at startup just after reset and |
caa45040 | 1:bad45e3ee8ec | 10 | * before branch to main program. This call is made inside |
caa45040 | 1:bad45e3ee8ec | 11 | * the "startup_stm32f3xx.s" file. |
caa45040 | 1:bad45e3ee8ec | 12 | * |
caa45040 | 1:bad45e3ee8ec | 13 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
caa45040 | 1:bad45e3ee8ec | 14 | * by the user application to setup the SysTick |
caa45040 | 1:bad45e3ee8ec | 15 | * timer or configure other parameters. |
caa45040 | 1:bad45e3ee8ec | 16 | * |
caa45040 | 1:bad45e3ee8ec | 17 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
caa45040 | 1:bad45e3ee8ec | 18 | * be called whenever the core clock is changed |
caa45040 | 1:bad45e3ee8ec | 19 | * during program execution. |
caa45040 | 1:bad45e3ee8ec | 20 | * |
caa45040 | 1:bad45e3ee8ec | 21 | * 2. After each device reset the HSI (8 MHz) is used as system clock source. |
caa45040 | 1:bad45e3ee8ec | 22 | * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to |
caa45040 | 1:bad45e3ee8ec | 23 | * configure the system clock before to branch to main program. |
caa45040 | 1:bad45e3ee8ec | 24 | * |
caa45040 | 1:bad45e3ee8ec | 25 | * 3. This file configures the system clock as follows: |
caa45040 | 1:bad45e3ee8ec | 26 | *============================================================================= |
caa45040 | 1:bad45e3ee8ec | 27 | * Supported STM32F3xx device |
caa45040 | 1:bad45e3ee8ec | 28 | *----------------------------------------------------------------------------- |
caa45040 | 1:bad45e3ee8ec | 29 | * System Clock source | HSI |
caa45040 | 1:bad45e3ee8ec | 30 | *----------------------------------------------------------------------------- |
caa45040 | 1:bad45e3ee8ec | 31 | * SYSCLK(Hz) | 8000000 |
caa45040 | 1:bad45e3ee8ec | 32 | *----------------------------------------------------------------------------- |
caa45040 | 1:bad45e3ee8ec | 33 | * HCLK(Hz) | 8000000 |
caa45040 | 1:bad45e3ee8ec | 34 | *----------------------------------------------------------------------------- |
caa45040 | 1:bad45e3ee8ec | 35 | * AHB Prescaler | 1 |
caa45040 | 1:bad45e3ee8ec | 36 | *----------------------------------------------------------------------------- |
caa45040 | 1:bad45e3ee8ec | 37 | * APB2 Prescaler | 1 |
caa45040 | 1:bad45e3ee8ec | 38 | *----------------------------------------------------------------------------- |
caa45040 | 1:bad45e3ee8ec | 39 | * APB1 Prescaler | 1 |
caa45040 | 1:bad45e3ee8ec | 40 | *----------------------------------------------------------------------------- |
caa45040 | 1:bad45e3ee8ec | 41 | * USB Clock | DISABLE |
caa45040 | 1:bad45e3ee8ec | 42 | *----------------------------------------------------------------------------- |
caa45040 | 1:bad45e3ee8ec | 43 | *============================================================================= |
caa45040 | 1:bad45e3ee8ec | 44 | ****************************************************************************** |
caa45040 | 1:bad45e3ee8ec | 45 | * @attention |
caa45040 | 1:bad45e3ee8ec | 46 | * |
caa45040 | 1:bad45e3ee8ec | 47 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
caa45040 | 1:bad45e3ee8ec | 48 | * All rights reserved.</center></h2> |
caa45040 | 1:bad45e3ee8ec | 49 | * |
caa45040 | 1:bad45e3ee8ec | 50 | * This software component is licensed by ST under BSD 3-Clause license, |
caa45040 | 1:bad45e3ee8ec | 51 | * the "License"; You may not use this file except in compliance with the |
caa45040 | 1:bad45e3ee8ec | 52 | * License. You may obtain a copy of the License at: |
caa45040 | 1:bad45e3ee8ec | 53 | * opensource.org/licenses/BSD-3-Clause |
caa45040 | 1:bad45e3ee8ec | 54 | * |
caa45040 | 1:bad45e3ee8ec | 55 | ****************************************************************************** |
caa45040 | 1:bad45e3ee8ec | 56 | */ |
caa45040 | 1:bad45e3ee8ec | 57 | |
caa45040 | 1:bad45e3ee8ec | 58 | /** @addtogroup CMSIS |
caa45040 | 1:bad45e3ee8ec | 59 | * @{ |
caa45040 | 1:bad45e3ee8ec | 60 | */ |
caa45040 | 1:bad45e3ee8ec | 61 | |
caa45040 | 1:bad45e3ee8ec | 62 | /** @addtogroup stm32f3xx_system |
caa45040 | 1:bad45e3ee8ec | 63 | * @{ |
caa45040 | 1:bad45e3ee8ec | 64 | */ |
caa45040 | 1:bad45e3ee8ec | 65 | |
caa45040 | 1:bad45e3ee8ec | 66 | /** @addtogroup STM32F3xx_System_Private_Includes |
caa45040 | 1:bad45e3ee8ec | 67 | * @{ |
caa45040 | 1:bad45e3ee8ec | 68 | */ |
caa45040 | 1:bad45e3ee8ec | 69 | |
caa45040 | 1:bad45e3ee8ec | 70 | #include "stm32f3xx.h" |
caa45040 | 1:bad45e3ee8ec | 71 | |
caa45040 | 1:bad45e3ee8ec | 72 | /** |
caa45040 | 1:bad45e3ee8ec | 73 | * @} |
caa45040 | 1:bad45e3ee8ec | 74 | */ |
caa45040 | 1:bad45e3ee8ec | 75 | |
caa45040 | 1:bad45e3ee8ec | 76 | /** @addtogroup STM32F3xx_System_Private_TypesDefinitions |
caa45040 | 1:bad45e3ee8ec | 77 | * @{ |
caa45040 | 1:bad45e3ee8ec | 78 | */ |
caa45040 | 1:bad45e3ee8ec | 79 | |
caa45040 | 1:bad45e3ee8ec | 80 | /** |
caa45040 | 1:bad45e3ee8ec | 81 | * @} |
caa45040 | 1:bad45e3ee8ec | 82 | */ |
caa45040 | 1:bad45e3ee8ec | 83 | |
caa45040 | 1:bad45e3ee8ec | 84 | /** @addtogroup STM32F3xx_System_Private_Defines |
caa45040 | 1:bad45e3ee8ec | 85 | * @{ |
caa45040 | 1:bad45e3ee8ec | 86 | */ |
caa45040 | 1:bad45e3ee8ec | 87 | #if !defined (HSE_VALUE) |
caa45040 | 1:bad45e3ee8ec | 88 | #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. |
caa45040 | 1:bad45e3ee8ec | 89 | This value can be provided and adapted by the user application. */ |
caa45040 | 1:bad45e3ee8ec | 90 | #endif /* HSE_VALUE */ |
caa45040 | 1:bad45e3ee8ec | 91 | |
caa45040 | 1:bad45e3ee8ec | 92 | #if !defined (HSI_VALUE) |
caa45040 | 1:bad45e3ee8ec | 93 | #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. |
caa45040 | 1:bad45e3ee8ec | 94 | This value can be provided and adapted by the user application. */ |
caa45040 | 1:bad45e3ee8ec | 95 | #endif /* HSI_VALUE */ |
caa45040 | 1:bad45e3ee8ec | 96 | |
caa45040 | 1:bad45e3ee8ec | 97 | /* Note: Following vector table addresses must be defined in line with linker |
caa45040 | 1:bad45e3ee8ec | 98 | configuration. */ |
caa45040 | 1:bad45e3ee8ec | 99 | /*!< Uncomment the following line if you need to relocate the vector table |
caa45040 | 1:bad45e3ee8ec | 100 | anywhere in Flash or Sram, else the vector table is kept at the automatic |
caa45040 | 1:bad45e3ee8ec | 101 | remap of boot address selected */ |
caa45040 | 1:bad45e3ee8ec | 102 | /* #define USER_VECT_TAB_ADDRESS */ |
caa45040 | 1:bad45e3ee8ec | 103 | |
caa45040 | 1:bad45e3ee8ec | 104 | #if defined(USER_VECT_TAB_ADDRESS) |
caa45040 | 1:bad45e3ee8ec | 105 | /*!< Uncomment the following line if you need to relocate your vector Table |
caa45040 | 1:bad45e3ee8ec | 106 | in Sram else user remap will be done in Flash. */ |
caa45040 | 1:bad45e3ee8ec | 107 | /* #define VECT_TAB_SRAM */ |
caa45040 | 1:bad45e3ee8ec | 108 | #if defined(VECT_TAB_SRAM) |
caa45040 | 1:bad45e3ee8ec | 109 | #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. |
caa45040 | 1:bad45e3ee8ec | 110 | This value must be a multiple of 0x200. */ |
caa45040 | 1:bad45e3ee8ec | 111 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. |
caa45040 | 1:bad45e3ee8ec | 112 | This value must be a multiple of 0x200. */ |
caa45040 | 1:bad45e3ee8ec | 113 | #else |
caa45040 | 1:bad45e3ee8ec | 114 | #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. |
caa45040 | 1:bad45e3ee8ec | 115 | This value must be a multiple of 0x200. */ |
caa45040 | 1:bad45e3ee8ec | 116 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. |
caa45040 | 1:bad45e3ee8ec | 117 | This value must be a multiple of 0x200. */ |
caa45040 | 1:bad45e3ee8ec | 118 | #endif /* VECT_TAB_SRAM */ |
caa45040 | 1:bad45e3ee8ec | 119 | #endif /* USER_VECT_TAB_ADDRESS */ |
caa45040 | 1:bad45e3ee8ec | 120 | |
caa45040 | 1:bad45e3ee8ec | 121 | /******************************************************************************/ |
caa45040 | 1:bad45e3ee8ec | 122 | /** |
caa45040 | 1:bad45e3ee8ec | 123 | * @} |
caa45040 | 1:bad45e3ee8ec | 124 | */ |
caa45040 | 1:bad45e3ee8ec | 125 | |
caa45040 | 1:bad45e3ee8ec | 126 | /** @addtogroup STM32F3xx_System_Private_Macros |
caa45040 | 1:bad45e3ee8ec | 127 | * @{ |
caa45040 | 1:bad45e3ee8ec | 128 | */ |
caa45040 | 1:bad45e3ee8ec | 129 | |
caa45040 | 1:bad45e3ee8ec | 130 | /** |
caa45040 | 1:bad45e3ee8ec | 131 | * @} |
caa45040 | 1:bad45e3ee8ec | 132 | */ |
caa45040 | 1:bad45e3ee8ec | 133 | |
caa45040 | 1:bad45e3ee8ec | 134 | /** @addtogroup STM32F3xx_System_Private_Variables |
caa45040 | 1:bad45e3ee8ec | 135 | * @{ |
caa45040 | 1:bad45e3ee8ec | 136 | */ |
caa45040 | 1:bad45e3ee8ec | 137 | /* This variable is updated in three ways: |
caa45040 | 1:bad45e3ee8ec | 138 | 1) by calling CMSIS function SystemCoreClockUpdate() |
caa45040 | 1:bad45e3ee8ec | 139 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
caa45040 | 1:bad45e3ee8ec | 140 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
caa45040 | 1:bad45e3ee8ec | 141 | Note: If you use this function to configure the system clock there is no need to |
caa45040 | 1:bad45e3ee8ec | 142 | call the 2 first functions listed above, since SystemCoreClock variable is |
caa45040 | 1:bad45e3ee8ec | 143 | updated automatically. |
caa45040 | 1:bad45e3ee8ec | 144 | */ |
caa45040 | 1:bad45e3ee8ec | 145 | uint32_t SystemCoreClock = 8000000; |
caa45040 | 1:bad45e3ee8ec | 146 | |
caa45040 | 1:bad45e3ee8ec | 147 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
caa45040 | 1:bad45e3ee8ec | 148 | const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; |
caa45040 | 1:bad45e3ee8ec | 149 | |
caa45040 | 1:bad45e3ee8ec | 150 | /** |
caa45040 | 1:bad45e3ee8ec | 151 | * @} |
caa45040 | 1:bad45e3ee8ec | 152 | */ |
caa45040 | 1:bad45e3ee8ec | 153 | |
caa45040 | 1:bad45e3ee8ec | 154 | /** @addtogroup STM32F3xx_System_Private_FunctionPrototypes |
caa45040 | 1:bad45e3ee8ec | 155 | * @{ |
caa45040 | 1:bad45e3ee8ec | 156 | */ |
caa45040 | 1:bad45e3ee8ec | 157 | |
caa45040 | 1:bad45e3ee8ec | 158 | /** |
caa45040 | 1:bad45e3ee8ec | 159 | * @} |
caa45040 | 1:bad45e3ee8ec | 160 | */ |
caa45040 | 1:bad45e3ee8ec | 161 | |
caa45040 | 1:bad45e3ee8ec | 162 | /** @addtogroup STM32F3xx_System_Private_Functions |
caa45040 | 1:bad45e3ee8ec | 163 | * @{ |
caa45040 | 1:bad45e3ee8ec | 164 | */ |
caa45040 | 1:bad45e3ee8ec | 165 | |
caa45040 | 1:bad45e3ee8ec | 166 | /** |
caa45040 | 1:bad45e3ee8ec | 167 | * @brief Setup the microcontroller system |
caa45040 | 1:bad45e3ee8ec | 168 | * @param None |
caa45040 | 1:bad45e3ee8ec | 169 | * @retval None |
caa45040 | 1:bad45e3ee8ec | 170 | */ |
caa45040 | 1:bad45e3ee8ec | 171 | void SystemInit(void) |
caa45040 | 1:bad45e3ee8ec | 172 | { |
caa45040 | 1:bad45e3ee8ec | 173 | /* FPU settings --------------------------------------------------------------*/ |
caa45040 | 1:bad45e3ee8ec | 174 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
caa45040 | 1:bad45e3ee8ec | 175 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ |
caa45040 | 1:bad45e3ee8ec | 176 | #endif |
caa45040 | 1:bad45e3ee8ec | 177 | |
caa45040 | 1:bad45e3ee8ec | 178 | /* Configure the Vector Table location -------------------------------------*/ |
caa45040 | 1:bad45e3ee8ec | 179 | #if defined(USER_VECT_TAB_ADDRESS) |
caa45040 | 1:bad45e3ee8ec | 180 | SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
caa45040 | 1:bad45e3ee8ec | 181 | #endif /* USER_VECT_TAB_ADDRESS */ |
caa45040 | 1:bad45e3ee8ec | 182 | } |
caa45040 | 1:bad45e3ee8ec | 183 | |
caa45040 | 1:bad45e3ee8ec | 184 | /** |
caa45040 | 1:bad45e3ee8ec | 185 | * @brief Update SystemCoreClock variable according to Clock Register Values. |
caa45040 | 1:bad45e3ee8ec | 186 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
caa45040 | 1:bad45e3ee8ec | 187 | * be used by the user application to setup the SysTick timer or configure |
caa45040 | 1:bad45e3ee8ec | 188 | * other parameters. |
caa45040 | 1:bad45e3ee8ec | 189 | * |
caa45040 | 1:bad45e3ee8ec | 190 | * @note Each time the core clock (HCLK) changes, this function must be called |
caa45040 | 1:bad45e3ee8ec | 191 | * to update SystemCoreClock variable value. Otherwise, any configuration |
caa45040 | 1:bad45e3ee8ec | 192 | * based on this variable will be incorrect. |
caa45040 | 1:bad45e3ee8ec | 193 | * |
caa45040 | 1:bad45e3ee8ec | 194 | * @note - The system frequency computed by this function is not the real |
caa45040 | 1:bad45e3ee8ec | 195 | * frequency in the chip. It is calculated based on the predefined |
caa45040 | 1:bad45e3ee8ec | 196 | * constant and the selected clock source: |
caa45040 | 1:bad45e3ee8ec | 197 | * |
caa45040 | 1:bad45e3ee8ec | 198 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
caa45040 | 1:bad45e3ee8ec | 199 | * |
caa45040 | 1:bad45e3ee8ec | 200 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
caa45040 | 1:bad45e3ee8ec | 201 | * |
caa45040 | 1:bad45e3ee8ec | 202 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
caa45040 | 1:bad45e3ee8ec | 203 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
caa45040 | 1:bad45e3ee8ec | 204 | * |
caa45040 | 1:bad45e3ee8ec | 205 | * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value |
caa45040 | 1:bad45e3ee8ec | 206 | * 8 MHz) but the real value may vary depending on the variations |
caa45040 | 1:bad45e3ee8ec | 207 | * in voltage and temperature. |
caa45040 | 1:bad45e3ee8ec | 208 | * |
caa45040 | 1:bad45e3ee8ec | 209 | * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value |
caa45040 | 1:bad45e3ee8ec | 210 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real |
caa45040 | 1:bad45e3ee8ec | 211 | * frequency of the crystal used. Otherwise, this function may |
caa45040 | 1:bad45e3ee8ec | 212 | * have wrong result. |
caa45040 | 1:bad45e3ee8ec | 213 | * |
caa45040 | 1:bad45e3ee8ec | 214 | * - The result of this function could be not correct when using fractional |
caa45040 | 1:bad45e3ee8ec | 215 | * value for HSE crystal. |
caa45040 | 1:bad45e3ee8ec | 216 | * |
caa45040 | 1:bad45e3ee8ec | 217 | * @param None |
caa45040 | 1:bad45e3ee8ec | 218 | * @retval None |
caa45040 | 1:bad45e3ee8ec | 219 | */ |
caa45040 | 1:bad45e3ee8ec | 220 | void SystemCoreClockUpdate (void) |
caa45040 | 1:bad45e3ee8ec | 221 | { |
caa45040 | 1:bad45e3ee8ec | 222 | uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; |
caa45040 | 1:bad45e3ee8ec | 223 | |
caa45040 | 1:bad45e3ee8ec | 224 | /* Get SYSCLK source -------------------------------------------------------*/ |
caa45040 | 1:bad45e3ee8ec | 225 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
caa45040 | 1:bad45e3ee8ec | 226 | |
caa45040 | 1:bad45e3ee8ec | 227 | switch (tmp) |
caa45040 | 1:bad45e3ee8ec | 228 | { |
caa45040 | 1:bad45e3ee8ec | 229 | case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ |
caa45040 | 1:bad45e3ee8ec | 230 | SystemCoreClock = HSI_VALUE; |
caa45040 | 1:bad45e3ee8ec | 231 | break; |
caa45040 | 1:bad45e3ee8ec | 232 | case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ |
caa45040 | 1:bad45e3ee8ec | 233 | SystemCoreClock = HSE_VALUE; |
caa45040 | 1:bad45e3ee8ec | 234 | break; |
caa45040 | 1:bad45e3ee8ec | 235 | case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ |
caa45040 | 1:bad45e3ee8ec | 236 | /* Get PLL clock source and multiplication factor ----------------------*/ |
caa45040 | 1:bad45e3ee8ec | 237 | pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; |
caa45040 | 1:bad45e3ee8ec | 238 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
caa45040 | 1:bad45e3ee8ec | 239 | pllmull = ( pllmull >> 18) + 2; |
caa45040 | 1:bad45e3ee8ec | 240 | |
caa45040 | 1:bad45e3ee8ec | 241 | #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) |
caa45040 | 1:bad45e3ee8ec | 242 | predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; |
caa45040 | 1:bad45e3ee8ec | 243 | if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) |
caa45040 | 1:bad45e3ee8ec | 244 | { |
caa45040 | 1:bad45e3ee8ec | 245 | /* HSE oscillator clock selected as PREDIV1 clock entry */ |
caa45040 | 1:bad45e3ee8ec | 246 | SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; |
caa45040 | 1:bad45e3ee8ec | 247 | } |
caa45040 | 1:bad45e3ee8ec | 248 | else |
caa45040 | 1:bad45e3ee8ec | 249 | { |
caa45040 | 1:bad45e3ee8ec | 250 | /* HSI oscillator clock selected as PREDIV1 clock entry */ |
caa45040 | 1:bad45e3ee8ec | 251 | SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull; |
caa45040 | 1:bad45e3ee8ec | 252 | } |
caa45040 | 1:bad45e3ee8ec | 253 | #else |
caa45040 | 1:bad45e3ee8ec | 254 | if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2) |
caa45040 | 1:bad45e3ee8ec | 255 | { |
caa45040 | 1:bad45e3ee8ec | 256 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */ |
caa45040 | 1:bad45e3ee8ec | 257 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; |
caa45040 | 1:bad45e3ee8ec | 258 | } |
caa45040 | 1:bad45e3ee8ec | 259 | else |
caa45040 | 1:bad45e3ee8ec | 260 | { |
caa45040 | 1:bad45e3ee8ec | 261 | predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; |
caa45040 | 1:bad45e3ee8ec | 262 | /* HSE oscillator clock selected as PREDIV1 clock entry */ |
caa45040 | 1:bad45e3ee8ec | 263 | SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; |
caa45040 | 1:bad45e3ee8ec | 264 | } |
caa45040 | 1:bad45e3ee8ec | 265 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ |
caa45040 | 1:bad45e3ee8ec | 266 | break; |
caa45040 | 1:bad45e3ee8ec | 267 | default: /* HSI used as system clock */ |
caa45040 | 1:bad45e3ee8ec | 268 | SystemCoreClock = HSI_VALUE; |
caa45040 | 1:bad45e3ee8ec | 269 | break; |
caa45040 | 1:bad45e3ee8ec | 270 | } |
caa45040 | 1:bad45e3ee8ec | 271 | /* Compute HCLK clock frequency ----------------*/ |
caa45040 | 1:bad45e3ee8ec | 272 | /* Get HCLK prescaler */ |
caa45040 | 1:bad45e3ee8ec | 273 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
caa45040 | 1:bad45e3ee8ec | 274 | /* HCLK clock frequency */ |
caa45040 | 1:bad45e3ee8ec | 275 | SystemCoreClock >>= tmp; |
caa45040 | 1:bad45e3ee8ec | 276 | } |
caa45040 | 1:bad45e3ee8ec | 277 | |
caa45040 | 1:bad45e3ee8ec | 278 | /** |
caa45040 | 1:bad45e3ee8ec | 279 | * @} |
caa45040 | 1:bad45e3ee8ec | 280 | */ |
caa45040 | 1:bad45e3ee8ec | 281 | |
caa45040 | 1:bad45e3ee8ec | 282 | /** |
caa45040 | 1:bad45e3ee8ec | 283 | * @} |
caa45040 | 1:bad45e3ee8ec | 284 | */ |
caa45040 | 1:bad45e3ee8ec | 285 | |
caa45040 | 1:bad45e3ee8ec | 286 | /** |
caa45040 | 1:bad45e3ee8ec | 287 | * @} |
caa45040 | 1:bad45e3ee8ec | 288 | */ |
caa45040 | 1:bad45e3ee8ec | 289 | |
caa45040 | 1:bad45e3ee8ec | 290 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
caa45040 | 1:bad45e3ee8ec | 291 | |
caa45040 | 1:bad45e3ee8ec | 292 |