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LCD_ACM1602K_9701_010_1/system_stm32l0xx.c@5:ab0a44c29d4a, 2021-11-20 (annotated)

Committer:
caa45040
Date:
Sat Nov 20 11:46:41 2021 +0000
Revision:
5:ab0a44c29d4a
LCD_ACM1602K_9701_010_1

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caa45040 5:ab0a44c29d4a 1 /**
caa45040 5:ab0a44c29d4a 2 ******************************************************************************
caa45040 5:ab0a44c29d4a 3 * @file system_stm32l0xx.c
caa45040 5:ab0a44c29d4a 4 * @author MCD Application Team
caa45040 5:ab0a44c29d4a 5 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
caa45040 5:ab0a44c29d4a 6 *
caa45040 5:ab0a44c29d4a 7 * This file provides two functions and one global variable to be called from
caa45040 5:ab0a44c29d4a 8 * user application:
caa45040 5:ab0a44c29d4a 9 * - SystemInit(): This function is called at startup just after reset and
caa45040 5:ab0a44c29d4a 10 * before branch to main program. This call is made inside
caa45040 5:ab0a44c29d4a 11 * the "startup_stm32l0xx.s" file.
caa45040 5:ab0a44c29d4a 12 *
caa45040 5:ab0a44c29d4a 13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
caa45040 5:ab0a44c29d4a 14 * by the user application to setup the SysTick
caa45040 5:ab0a44c29d4a 15 * timer or configure other parameters.
caa45040 5:ab0a44c29d4a 16 *
caa45040 5:ab0a44c29d4a 17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
caa45040 5:ab0a44c29d4a 18 * be called whenever the core clock is changed
caa45040 5:ab0a44c29d4a 19 * during program execution.
caa45040 5:ab0a44c29d4a 20 *
caa45040 5:ab0a44c29d4a 21 *
caa45040 5:ab0a44c29d4a 22 ******************************************************************************
caa45040 5:ab0a44c29d4a 23 * @attention
caa45040 5:ab0a44c29d4a 24 *
caa45040 5:ab0a44c29d4a 25 * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
caa45040 5:ab0a44c29d4a 26 * All rights reserved.</center></h2>
caa45040 5:ab0a44c29d4a 27 *
caa45040 5:ab0a44c29d4a 28 * This software component is licensed by ST under BSD 3-Clause license,
caa45040 5:ab0a44c29d4a 29 * the "License"; You may not use this file except in compliance with the
caa45040 5:ab0a44c29d4a 30 * License. You may obtain a copy of the License at:
caa45040 5:ab0a44c29d4a 31 * opensource.org/licenses/BSD-3-Clause
caa45040 5:ab0a44c29d4a 32 *
caa45040 5:ab0a44c29d4a 33 ******************************************************************************
caa45040 5:ab0a44c29d4a 34 */
caa45040 5:ab0a44c29d4a 35
caa45040 5:ab0a44c29d4a 36 /** @addtogroup CMSIS
caa45040 5:ab0a44c29d4a 37 * @{
caa45040 5:ab0a44c29d4a 38 */
caa45040 5:ab0a44c29d4a 39
caa45040 5:ab0a44c29d4a 40 /** @addtogroup stm32l0xx_system
caa45040 5:ab0a44c29d4a 41 * @{
caa45040 5:ab0a44c29d4a 42 */
caa45040 5:ab0a44c29d4a 43
caa45040 5:ab0a44c29d4a 44 /** @addtogroup STM32L0xx_System_Private_Includes
caa45040 5:ab0a44c29d4a 45 * @{
caa45040 5:ab0a44c29d4a 46 */
caa45040 5:ab0a44c29d4a 47
caa45040 5:ab0a44c29d4a 48 #include "stm32l0xx.h"
caa45040 5:ab0a44c29d4a 49
caa45040 5:ab0a44c29d4a 50 #if !defined (HSE_VALUE)
caa45040 5:ab0a44c29d4a 51 #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
caa45040 5:ab0a44c29d4a 52 #endif /* HSE_VALUE */
caa45040 5:ab0a44c29d4a 53
caa45040 5:ab0a44c29d4a 54 #if !defined (MSI_VALUE)
caa45040 5:ab0a44c29d4a 55 #define MSI_VALUE ((uint32_t)2097152U) /*!< Value of the Internal oscillator in Hz*/
caa45040 5:ab0a44c29d4a 56 #endif /* MSI_VALUE */
caa45040 5:ab0a44c29d4a 57
caa45040 5:ab0a44c29d4a 58 #if !defined (HSI_VALUE)
caa45040 5:ab0a44c29d4a 59 #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
caa45040 5:ab0a44c29d4a 60 #endif /* HSI_VALUE */
caa45040 5:ab0a44c29d4a 61
caa45040 5:ab0a44c29d4a 62
caa45040 5:ab0a44c29d4a 63 /**
caa45040 5:ab0a44c29d4a 64 * @}
caa45040 5:ab0a44c29d4a 65 */
caa45040 5:ab0a44c29d4a 66
caa45040 5:ab0a44c29d4a 67 /** @addtogroup STM32L0xx_System_Private_TypesDefinitions
caa45040 5:ab0a44c29d4a 68 * @{
caa45040 5:ab0a44c29d4a 69 */
caa45040 5:ab0a44c29d4a 70
caa45040 5:ab0a44c29d4a 71 /**
caa45040 5:ab0a44c29d4a 72 * @}
caa45040 5:ab0a44c29d4a 73 */
caa45040 5:ab0a44c29d4a 74
caa45040 5:ab0a44c29d4a 75 /** @addtogroup STM32L0xx_System_Private_Defines
caa45040 5:ab0a44c29d4a 76 * @{
caa45040 5:ab0a44c29d4a 77 */
caa45040 5:ab0a44c29d4a 78 /************************* Miscellaneous Configuration ************************/
caa45040 5:ab0a44c29d4a 79
caa45040 5:ab0a44c29d4a 80 /* Note: Following vector table addresses must be defined in line with linker
caa45040 5:ab0a44c29d4a 81 configuration. */
caa45040 5:ab0a44c29d4a 82 /*!< Uncomment the following line if you need to relocate the vector table
caa45040 5:ab0a44c29d4a 83 anywhere in Flash or Sram, else the vector table is kept at the automatic
caa45040 5:ab0a44c29d4a 84 remap of boot address selected */
caa45040 5:ab0a44c29d4a 85 /* #define USER_VECT_TAB_ADDRESS */
caa45040 5:ab0a44c29d4a 86
caa45040 5:ab0a44c29d4a 87 #if defined(USER_VECT_TAB_ADDRESS)
caa45040 5:ab0a44c29d4a 88 /*!< Uncomment the following line if you need to relocate your vector Table
caa45040 5:ab0a44c29d4a 89 in Sram else user remap will be done in Flash. */
caa45040 5:ab0a44c29d4a 90 /* #define VECT_TAB_SRAM */
caa45040 5:ab0a44c29d4a 91 #if defined(VECT_TAB_SRAM)
caa45040 5:ab0a44c29d4a 92 #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
caa45040 5:ab0a44c29d4a 93 This value must be a multiple of 0x200. */
caa45040 5:ab0a44c29d4a 94 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
caa45040 5:ab0a44c29d4a 95 This value must be a multiple of 0x200. */
caa45040 5:ab0a44c29d4a 96 #else
caa45040 5:ab0a44c29d4a 97 #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
caa45040 5:ab0a44c29d4a 98 This value must be a multiple of 0x200. */
caa45040 5:ab0a44c29d4a 99 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
caa45040 5:ab0a44c29d4a 100 This value must be a multiple of 0x200. */
caa45040 5:ab0a44c29d4a 101 #endif /* VECT_TAB_SRAM */
caa45040 5:ab0a44c29d4a 102 #endif /* USER_VECT_TAB_ADDRESS */
caa45040 5:ab0a44c29d4a 103
caa45040 5:ab0a44c29d4a 104 /******************************************************************************/
caa45040 5:ab0a44c29d4a 105 /**
caa45040 5:ab0a44c29d4a 106 * @}
caa45040 5:ab0a44c29d4a 107 */
caa45040 5:ab0a44c29d4a 108
caa45040 5:ab0a44c29d4a 109 /** @addtogroup STM32L0xx_System_Private_Macros
caa45040 5:ab0a44c29d4a 110 * @{
caa45040 5:ab0a44c29d4a 111 */
caa45040 5:ab0a44c29d4a 112
caa45040 5:ab0a44c29d4a 113 /**
caa45040 5:ab0a44c29d4a 114 * @}
caa45040 5:ab0a44c29d4a 115 */
caa45040 5:ab0a44c29d4a 116
caa45040 5:ab0a44c29d4a 117 /** @addtogroup STM32L0xx_System_Private_Variables
caa45040 5:ab0a44c29d4a 118 * @{
caa45040 5:ab0a44c29d4a 119 */
caa45040 5:ab0a44c29d4a 120 /* This variable is updated in three ways:
caa45040 5:ab0a44c29d4a 121 1) by calling CMSIS function SystemCoreClockUpdate()
caa45040 5:ab0a44c29d4a 122 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
caa45040 5:ab0a44c29d4a 123 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
caa45040 5:ab0a44c29d4a 124 Note: If you use this function to configure the system clock; then there
caa45040 5:ab0a44c29d4a 125 is no need to call the 2 first functions listed above, since SystemCoreClock
caa45040 5:ab0a44c29d4a 126 variable is updated automatically.
caa45040 5:ab0a44c29d4a 127 */
caa45040 5:ab0a44c29d4a 128 uint32_t SystemCoreClock = 2097152U; /* 32.768 kHz * 2^6 */
caa45040 5:ab0a44c29d4a 129 const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
caa45040 5:ab0a44c29d4a 130 const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
caa45040 5:ab0a44c29d4a 131 const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
caa45040 5:ab0a44c29d4a 132
caa45040 5:ab0a44c29d4a 133 /**
caa45040 5:ab0a44c29d4a 134 * @}
caa45040 5:ab0a44c29d4a 135 */
caa45040 5:ab0a44c29d4a 136
caa45040 5:ab0a44c29d4a 137 /** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
caa45040 5:ab0a44c29d4a 138 * @{
caa45040 5:ab0a44c29d4a 139 */
caa45040 5:ab0a44c29d4a 140
caa45040 5:ab0a44c29d4a 141 /**
caa45040 5:ab0a44c29d4a 142 * @}
caa45040 5:ab0a44c29d4a 143 */
caa45040 5:ab0a44c29d4a 144
caa45040 5:ab0a44c29d4a 145 /** @addtogroup STM32L0xx_System_Private_Functions
caa45040 5:ab0a44c29d4a 146 * @{
caa45040 5:ab0a44c29d4a 147 */
caa45040 5:ab0a44c29d4a 148
caa45040 5:ab0a44c29d4a 149 /**
caa45040 5:ab0a44c29d4a 150 * @brief Setup the microcontroller system.
caa45040 5:ab0a44c29d4a 151 * @param None
caa45040 5:ab0a44c29d4a 152 * @retval None
caa45040 5:ab0a44c29d4a 153 */
caa45040 5:ab0a44c29d4a 154 void SystemInit (void)
caa45040 5:ab0a44c29d4a 155 {
caa45040 5:ab0a44c29d4a 156 /* Configure the Vector Table location add offset address ------------------*/
caa45040 5:ab0a44c29d4a 157 #if defined (USER_VECT_TAB_ADDRESS)
caa45040 5:ab0a44c29d4a 158 SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
caa45040 5:ab0a44c29d4a 159 #endif /* USER_VECT_TAB_ADDRESS */
caa45040 5:ab0a44c29d4a 160 }
caa45040 5:ab0a44c29d4a 161
caa45040 5:ab0a44c29d4a 162 /**
caa45040 5:ab0a44c29d4a 163 * @brief Update SystemCoreClock variable according to Clock Register Values.
caa45040 5:ab0a44c29d4a 164 * The SystemCoreClock variable contains the core clock (HCLK), it can
caa45040 5:ab0a44c29d4a 165 * be used by the user application to setup the SysTick timer or configure
caa45040 5:ab0a44c29d4a 166 * other parameters.
caa45040 5:ab0a44c29d4a 167 *
caa45040 5:ab0a44c29d4a 168 * @note Each time the core clock (HCLK) changes, this function must be called
caa45040 5:ab0a44c29d4a 169 * to update SystemCoreClock variable value. Otherwise, any configuration
caa45040 5:ab0a44c29d4a 170 * based on this variable will be incorrect.
caa45040 5:ab0a44c29d4a 171 *
caa45040 5:ab0a44c29d4a 172 * @note - The system frequency computed by this function is not the real
caa45040 5:ab0a44c29d4a 173 * frequency in the chip. It is calculated based on the predefined
caa45040 5:ab0a44c29d4a 174 * constant and the selected clock source:
caa45040 5:ab0a44c29d4a 175 *
caa45040 5:ab0a44c29d4a 176 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
caa45040 5:ab0a44c29d4a 177 * value as defined by the MSI range.
caa45040 5:ab0a44c29d4a 178 *
caa45040 5:ab0a44c29d4a 179 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
caa45040 5:ab0a44c29d4a 180 *
caa45040 5:ab0a44c29d4a 181 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
caa45040 5:ab0a44c29d4a 182 *
caa45040 5:ab0a44c29d4a 183 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
caa45040 5:ab0a44c29d4a 184 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
caa45040 5:ab0a44c29d4a 185 *
caa45040 5:ab0a44c29d4a 186 * (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
caa45040 5:ab0a44c29d4a 187 * 16 MHz) but the real value may vary depending on the variations
caa45040 5:ab0a44c29d4a 188 * in voltage and temperature.
caa45040 5:ab0a44c29d4a 189 *
caa45040 5:ab0a44c29d4a 190 * (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
caa45040 5:ab0a44c29d4a 191 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
caa45040 5:ab0a44c29d4a 192 * frequency of the crystal used. Otherwise, this function may
caa45040 5:ab0a44c29d4a 193 * have wrong result.
caa45040 5:ab0a44c29d4a 194 *
caa45040 5:ab0a44c29d4a 195 * - The result of this function could be not correct when using fractional
caa45040 5:ab0a44c29d4a 196 * value for HSE crystal.
caa45040 5:ab0a44c29d4a 197 * @param None
caa45040 5:ab0a44c29d4a 198 * @retval None
caa45040 5:ab0a44c29d4a 199 */
caa45040 5:ab0a44c29d4a 200 void SystemCoreClockUpdate (void)
caa45040 5:ab0a44c29d4a 201 {
caa45040 5:ab0a44c29d4a 202 uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
caa45040 5:ab0a44c29d4a 203
caa45040 5:ab0a44c29d4a 204 /* Get SYSCLK source -------------------------------------------------------*/
caa45040 5:ab0a44c29d4a 205 tmp = RCC->CFGR & RCC_CFGR_SWS;
caa45040 5:ab0a44c29d4a 206
caa45040 5:ab0a44c29d4a 207 switch (tmp)
caa45040 5:ab0a44c29d4a 208 {
caa45040 5:ab0a44c29d4a 209 case 0x00U: /* MSI used as system clock */
caa45040 5:ab0a44c29d4a 210 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> RCC_ICSCR_MSIRANGE_Pos;
caa45040 5:ab0a44c29d4a 211 SystemCoreClock = (32768U * (1U << (msirange + 1U)));
caa45040 5:ab0a44c29d4a 212 break;
caa45040 5:ab0a44c29d4a 213 case 0x04U: /* HSI used as system clock */
caa45040 5:ab0a44c29d4a 214 if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
caa45040 5:ab0a44c29d4a 215 {
caa45040 5:ab0a44c29d4a 216 SystemCoreClock = HSI_VALUE / 4U;
caa45040 5:ab0a44c29d4a 217 }
caa45040 5:ab0a44c29d4a 218 else
caa45040 5:ab0a44c29d4a 219 {
caa45040 5:ab0a44c29d4a 220 SystemCoreClock = HSI_VALUE;
caa45040 5:ab0a44c29d4a 221 }
caa45040 5:ab0a44c29d4a 222 break;
caa45040 5:ab0a44c29d4a 223 case 0x08U: /* HSE used as system clock */
caa45040 5:ab0a44c29d4a 224 SystemCoreClock = HSE_VALUE;
caa45040 5:ab0a44c29d4a 225 break;
caa45040 5:ab0a44c29d4a 226 default: /* PLL used as system clock */
caa45040 5:ab0a44c29d4a 227 /* Get PLL clock source and multiplication factor ----------------------*/
caa45040 5:ab0a44c29d4a 228 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
caa45040 5:ab0a44c29d4a 229 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
caa45040 5:ab0a44c29d4a 230 pllmul = PLLMulTable[(pllmul >> RCC_CFGR_PLLMUL_Pos)];
caa45040 5:ab0a44c29d4a 231 plldiv = (plldiv >> RCC_CFGR_PLLDIV_Pos) + 1U;
caa45040 5:ab0a44c29d4a 232
caa45040 5:ab0a44c29d4a 233 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
caa45040 5:ab0a44c29d4a 234
caa45040 5:ab0a44c29d4a 235 if (pllsource == 0x00U)
caa45040 5:ab0a44c29d4a 236 {
caa45040 5:ab0a44c29d4a 237 /* HSI oscillator clock selected as PLL clock entry */
caa45040 5:ab0a44c29d4a 238 if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
caa45040 5:ab0a44c29d4a 239 {
caa45040 5:ab0a44c29d4a 240 SystemCoreClock = (((HSI_VALUE / 4U) * pllmul) / plldiv);
caa45040 5:ab0a44c29d4a 241 }
caa45040 5:ab0a44c29d4a 242 else
caa45040 5:ab0a44c29d4a 243 {
caa45040 5:ab0a44c29d4a 244 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
caa45040 5:ab0a44c29d4a 245 }
caa45040 5:ab0a44c29d4a 246 }
caa45040 5:ab0a44c29d4a 247 else
caa45040 5:ab0a44c29d4a 248 {
caa45040 5:ab0a44c29d4a 249 /* HSE selected as PLL clock entry */
caa45040 5:ab0a44c29d4a 250 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
caa45040 5:ab0a44c29d4a 251 }
caa45040 5:ab0a44c29d4a 252 break;
caa45040 5:ab0a44c29d4a 253 }
caa45040 5:ab0a44c29d4a 254 /* Compute HCLK clock frequency --------------------------------------------*/
caa45040 5:ab0a44c29d4a 255 /* Get HCLK prescaler */
caa45040 5:ab0a44c29d4a 256 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
caa45040 5:ab0a44c29d4a 257 /* HCLK clock frequency */
caa45040 5:ab0a44c29d4a 258 SystemCoreClock >>= tmp;
caa45040 5:ab0a44c29d4a 259 }
caa45040 5:ab0a44c29d4a 260
caa45040 5:ab0a44c29d4a 261
caa45040 5:ab0a44c29d4a 262
caa45040 5:ab0a44c29d4a 263 /**
caa45040 5:ab0a44c29d4a 264 * @}
caa45040 5:ab0a44c29d4a 265 */
caa45040 5:ab0a44c29d4a 266
caa45040 5:ab0a44c29d4a 267 /**
caa45040 5:ab0a44c29d4a 268 * @}
caa45040 5:ab0a44c29d4a 269 */
caa45040 5:ab0a44c29d4a 270
caa45040 5:ab0a44c29d4a 271 /**
caa45040 5:ab0a44c29d4a 272 * @}
caa45040 5:ab0a44c29d4a 273 */
caa45040 5:ab0a44c29d4a 274
caa45040 5:ab0a44c29d4a 275 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
caa45040 5:ab0a44c29d4a 276