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stm32g031_i2c_1/system_stm32g0xx.c@26:a047b389adfd, 2022-05-06 (annotated)

Committer:
caa45040
Date:
Fri May 06 14:22:30 2022 +0000
Revision:
26:a047b389adfd
Parent:
17:0379bd4fea21 
i2c_slave_HC_SR04_010_BIN re

Who changed what in which revision?

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caa45040 17:0379bd4fea21 1 /**
caa45040 17:0379bd4fea21 2 ******************************************************************************
caa45040 17:0379bd4fea21 3 * @file system_stm32g0xx.c
caa45040 17:0379bd4fea21 4 * @author MCD Application Team
caa45040 17:0379bd4fea21 5 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File
caa45040 17:0379bd4fea21 6 *
caa45040 17:0379bd4fea21 7 * This file provides two functions and one global variable to be called from
caa45040 17:0379bd4fea21 8 * user application:
caa45040 17:0379bd4fea21 9 * - SystemInit(): This function is called at startup just after reset and
caa45040 17:0379bd4fea21 10 * before branch to main program. This call is made inside
caa45040 17:0379bd4fea21 11 * the "startup_stm32g0xx.s" file.
caa45040 17:0379bd4fea21 12 *
caa45040 17:0379bd4fea21 13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
caa45040 17:0379bd4fea21 14 * by the user application to setup the SysTick
caa45040 17:0379bd4fea21 15 * timer or configure other parameters.
caa45040 17:0379bd4fea21 16 *
caa45040 17:0379bd4fea21 17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
caa45040 17:0379bd4fea21 18 * be called whenever the core clock is changed
caa45040 17:0379bd4fea21 19 * during program execution.
caa45040 17:0379bd4fea21 20 *
caa45040 17:0379bd4fea21 21 * After each device reset the HSI (8 MHz then 16 MHz) is used as system clock source.
caa45040 17:0379bd4fea21 22 * Then SystemInit() function is called, in "startup_stm32g0xx.s" file, to
caa45040 17:0379bd4fea21 23 * configure the system clock before to branch to main program.
caa45040 17:0379bd4fea21 24 *
caa45040 17:0379bd4fea21 25 * This file configures the system clock as follows:
caa45040 17:0379bd4fea21 26 *=============================================================================
caa45040 17:0379bd4fea21 27 *-----------------------------------------------------------------------------
caa45040 17:0379bd4fea21 28 * System Clock source | HSI
caa45040 17:0379bd4fea21 29 *-----------------------------------------------------------------------------
caa45040 17:0379bd4fea21 30 * SYSCLK(Hz) | 16000000
caa45040 17:0379bd4fea21 31 *-----------------------------------------------------------------------------
caa45040 17:0379bd4fea21 32 * HCLK(Hz) | 16000000
caa45040 17:0379bd4fea21 33 *-----------------------------------------------------------------------------
caa45040 17:0379bd4fea21 34 * AHB Prescaler | 1
caa45040 17:0379bd4fea21 35 *-----------------------------------------------------------------------------
caa45040 17:0379bd4fea21 36 * APB Prescaler | 1
caa45040 17:0379bd4fea21 37 *-----------------------------------------------------------------------------
caa45040 17:0379bd4fea21 38 * HSI Division factor | 1
caa45040 17:0379bd4fea21 39 *-----------------------------------------------------------------------------
caa45040 17:0379bd4fea21 40 * PLL_M | 1
caa45040 17:0379bd4fea21 41 *-----------------------------------------------------------------------------
caa45040 17:0379bd4fea21 42 * PLL_N | 8
caa45040 17:0379bd4fea21 43 *-----------------------------------------------------------------------------
caa45040 17:0379bd4fea21 44 * PLL_P | 7
caa45040 17:0379bd4fea21 45 *-----------------------------------------------------------------------------
caa45040 17:0379bd4fea21 46 * PLL_Q | 2
caa45040 17:0379bd4fea21 47 *-----------------------------------------------------------------------------
caa45040 17:0379bd4fea21 48 * PLL_R | 2
caa45040 17:0379bd4fea21 49 *-----------------------------------------------------------------------------
caa45040 17:0379bd4fea21 50 * Require 48MHz for RNG | Disabled
caa45040 17:0379bd4fea21 51 *-----------------------------------------------------------------------------
caa45040 17:0379bd4fea21 52 *=============================================================================
caa45040 17:0379bd4fea21 53 ******************************************************************************
caa45040 17:0379bd4fea21 54 * @attention
caa45040 17:0379bd4fea21 55 *
caa45040 17:0379bd4fea21 56 * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
caa45040 17:0379bd4fea21 57 * All rights reserved.</center></h2>
caa45040 17:0379bd4fea21 58 *
caa45040 17:0379bd4fea21 59 * This software component is licensed by ST under Apache License, Version 2.0,
caa45040 17:0379bd4fea21 60 * the "License"; You may not use this file except in compliance with the
caa45040 17:0379bd4fea21 61 * License. You may obtain a copy of the License at:
caa45040 17:0379bd4fea21 62 * opensource.org/licenses/Apache-2.0
caa45040 17:0379bd4fea21 63 *
caa45040 17:0379bd4fea21 64 ******************************************************************************
caa45040 17:0379bd4fea21 65 */
caa45040 17:0379bd4fea21 66
caa45040 17:0379bd4fea21 67 /** @addtogroup CMSIS
caa45040 17:0379bd4fea21 68 * @{
caa45040 17:0379bd4fea21 69 */
caa45040 17:0379bd4fea21 70
caa45040 17:0379bd4fea21 71 /** @addtogroup stm32g0xx_system
caa45040 17:0379bd4fea21 72 * @{
caa45040 17:0379bd4fea21 73 */
caa45040 17:0379bd4fea21 74
caa45040 17:0379bd4fea21 75 /** @addtogroup STM32G0xx_System_Private_Includes
caa45040 17:0379bd4fea21 76 * @{
caa45040 17:0379bd4fea21 77 */
caa45040 17:0379bd4fea21 78
caa45040 17:0379bd4fea21 79 #include "stm32g0xx.h"
caa45040 17:0379bd4fea21 80
caa45040 17:0379bd4fea21 81 #if !defined (HSE_VALUE)
caa45040 17:0379bd4fea21 82 #define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */
caa45040 17:0379bd4fea21 83 #endif /* HSE_VALUE */
caa45040 17:0379bd4fea21 84
caa45040 17:0379bd4fea21 85 #if !defined (HSI_VALUE)
caa45040 17:0379bd4fea21 86 #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
caa45040 17:0379bd4fea21 87 #endif /* HSI_VALUE */
caa45040 17:0379bd4fea21 88
caa45040 17:0379bd4fea21 89 #if !defined (LSI_VALUE)
caa45040 17:0379bd4fea21 90 #define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/
caa45040 17:0379bd4fea21 91 #endif /* LSI_VALUE */
caa45040 17:0379bd4fea21 92
caa45040 17:0379bd4fea21 93 #if !defined (LSE_VALUE)
caa45040 17:0379bd4fea21 94 #define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/
caa45040 17:0379bd4fea21 95 #endif /* LSE_VALUE */
caa45040 17:0379bd4fea21 96
caa45040 17:0379bd4fea21 97 /**
caa45040 17:0379bd4fea21 98 * @}
caa45040 17:0379bd4fea21 99 */
caa45040 17:0379bd4fea21 100
caa45040 17:0379bd4fea21 101 /** @addtogroup STM32G0xx_System_Private_TypesDefinitions
caa45040 17:0379bd4fea21 102 * @{
caa45040 17:0379bd4fea21 103 */
caa45040 17:0379bd4fea21 104
caa45040 17:0379bd4fea21 105 /**
caa45040 17:0379bd4fea21 106 * @}
caa45040 17:0379bd4fea21 107 */
caa45040 17:0379bd4fea21 108
caa45040 17:0379bd4fea21 109 /** @addtogroup STM32G0xx_System_Private_Defines
caa45040 17:0379bd4fea21 110 * @{
caa45040 17:0379bd4fea21 111 */
caa45040 17:0379bd4fea21 112
caa45040 17:0379bd4fea21 113 /************************* Miscellaneous Configuration ************************/
caa45040 17:0379bd4fea21 114 /*!< Uncomment the following line if you need to relocate your vector Table in
caa45040 17:0379bd4fea21 115 Internal SRAM. */
caa45040 17:0379bd4fea21 116 /* #define VECT_TAB_SRAM */
caa45040 17:0379bd4fea21 117 #define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field.
caa45040 17:0379bd4fea21 118 This value must be a multiple of 0x100. */
caa45040 17:0379bd4fea21 119 /******************************************************************************/
caa45040 17:0379bd4fea21 120 /**
caa45040 17:0379bd4fea21 121 * @}
caa45040 17:0379bd4fea21 122 */
caa45040 17:0379bd4fea21 123
caa45040 17:0379bd4fea21 124 /** @addtogroup STM32G0xx_System_Private_Macros
caa45040 17:0379bd4fea21 125 * @{
caa45040 17:0379bd4fea21 126 */
caa45040 17:0379bd4fea21 127
caa45040 17:0379bd4fea21 128 /**
caa45040 17:0379bd4fea21 129 * @}
caa45040 17:0379bd4fea21 130 */
caa45040 17:0379bd4fea21 131
caa45040 17:0379bd4fea21 132 /** @addtogroup STM32G0xx_System_Private_Variables
caa45040 17:0379bd4fea21 133 * @{
caa45040 17:0379bd4fea21 134 */
caa45040 17:0379bd4fea21 135 /* The SystemCoreClock variable is updated in three ways:
caa45040 17:0379bd4fea21 136 1) by calling CMSIS function SystemCoreClockUpdate()
caa45040 17:0379bd4fea21 137 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
caa45040 17:0379bd4fea21 138 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
caa45040 17:0379bd4fea21 139 Note: If you use this function to configure the system clock; then there
caa45040 17:0379bd4fea21 140 is no need to call the 2 first functions listed above, since SystemCoreClock
caa45040 17:0379bd4fea21 141 variable is updated automatically.
caa45040 17:0379bd4fea21 142 */
caa45040 17:0379bd4fea21 143 uint32_t SystemCoreClock = 16000000UL;
caa45040 17:0379bd4fea21 144
caa45040 17:0379bd4fea21 145 const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL};
caa45040 17:0379bd4fea21 146 const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
caa45040 17:0379bd4fea21 147
caa45040 17:0379bd4fea21 148 /**
caa45040 17:0379bd4fea21 149 * @}
caa45040 17:0379bd4fea21 150 */
caa45040 17:0379bd4fea21 151
caa45040 17:0379bd4fea21 152 /** @addtogroup STM32G0xx_System_Private_FunctionPrototypes
caa45040 17:0379bd4fea21 153 * @{
caa45040 17:0379bd4fea21 154 */
caa45040 17:0379bd4fea21 155
caa45040 17:0379bd4fea21 156 /**
caa45040 17:0379bd4fea21 157 * @}
caa45040 17:0379bd4fea21 158 */
caa45040 17:0379bd4fea21 159
caa45040 17:0379bd4fea21 160 /** @addtogroup STM32G0xx_System_Private_Functions
caa45040 17:0379bd4fea21 161 * @{
caa45040 17:0379bd4fea21 162 */
caa45040 17:0379bd4fea21 163
caa45040 17:0379bd4fea21 164 /**
caa45040 17:0379bd4fea21 165 * @brief Setup the microcontroller system.
caa45040 17:0379bd4fea21 166 * @param None
caa45040 17:0379bd4fea21 167 * @retval None
caa45040 17:0379bd4fea21 168 */
caa45040 17:0379bd4fea21 169 void SystemInit(void)
caa45040 17:0379bd4fea21 170 {
caa45040 17:0379bd4fea21 171 /* Configure the Vector Table location add offset address ------------------*/
caa45040 17:0379bd4fea21 172 #ifdef VECT_TAB_SRAM
caa45040 17:0379bd4fea21 173 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
caa45040 17:0379bd4fea21 174 #else
caa45040 17:0379bd4fea21 175 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
caa45040 17:0379bd4fea21 176 #endif
caa45040 17:0379bd4fea21 177 }
caa45040 17:0379bd4fea21 178
caa45040 17:0379bd4fea21 179 /**
caa45040 17:0379bd4fea21 180 * @brief Update SystemCoreClock variable according to Clock Register Values.
caa45040 17:0379bd4fea21 181 * The SystemCoreClock variable contains the core clock (HCLK), it can
caa45040 17:0379bd4fea21 182 * be used by the user application to setup the SysTick timer or configure
caa45040 17:0379bd4fea21 183 * other parameters.
caa45040 17:0379bd4fea21 184 *
caa45040 17:0379bd4fea21 185 * @note Each time the core clock (HCLK) changes, this function must be called
caa45040 17:0379bd4fea21 186 * to update SystemCoreClock variable value. Otherwise, any configuration
caa45040 17:0379bd4fea21 187 * based on this variable will be incorrect.
caa45040 17:0379bd4fea21 188 *
caa45040 17:0379bd4fea21 189 * @note - The system frequency computed by this function is not the real
caa45040 17:0379bd4fea21 190 * frequency in the chip. It is calculated based on the predefined
caa45040 17:0379bd4fea21 191 * constant and the selected clock source:
caa45040 17:0379bd4fea21 192 *
caa45040 17:0379bd4fea21 193 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor
caa45040 17:0379bd4fea21 194 *
caa45040 17:0379bd4fea21 195 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
caa45040 17:0379bd4fea21 196 *
caa45040 17:0379bd4fea21 197 * - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE
caa45040 17:0379bd4fea21 198 *
caa45040 17:0379bd4fea21 199 * - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE
caa45040 17:0379bd4fea21 200 *
caa45040 17:0379bd4fea21 201 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
caa45040 17:0379bd4fea21 202 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
caa45040 17:0379bd4fea21 203 *
caa45040 17:0379bd4fea21 204 * (**) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
caa45040 17:0379bd4fea21 205 * 16 MHz) but the real value may vary depending on the variations
caa45040 17:0379bd4fea21 206 * in voltage and temperature.
caa45040 17:0379bd4fea21 207 *
caa45040 17:0379bd4fea21 208 * (***) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
caa45040 17:0379bd4fea21 209 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
caa45040 17:0379bd4fea21 210 * frequency of the crystal used. Otherwise, this function may
caa45040 17:0379bd4fea21 211 * have wrong result.
caa45040 17:0379bd4fea21 212 *
caa45040 17:0379bd4fea21 213 * - The result of this function could be not correct when using fractional
caa45040 17:0379bd4fea21 214 * value for HSE crystal.
caa45040 17:0379bd4fea21 215 *
caa45040 17:0379bd4fea21 216 * @param None
caa45040 17:0379bd4fea21 217 * @retval None
caa45040 17:0379bd4fea21 218 */
caa45040 17:0379bd4fea21 219 void SystemCoreClockUpdate(void)
caa45040 17:0379bd4fea21 220 {
caa45040 17:0379bd4fea21 221 uint32_t tmp;
caa45040 17:0379bd4fea21 222 uint32_t pllvco;
caa45040 17:0379bd4fea21 223 uint32_t pllr;
caa45040 17:0379bd4fea21 224 uint32_t pllsource;
caa45040 17:0379bd4fea21 225 uint32_t pllm;
caa45040 17:0379bd4fea21 226 uint32_t hsidiv;
caa45040 17:0379bd4fea21 227
caa45040 17:0379bd4fea21 228 /* Get SYSCLK source -------------------------------------------------------*/
caa45040 17:0379bd4fea21 229 switch (RCC->CFGR & RCC_CFGR_SWS)
caa45040 17:0379bd4fea21 230 {
caa45040 17:0379bd4fea21 231 case RCC_CFGR_SWS_0: /* HSE used as system clock */
caa45040 17:0379bd4fea21 232 SystemCoreClock = HSE_VALUE;
caa45040 17:0379bd4fea21 233 break;
caa45040 17:0379bd4fea21 234
caa45040 17:0379bd4fea21 235 case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */
caa45040 17:0379bd4fea21 236 SystemCoreClock = LSI_VALUE;
caa45040 17:0379bd4fea21 237 break;
caa45040 17:0379bd4fea21 238
caa45040 17:0379bd4fea21 239 case RCC_CFGR_SWS_2: /* LSE used as system clock */
caa45040 17:0379bd4fea21 240 SystemCoreClock = LSE_VALUE;
caa45040 17:0379bd4fea21 241 break;
caa45040 17:0379bd4fea21 242
caa45040 17:0379bd4fea21 243 case RCC_CFGR_SWS_1: /* PLL used as system clock */
caa45040 17:0379bd4fea21 244 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
caa45040 17:0379bd4fea21 245 SYSCLK = PLL_VCO / PLLR
caa45040 17:0379bd4fea21 246 */
caa45040 17:0379bd4fea21 247 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
caa45040 17:0379bd4fea21 248 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL;
caa45040 17:0379bd4fea21 249
caa45040 17:0379bd4fea21 250 if(pllsource == 0x03UL) /* HSE used as PLL clock source */
caa45040 17:0379bd4fea21 251 {
caa45040 17:0379bd4fea21 252 pllvco = (HSE_VALUE / pllm);
caa45040 17:0379bd4fea21 253 }
caa45040 17:0379bd4fea21 254 else /* HSI used as PLL clock source */
caa45040 17:0379bd4fea21 255 {
caa45040 17:0379bd4fea21 256 pllvco = (HSI_VALUE / pllm);
caa45040 17:0379bd4fea21 257 }
caa45040 17:0379bd4fea21 258 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
caa45040 17:0379bd4fea21 259 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
caa45040 17:0379bd4fea21 260
caa45040 17:0379bd4fea21 261 SystemCoreClock = pllvco/pllr;
caa45040 17:0379bd4fea21 262 break;
caa45040 17:0379bd4fea21 263
caa45040 17:0379bd4fea21 264 case 0x00000000U: /* HSI used as system clock */
caa45040 17:0379bd4fea21 265 default: /* HSI used as system clock */
caa45040 17:0379bd4fea21 266 hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));
caa45040 17:0379bd4fea21 267 SystemCoreClock = (HSI_VALUE/hsidiv);
caa45040 17:0379bd4fea21 268 break;
caa45040 17:0379bd4fea21 269 }
caa45040 17:0379bd4fea21 270 /* Compute HCLK clock frequency --------------------------------------------*/
caa45040 17:0379bd4fea21 271 /* Get HCLK prescaler */
caa45040 17:0379bd4fea21 272 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
caa45040 17:0379bd4fea21 273 /* HCLK clock frequency */
caa45040 17:0379bd4fea21 274 SystemCoreClock >>= tmp;
caa45040 17:0379bd4fea21 275 }
caa45040 17:0379bd4fea21 276
caa45040 17:0379bd4fea21 277
caa45040 17:0379bd4fea21 278 /**
caa45040 17:0379bd4fea21 279 * @}
caa45040 17:0379bd4fea21 280 */
caa45040 17:0379bd4fea21 281
caa45040 17:0379bd4fea21 282 /**
caa45040 17:0379bd4fea21 283 * @}
caa45040 17:0379bd4fea21 284 */
caa45040 17:0379bd4fea21 285
caa45040 17:0379bd4fea21 286 /**
caa45040 17:0379bd4fea21 287 * @}
caa45040 17:0379bd4fea21 288 */
caa45040 17:0379bd4fea21 289
caa45040 17:0379bd4fea21 290 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
caa45040 17:0379bd4fea21 291