keniti akiba / Mbed 2 deprecated f303_h_p1

f303_h_p1 1

Dependencies:   mbed

nu_l010_i2c_1/main.c@26:a047b389adfd, 2022-05-06 (annotated)

Committer:
caa45040
Date:
Fri May 06 14:22:30 2022 +0000
Revision:
26:a047b389adfd
Parent:
7:02fa6ef78ec9 
i2c_slave_HC_SR04_010_BIN re

Who changed what in which revision?

UserRevisionLine numberNew contents of line
caa45040 7:02fa6ef78ec9 1 /* USER CODE BEGIN Header */
caa45040 7:02fa6ef78ec9 2 /**
caa45040 7:02fa6ef78ec9 3 ******************************************************************************
caa45040 7:02fa6ef78ec9 4 * @file : main.c
caa45040 7:02fa6ef78ec9 5 * @brief : Main program body
caa45040 7:02fa6ef78ec9 6 ******************************************************************************
caa45040 7:02fa6ef78ec9 7 * @attention
caa45040 7:02fa6ef78ec9 8 *
caa45040 7:02fa6ef78ec9 9 * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.
caa45040 7:02fa6ef78ec9 10 * All rights reserved.</center></h2>
caa45040 7:02fa6ef78ec9 11 *
caa45040 7:02fa6ef78ec9 12 * This software component is licensed by ST under BSD 3-Clause license,
caa45040 7:02fa6ef78ec9 13 * the "License"; You may not use this file except in compliance with the
caa45040 7:02fa6ef78ec9 14 * License. You may obtain a copy of the License at:
caa45040 7:02fa6ef78ec9 15 * opensource.org/licenses/BSD-3-Clause
caa45040 7:02fa6ef78ec9 16 *
caa45040 7:02fa6ef78ec9 17 ******************************************************************************
caa45040 7:02fa6ef78ec9 18 */
caa45040 7:02fa6ef78ec9 19 /* USER CODE END Header */
caa45040 7:02fa6ef78ec9 20 /* Includes ------------------------------------------------------------------*/
caa45040 7:02fa6ef78ec9 21 #include "main.h"
caa45040 7:02fa6ef78ec9 22
caa45040 7:02fa6ef78ec9 23 /* Private includes ----------------------------------------------------------*/
caa45040 7:02fa6ef78ec9 24 /* USER CODE BEGIN Includes */
caa45040 7:02fa6ef78ec9 25
caa45040 7:02fa6ef78ec9 26 /* USER CODE END Includes */
caa45040 7:02fa6ef78ec9 27
caa45040 7:02fa6ef78ec9 28 /* Private typedef -----------------------------------------------------------*/
caa45040 7:02fa6ef78ec9 29 /* USER CODE BEGIN PTD */
caa45040 7:02fa6ef78ec9 30
caa45040 7:02fa6ef78ec9 31 /* USER CODE END PTD */
caa45040 7:02fa6ef78ec9 32
caa45040 7:02fa6ef78ec9 33 /* Private define ------------------------------------------------------------*/
caa45040 7:02fa6ef78ec9 34 /* USER CODE BEGIN PD */
caa45040 7:02fa6ef78ec9 35 /* USER CODE END PD */
caa45040 7:02fa6ef78ec9 36
caa45040 7:02fa6ef78ec9 37 /* Private macro -------------------------------------------------------------*/
caa45040 7:02fa6ef78ec9 38 /* USER CODE BEGIN PM */
caa45040 7:02fa6ef78ec9 39
caa45040 7:02fa6ef78ec9 40 /* USER CODE END PM */
caa45040 7:02fa6ef78ec9 41
caa45040 7:02fa6ef78ec9 42 /* Private variables ---------------------------------------------------------*/
caa45040 7:02fa6ef78ec9 43 I2C_HandleTypeDef hi2c1;
caa45040 7:02fa6ef78ec9 44
caa45040 7:02fa6ef78ec9 45 UART_HandleTypeDef huart2;
caa45040 7:02fa6ef78ec9 46
caa45040 7:02fa6ef78ec9 47 /* USER CODE BEGIN PV */
caa45040 7:02fa6ef78ec9 48
caa45040 7:02fa6ef78ec9 49 /* USER CODE END PV */
caa45040 7:02fa6ef78ec9 50
caa45040 7:02fa6ef78ec9 51 /* Private function prototypes -----------------------------------------------*/
caa45040 7:02fa6ef78ec9 52 void SystemClock_Config(void);
caa45040 7:02fa6ef78ec9 53 static void MX_GPIO_Init(void);
caa45040 7:02fa6ef78ec9 54 static void MX_I2C1_Init(void);
caa45040 7:02fa6ef78ec9 55 static void MX_USART2_UART_Init(void);
caa45040 7:02fa6ef78ec9 56 /* USER CODE BEGIN PFP */
caa45040 7:02fa6ef78ec9 57
caa45040 7:02fa6ef78ec9 58 /* USER CODE END PFP */
caa45040 7:02fa6ef78ec9 59
caa45040 7:02fa6ef78ec9 60 /* Private user code ---------------------------------------------------------*/
caa45040 7:02fa6ef78ec9 61 /* USER CODE BEGIN 0 */
caa45040 7:02fa6ef78ec9 62
caa45040 7:02fa6ef78ec9 63 /* USER CODE END 0 */
caa45040 7:02fa6ef78ec9 64
caa45040 7:02fa6ef78ec9 65 /**
caa45040 7:02fa6ef78ec9 66 * @brief The application entry point.
caa45040 7:02fa6ef78ec9 67 * @retval int
caa45040 7:02fa6ef78ec9 68 */
caa45040 7:02fa6ef78ec9 69 int main(void)
caa45040 7:02fa6ef78ec9 70 {
caa45040 7:02fa6ef78ec9 71 /* USER CODE BEGIN 1 */
caa45040 7:02fa6ef78ec9 72
caa45040 7:02fa6ef78ec9 73 /* USER CODE END 1 */
caa45040 7:02fa6ef78ec9 74
caa45040 7:02fa6ef78ec9 75 /* MCU Configuration--------------------------------------------------------*/
caa45040 7:02fa6ef78ec9 76
caa45040 7:02fa6ef78ec9 77 /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
caa45040 7:02fa6ef78ec9 78 HAL_Init();
caa45040 7:02fa6ef78ec9 79
caa45040 7:02fa6ef78ec9 80 /* USER CODE BEGIN Init */
caa45040 7:02fa6ef78ec9 81
caa45040 7:02fa6ef78ec9 82 /* USER CODE END Init */
caa45040 7:02fa6ef78ec9 83
caa45040 7:02fa6ef78ec9 84 /* Configure the system clock */
caa45040 7:02fa6ef78ec9 85 SystemClock_Config();
caa45040 7:02fa6ef78ec9 86
caa45040 7:02fa6ef78ec9 87 /* USER CODE BEGIN SysInit */
caa45040 7:02fa6ef78ec9 88
caa45040 7:02fa6ef78ec9 89 /* USER CODE END SysInit */
caa45040 7:02fa6ef78ec9 90
caa45040 7:02fa6ef78ec9 91 /* Initialize all configured peripherals */
caa45040 7:02fa6ef78ec9 92 MX_GPIO_Init();
caa45040 7:02fa6ef78ec9 93 MX_I2C1_Init();
caa45040 7:02fa6ef78ec9 94 MX_USART2_UART_Init();
caa45040 7:02fa6ef78ec9 95 /* USER CODE BEGIN 2 */
caa45040 7:02fa6ef78ec9 96
caa45040 7:02fa6ef78ec9 97 #define ADDR (0x70<<1) // address
caa45040 7:02fa6ef78ec9 98
caa45040 7:02fa6ef78ec9 99 uint8_t buf[16];
caa45040 7:02fa6ef78ec9 100
caa45040 7:02fa6ef78ec9 101 buf[0]=0x21;
caa45040 7:02fa6ef78ec9 102 HAL_I2C_Master_Transmit(&hi2c1, ADDR, buf, 1, 3000);HAL_Delay(1);
caa45040 7:02fa6ef78ec9 103
caa45040 7:02fa6ef78ec9 104 buf[0]=0x81;
caa45040 7:02fa6ef78ec9 105 HAL_I2C_Master_Transmit(&hi2c1, ADDR, buf, 1, 3000);HAL_Delay(1);
caa45040 7:02fa6ef78ec9 106
caa45040 7:02fa6ef78ec9 107 buf[0]=0xef;
caa45040 7:02fa6ef78ec9 108 HAL_I2C_Master_Transmit(&hi2c1, ADDR, buf, 1, 3000);HAL_Delay(1);
caa45040 7:02fa6ef78ec9 109
caa45040 7:02fa6ef78ec9 110 for(int ii=0;ii<16;ii++){
caa45040 7:02fa6ef78ec9 111 buf[0]=ii;
caa45040 7:02fa6ef78ec9 112 buf[1]=0x00;
caa45040 7:02fa6ef78ec9 113 HAL_I2C_Master_Transmit(&hi2c1, ADDR, buf, 2, 3000);HAL_Delay(1);
caa45040 7:02fa6ef78ec9 114 }//for
caa45040 7:02fa6ef78ec9 115
caa45040 7:02fa6ef78ec9 116
caa45040 7:02fa6ef78ec9 117
caa45040 7:02fa6ef78ec9 118 /* USER CODE END 2 */
caa45040 7:02fa6ef78ec9 119
caa45040 7:02fa6ef78ec9 120 /* Infinite loop */
caa45040 7:02fa6ef78ec9 121 /* USER CODE BEGIN WHILE */
caa45040 7:02fa6ef78ec9 122 while (1)
caa45040 7:02fa6ef78ec9 123 {
caa45040 7:02fa6ef78ec9 124 /* USER CODE END WHILE */
caa45040 7:02fa6ef78ec9 125
caa45040 7:02fa6ef78ec9 126
caa45040 7:02fa6ef78ec9 127
caa45040 7:02fa6ef78ec9 128 while(1) {
caa45040 7:02fa6ef78ec9 129
caa45040 7:02fa6ef78ec9 130
caa45040 7:02fa6ef78ec9 131
caa45040 7:02fa6ef78ec9 132 buf[0]=0;
caa45040 7:02fa6ef78ec9 133 buf[1]=1;
caa45040 7:02fa6ef78ec9 134 HAL_I2C_Master_Transmit(&hi2c1, ADDR, buf, 2, 3000);HAL_Delay(600);
caa45040 7:02fa6ef78ec9 135
caa45040 7:02fa6ef78ec9 136 buf[0]=0;
caa45040 7:02fa6ef78ec9 137 buf[1]=0;
caa45040 7:02fa6ef78ec9 138 HAL_I2C_Master_Transmit(&hi2c1, ADDR, buf, 2, 3000);HAL_Delay(600);
caa45040 7:02fa6ef78ec9 139
caa45040 7:02fa6ef78ec9 140
caa45040 7:02fa6ef78ec9 141
caa45040 7:02fa6ef78ec9 142 }//while
caa45040 7:02fa6ef78ec9 143
caa45040 7:02fa6ef78ec9 144
caa45040 7:02fa6ef78ec9 145
caa45040 7:02fa6ef78ec9 146 /* USER CODE BEGIN 3 */
caa45040 7:02fa6ef78ec9 147 }
caa45040 7:02fa6ef78ec9 148 /* USER CODE END 3 */
caa45040 7:02fa6ef78ec9 149 }
caa45040 7:02fa6ef78ec9 150
caa45040 7:02fa6ef78ec9 151 /**
caa45040 7:02fa6ef78ec9 152 * @brief System Clock Configuration
caa45040 7:02fa6ef78ec9 153 * @retval None
caa45040 7:02fa6ef78ec9 154 */
caa45040 7:02fa6ef78ec9 155 void SystemClock_Config(void)
caa45040 7:02fa6ef78ec9 156 {
caa45040 7:02fa6ef78ec9 157 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
caa45040 7:02fa6ef78ec9 158 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
caa45040 7:02fa6ef78ec9 159 RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
caa45040 7:02fa6ef78ec9 160
caa45040 7:02fa6ef78ec9 161 /** Configure the main internal regulator output voltage
caa45040 7:02fa6ef78ec9 162 */
caa45040 7:02fa6ef78ec9 163 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
caa45040 7:02fa6ef78ec9 164 /** Initializes the RCC Oscillators according to the specified parameters
caa45040 7:02fa6ef78ec9 165 * in the RCC_OscInitTypeDef structure.
caa45040 7:02fa6ef78ec9 166 */
caa45040 7:02fa6ef78ec9 167 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
caa45040 7:02fa6ef78ec9 168 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
caa45040 7:02fa6ef78ec9 169 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
caa45040 7:02fa6ef78ec9 170 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
caa45040 7:02fa6ef78ec9 171 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
caa45040 7:02fa6ef78ec9 172 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
caa45040 7:02fa6ef78ec9 173 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
caa45040 7:02fa6ef78ec9 174 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
caa45040 7:02fa6ef78ec9 175 {
caa45040 7:02fa6ef78ec9 176 Error_Handler();
caa45040 7:02fa6ef78ec9 177 }
caa45040 7:02fa6ef78ec9 178 /** Initializes the CPU, AHB and APB buses clocks
caa45040 7:02fa6ef78ec9 179 */
caa45040 7:02fa6ef78ec9 180 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
caa45040 7:02fa6ef78ec9 181 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
caa45040 7:02fa6ef78ec9 182 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
caa45040 7:02fa6ef78ec9 183 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
caa45040 7:02fa6ef78ec9 184 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
caa45040 7:02fa6ef78ec9 185 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
caa45040 7:02fa6ef78ec9 186
caa45040 7:02fa6ef78ec9 187 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
caa45040 7:02fa6ef78ec9 188 {
caa45040 7:02fa6ef78ec9 189 Error_Handler();
caa45040 7:02fa6ef78ec9 190 }
caa45040 7:02fa6ef78ec9 191 PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2|RCC_PERIPHCLK_I2C1;
caa45040 7:02fa6ef78ec9 192 PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
caa45040 7:02fa6ef78ec9 193 PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
caa45040 7:02fa6ef78ec9 194 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
caa45040 7:02fa6ef78ec9 195 {
caa45040 7:02fa6ef78ec9 196 Error_Handler();
caa45040 7:02fa6ef78ec9 197 }
caa45040 7:02fa6ef78ec9 198 }
caa45040 7:02fa6ef78ec9 199
caa45040 7:02fa6ef78ec9 200 /**
caa45040 7:02fa6ef78ec9 201 * @brief I2C1 Initialization Function
caa45040 7:02fa6ef78ec9 202 * @param None
caa45040 7:02fa6ef78ec9 203 * @retval None
caa45040 7:02fa6ef78ec9 204 */
caa45040 7:02fa6ef78ec9 205 static void MX_I2C1_Init(void)
caa45040 7:02fa6ef78ec9 206 {
caa45040 7:02fa6ef78ec9 207
caa45040 7:02fa6ef78ec9 208 /* USER CODE BEGIN I2C1_Init 0 */
caa45040 7:02fa6ef78ec9 209
caa45040 7:02fa6ef78ec9 210 /* USER CODE END I2C1_Init 0 */
caa45040 7:02fa6ef78ec9 211
caa45040 7:02fa6ef78ec9 212 /* USER CODE BEGIN I2C1_Init 1 */
caa45040 7:02fa6ef78ec9 213
caa45040 7:02fa6ef78ec9 214 /* USER CODE END I2C1_Init 1 */
caa45040 7:02fa6ef78ec9 215 hi2c1.Instance = I2C1;
caa45040 7:02fa6ef78ec9 216 hi2c1.Init.Timing = 0x00707CBB;
caa45040 7:02fa6ef78ec9 217 hi2c1.Init.OwnAddress1 = 0;
caa45040 7:02fa6ef78ec9 218 hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
caa45040 7:02fa6ef78ec9 219 hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
caa45040 7:02fa6ef78ec9 220 hi2c1.Init.OwnAddress2 = 0;
caa45040 7:02fa6ef78ec9 221 hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
caa45040 7:02fa6ef78ec9 222 hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
caa45040 7:02fa6ef78ec9 223 hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
caa45040 7:02fa6ef78ec9 224 if (HAL_I2C_Init(&hi2c1) != HAL_OK)
caa45040 7:02fa6ef78ec9 225 {
caa45040 7:02fa6ef78ec9 226 Error_Handler();
caa45040 7:02fa6ef78ec9 227 }
caa45040 7:02fa6ef78ec9 228 /** Configure Analogue filter
caa45040 7:02fa6ef78ec9 229 */
caa45040 7:02fa6ef78ec9 230 if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
caa45040 7:02fa6ef78ec9 231 {
caa45040 7:02fa6ef78ec9 232 Error_Handler();
caa45040 7:02fa6ef78ec9 233 }
caa45040 7:02fa6ef78ec9 234 /** Configure Digital filter
caa45040 7:02fa6ef78ec9 235 */
caa45040 7:02fa6ef78ec9 236 if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
caa45040 7:02fa6ef78ec9 237 {
caa45040 7:02fa6ef78ec9 238 Error_Handler();
caa45040 7:02fa6ef78ec9 239 }
caa45040 7:02fa6ef78ec9 240 /* USER CODE BEGIN I2C1_Init 2 */
caa45040 7:02fa6ef78ec9 241
caa45040 7:02fa6ef78ec9 242 /* USER CODE END I2C1_Init 2 */
caa45040 7:02fa6ef78ec9 243
caa45040 7:02fa6ef78ec9 244 }
caa45040 7:02fa6ef78ec9 245
caa45040 7:02fa6ef78ec9 246 /**
caa45040 7:02fa6ef78ec9 247 * @brief USART2 Initialization Function
caa45040 7:02fa6ef78ec9 248 * @param None
caa45040 7:02fa6ef78ec9 249 * @retval None
caa45040 7:02fa6ef78ec9 250 */
caa45040 7:02fa6ef78ec9 251 static void MX_USART2_UART_Init(void)
caa45040 7:02fa6ef78ec9 252 {
caa45040 7:02fa6ef78ec9 253
caa45040 7:02fa6ef78ec9 254 /* USER CODE BEGIN USART2_Init 0 */
caa45040 7:02fa6ef78ec9 255
caa45040 7:02fa6ef78ec9 256 /* USER CODE END USART2_Init 0 */
caa45040 7:02fa6ef78ec9 257
caa45040 7:02fa6ef78ec9 258 /* USER CODE BEGIN USART2_Init 1 */
caa45040 7:02fa6ef78ec9 259
caa45040 7:02fa6ef78ec9 260 /* USER CODE END USART2_Init 1 */
caa45040 7:02fa6ef78ec9 261 huart2.Instance = USART2;
caa45040 7:02fa6ef78ec9 262 huart2.Init.BaudRate = 115200;
caa45040 7:02fa6ef78ec9 263 huart2.Init.WordLength = UART_WORDLENGTH_8B;
caa45040 7:02fa6ef78ec9 264 huart2.Init.StopBits = UART_STOPBITS_1;
caa45040 7:02fa6ef78ec9 265 huart2.Init.Parity = UART_PARITY_NONE;
caa45040 7:02fa6ef78ec9 266 huart2.Init.Mode = UART_MODE_TX_RX;
caa45040 7:02fa6ef78ec9 267 huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
caa45040 7:02fa6ef78ec9 268 huart2.Init.OverSampling = UART_OVERSAMPLING_16;
caa45040 7:02fa6ef78ec9 269 huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
caa45040 7:02fa6ef78ec9 270 huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
caa45040 7:02fa6ef78ec9 271 if (HAL_UART_Init(&huart2) != HAL_OK)
caa45040 7:02fa6ef78ec9 272 {
caa45040 7:02fa6ef78ec9 273 Error_Handler();
caa45040 7:02fa6ef78ec9 274 }
caa45040 7:02fa6ef78ec9 275 /* USER CODE BEGIN USART2_Init 2 */
caa45040 7:02fa6ef78ec9 276
caa45040 7:02fa6ef78ec9 277 /* USER CODE END USART2_Init 2 */
caa45040 7:02fa6ef78ec9 278
caa45040 7:02fa6ef78ec9 279 }
caa45040 7:02fa6ef78ec9 280
caa45040 7:02fa6ef78ec9 281 /**
caa45040 7:02fa6ef78ec9 282 * @brief GPIO Initialization Function
caa45040 7:02fa6ef78ec9 283 * @param None
caa45040 7:02fa6ef78ec9 284 * @retval None
caa45040 7:02fa6ef78ec9 285 */
caa45040 7:02fa6ef78ec9 286 static void MX_GPIO_Init(void)
caa45040 7:02fa6ef78ec9 287 {
caa45040 7:02fa6ef78ec9 288 GPIO_InitTypeDef GPIO_InitStruct = {0};
caa45040 7:02fa6ef78ec9 289
caa45040 7:02fa6ef78ec9 290 /* GPIO Ports Clock Enable */
caa45040 7:02fa6ef78ec9 291 __HAL_RCC_GPIOC_CLK_ENABLE();
caa45040 7:02fa6ef78ec9 292 __HAL_RCC_GPIOA_CLK_ENABLE();
caa45040 7:02fa6ef78ec9 293 __HAL_RCC_GPIOB_CLK_ENABLE();
caa45040 7:02fa6ef78ec9 294
caa45040 7:02fa6ef78ec9 295 /*Configure GPIO pin Output Level */
caa45040 7:02fa6ef78ec9 296 HAL_GPIO_WritePin(LD3_GPIO_Port, LD3_Pin, GPIO_PIN_RESET);
caa45040 7:02fa6ef78ec9 297
caa45040 7:02fa6ef78ec9 298 /*Configure GPIO pin : LD3_Pin */
caa45040 7:02fa6ef78ec9 299 GPIO_InitStruct.Pin = LD3_Pin;
caa45040 7:02fa6ef78ec9 300 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
caa45040 7:02fa6ef78ec9 301 GPIO_InitStruct.Pull = GPIO_NOPULL;
caa45040 7:02fa6ef78ec9 302 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
caa45040 7:02fa6ef78ec9 303 HAL_GPIO_Init(LD3_GPIO_Port, &GPIO_InitStruct);
caa45040 7:02fa6ef78ec9 304
caa45040 7:02fa6ef78ec9 305 }
caa45040 7:02fa6ef78ec9 306
caa45040 7:02fa6ef78ec9 307 /* USER CODE BEGIN 4 */
caa45040 7:02fa6ef78ec9 308
caa45040 7:02fa6ef78ec9 309 /* USER CODE END 4 */
caa45040 7:02fa6ef78ec9 310
caa45040 7:02fa6ef78ec9 311 /**
caa45040 7:02fa6ef78ec9 312 * @brief This function is executed in case of error occurrence.
caa45040 7:02fa6ef78ec9 313 * @retval None
caa45040 7:02fa6ef78ec9 314 */
caa45040 7:02fa6ef78ec9 315 void Error_Handler(void)
caa45040 7:02fa6ef78ec9 316 {
caa45040 7:02fa6ef78ec9 317 /* USER CODE BEGIN Error_Handler_Debug */
caa45040 7:02fa6ef78ec9 318 /* User can add his own implementation to report the HAL error return state */
caa45040 7:02fa6ef78ec9 319 __disable_irq();
caa45040 7:02fa6ef78ec9 320 while (1)
caa45040 7:02fa6ef78ec9 321 {
caa45040 7:02fa6ef78ec9 322 }
caa45040 7:02fa6ef78ec9 323 /* USER CODE END Error_Handler_Debug */
caa45040 7:02fa6ef78ec9 324 }
caa45040 7:02fa6ef78ec9 325
caa45040 7:02fa6ef78ec9 326 #ifdef USE_FULL_ASSERT
caa45040 7:02fa6ef78ec9 327 /**
caa45040 7:02fa6ef78ec9 328 * @brief Reports the name of the source file and the source line number
caa45040 7:02fa6ef78ec9 329 * where the assert_param error has occurred.
caa45040 7:02fa6ef78ec9 330 * @param file: pointer to the source file name
caa45040 7:02fa6ef78ec9 331 * @param line: assert_param error line source number
caa45040 7:02fa6ef78ec9 332 * @retval None
caa45040 7:02fa6ef78ec9 333 */
caa45040 7:02fa6ef78ec9 334 void assert_failed(uint8_t *file, uint32_t line)
caa45040 7:02fa6ef78ec9 335 {
caa45040 7:02fa6ef78ec9 336 /* USER CODE BEGIN 6 */
caa45040 7:02fa6ef78ec9 337 /* User can add his own implementation to report the file name and line number,
caa45040 7:02fa6ef78ec9 338 ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
caa45040 7:02fa6ef78ec9 339 /* USER CODE END 6 */
caa45040 7:02fa6ef78ec9 340 }
caa45040 7:02fa6ef78ec9 341 #endif /* USE_FULL_ASSERT */
caa45040 7:02fa6ef78ec9 342
caa45040 7:02fa6ef78ec9 343 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
caa45040 7:02fa6ef78ec9 344