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I2C_SLAVE_TEST2_031_2/system_stm32g0xx.c@26:a047b389adfd, 2022-05-06 (annotated)

Committer:
caa45040
Date:
Fri May 06 14:22:30 2022 +0000
Revision:
26:a047b389adfd
Parent:
20:745e8267e7f5 
i2c_slave_HC_SR04_010_BIN re

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caa45040 20:745e8267e7f5 1 /**
caa45040 20:745e8267e7f5 2 ******************************************************************************
caa45040 20:745e8267e7f5 3 * @file system_stm32g0xx.c
caa45040 20:745e8267e7f5 4 * @author MCD Application Team
caa45040 20:745e8267e7f5 5 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File
caa45040 20:745e8267e7f5 6 *
caa45040 20:745e8267e7f5 7 * This file provides two functions and one global variable to be called from
caa45040 20:745e8267e7f5 8 * user application:
caa45040 20:745e8267e7f5 9 * - SystemInit(): This function is called at startup just after reset and
caa45040 20:745e8267e7f5 10 * before branch to main program. This call is made inside
caa45040 20:745e8267e7f5 11 * the "startup_stm32g0xx.s" file.
caa45040 20:745e8267e7f5 12 *
caa45040 20:745e8267e7f5 13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
caa45040 20:745e8267e7f5 14 * by the user application to setup the SysTick
caa45040 20:745e8267e7f5 15 * timer or configure other parameters.
caa45040 20:745e8267e7f5 16 *
caa45040 20:745e8267e7f5 17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
caa45040 20:745e8267e7f5 18 * be called whenever the core clock is changed
caa45040 20:745e8267e7f5 19 * during program execution.
caa45040 20:745e8267e7f5 20 *
caa45040 20:745e8267e7f5 21 * After each device reset the HSI (8 MHz then 16 MHz) is used as system clock source.
caa45040 20:745e8267e7f5 22 * Then SystemInit() function is called, in "startup_stm32g0xx.s" file, to
caa45040 20:745e8267e7f5 23 * configure the system clock before to branch to main program.
caa45040 20:745e8267e7f5 24 *
caa45040 20:745e8267e7f5 25 * This file configures the system clock as follows:
caa45040 20:745e8267e7f5 26 *=============================================================================
caa45040 20:745e8267e7f5 27 *-----------------------------------------------------------------------------
caa45040 20:745e8267e7f5 28 * System Clock source | HSI
caa45040 20:745e8267e7f5 29 *-----------------------------------------------------------------------------
caa45040 20:745e8267e7f5 30 * SYSCLK(Hz) | 16000000
caa45040 20:745e8267e7f5 31 *-----------------------------------------------------------------------------
caa45040 20:745e8267e7f5 32 * HCLK(Hz) | 16000000
caa45040 20:745e8267e7f5 33 *-----------------------------------------------------------------------------
caa45040 20:745e8267e7f5 34 * AHB Prescaler | 1
caa45040 20:745e8267e7f5 35 *-----------------------------------------------------------------------------
caa45040 20:745e8267e7f5 36 * APB Prescaler | 1
caa45040 20:745e8267e7f5 37 *-----------------------------------------------------------------------------
caa45040 20:745e8267e7f5 38 * HSI Division factor | 1
caa45040 20:745e8267e7f5 39 *-----------------------------------------------------------------------------
caa45040 20:745e8267e7f5 40 * PLL_M | 1
caa45040 20:745e8267e7f5 41 *-----------------------------------------------------------------------------
caa45040 20:745e8267e7f5 42 * PLL_N | 8
caa45040 20:745e8267e7f5 43 *-----------------------------------------------------------------------------
caa45040 20:745e8267e7f5 44 * PLL_P | 7
caa45040 20:745e8267e7f5 45 *-----------------------------------------------------------------------------
caa45040 20:745e8267e7f5 46 * PLL_Q | 2
caa45040 20:745e8267e7f5 47 *-----------------------------------------------------------------------------
caa45040 20:745e8267e7f5 48 * PLL_R | 2
caa45040 20:745e8267e7f5 49 *-----------------------------------------------------------------------------
caa45040 20:745e8267e7f5 50 * Require 48MHz for RNG | Disabled
caa45040 20:745e8267e7f5 51 *-----------------------------------------------------------------------------
caa45040 20:745e8267e7f5 52 *=============================================================================
caa45040 20:745e8267e7f5 53 ******************************************************************************
caa45040 20:745e8267e7f5 54 * @attention
caa45040 20:745e8267e7f5 55 *
caa45040 20:745e8267e7f5 56 * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
caa45040 20:745e8267e7f5 57 * All rights reserved.</center></h2>
caa45040 20:745e8267e7f5 58 *
caa45040 20:745e8267e7f5 59 * This software component is licensed by ST under Apache License, Version 2.0,
caa45040 20:745e8267e7f5 60 * the "License"; You may not use this file except in compliance with the
caa45040 20:745e8267e7f5 61 * License. You may obtain a copy of the License at:
caa45040 20:745e8267e7f5 62 * opensource.org/licenses/Apache-2.0
caa45040 20:745e8267e7f5 63 *
caa45040 20:745e8267e7f5 64 ******************************************************************************
caa45040 20:745e8267e7f5 65 */
caa45040 20:745e8267e7f5 66
caa45040 20:745e8267e7f5 67 /** @addtogroup CMSIS
caa45040 20:745e8267e7f5 68 * @{
caa45040 20:745e8267e7f5 69 */
caa45040 20:745e8267e7f5 70
caa45040 20:745e8267e7f5 71 /** @addtogroup stm32g0xx_system
caa45040 20:745e8267e7f5 72 * @{
caa45040 20:745e8267e7f5 73 */
caa45040 20:745e8267e7f5 74
caa45040 20:745e8267e7f5 75 /** @addtogroup STM32G0xx_System_Private_Includes
caa45040 20:745e8267e7f5 76 * @{
caa45040 20:745e8267e7f5 77 */
caa45040 20:745e8267e7f5 78
caa45040 20:745e8267e7f5 79 #include "stm32g0xx.h"
caa45040 20:745e8267e7f5 80
caa45040 20:745e8267e7f5 81 #if !defined (HSE_VALUE)
caa45040 20:745e8267e7f5 82 #define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */
caa45040 20:745e8267e7f5 83 #endif /* HSE_VALUE */
caa45040 20:745e8267e7f5 84
caa45040 20:745e8267e7f5 85 #if !defined (HSI_VALUE)
caa45040 20:745e8267e7f5 86 #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
caa45040 20:745e8267e7f5 87 #endif /* HSI_VALUE */
caa45040 20:745e8267e7f5 88
caa45040 20:745e8267e7f5 89 #if !defined (LSI_VALUE)
caa45040 20:745e8267e7f5 90 #define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/
caa45040 20:745e8267e7f5 91 #endif /* LSI_VALUE */
caa45040 20:745e8267e7f5 92
caa45040 20:745e8267e7f5 93 #if !defined (LSE_VALUE)
caa45040 20:745e8267e7f5 94 #define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/
caa45040 20:745e8267e7f5 95 #endif /* LSE_VALUE */
caa45040 20:745e8267e7f5 96
caa45040 20:745e8267e7f5 97 /**
caa45040 20:745e8267e7f5 98 * @}
caa45040 20:745e8267e7f5 99 */
caa45040 20:745e8267e7f5 100
caa45040 20:745e8267e7f5 101 /** @addtogroup STM32G0xx_System_Private_TypesDefinitions
caa45040 20:745e8267e7f5 102 * @{
caa45040 20:745e8267e7f5 103 */
caa45040 20:745e8267e7f5 104
caa45040 20:745e8267e7f5 105 /**
caa45040 20:745e8267e7f5 106 * @}
caa45040 20:745e8267e7f5 107 */
caa45040 20:745e8267e7f5 108
caa45040 20:745e8267e7f5 109 /** @addtogroup STM32G0xx_System_Private_Defines
caa45040 20:745e8267e7f5 110 * @{
caa45040 20:745e8267e7f5 111 */
caa45040 20:745e8267e7f5 112
caa45040 20:745e8267e7f5 113 /************************* Miscellaneous Configuration ************************/
caa45040 20:745e8267e7f5 114 /*!< Uncomment the following line if you need to relocate your vector Table in
caa45040 20:745e8267e7f5 115 Internal SRAM. */
caa45040 20:745e8267e7f5 116 /* #define VECT_TAB_SRAM */
caa45040 20:745e8267e7f5 117 #define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field.
caa45040 20:745e8267e7f5 118 This value must be a multiple of 0x100. */
caa45040 20:745e8267e7f5 119 /******************************************************************************/
caa45040 20:745e8267e7f5 120 /**
caa45040 20:745e8267e7f5 121 * @}
caa45040 20:745e8267e7f5 122 */
caa45040 20:745e8267e7f5 123
caa45040 20:745e8267e7f5 124 /** @addtogroup STM32G0xx_System_Private_Macros
caa45040 20:745e8267e7f5 125 * @{
caa45040 20:745e8267e7f5 126 */
caa45040 20:745e8267e7f5 127
caa45040 20:745e8267e7f5 128 /**
caa45040 20:745e8267e7f5 129 * @}
caa45040 20:745e8267e7f5 130 */
caa45040 20:745e8267e7f5 131
caa45040 20:745e8267e7f5 132 /** @addtogroup STM32G0xx_System_Private_Variables
caa45040 20:745e8267e7f5 133 * @{
caa45040 20:745e8267e7f5 134 */
caa45040 20:745e8267e7f5 135 /* The SystemCoreClock variable is updated in three ways:
caa45040 20:745e8267e7f5 136 1) by calling CMSIS function SystemCoreClockUpdate()
caa45040 20:745e8267e7f5 137 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
caa45040 20:745e8267e7f5 138 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
caa45040 20:745e8267e7f5 139 Note: If you use this function to configure the system clock; then there
caa45040 20:745e8267e7f5 140 is no need to call the 2 first functions listed above, since SystemCoreClock
caa45040 20:745e8267e7f5 141 variable is updated automatically.
caa45040 20:745e8267e7f5 142 */
caa45040 20:745e8267e7f5 143 uint32_t SystemCoreClock = 16000000UL;
caa45040 20:745e8267e7f5 144
caa45040 20:745e8267e7f5 145 const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL};
caa45040 20:745e8267e7f5 146 const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
caa45040 20:745e8267e7f5 147
caa45040 20:745e8267e7f5 148 /**
caa45040 20:745e8267e7f5 149 * @}
caa45040 20:745e8267e7f5 150 */
caa45040 20:745e8267e7f5 151
caa45040 20:745e8267e7f5 152 /** @addtogroup STM32G0xx_System_Private_FunctionPrototypes
caa45040 20:745e8267e7f5 153 * @{
caa45040 20:745e8267e7f5 154 */
caa45040 20:745e8267e7f5 155
caa45040 20:745e8267e7f5 156 /**
caa45040 20:745e8267e7f5 157 * @}
caa45040 20:745e8267e7f5 158 */
caa45040 20:745e8267e7f5 159
caa45040 20:745e8267e7f5 160 /** @addtogroup STM32G0xx_System_Private_Functions
caa45040 20:745e8267e7f5 161 * @{
caa45040 20:745e8267e7f5 162 */
caa45040 20:745e8267e7f5 163
caa45040 20:745e8267e7f5 164 /**
caa45040 20:745e8267e7f5 165 * @brief Setup the microcontroller system.
caa45040 20:745e8267e7f5 166 * @param None
caa45040 20:745e8267e7f5 167 * @retval None
caa45040 20:745e8267e7f5 168 */
caa45040 20:745e8267e7f5 169 void SystemInit(void)
caa45040 20:745e8267e7f5 170 {
caa45040 20:745e8267e7f5 171 /* Configure the Vector Table location add offset address ------------------*/
caa45040 20:745e8267e7f5 172 #ifdef VECT_TAB_SRAM
caa45040 20:745e8267e7f5 173 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
caa45040 20:745e8267e7f5 174 #else
caa45040 20:745e8267e7f5 175 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
caa45040 20:745e8267e7f5 176 #endif
caa45040 20:745e8267e7f5 177 }
caa45040 20:745e8267e7f5 178
caa45040 20:745e8267e7f5 179 /**
caa45040 20:745e8267e7f5 180 * @brief Update SystemCoreClock variable according to Clock Register Values.
caa45040 20:745e8267e7f5 181 * The SystemCoreClock variable contains the core clock (HCLK), it can
caa45040 20:745e8267e7f5 182 * be used by the user application to setup the SysTick timer or configure
caa45040 20:745e8267e7f5 183 * other parameters.
caa45040 20:745e8267e7f5 184 *
caa45040 20:745e8267e7f5 185 * @note Each time the core clock (HCLK) changes, this function must be called
caa45040 20:745e8267e7f5 186 * to update SystemCoreClock variable value. Otherwise, any configuration
caa45040 20:745e8267e7f5 187 * based on this variable will be incorrect.
caa45040 20:745e8267e7f5 188 *
caa45040 20:745e8267e7f5 189 * @note - The system frequency computed by this function is not the real
caa45040 20:745e8267e7f5 190 * frequency in the chip. It is calculated based on the predefined
caa45040 20:745e8267e7f5 191 * constant and the selected clock source:
caa45040 20:745e8267e7f5 192 *
caa45040 20:745e8267e7f5 193 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor
caa45040 20:745e8267e7f5 194 *
caa45040 20:745e8267e7f5 195 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
caa45040 20:745e8267e7f5 196 *
caa45040 20:745e8267e7f5 197 * - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE
caa45040 20:745e8267e7f5 198 *
caa45040 20:745e8267e7f5 199 * - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE
caa45040 20:745e8267e7f5 200 *
caa45040 20:745e8267e7f5 201 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
caa45040 20:745e8267e7f5 202 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
caa45040 20:745e8267e7f5 203 *
caa45040 20:745e8267e7f5 204 * (**) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
caa45040 20:745e8267e7f5 205 * 16 MHz) but the real value may vary depending on the variations
caa45040 20:745e8267e7f5 206 * in voltage and temperature.
caa45040 20:745e8267e7f5 207 *
caa45040 20:745e8267e7f5 208 * (***) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
caa45040 20:745e8267e7f5 209 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
caa45040 20:745e8267e7f5 210 * frequency of the crystal used. Otherwise, this function may
caa45040 20:745e8267e7f5 211 * have wrong result.
caa45040 20:745e8267e7f5 212 *
caa45040 20:745e8267e7f5 213 * - The result of this function could be not correct when using fractional
caa45040 20:745e8267e7f5 214 * value for HSE crystal.
caa45040 20:745e8267e7f5 215 *
caa45040 20:745e8267e7f5 216 * @param None
caa45040 20:745e8267e7f5 217 * @retval None
caa45040 20:745e8267e7f5 218 */
caa45040 20:745e8267e7f5 219 void SystemCoreClockUpdate(void)
caa45040 20:745e8267e7f5 220 {
caa45040 20:745e8267e7f5 221 uint32_t tmp;
caa45040 20:745e8267e7f5 222 uint32_t pllvco;
caa45040 20:745e8267e7f5 223 uint32_t pllr;
caa45040 20:745e8267e7f5 224 uint32_t pllsource;
caa45040 20:745e8267e7f5 225 uint32_t pllm;
caa45040 20:745e8267e7f5 226 uint32_t hsidiv;
caa45040 20:745e8267e7f5 227
caa45040 20:745e8267e7f5 228 /* Get SYSCLK source -------------------------------------------------------*/
caa45040 20:745e8267e7f5 229 switch (RCC->CFGR & RCC_CFGR_SWS)
caa45040 20:745e8267e7f5 230 {
caa45040 20:745e8267e7f5 231 case RCC_CFGR_SWS_0: /* HSE used as system clock */
caa45040 20:745e8267e7f5 232 SystemCoreClock = HSE_VALUE;
caa45040 20:745e8267e7f5 233 break;
caa45040 20:745e8267e7f5 234
caa45040 20:745e8267e7f5 235 case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */
caa45040 20:745e8267e7f5 236 SystemCoreClock = LSI_VALUE;
caa45040 20:745e8267e7f5 237 break;
caa45040 20:745e8267e7f5 238
caa45040 20:745e8267e7f5 239 case RCC_CFGR_SWS_2: /* LSE used as system clock */
caa45040 20:745e8267e7f5 240 SystemCoreClock = LSE_VALUE;
caa45040 20:745e8267e7f5 241 break;
caa45040 20:745e8267e7f5 242
caa45040 20:745e8267e7f5 243 case RCC_CFGR_SWS_1: /* PLL used as system clock */
caa45040 20:745e8267e7f5 244 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
caa45040 20:745e8267e7f5 245 SYSCLK = PLL_VCO / PLLR
caa45040 20:745e8267e7f5 246 */
caa45040 20:745e8267e7f5 247 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
caa45040 20:745e8267e7f5 248 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL;
caa45040 20:745e8267e7f5 249
caa45040 20:745e8267e7f5 250 if(pllsource == 0x03UL) /* HSE used as PLL clock source */
caa45040 20:745e8267e7f5 251 {
caa45040 20:745e8267e7f5 252 pllvco = (HSE_VALUE / pllm);
caa45040 20:745e8267e7f5 253 }
caa45040 20:745e8267e7f5 254 else /* HSI used as PLL clock source */
caa45040 20:745e8267e7f5 255 {
caa45040 20:745e8267e7f5 256 pllvco = (HSI_VALUE / pllm);
caa45040 20:745e8267e7f5 257 }
caa45040 20:745e8267e7f5 258 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
caa45040 20:745e8267e7f5 259 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
caa45040 20:745e8267e7f5 260
caa45040 20:745e8267e7f5 261 SystemCoreClock = pllvco/pllr;
caa45040 20:745e8267e7f5 262 break;
caa45040 20:745e8267e7f5 263
caa45040 20:745e8267e7f5 264 case 0x00000000U: /* HSI used as system clock */
caa45040 20:745e8267e7f5 265 default: /* HSI used as system clock */
caa45040 20:745e8267e7f5 266 hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));
caa45040 20:745e8267e7f5 267 SystemCoreClock = (HSI_VALUE/hsidiv);
caa45040 20:745e8267e7f5 268 break;
caa45040 20:745e8267e7f5 269 }
caa45040 20:745e8267e7f5 270 /* Compute HCLK clock frequency --------------------------------------------*/
caa45040 20:745e8267e7f5 271 /* Get HCLK prescaler */
caa45040 20:745e8267e7f5 272 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
caa45040 20:745e8267e7f5 273 /* HCLK clock frequency */
caa45040 20:745e8267e7f5 274 SystemCoreClock >>= tmp;
caa45040 20:745e8267e7f5 275 }
caa45040 20:745e8267e7f5 276
caa45040 20:745e8267e7f5 277
caa45040 20:745e8267e7f5 278 /**
caa45040 20:745e8267e7f5 279 * @}
caa45040 20:745e8267e7f5 280 */
caa45040 20:745e8267e7f5 281
caa45040 20:745e8267e7f5 282 /**
caa45040 20:745e8267e7f5 283 * @}
caa45040 20:745e8267e7f5 284 */
caa45040 20:745e8267e7f5 285
caa45040 20:745e8267e7f5 286 /**
caa45040 20:745e8267e7f5 287 * @}
caa45040 20:745e8267e7f5 288 */
caa45040 20:745e8267e7f5 289
caa45040 20:745e8267e7f5 290 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
caa45040 20:745e8267e7f5 291