Giuseppe Giglio / SX1272Lib

Added support to TARGET_NUCLEO_L073RZ

Dependents:   SX1272PingPong

Fork of SX1272Lib by Semtech

sx1272/sx1272.cpp@0:45c4f0364ca4, 2016-01-05 (annotated)

Committer:
mluis
Date:
Tue Jan 05 16:43:48 2016 +0000
Revision:
0:45c4f0364ca4
Child:
3:5baff45eb3c5
Child:
7:b988b60083a1
Library creation based on SX1276Lib and https://github.com/Lora-net/LoRaMac-node

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mluis 0:45c4f0364ca4 1 /*
mluis 0:45c4f0364ca4 2 / _____) _ | |
mluis 0:45c4f0364ca4 3 ( (____ _____ ____ _| |_ _____ ____| |__
mluis 0:45c4f0364ca4 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
mluis 0:45c4f0364ca4 5 _____) ) ____| | | || |_| ____( (___| | | |
mluis 0:45c4f0364ca4 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 0:45c4f0364ca4 7 (C) 2015 Semtech
mluis 0:45c4f0364ca4 8
mluis 0:45c4f0364ca4 9 Description: Actual implementation of a SX1272 radio, inherits Radio
mluis 0:45c4f0364ca4 10
mluis 0:45c4f0364ca4 11 License: Revised BSD License, see LICENSE.TXT file include in the project
mluis 0:45c4f0364ca4 12
mluis 0:45c4f0364ca4 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
mluis 0:45c4f0364ca4 14 */
mluis 0:45c4f0364ca4 15 #include "sx1272.h"
mluis 0:45c4f0364ca4 16
mluis 0:45c4f0364ca4 17 const FskBandwidth_t SX1272::FskBandwidths[] =
mluis 0:45c4f0364ca4 18 {
mluis 0:45c4f0364ca4 19 { 2600 , 0x17 },
mluis 0:45c4f0364ca4 20 { 3100 , 0x0F },
mluis 0:45c4f0364ca4 21 { 3900 , 0x07 },
mluis 0:45c4f0364ca4 22 { 5200 , 0x16 },
mluis 0:45c4f0364ca4 23 { 6300 , 0x0E },
mluis 0:45c4f0364ca4 24 { 7800 , 0x06 },
mluis 0:45c4f0364ca4 25 { 10400 , 0x15 },
mluis 0:45c4f0364ca4 26 { 12500 , 0x0D },
mluis 0:45c4f0364ca4 27 { 15600 , 0x05 },
mluis 0:45c4f0364ca4 28 { 20800 , 0x14 },
mluis 0:45c4f0364ca4 29 { 25000 , 0x0C },
mluis 0:45c4f0364ca4 30 { 31300 , 0x04 },
mluis 0:45c4f0364ca4 31 { 41700 , 0x13 },
mluis 0:45c4f0364ca4 32 { 50000 , 0x0B },
mluis 0:45c4f0364ca4 33 { 62500 , 0x03 },
mluis 0:45c4f0364ca4 34 { 83333 , 0x12 },
mluis 0:45c4f0364ca4 35 { 100000, 0x0A },
mluis 0:45c4f0364ca4 36 { 125000, 0x02 },
mluis 0:45c4f0364ca4 37 { 166700, 0x11 },
mluis 0:45c4f0364ca4 38 { 200000, 0x09 },
mluis 0:45c4f0364ca4 39 { 250000, 0x01 },
mluis 0:45c4f0364ca4 40 { 300000, 0x00 }, // Invalid Badwidth
mluis 0:45c4f0364ca4 41 };
mluis 0:45c4f0364ca4 42
mluis 0:45c4f0364ca4 43
mluis 0:45c4f0364ca4 44 SX1272::SX1272( RadioEvents_t *events,
mluis 0:45c4f0364ca4 45 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
mluis 0:45c4f0364ca4 46 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
mluis 0:45c4f0364ca4 47 : Radio( events ),
mluis 0:45c4f0364ca4 48 spi( mosi, miso, sclk ),
mluis 0:45c4f0364ca4 49 nss( nss ),
mluis 0:45c4f0364ca4 50 reset( reset ),
mluis 0:45c4f0364ca4 51 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
mluis 0:45c4f0364ca4 52 isRadioActive( false )
mluis 0:45c4f0364ca4 53 {
mluis 0:45c4f0364ca4 54 wait_ms( 10 );
mluis 0:45c4f0364ca4 55 this->rxTx = 0;
mluis 0:45c4f0364ca4 56 this->rxBuffer = new uint8_t[RX_BUFFER_SIZE];
mluis 0:45c4f0364ca4 57 currentOpMode = RF_OPMODE_STANDBY;
mluis 0:45c4f0364ca4 58
mluis 0:45c4f0364ca4 59 this->RadioEvents = events;
mluis 0:45c4f0364ca4 60
mluis 0:45c4f0364ca4 61 this->dioIrq = new DioIrqHandler[6];
mluis 0:45c4f0364ca4 62
mluis 0:45c4f0364ca4 63 this->dioIrq[0] = &SX1272::OnDio0Irq;
mluis 0:45c4f0364ca4 64 this->dioIrq[1] = &SX1272::OnDio1Irq;
mluis 0:45c4f0364ca4 65 this->dioIrq[2] = &SX1272::OnDio2Irq;
mluis 0:45c4f0364ca4 66 this->dioIrq[3] = &SX1272::OnDio3Irq;
mluis 0:45c4f0364ca4 67 this->dioIrq[4] = &SX1272::OnDio4Irq;
mluis 0:45c4f0364ca4 68 this->dioIrq[5] = NULL;
mluis 0:45c4f0364ca4 69
mluis 0:45c4f0364ca4 70 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 71 }
mluis 0:45c4f0364ca4 72
mluis 0:45c4f0364ca4 73 SX1272::~SX1272( )
mluis 0:45c4f0364ca4 74 {
mluis 0:45c4f0364ca4 75 delete this->rxBuffer;
mluis 0:45c4f0364ca4 76 delete this->dioIrq;
mluis 0:45c4f0364ca4 77 }
mluis 0:45c4f0364ca4 78
mluis 0:45c4f0364ca4 79 void SX1272::Init( RadioEvents_t *events )
mluis 0:45c4f0364ca4 80 {
mluis 0:45c4f0364ca4 81 this->RadioEvents = events;
mluis 0:45c4f0364ca4 82 }
mluis 0:45c4f0364ca4 83
mluis 0:45c4f0364ca4 84 RadioState SX1272::GetStatus( void )
mluis 0:45c4f0364ca4 85 {
mluis 0:45c4f0364ca4 86 return this->settings.State;
mluis 0:45c4f0364ca4 87 }
mluis 0:45c4f0364ca4 88
mluis 0:45c4f0364ca4 89 void SX1272::SetChannel( uint32_t freq )
mluis 0:45c4f0364ca4 90 {
mluis 0:45c4f0364ca4 91 this->settings.Channel = freq;
mluis 0:45c4f0364ca4 92 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
mluis 0:45c4f0364ca4 93 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
mluis 0:45c4f0364ca4 94 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
mluis 0:45c4f0364ca4 95 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
mluis 0:45c4f0364ca4 96 }
mluis 0:45c4f0364ca4 97
mluis 0:45c4f0364ca4 98 bool SX1272::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
mluis 0:45c4f0364ca4 99 {
mluis 0:45c4f0364ca4 100 int16_t rssi = 0;
mluis 0:45c4f0364ca4 101
mluis 0:45c4f0364ca4 102 SetModem( modem );
mluis 0:45c4f0364ca4 103
mluis 0:45c4f0364ca4 104 SetChannel( freq );
mluis 0:45c4f0364ca4 105
mluis 0:45c4f0364ca4 106 SetOpMode( RF_OPMODE_RECEIVER );
mluis 0:45c4f0364ca4 107
mluis 0:45c4f0364ca4 108 wait_ms( 1 );
mluis 0:45c4f0364ca4 109
mluis 0:45c4f0364ca4 110 rssi = GetRssi( modem );
mluis 0:45c4f0364ca4 111
mluis 0:45c4f0364ca4 112 Sleep( );
mluis 0:45c4f0364ca4 113
mluis 0:45c4f0364ca4 114 if( rssi > rssiThresh )
mluis 0:45c4f0364ca4 115 {
mluis 0:45c4f0364ca4 116 return false;
mluis 0:45c4f0364ca4 117 }
mluis 0:45c4f0364ca4 118 return true;
mluis 0:45c4f0364ca4 119 }
mluis 0:45c4f0364ca4 120
mluis 0:45c4f0364ca4 121 uint32_t SX1272::Random( void )
mluis 0:45c4f0364ca4 122 {
mluis 0:45c4f0364ca4 123 uint8_t i;
mluis 0:45c4f0364ca4 124 uint32_t rnd = 0;
mluis 0:45c4f0364ca4 125
mluis 0:45c4f0364ca4 126 /*
mluis 0:45c4f0364ca4 127 * Radio setup for random number generation
mluis 0:45c4f0364ca4 128 */
mluis 0:45c4f0364ca4 129 // Set LoRa modem ON
mluis 0:45c4f0364ca4 130 SetModem( MODEM_LORA );
mluis 0:45c4f0364ca4 131
mluis 0:45c4f0364ca4 132 // Disable LoRa modem interrupts
mluis 0:45c4f0364ca4 133 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 134 RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 135 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 136 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 137 RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 138 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 139 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 140 RFLR_IRQFLAGS_CADDETECTED );
mluis 0:45c4f0364ca4 141
mluis 0:45c4f0364ca4 142 // Set radio in continuous reception
mluis 0:45c4f0364ca4 143 SetOpMode( RF_OPMODE_RECEIVER );
mluis 0:45c4f0364ca4 144
mluis 0:45c4f0364ca4 145 for( i = 0; i < 32; i++ )
mluis 0:45c4f0364ca4 146 {
mluis 0:45c4f0364ca4 147 wait_ms( 1 );
mluis 0:45c4f0364ca4 148 // Unfiltered RSSI value reading. Only takes the LSB value
mluis 0:45c4f0364ca4 149 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
mluis 0:45c4f0364ca4 150 }
mluis 0:45c4f0364ca4 151
mluis 0:45c4f0364ca4 152 Sleep( );
mluis 0:45c4f0364ca4 153
mluis 0:45c4f0364ca4 154 return rnd;
mluis 0:45c4f0364ca4 155 }
mluis 0:45c4f0364ca4 156
mluis 0:45c4f0364ca4 157 /*!
mluis 0:45c4f0364ca4 158 * Returns the known FSK bandwidth registers value
mluis 0:45c4f0364ca4 159 *
mluis 0:45c4f0364ca4 160 * \param [IN] bandwidth Bandwidth value in Hz
mluis 0:45c4f0364ca4 161 * \retval regValue Bandwidth register value.
mluis 0:45c4f0364ca4 162 */
mluis 0:45c4f0364ca4 163 uint8_t SX1272::GetFskBandwidthRegValue( uint32_t bandwidth )
mluis 0:45c4f0364ca4 164 {
mluis 0:45c4f0364ca4 165 uint8_t i;
mluis 0:45c4f0364ca4 166
mluis 0:45c4f0364ca4 167 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
mluis 0:45c4f0364ca4 168 {
mluis 0:45c4f0364ca4 169 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
mluis 0:45c4f0364ca4 170 {
mluis 0:45c4f0364ca4 171 return FskBandwidths[i].RegValue;
mluis 0:45c4f0364ca4 172 }
mluis 0:45c4f0364ca4 173 }
mluis 0:45c4f0364ca4 174 // ERROR: Value not found
mluis 0:45c4f0364ca4 175 while( 1 );
mluis 0:45c4f0364ca4 176 }
mluis 0:45c4f0364ca4 177
mluis 0:45c4f0364ca4 178 void SX1272::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
mluis 0:45c4f0364ca4 179 uint32_t datarate, uint8_t coderate,
mluis 0:45c4f0364ca4 180 uint32_t bandwidthAfc, uint16_t preambleLen,
mluis 0:45c4f0364ca4 181 uint16_t symbTimeout, bool fixLen,
mluis 0:45c4f0364ca4 182 uint8_t payloadLen,
mluis 0:45c4f0364ca4 183 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
mluis 0:45c4f0364ca4 184 bool iqInverted, bool rxContinuous )
mluis 0:45c4f0364ca4 185 {
mluis 0:45c4f0364ca4 186 SetModem( modem );
mluis 0:45c4f0364ca4 187
mluis 0:45c4f0364ca4 188 switch( modem )
mluis 0:45c4f0364ca4 189 {
mluis 0:45c4f0364ca4 190 case MODEM_FSK:
mluis 0:45c4f0364ca4 191 {
mluis 0:45c4f0364ca4 192 this->settings.Fsk.Bandwidth = bandwidth;
mluis 0:45c4f0364ca4 193 this->settings.Fsk.Datarate = datarate;
mluis 0:45c4f0364ca4 194 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
mluis 0:45c4f0364ca4 195 this->settings.Fsk.FixLen = fixLen;
mluis 0:45c4f0364ca4 196 this->settings.Fsk.PayloadLen = payloadLen;
mluis 0:45c4f0364ca4 197 this->settings.Fsk.CrcOn = crcOn;
mluis 0:45c4f0364ca4 198 this->settings.Fsk.IqInverted = iqInverted;
mluis 0:45c4f0364ca4 199 this->settings.Fsk.RxContinuous = rxContinuous;
mluis 0:45c4f0364ca4 200 this->settings.Fsk.PreambleLen = preambleLen;
mluis 0:45c4f0364ca4 201
mluis 0:45c4f0364ca4 202 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
mluis 0:45c4f0364ca4 203 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
mluis 0:45c4f0364ca4 204 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
mluis 0:45c4f0364ca4 205
mluis 0:45c4f0364ca4 206 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
mluis 0:45c4f0364ca4 207 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
mluis 0:45c4f0364ca4 208
mluis 0:45c4f0364ca4 209 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 0:45c4f0364ca4 210 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
mluis 0:45c4f0364ca4 211
mluis 0:45c4f0364ca4 212 if( fixLen == 1 )
mluis 0:45c4f0364ca4 213 {
mluis 0:45c4f0364ca4 214 Write( REG_PAYLOADLENGTH, payloadLen );
mluis 0:45c4f0364ca4 215 }
mluis 0:45c4f0364ca4 216
mluis 0:45c4f0364ca4 217 Write( REG_PACKETCONFIG1,
mluis 0:45c4f0364ca4 218 ( Read( REG_PACKETCONFIG1 ) &
mluis 0:45c4f0364ca4 219 RF_PACKETCONFIG1_CRC_MASK &
mluis 0:45c4f0364ca4 220 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
mluis 0:45c4f0364ca4 221 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
mluis 0:45c4f0364ca4 222 ( crcOn << 4 ) );
mluis 0:45c4f0364ca4 223 }
mluis 0:45c4f0364ca4 224 break;
mluis 0:45c4f0364ca4 225 case MODEM_LORA:
mluis 0:45c4f0364ca4 226 {
mluis 0:45c4f0364ca4 227 this->settings.LoRa.Bandwidth = bandwidth;
mluis 0:45c4f0364ca4 228 this->settings.LoRa.Datarate = datarate;
mluis 0:45c4f0364ca4 229 this->settings.LoRa.Coderate = coderate;
mluis 0:45c4f0364ca4 230 this->settings.LoRa.PreambleLen = preambleLen;
mluis 0:45c4f0364ca4 231 this->settings.LoRa.FixLen = fixLen;
mluis 0:45c4f0364ca4 232 this->settings.LoRa.PayloadLen = payloadLen;
mluis 0:45c4f0364ca4 233 this->settings.LoRa.CrcOn = crcOn;
mluis 0:45c4f0364ca4 234 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 0:45c4f0364ca4 235 this->settings.LoRa.HopPeriod = hopPeriod;
mluis 0:45c4f0364ca4 236 this->settings.LoRa.IqInverted = iqInverted;
mluis 0:45c4f0364ca4 237 this->settings.LoRa.RxContinuous = rxContinuous;
mluis 0:45c4f0364ca4 238
mluis 0:45c4f0364ca4 239 if( datarate > 12 )
mluis 0:45c4f0364ca4 240 {
mluis 0:45c4f0364ca4 241 datarate = 12;
mluis 0:45c4f0364ca4 242 }
mluis 0:45c4f0364ca4 243 else if( datarate < 6 )
mluis 0:45c4f0364ca4 244 {
mluis 0:45c4f0364ca4 245 datarate = 6;
mluis 0:45c4f0364ca4 246 }
mluis 0:45c4f0364ca4 247
mluis 0:45c4f0364ca4 248 if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
mluis 0:45c4f0364ca4 249 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
mluis 0:45c4f0364ca4 250 {
mluis 0:45c4f0364ca4 251 this->settings.LoRa.LowDatarateOptimize = 0x01;
mluis 0:45c4f0364ca4 252 }
mluis 0:45c4f0364ca4 253 else
mluis 0:45c4f0364ca4 254 {
mluis 0:45c4f0364ca4 255 this->settings.LoRa.LowDatarateOptimize = 0x00;
mluis 0:45c4f0364ca4 256 }
mluis 0:45c4f0364ca4 257
mluis 0:45c4f0364ca4 258 Write( REG_LR_MODEMCONFIG1,
mluis 0:45c4f0364ca4 259 ( Read( REG_LR_MODEMCONFIG1 ) &
mluis 0:45c4f0364ca4 260 RFLR_MODEMCONFIG1_BW_MASK &
mluis 0:45c4f0364ca4 261 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
mluis 0:45c4f0364ca4 262 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
mluis 0:45c4f0364ca4 263 RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
mluis 0:45c4f0364ca4 264 RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 265 ( bandwidth << 6 ) | ( coderate << 3 ) |
mluis 0:45c4f0364ca4 266 ( fixLen << 2 ) | ( crcOn << 1 ) |
mluis 0:45c4f0364ca4 267 this->settings.LoRa.LowDatarateOptimize );
mluis 0:45c4f0364ca4 268
mluis 0:45c4f0364ca4 269 Write( REG_LR_MODEMCONFIG2,
mluis 0:45c4f0364ca4 270 ( Read( REG_LR_MODEMCONFIG2 ) &
mluis 0:45c4f0364ca4 271 RFLR_MODEMCONFIG2_SF_MASK &
mluis 0:45c4f0364ca4 272 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
mluis 0:45c4f0364ca4 273 ( datarate << 4 ) |
mluis 0:45c4f0364ca4 274 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
mluis 0:45c4f0364ca4 275
mluis 0:45c4f0364ca4 276 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
mluis 0:45c4f0364ca4 277
mluis 0:45c4f0364ca4 278 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 0:45c4f0364ca4 279 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
mluis 0:45c4f0364ca4 280
mluis 0:45c4f0364ca4 281 if( fixLen == 1 )
mluis 0:45c4f0364ca4 282 {
mluis 0:45c4f0364ca4 283 Write( REG_LR_PAYLOADLENGTH, payloadLen );
mluis 0:45c4f0364ca4 284 }
mluis 0:45c4f0364ca4 285
mluis 0:45c4f0364ca4 286 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 287 {
mluis 0:45c4f0364ca4 288 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
mluis 0:45c4f0364ca4 289 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
mluis 0:45c4f0364ca4 290 }
mluis 0:45c4f0364ca4 291
mluis 0:45c4f0364ca4 292 if( datarate == 6 )
mluis 0:45c4f0364ca4 293 {
mluis 0:45c4f0364ca4 294 Write( REG_LR_DETECTOPTIMIZE,
mluis 0:45c4f0364ca4 295 ( Read( REG_LR_DETECTOPTIMIZE ) &
mluis 0:45c4f0364ca4 296 RFLR_DETECTIONOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 297 RFLR_DETECTIONOPTIMIZE_SF6 );
mluis 0:45c4f0364ca4 298 Write( REG_LR_DETECTIONTHRESHOLD,
mluis 0:45c4f0364ca4 299 RFLR_DETECTIONTHRESH_SF6 );
mluis 0:45c4f0364ca4 300 }
mluis 0:45c4f0364ca4 301 else
mluis 0:45c4f0364ca4 302 {
mluis 0:45c4f0364ca4 303 Write( REG_LR_DETECTOPTIMIZE,
mluis 0:45c4f0364ca4 304 ( Read( REG_LR_DETECTOPTIMIZE ) &
mluis 0:45c4f0364ca4 305 RFLR_DETECTIONOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 306 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
mluis 0:45c4f0364ca4 307 Write( REG_LR_DETECTIONTHRESHOLD,
mluis 0:45c4f0364ca4 308 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
mluis 0:45c4f0364ca4 309 }
mluis 0:45c4f0364ca4 310 }
mluis 0:45c4f0364ca4 311 break;
mluis 0:45c4f0364ca4 312 }
mluis 0:45c4f0364ca4 313 }
mluis 0:45c4f0364ca4 314 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 315 /* PD_2=0 PD_2=1
mluis 0:45c4f0364ca4 316 op PaB rfo rfo
mluis 0:45c4f0364ca4 317 0 4.6 18.5 27.0
mluis 0:45c4f0364ca4 318 1 5.6 21.1 28.1
mluis 0:45c4f0364ca4 319 2 6.7 23.3 29.1
mluis 0:45c4f0364ca4 320 3 7.7 25.3 30.1
mluis 0:45c4f0364ca4 321 4 8.8 26.2 30.7
mluis 0:45c4f0364ca4 322 5 9.8 27.3 31.2
mluis 0:45c4f0364ca4 323 6 10.7 28.1 31.6
mluis 0:45c4f0364ca4 324 7 11.7 28.6 32.2
mluis 0:45c4f0364ca4 325 8 12.8 29.2 32.4
mluis 0:45c4f0364ca4 326 9 13.7 29.9 32.9
mluis 0:45c4f0364ca4 327 10 14.7 30.5 33.1
mluis 0:45c4f0364ca4 328 11 15.6 30.8 33.4
mluis 0:45c4f0364ca4 329 12 16.4 30.9 33.6
mluis 0:45c4f0364ca4 330 13 17.1 31.0 33.7
mluis 0:45c4f0364ca4 331 14 17.8 31.1 33.7
mluis 0:45c4f0364ca4 332 15 18.4 31.1 33.7
mluis 0:45c4f0364ca4 333 */
mluis 0:45c4f0364ca4 334 // txpow: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
mluis 0:45c4f0364ca4 335 static const uint8_t PaBTable[20] = { 0, 0, 0, 0, 0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15 };
mluis 0:45c4f0364ca4 336
mluis 0:45c4f0364ca4 337 // txpow: 20 21 22 23 24 25 26 27 28 29 30
mluis 0:45c4f0364ca4 338 static const uint8_t RfoTable[11] = { 1, 1, 1, 2, 2, 3, 4, 5, 6, 8, 9 };
mluis 0:45c4f0364ca4 339 #endif
mluis 0:45c4f0364ca4 340
mluis 0:45c4f0364ca4 341 void SX1272::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
mluis 0:45c4f0364ca4 342 uint32_t bandwidth, uint32_t datarate,
mluis 0:45c4f0364ca4 343 uint8_t coderate, uint16_t preambleLen,
mluis 0:45c4f0364ca4 344 bool fixLen, bool crcOn, bool freqHopOn,
mluis 0:45c4f0364ca4 345 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
mluis 0:45c4f0364ca4 346 {
mluis 0:45c4f0364ca4 347 uint8_t paConfig = 0;
mluis 0:45c4f0364ca4 348 uint8_t paDac = 0;
mluis 0:45c4f0364ca4 349
mluis 0:45c4f0364ca4 350 SetModem( modem );
mluis 0:45c4f0364ca4 351
mluis 0:45c4f0364ca4 352 paConfig = Read( REG_PACONFIG );
mluis 0:45c4f0364ca4 353 paDac = Read( REG_PADAC );
mluis 0:45c4f0364ca4 354
mluis 0:45c4f0364ca4 355 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 356 if( power > 19 )
mluis 0:45c4f0364ca4 357 {
mluis 0:45c4f0364ca4 358 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | RF_PACONFIG_PASELECT_RFO;
mluis 0:45c4f0364ca4 359 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | RfoTable[power - 20];
mluis 0:45c4f0364ca4 360 }
mluis 0:45c4f0364ca4 361 else
mluis 0:45c4f0364ca4 362 {
mluis 0:45c4f0364ca4 363 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | RF_PACONFIG_PASELECT_PABOOST;
mluis 0:45c4f0364ca4 364 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | PaBTable[power];
mluis 0:45c4f0364ca4 365 }
mluis 0:45c4f0364ca4 366 #else
mluis 0:45c4f0364ca4 367 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
mluis 0:45c4f0364ca4 368
mluis 0:45c4f0364ca4 369 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
mluis 0:45c4f0364ca4 370 {
mluis 0:45c4f0364ca4 371 if( power > 17 )
mluis 0:45c4f0364ca4 372 {
mluis 0:45c4f0364ca4 373 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
mluis 0:45c4f0364ca4 374 }
mluis 0:45c4f0364ca4 375 else
mluis 0:45c4f0364ca4 376 {
mluis 0:45c4f0364ca4 377 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
mluis 0:45c4f0364ca4 378 }
mluis 0:45c4f0364ca4 379 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
mluis 0:45c4f0364ca4 380 {
mluis 0:45c4f0364ca4 381 if( power < 5 )
mluis 0:45c4f0364ca4 382 {
mluis 0:45c4f0364ca4 383 power = 5;
mluis 0:45c4f0364ca4 384 }
mluis 0:45c4f0364ca4 385 if( power > 20 )
mluis 0:45c4f0364ca4 386 {
mluis 0:45c4f0364ca4 387 power = 20;
mluis 0:45c4f0364ca4 388 }
mluis 0:45c4f0364ca4 389 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
mluis 0:45c4f0364ca4 390 }
mluis 0:45c4f0364ca4 391 else
mluis 0:45c4f0364ca4 392 {
mluis 0:45c4f0364ca4 393 if( power < 2 )
mluis 0:45c4f0364ca4 394 {
mluis 0:45c4f0364ca4 395 power = 2;
mluis 0:45c4f0364ca4 396 }
mluis 0:45c4f0364ca4 397 if( power > 17 )
mluis 0:45c4f0364ca4 398 {
mluis 0:45c4f0364ca4 399 power = 17;
mluis 0:45c4f0364ca4 400 }
mluis 0:45c4f0364ca4 401 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
mluis 0:45c4f0364ca4 402 }
mluis 0:45c4f0364ca4 403 }
mluis 0:45c4f0364ca4 404 else
mluis 0:45c4f0364ca4 405 {
mluis 0:45c4f0364ca4 406 if( power < -1 )
mluis 0:45c4f0364ca4 407 {
mluis 0:45c4f0364ca4 408 power = -1;
mluis 0:45c4f0364ca4 409 }
mluis 0:45c4f0364ca4 410 if( power > 14 )
mluis 0:45c4f0364ca4 411 {
mluis 0:45c4f0364ca4 412 power = 14;
mluis 0:45c4f0364ca4 413 }
mluis 0:45c4f0364ca4 414 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
mluis 0:45c4f0364ca4 415 }
mluis 0:45c4f0364ca4 416 #endif
mluis 0:45c4f0364ca4 417
mluis 0:45c4f0364ca4 418 Write( REG_PACONFIG, paConfig );
mluis 0:45c4f0364ca4 419 Write( REG_PADAC, paDac );
mluis 0:45c4f0364ca4 420
mluis 0:45c4f0364ca4 421 switch( modem )
mluis 0:45c4f0364ca4 422 {
mluis 0:45c4f0364ca4 423 case MODEM_FSK:
mluis 0:45c4f0364ca4 424 {
mluis 0:45c4f0364ca4 425 this->settings.Fsk.Power = power;
mluis 0:45c4f0364ca4 426 this->settings.Fsk.Fdev = fdev;
mluis 0:45c4f0364ca4 427 this->settings.Fsk.Bandwidth = bandwidth;
mluis 0:45c4f0364ca4 428 this->settings.Fsk.Datarate = datarate;
mluis 0:45c4f0364ca4 429 this->settings.Fsk.PreambleLen = preambleLen;
mluis 0:45c4f0364ca4 430 this->settings.Fsk.FixLen = fixLen;
mluis 0:45c4f0364ca4 431 this->settings.Fsk.CrcOn = crcOn;
mluis 0:45c4f0364ca4 432 this->settings.Fsk.IqInverted = iqInverted;
mluis 0:45c4f0364ca4 433 this->settings.Fsk.TxTimeout = timeout;
mluis 0:45c4f0364ca4 434
mluis 0:45c4f0364ca4 435 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
mluis 0:45c4f0364ca4 436 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
mluis 0:45c4f0364ca4 437 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
mluis 0:45c4f0364ca4 438
mluis 0:45c4f0364ca4 439 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
mluis 0:45c4f0364ca4 440 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
mluis 0:45c4f0364ca4 441 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
mluis 0:45c4f0364ca4 442
mluis 0:45c4f0364ca4 443 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
mluis 0:45c4f0364ca4 444 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
mluis 0:45c4f0364ca4 445
mluis 0:45c4f0364ca4 446 Write( REG_PACKETCONFIG1,
mluis 0:45c4f0364ca4 447 ( Read( REG_PACKETCONFIG1 ) &
mluis 0:45c4f0364ca4 448 RF_PACKETCONFIG1_CRC_MASK &
mluis 0:45c4f0364ca4 449 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
mluis 0:45c4f0364ca4 450 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
mluis 0:45c4f0364ca4 451 ( crcOn << 4 ) );
mluis 0:45c4f0364ca4 452
mluis 0:45c4f0364ca4 453 }
mluis 0:45c4f0364ca4 454 break;
mluis 0:45c4f0364ca4 455 case MODEM_LORA:
mluis 0:45c4f0364ca4 456 {
mluis 0:45c4f0364ca4 457 this->settings.LoRa.Power = power;
mluis 0:45c4f0364ca4 458 this->settings.LoRa.Bandwidth = bandwidth;
mluis 0:45c4f0364ca4 459 this->settings.LoRa.Datarate = datarate;
mluis 0:45c4f0364ca4 460 this->settings.LoRa.Coderate = coderate;
mluis 0:45c4f0364ca4 461 this->settings.LoRa.PreambleLen = preambleLen;
mluis 0:45c4f0364ca4 462 this->settings.LoRa.FixLen = fixLen;
mluis 0:45c4f0364ca4 463 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 0:45c4f0364ca4 464 this->settings.LoRa.HopPeriod = hopPeriod;
mluis 0:45c4f0364ca4 465 this->settings.LoRa.CrcOn = crcOn;
mluis 0:45c4f0364ca4 466 this->settings.LoRa.IqInverted = iqInverted;
mluis 0:45c4f0364ca4 467 this->settings.LoRa.TxTimeout = timeout;
mluis 0:45c4f0364ca4 468
mluis 0:45c4f0364ca4 469 if( datarate > 12 )
mluis 0:45c4f0364ca4 470 {
mluis 0:45c4f0364ca4 471 datarate = 12;
mluis 0:45c4f0364ca4 472 }
mluis 0:45c4f0364ca4 473 else if( datarate < 6 )
mluis 0:45c4f0364ca4 474 {
mluis 0:45c4f0364ca4 475 datarate = 6;
mluis 0:45c4f0364ca4 476 }
mluis 0:45c4f0364ca4 477 if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
mluis 0:45c4f0364ca4 478 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
mluis 0:45c4f0364ca4 479 {
mluis 0:45c4f0364ca4 480 this->settings.LoRa.LowDatarateOptimize = 0x01;
mluis 0:45c4f0364ca4 481 }
mluis 0:45c4f0364ca4 482 else
mluis 0:45c4f0364ca4 483 {
mluis 0:45c4f0364ca4 484 this->settings.LoRa.LowDatarateOptimize = 0x00;
mluis 0:45c4f0364ca4 485 }
mluis 0:45c4f0364ca4 486
mluis 0:45c4f0364ca4 487 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 488 {
mluis 0:45c4f0364ca4 489 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
mluis 0:45c4f0364ca4 490 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
mluis 0:45c4f0364ca4 491 }
mluis 0:45c4f0364ca4 492
mluis 0:45c4f0364ca4 493 Write( REG_LR_MODEMCONFIG1,
mluis 0:45c4f0364ca4 494 ( Read( REG_LR_MODEMCONFIG1 ) &
mluis 0:45c4f0364ca4 495 RFLR_MODEMCONFIG1_BW_MASK &
mluis 0:45c4f0364ca4 496 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
mluis 0:45c4f0364ca4 497 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
mluis 0:45c4f0364ca4 498 RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
mluis 0:45c4f0364ca4 499 RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 500 ( bandwidth << 6 ) | ( coderate << 3 ) |
mluis 0:45c4f0364ca4 501 ( fixLen << 2 ) | ( crcOn << 1 ) |
mluis 0:45c4f0364ca4 502 this->settings.LoRa.LowDatarateOptimize );
mluis 0:45c4f0364ca4 503
mluis 0:45c4f0364ca4 504 Write( REG_LR_MODEMCONFIG2,
mluis 0:45c4f0364ca4 505 ( Read( REG_LR_MODEMCONFIG2 ) &
mluis 0:45c4f0364ca4 506 RFLR_MODEMCONFIG2_SF_MASK ) |
mluis 0:45c4f0364ca4 507 ( datarate << 4 ) );
mluis 0:45c4f0364ca4 508
mluis 0:45c4f0364ca4 509
mluis 0:45c4f0364ca4 510 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
mluis 0:45c4f0364ca4 511 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
mluis 0:45c4f0364ca4 512
mluis 0:45c4f0364ca4 513 if( datarate == 6 )
mluis 0:45c4f0364ca4 514 {
mluis 0:45c4f0364ca4 515 Write( REG_LR_DETECTOPTIMIZE,
mluis 0:45c4f0364ca4 516 ( Read( REG_LR_DETECTOPTIMIZE ) &
mluis 0:45c4f0364ca4 517 RFLR_DETECTIONOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 518 RFLR_DETECTIONOPTIMIZE_SF6 );
mluis 0:45c4f0364ca4 519 Write( REG_LR_DETECTIONTHRESHOLD,
mluis 0:45c4f0364ca4 520 RFLR_DETECTIONTHRESH_SF6 );
mluis 0:45c4f0364ca4 521 }
mluis 0:45c4f0364ca4 522 else
mluis 0:45c4f0364ca4 523 {
mluis 0:45c4f0364ca4 524 Write( REG_LR_DETECTOPTIMIZE,
mluis 0:45c4f0364ca4 525 ( Read( REG_LR_DETECTOPTIMIZE ) &
mluis 0:45c4f0364ca4 526 RFLR_DETECTIONOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 527 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
mluis 0:45c4f0364ca4 528 Write( REG_LR_DETECTIONTHRESHOLD,
mluis 0:45c4f0364ca4 529 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
mluis 0:45c4f0364ca4 530 }
mluis 0:45c4f0364ca4 531 }
mluis 0:45c4f0364ca4 532 break;
mluis 0:45c4f0364ca4 533 }
mluis 0:45c4f0364ca4 534 }
mluis 0:45c4f0364ca4 535
mluis 0:45c4f0364ca4 536 double SX1272::TimeOnAir( RadioModems_t modem, uint8_t pktLen )
mluis 0:45c4f0364ca4 537 {
mluis 0:45c4f0364ca4 538 uint32_t airTime = 0;
mluis 0:45c4f0364ca4 539
mluis 0:45c4f0364ca4 540 switch( modem )
mluis 0:45c4f0364ca4 541 {
mluis 0:45c4f0364ca4 542 case MODEM_FSK:
mluis 0:45c4f0364ca4 543 {
mluis 0:45c4f0364ca4 544 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
mluis 0:45c4f0364ca4 545 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
mluis 0:45c4f0364ca4 546 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
mluis 0:45c4f0364ca4 547 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
mluis 0:45c4f0364ca4 548 pktLen +
mluis 0:45c4f0364ca4 549 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
mluis 0:45c4f0364ca4 550 this->settings.Fsk.Datarate ) * 1e6 );
mluis 0:45c4f0364ca4 551 }
mluis 0:45c4f0364ca4 552 break;
mluis 0:45c4f0364ca4 553 case MODEM_LORA:
mluis 0:45c4f0364ca4 554 {
mluis 0:45c4f0364ca4 555 double bw = 0.0;
mluis 0:45c4f0364ca4 556 switch( this->settings.LoRa.Bandwidth )
mluis 0:45c4f0364ca4 557 {
mluis 0:45c4f0364ca4 558 case 0: // 125 kHz
mluis 0:45c4f0364ca4 559 bw = 125e3;
mluis 0:45c4f0364ca4 560 break;
mluis 0:45c4f0364ca4 561 case 1: // 250 kHz
mluis 0:45c4f0364ca4 562 bw = 250e3;
mluis 0:45c4f0364ca4 563 break;
mluis 0:45c4f0364ca4 564 case 2: // 500 kHz
mluis 0:45c4f0364ca4 565 bw = 500e3;
mluis 0:45c4f0364ca4 566 break;
mluis 0:45c4f0364ca4 567 }
mluis 0:45c4f0364ca4 568
mluis 0:45c4f0364ca4 569 // Symbol rate : time for one symbol (secs)
mluis 0:45c4f0364ca4 570 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
mluis 0:45c4f0364ca4 571 double ts = 1 / rs;
mluis 0:45c4f0364ca4 572 // time of preamble
mluis 0:45c4f0364ca4 573 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
mluis 0:45c4f0364ca4 574 // Symbol length of payload and time
mluis 0:45c4f0364ca4 575 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
mluis 0:45c4f0364ca4 576 28 + 16 * this->settings.LoRa.CrcOn -
mluis 0:45c4f0364ca4 577 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
mluis 0:45c4f0364ca4 578 ( double )( 4 * this->settings.LoRa.Datarate -
mluis 0:45c4f0364ca4 579 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) *
mluis 0:45c4f0364ca4 580 ( this->settings.LoRa.Coderate + 4 );
mluis 0:45c4f0364ca4 581 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
mluis 0:45c4f0364ca4 582 double tPayload = nPayload * ts;
mluis 0:45c4f0364ca4 583 // Time on air
mluis 0:45c4f0364ca4 584 double tOnAir = tPreamble + tPayload;
mluis 0:45c4f0364ca4 585 // return us secs
mluis 0:45c4f0364ca4 586 airTime = floor( tOnAir * 1e6 + 0.999 );
mluis 0:45c4f0364ca4 587 }
mluis 0:45c4f0364ca4 588 break;
mluis 0:45c4f0364ca4 589 }
mluis 0:45c4f0364ca4 590 return airTime;
mluis 0:45c4f0364ca4 591 }
mluis 0:45c4f0364ca4 592
mluis 0:45c4f0364ca4 593 void SX1272::Send( uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 594 {
mluis 0:45c4f0364ca4 595 uint32_t txTimeout = 0;
mluis 0:45c4f0364ca4 596
mluis 0:45c4f0364ca4 597 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 598 {
mluis 0:45c4f0364ca4 599 case MODEM_FSK:
mluis 0:45c4f0364ca4 600 {
mluis 0:45c4f0364ca4 601 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 602 this->settings.FskPacketHandler.Size = size;
mluis 0:45c4f0364ca4 603
mluis 0:45c4f0364ca4 604 if( this->settings.Fsk.FixLen == false )
mluis 0:45c4f0364ca4 605 {
mluis 0:45c4f0364ca4 606 WriteFifo( ( uint8_t* )&size, 1 );
mluis 0:45c4f0364ca4 607 }
mluis 0:45c4f0364ca4 608 else
mluis 0:45c4f0364ca4 609 {
mluis 0:45c4f0364ca4 610 Write( REG_PAYLOADLENGTH, size );
mluis 0:45c4f0364ca4 611 }
mluis 0:45c4f0364ca4 612
mluis 0:45c4f0364ca4 613 if( ( size > 0 ) && ( size <= 64 ) )
mluis 0:45c4f0364ca4 614 {
mluis 0:45c4f0364ca4 615 this->settings.FskPacketHandler.ChunkSize = size;
mluis 0:45c4f0364ca4 616 }
mluis 0:45c4f0364ca4 617 else
mluis 0:45c4f0364ca4 618 {
mluis 0:45c4f0364ca4 619 this->settings.FskPacketHandler.ChunkSize = 32;
mluis 0:45c4f0364ca4 620 }
mluis 0:45c4f0364ca4 621
mluis 0:45c4f0364ca4 622 // Write payload buffer
mluis 0:45c4f0364ca4 623 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
mluis 0:45c4f0364ca4 624 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
mluis 0:45c4f0364ca4 625 txTimeout = this->settings.Fsk.TxTimeout;
mluis 0:45c4f0364ca4 626 }
mluis 0:45c4f0364ca4 627 break;
mluis 0:45c4f0364ca4 628 case MODEM_LORA:
mluis 0:45c4f0364ca4 629 {
mluis 0:45c4f0364ca4 630 if( this->settings.LoRa.IqInverted == true )
mluis 0:45c4f0364ca4 631 {
mluis 0:45c4f0364ca4 632 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
mluis 0:45c4f0364ca4 633 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
mluis 0:45c4f0364ca4 634 }
mluis 0:45c4f0364ca4 635 else
mluis 0:45c4f0364ca4 636 {
mluis 0:45c4f0364ca4 637 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 0:45c4f0364ca4 638 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
mluis 0:45c4f0364ca4 639 }
mluis 0:45c4f0364ca4 640
mluis 0:45c4f0364ca4 641 this->settings.LoRaPacketHandler.Size = size;
mluis 0:45c4f0364ca4 642
mluis 0:45c4f0364ca4 643 // Initializes the payload size
mluis 0:45c4f0364ca4 644 Write( REG_LR_PAYLOADLENGTH, size );
mluis 0:45c4f0364ca4 645
mluis 0:45c4f0364ca4 646 // Full buffer used for Tx
mluis 0:45c4f0364ca4 647 Write( REG_LR_FIFOTXBASEADDR, 0 );
mluis 0:45c4f0364ca4 648 Write( REG_LR_FIFOADDRPTR, 0 );
mluis 0:45c4f0364ca4 649
mluis 0:45c4f0364ca4 650 // FIFO operations can not take place in Sleep mode
mluis 0:45c4f0364ca4 651 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
mluis 0:45c4f0364ca4 652 {
mluis 0:45c4f0364ca4 653 Standby( );
mluis 0:45c4f0364ca4 654 wait_ms( 1 );
mluis 0:45c4f0364ca4 655 }
mluis 0:45c4f0364ca4 656 // Write payload buffer
mluis 0:45c4f0364ca4 657 WriteFifo( buffer, size );
mluis 0:45c4f0364ca4 658 txTimeout = this->settings.LoRa.TxTimeout;
mluis 0:45c4f0364ca4 659 }
mluis 0:45c4f0364ca4 660 break;
mluis 0:45c4f0364ca4 661 }
mluis 0:45c4f0364ca4 662
mluis 0:45c4f0364ca4 663 Tx( txTimeout );
mluis 0:45c4f0364ca4 664 }
mluis 0:45c4f0364ca4 665
mluis 0:45c4f0364ca4 666 void SX1272::Sleep( void )
mluis 0:45c4f0364ca4 667 {
mluis 0:45c4f0364ca4 668 txTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 669 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 670
mluis 0:45c4f0364ca4 671 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 672 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 673 }
mluis 0:45c4f0364ca4 674
mluis 0:45c4f0364ca4 675 void SX1272::Standby( void )
mluis 0:45c4f0364ca4 676 {
mluis 0:45c4f0364ca4 677 txTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 678 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 679
mluis 0:45c4f0364ca4 680 SetOpMode( RF_OPMODE_STANDBY );
mluis 0:45c4f0364ca4 681 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 682 }
mluis 0:45c4f0364ca4 683
mluis 0:45c4f0364ca4 684 void SX1272::Rx( uint32_t timeout )
mluis 0:45c4f0364ca4 685 {
mluis 0:45c4f0364ca4 686 bool rxContinuous = false;
mluis 0:45c4f0364ca4 687
mluis 0:45c4f0364ca4 688 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 689 {
mluis 0:45c4f0364ca4 690 case MODEM_FSK:
mluis 0:45c4f0364ca4 691 {
mluis 0:45c4f0364ca4 692 rxContinuous = this->settings.Fsk.RxContinuous;
mluis 0:45c4f0364ca4 693
mluis 0:45c4f0364ca4 694 // DIO0=PayloadReady
mluis 0:45c4f0364ca4 695 // DIO1=FifoLevel
mluis 0:45c4f0364ca4 696 // DIO2=SyncAddr
mluis 0:45c4f0364ca4 697 // DIO3=FifoEmpty
mluis 0:45c4f0364ca4 698 // DIO4=Preamble
mluis 0:45c4f0364ca4 699 // DIO5=ModeReady
mluis 0:45c4f0364ca4 700 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
mluis 0:45c4f0364ca4 701 RF_DIOMAPPING1_DIO2_MASK ) |
mluis 0:45c4f0364ca4 702 RF_DIOMAPPING1_DIO0_00 |
mluis 0:45c4f0364ca4 703 RF_DIOMAPPING1_DIO2_11 );
mluis 0:45c4f0364ca4 704
mluis 0:45c4f0364ca4 705 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
mluis 0:45c4f0364ca4 706 RF_DIOMAPPING2_MAP_MASK ) |
mluis 0:45c4f0364ca4 707 RF_DIOMAPPING2_DIO4_11 |
mluis 0:45c4f0364ca4 708 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
mluis 0:45c4f0364ca4 709
mluis 0:45c4f0364ca4 710 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
mluis 0:45c4f0364ca4 711
mluis 0:45c4f0364ca4 712 this->settings.FskPacketHandler.PreambleDetected = false;
mluis 0:45c4f0364ca4 713 this->settings.FskPacketHandler.SyncWordDetected = false;
mluis 0:45c4f0364ca4 714 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 715 this->settings.FskPacketHandler.Size = 0;
mluis 0:45c4f0364ca4 716 }
mluis 0:45c4f0364ca4 717 break;
mluis 0:45c4f0364ca4 718 case MODEM_LORA:
mluis 0:45c4f0364ca4 719 {
mluis 0:45c4f0364ca4 720 if( this->settings.LoRa.IqInverted == true )
mluis 0:45c4f0364ca4 721 {
mluis 0:45c4f0364ca4 722 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
mluis 0:45c4f0364ca4 723 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
mluis 0:45c4f0364ca4 724 }
mluis 0:45c4f0364ca4 725 else
mluis 0:45c4f0364ca4 726 {
mluis 0:45c4f0364ca4 727 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 0:45c4f0364ca4 728 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
mluis 0:45c4f0364ca4 729 }
mluis 0:45c4f0364ca4 730
mluis 0:45c4f0364ca4 731 rxContinuous = this->settings.LoRa.RxContinuous;
mluis 0:45c4f0364ca4 732
mluis 0:45c4f0364ca4 733 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 734 {
mluis 0:45c4f0364ca4 735 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 736 //RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 737 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 738 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 739 RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 740 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 741 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 742 RFLR_IRQFLAGS_CADDETECTED );
mluis 0:45c4f0364ca4 743
mluis 0:45c4f0364ca4 744 // DIO0=RxDone, DIO2=FhssChangeChannel
mluis 0:45c4f0364ca4 745 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
mluis 0:45c4f0364ca4 746 }
mluis 0:45c4f0364ca4 747 else
mluis 0:45c4f0364ca4 748 {
mluis 0:45c4f0364ca4 749 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 750 //RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 751 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 752 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 753 RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 754 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 755 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 756 RFLR_IRQFLAGS_CADDETECTED );
mluis 0:45c4f0364ca4 757
mluis 0:45c4f0364ca4 758 // DIO0=RxDone
mluis 0:45c4f0364ca4 759 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
mluis 0:45c4f0364ca4 760 }
mluis 0:45c4f0364ca4 761 Write( REG_LR_FIFORXBASEADDR, 0 );
mluis 0:45c4f0364ca4 762 Write( REG_LR_FIFOADDRPTR, 0 );
mluis 0:45c4f0364ca4 763 }
mluis 0:45c4f0364ca4 764 break;
mluis 0:45c4f0364ca4 765 }
mluis 0:45c4f0364ca4 766
mluis 0:45c4f0364ca4 767 memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
mluis 0:45c4f0364ca4 768
mluis 0:45c4f0364ca4 769 this->settings.State = RF_RX_RUNNING;
mluis 0:45c4f0364ca4 770 if( timeout != 0 )
mluis 0:45c4f0364ca4 771 {
mluis 0:45c4f0364ca4 772 rxTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
mluis 0:45c4f0364ca4 773 }
mluis 0:45c4f0364ca4 774
mluis 0:45c4f0364ca4 775 if( this->settings.Modem == MODEM_FSK )
mluis 0:45c4f0364ca4 776 {
mluis 0:45c4f0364ca4 777 SetOpMode( RF_OPMODE_RECEIVER );
mluis 0:45c4f0364ca4 778
mluis 0:45c4f0364ca4 779 if( rxContinuous == false )
mluis 0:45c4f0364ca4 780 {
mluis 0:45c4f0364ca4 781 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
mluis 0:45c4f0364ca4 782 ( ( Read( REG_SYNCCONFIG ) &
mluis 0:45c4f0364ca4 783 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 0:45c4f0364ca4 784 1.0 ) + 10.0 ) /
mluis 0:45c4f0364ca4 785 ( double )this->settings.Fsk.Datarate ) * 1e6 );
mluis 0:45c4f0364ca4 786 }
mluis 0:45c4f0364ca4 787 }
mluis 0:45c4f0364ca4 788 else
mluis 0:45c4f0364ca4 789 {
mluis 0:45c4f0364ca4 790 if( rxContinuous == true )
mluis 0:45c4f0364ca4 791 {
mluis 0:45c4f0364ca4 792 SetOpMode( RFLR_OPMODE_RECEIVER );
mluis 0:45c4f0364ca4 793 }
mluis 0:45c4f0364ca4 794 else
mluis 0:45c4f0364ca4 795 {
mluis 0:45c4f0364ca4 796 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
mluis 0:45c4f0364ca4 797 }
mluis 0:45c4f0364ca4 798 }
mluis 0:45c4f0364ca4 799 }
mluis 0:45c4f0364ca4 800
mluis 0:45c4f0364ca4 801 void SX1272::Tx( uint32_t timeout )
mluis 0:45c4f0364ca4 802 {
mluis 0:45c4f0364ca4 803
mluis 0:45c4f0364ca4 804 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 805 {
mluis 0:45c4f0364ca4 806 case MODEM_FSK:
mluis 0:45c4f0364ca4 807 {
mluis 0:45c4f0364ca4 808 // DIO0=PacketSent
mluis 0:45c4f0364ca4 809 // DIO1=FifoLevel
mluis 0:45c4f0364ca4 810 // DIO2=FifoFull
mluis 0:45c4f0364ca4 811 // DIO3=FifoEmpty
mluis 0:45c4f0364ca4 812 // DIO4=LowBat
mluis 0:45c4f0364ca4 813 // DIO5=ModeReady
mluis 0:45c4f0364ca4 814 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
mluis 0:45c4f0364ca4 815 RF_DIOMAPPING1_DIO2_MASK ) );
mluis 0:45c4f0364ca4 816
mluis 0:45c4f0364ca4 817 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
mluis 0:45c4f0364ca4 818 RF_DIOMAPPING2_MAP_MASK ) );
mluis 0:45c4f0364ca4 819 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
mluis 0:45c4f0364ca4 820 }
mluis 0:45c4f0364ca4 821 break;
mluis 0:45c4f0364ca4 822 case MODEM_LORA:
mluis 0:45c4f0364ca4 823 {
mluis 0:45c4f0364ca4 824 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 825 {
mluis 0:45c4f0364ca4 826 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 827 RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 828 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 829 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 830 //RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 831 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 832 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 833 RFLR_IRQFLAGS_CADDETECTED );
mluis 0:45c4f0364ca4 834
mluis 0:45c4f0364ca4 835 // DIO0=TxDone, DIO2=FhssChangeChannel
mluis 0:45c4f0364ca4 836 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
mluis 0:45c4f0364ca4 837 }
mluis 0:45c4f0364ca4 838 else
mluis 0:45c4f0364ca4 839 {
mluis 0:45c4f0364ca4 840 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 841 RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 842 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 843 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 844 //RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 845 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 846 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 847 RFLR_IRQFLAGS_CADDETECTED );
mluis 0:45c4f0364ca4 848
mluis 0:45c4f0364ca4 849 // DIO0=TxDone
mluis 0:45c4f0364ca4 850 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
mluis 0:45c4f0364ca4 851 }
mluis 0:45c4f0364ca4 852 }
mluis 0:45c4f0364ca4 853 break;
mluis 0:45c4f0364ca4 854 }
mluis 0:45c4f0364ca4 855
mluis 0:45c4f0364ca4 856 this->settings.State = RF_TX_RUNNING;
mluis 0:45c4f0364ca4 857 txTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
mluis 0:45c4f0364ca4 858 SetOpMode( RF_OPMODE_TRANSMITTER );
mluis 0:45c4f0364ca4 859 }
mluis 0:45c4f0364ca4 860
mluis 0:45c4f0364ca4 861 void SX1272::StartCad( void )
mluis 0:45c4f0364ca4 862 {
mluis 0:45c4f0364ca4 863 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 864 {
mluis 0:45c4f0364ca4 865 case MODEM_FSK:
mluis 0:45c4f0364ca4 866 {
mluis 0:45c4f0364ca4 867
mluis 0:45c4f0364ca4 868 }
mluis 0:45c4f0364ca4 869 break;
mluis 0:45c4f0364ca4 870 case MODEM_LORA:
mluis 0:45c4f0364ca4 871 {
mluis 0:45c4f0364ca4 872 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 873 RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 874 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 875 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 876 RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 877 //RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 878 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
mluis 0:45c4f0364ca4 879 //RFLR_IRQFLAGS_CADDETECTED
mluis 0:45c4f0364ca4 880 );
mluis 0:45c4f0364ca4 881
mluis 0:45c4f0364ca4 882 // DIO3=CADDone
mluis 0:45c4f0364ca4 883 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
mluis 0:45c4f0364ca4 884
mluis 0:45c4f0364ca4 885 this->settings.State = RF_CAD;
mluis 0:45c4f0364ca4 886 SetOpMode( RFLR_OPMODE_CAD );
mluis 0:45c4f0364ca4 887 }
mluis 0:45c4f0364ca4 888 break;
mluis 0:45c4f0364ca4 889 default:
mluis 0:45c4f0364ca4 890 break;
mluis 0:45c4f0364ca4 891 }
mluis 0:45c4f0364ca4 892 }
mluis 0:45c4f0364ca4 893
mluis 0:45c4f0364ca4 894 int16_t SX1272::GetRssi( RadioModems_t modem )
mluis 0:45c4f0364ca4 895 {
mluis 0:45c4f0364ca4 896 int16_t rssi = 0;
mluis 0:45c4f0364ca4 897
mluis 0:45c4f0364ca4 898 switch( modem )
mluis 0:45c4f0364ca4 899 {
mluis 0:45c4f0364ca4 900 case MODEM_FSK:
mluis 0:45c4f0364ca4 901 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
mluis 0:45c4f0364ca4 902 break;
mluis 0:45c4f0364ca4 903 case MODEM_LORA:
mluis 0:45c4f0364ca4 904 rssi = RSSI_OFFSET + Read( REG_LR_RSSIVALUE );
mluis 0:45c4f0364ca4 905 break;
mluis 0:45c4f0364ca4 906 default:
mluis 0:45c4f0364ca4 907 rssi = -1;
mluis 0:45c4f0364ca4 908 break;
mluis 0:45c4f0364ca4 909 }
mluis 0:45c4f0364ca4 910 return rssi;
mluis 0:45c4f0364ca4 911 }
mluis 0:45c4f0364ca4 912
mluis 0:45c4f0364ca4 913 void SX1272::SetOpMode( uint8_t opMode )
mluis 0:45c4f0364ca4 914 {
mluis 0:45c4f0364ca4 915 if( opMode != currentOpMode )
mluis 0:45c4f0364ca4 916 {
mluis 0:45c4f0364ca4 917 currentOpMode = opMode;
mluis 0:45c4f0364ca4 918 if( opMode == RF_OPMODE_SLEEP )
mluis 0:45c4f0364ca4 919 {
mluis 0:45c4f0364ca4 920 SetAntSwLowPower( true );
mluis 0:45c4f0364ca4 921 }
mluis 0:45c4f0364ca4 922 else
mluis 0:45c4f0364ca4 923 {
mluis 0:45c4f0364ca4 924 SetAntSwLowPower( false );
mluis 0:45c4f0364ca4 925 if( opMode == RF_OPMODE_TRANSMITTER )
mluis 0:45c4f0364ca4 926 {
mluis 0:45c4f0364ca4 927 SetAntSw( 1 );
mluis 0:45c4f0364ca4 928 }
mluis 0:45c4f0364ca4 929 else
mluis 0:45c4f0364ca4 930 {
mluis 0:45c4f0364ca4 931 SetAntSw( 0 );
mluis 0:45c4f0364ca4 932 }
mluis 0:45c4f0364ca4 933 }
mluis 0:45c4f0364ca4 934 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
mluis 0:45c4f0364ca4 935 }
mluis 0:45c4f0364ca4 936 }
mluis 0:45c4f0364ca4 937
mluis 0:45c4f0364ca4 938 void SX1272::SetModem( RadioModems_t modem )
mluis 0:45c4f0364ca4 939 {
mluis 0:45c4f0364ca4 940 if( this->settings.Modem == modem )
mluis 0:45c4f0364ca4 941 {
mluis 0:45c4f0364ca4 942 return;
mluis 0:45c4f0364ca4 943 }
mluis 0:45c4f0364ca4 944
mluis 0:45c4f0364ca4 945 this->settings.Modem = modem;
mluis 0:45c4f0364ca4 946 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 947 {
mluis 0:45c4f0364ca4 948 default:
mluis 0:45c4f0364ca4 949 case MODEM_FSK:
mluis 0:45c4f0364ca4 950 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 951 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
mluis 0:45c4f0364ca4 952
mluis 0:45c4f0364ca4 953 Write( REG_DIOMAPPING1, 0x00 );
mluis 0:45c4f0364ca4 954 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
mluis 0:45c4f0364ca4 955 break;
mluis 0:45c4f0364ca4 956 case MODEM_LORA:
mluis 0:45c4f0364ca4 957 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 958 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
mluis 0:45c4f0364ca4 959
mluis 0:45c4f0364ca4 960 Write( REG_DIOMAPPING1, 0x00 );
mluis 0:45c4f0364ca4 961 Write( REG_DIOMAPPING2, 0x00 );
mluis 0:45c4f0364ca4 962 break;
mluis 0:45c4f0364ca4 963 }
mluis 0:45c4f0364ca4 964 }
mluis 0:45c4f0364ca4 965
mluis 0:45c4f0364ca4 966 void SX1272::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
mluis 0:45c4f0364ca4 967 {
mluis 0:45c4f0364ca4 968 this->SetModem( modem );
mluis 0:45c4f0364ca4 969
mluis 0:45c4f0364ca4 970 switch( modem )
mluis 0:45c4f0364ca4 971 {
mluis 0:45c4f0364ca4 972 case MODEM_FSK:
mluis 0:45c4f0364ca4 973 if( this->settings.Fsk.FixLen == false )
mluis 0:45c4f0364ca4 974 {
mluis 0:45c4f0364ca4 975 this->Write( REG_PAYLOADLENGTH, max );
mluis 0:45c4f0364ca4 976 }
mluis 0:45c4f0364ca4 977 break;
mluis 0:45c4f0364ca4 978 case MODEM_LORA:
mluis 0:45c4f0364ca4 979 this->Write( REG_LR_PAYLOADMAXLENGTH, max );
mluis 0:45c4f0364ca4 980 break;
mluis 0:45c4f0364ca4 981 }
mluis 0:45c4f0364ca4 982 }
mluis 0:45c4f0364ca4 983
mluis 0:45c4f0364ca4 984 void SX1272::OnTimeoutIrq( void )
mluis 0:45c4f0364ca4 985 {
mluis 0:45c4f0364ca4 986 switch( this->settings.State )
mluis 0:45c4f0364ca4 987 {
mluis 0:45c4f0364ca4 988 case RF_RX_RUNNING:
mluis 0:45c4f0364ca4 989 if( this->settings.Modem == MODEM_FSK )
mluis 0:45c4f0364ca4 990 {
mluis 0:45c4f0364ca4 991 this->settings.FskPacketHandler.PreambleDetected = false;
mluis 0:45c4f0364ca4 992 this->settings.FskPacketHandler.SyncWordDetected = false;
mluis 0:45c4f0364ca4 993 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 994 this->settings.FskPacketHandler.Size = 0;
mluis 0:45c4f0364ca4 995
mluis 0:45c4f0364ca4 996 // Clear Irqs
mluis 0:45c4f0364ca4 997 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
mluis 0:45c4f0364ca4 998 RF_IRQFLAGS1_PREAMBLEDETECT |
mluis 0:45c4f0364ca4 999 RF_IRQFLAGS1_SYNCADDRESSMATCH );
mluis 0:45c4f0364ca4 1000 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
mluis 0:45c4f0364ca4 1001
mluis 0:45c4f0364ca4 1002 if( this->settings.Fsk.RxContinuous == true )
mluis 0:45c4f0364ca4 1003 {
mluis 0:45c4f0364ca4 1004 // Continuous mode restart Rx chain
mluis 0:45c4f0364ca4 1005 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
mluis 0:45c4f0364ca4 1006 }
mluis 0:45c4f0364ca4 1007 else
mluis 0:45c4f0364ca4 1008 {
mluis 0:45c4f0364ca4 1009 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1010 rxTimeoutSyncWord.detach( );
mluis 0:45c4f0364ca4 1011 }
mluis 0:45c4f0364ca4 1012 }
mluis 0:45c4f0364ca4 1013 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
mluis 0:45c4f0364ca4 1014 {
mluis 0:45c4f0364ca4 1015 this->RadioEvents->RxTimeout( );
mluis 0:45c4f0364ca4 1016 }
mluis 0:45c4f0364ca4 1017 break;
mluis 0:45c4f0364ca4 1018 case RF_TX_RUNNING:
mluis 0:45c4f0364ca4 1019 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1020 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) )
mluis 0:45c4f0364ca4 1021 {
mluis 0:45c4f0364ca4 1022 this->RadioEvents->TxTimeout( );
mluis 0:45c4f0364ca4 1023 }
mluis 0:45c4f0364ca4 1024 break;
mluis 0:45c4f0364ca4 1025 default:
mluis 0:45c4f0364ca4 1026 break;
mluis 0:45c4f0364ca4 1027 }
mluis 0:45c4f0364ca4 1028 }
mluis 0:45c4f0364ca4 1029
mluis 0:45c4f0364ca4 1030 void SX1272::OnDio0Irq( void )
mluis 0:45c4f0364ca4 1031 {
mluis 0:45c4f0364ca4 1032 volatile uint8_t irqFlags = 0;
mluis 0:45c4f0364ca4 1033
mluis 0:45c4f0364ca4 1034 switch( this->settings.State )
mluis 0:45c4f0364ca4 1035 {
mluis 0:45c4f0364ca4 1036 case RF_RX_RUNNING:
mluis 0:45c4f0364ca4 1037 //TimerStop( &RxTimeoutTimer );
mluis 0:45c4f0364ca4 1038 // RxDone interrupt
mluis 0:45c4f0364ca4 1039 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1040 {
mluis 0:45c4f0364ca4 1041 case MODEM_FSK:
mluis 0:45c4f0364ca4 1042 if( this->settings.Fsk.CrcOn == true )
mluis 0:45c4f0364ca4 1043 {
mluis 0:45c4f0364ca4 1044 irqFlags = Read( REG_IRQFLAGS2 );
mluis 0:45c4f0364ca4 1045 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
mluis 0:45c4f0364ca4 1046 {
mluis 0:45c4f0364ca4 1047 // Clear Irqs
mluis 0:45c4f0364ca4 1048 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
mluis 0:45c4f0364ca4 1049 RF_IRQFLAGS1_PREAMBLEDETECT |
mluis 0:45c4f0364ca4 1050 RF_IRQFLAGS1_SYNCADDRESSMATCH );
mluis 0:45c4f0364ca4 1051 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
mluis 0:45c4f0364ca4 1052
mluis 0:45c4f0364ca4 1053 if( this->settings.Fsk.RxContinuous == false )
mluis 0:45c4f0364ca4 1054 {
mluis 0:45c4f0364ca4 1055 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1056 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
mluis 0:45c4f0364ca4 1057 ( ( Read( REG_SYNCCONFIG ) &
mluis 0:45c4f0364ca4 1058 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 0:45c4f0364ca4 1059 1.0 ) + 10.0 ) /
mluis 0:45c4f0364ca4 1060 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
mluis 0:45c4f0364ca4 1061 }
mluis 0:45c4f0364ca4 1062 else
mluis 0:45c4f0364ca4 1063 {
mluis 0:45c4f0364ca4 1064 // Continuous mode restart Rx chain
mluis 0:45c4f0364ca4 1065 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
mluis 0:45c4f0364ca4 1066 }
mluis 0:45c4f0364ca4 1067 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1068
mluis 0:45c4f0364ca4 1069 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
mluis 0:45c4f0364ca4 1070 {
mluis 0:45c4f0364ca4 1071 this->RadioEvents->RxError( );
mluis 0:45c4f0364ca4 1072 }
mluis 0:45c4f0364ca4 1073 this->settings.FskPacketHandler.PreambleDetected = false;
mluis 0:45c4f0364ca4 1074 this->settings.FskPacketHandler.SyncWordDetected = false;
mluis 0:45c4f0364ca4 1075 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 1076 this->settings.FskPacketHandler.Size = 0;
mluis 0:45c4f0364ca4 1077 break;
mluis 0:45c4f0364ca4 1078 }
mluis 0:45c4f0364ca4 1079 }
mluis 0:45c4f0364ca4 1080
mluis 0:45c4f0364ca4 1081 // Read received packet size
mluis 0:45c4f0364ca4 1082 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
mluis 0:45c4f0364ca4 1083 {
mluis 0:45c4f0364ca4 1084 if( this->settings.Fsk.FixLen == false )
mluis 0:45c4f0364ca4 1085 {
mluis 0:45c4f0364ca4 1086 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
mluis 0:45c4f0364ca4 1087 }
mluis 0:45c4f0364ca4 1088 else
mluis 0:45c4f0364ca4 1089 {
mluis 0:45c4f0364ca4 1090 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
mluis 0:45c4f0364ca4 1091 }
mluis 0:45c4f0364ca4 1092 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1093 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1094 }
mluis 0:45c4f0364ca4 1095 else
mluis 0:45c4f0364ca4 1096 {
mluis 0:45c4f0364ca4 1097 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1098 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1099 }
mluis 0:45c4f0364ca4 1100
mluis 0:45c4f0364ca4 1101 if( this->settings.Fsk.RxContinuous == false )
mluis 0:45c4f0364ca4 1102 {
mluis 0:45c4f0364ca4 1103 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1104 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
mluis 0:45c4f0364ca4 1105 ( ( Read( REG_SYNCCONFIG ) &
mluis 0:45c4f0364ca4 1106 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 0:45c4f0364ca4 1107 1.0 ) + 10.0 ) /
mluis 0:45c4f0364ca4 1108 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
mluis 0:45c4f0364ca4 1109 }
mluis 0:45c4f0364ca4 1110 else
mluis 0:45c4f0364ca4 1111 {
mluis 0:45c4f0364ca4 1112 // Continuous mode restart Rx chain
mluis 0:45c4f0364ca4 1113 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
mluis 0:45c4f0364ca4 1114 }
mluis 0:45c4f0364ca4 1115 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1116
mluis 0:45c4f0364ca4 1117 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
mluis 0:45c4f0364ca4 1118 {
mluis 0:45c4f0364ca4 1119 this->RadioEvents->RxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
mluis 0:45c4f0364ca4 1120 }
mluis 0:45c4f0364ca4 1121 this->settings.FskPacketHandler.PreambleDetected = false;
mluis 0:45c4f0364ca4 1122 this->settings.FskPacketHandler.SyncWordDetected = false;
mluis 0:45c4f0364ca4 1123 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 1124 this->settings.FskPacketHandler.Size = 0;
mluis 0:45c4f0364ca4 1125 break;
mluis 0:45c4f0364ca4 1126 case MODEM_LORA:
mluis 0:45c4f0364ca4 1127 {
mluis 0:45c4f0364ca4 1128 int8_t snr = 0;
mluis 0:45c4f0364ca4 1129
mluis 0:45c4f0364ca4 1130 // Clear Irq
mluis 0:45c4f0364ca4 1131 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
mluis 0:45c4f0364ca4 1132
mluis 0:45c4f0364ca4 1133 irqFlags = Read( REG_LR_IRQFLAGS );
mluis 0:45c4f0364ca4 1134 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
mluis 0:45c4f0364ca4 1135 {
mluis 0:45c4f0364ca4 1136 // Clear Irq
mluis 0:45c4f0364ca4 1137 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
mluis 0:45c4f0364ca4 1138
mluis 0:45c4f0364ca4 1139 if( this->settings.LoRa.RxContinuous == false )
mluis 0:45c4f0364ca4 1140 {
mluis 0:45c4f0364ca4 1141 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1142 }
mluis 0:45c4f0364ca4 1143 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1144
mluis 0:45c4f0364ca4 1145 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
mluis 0:45c4f0364ca4 1146 {
mluis 0:45c4f0364ca4 1147 this->RadioEvents->RxError( );
mluis 0:45c4f0364ca4 1148 }
mluis 0:45c4f0364ca4 1149 break;
mluis 0:45c4f0364ca4 1150 }
mluis 0:45c4f0364ca4 1151
mluis 0:45c4f0364ca4 1152 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
mluis 0:45c4f0364ca4 1153 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
mluis 0:45c4f0364ca4 1154 {
mluis 0:45c4f0364ca4 1155 // Invert and divide by 4
mluis 0:45c4f0364ca4 1156 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
mluis 0:45c4f0364ca4 1157 snr = -snr;
mluis 0:45c4f0364ca4 1158 }
mluis 0:45c4f0364ca4 1159 else
mluis 0:45c4f0364ca4 1160 {
mluis 0:45c4f0364ca4 1161 // Divide by 4
mluis 0:45c4f0364ca4 1162 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
mluis 0:45c4f0364ca4 1163 }
mluis 0:45c4f0364ca4 1164
mluis 0:45c4f0364ca4 1165 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
mluis 0:45c4f0364ca4 1166 if( snr < 0 )
mluis 0:45c4f0364ca4 1167 {
mluis 0:45c4f0364ca4 1168 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 ) +
mluis 0:45c4f0364ca4 1169 snr;
mluis 0:45c4f0364ca4 1170 }
mluis 0:45c4f0364ca4 1171 else
mluis 0:45c4f0364ca4 1172 {
mluis 0:45c4f0364ca4 1173 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 );
mluis 0:45c4f0364ca4 1174 }
mluis 0:45c4f0364ca4 1175
mluis 0:45c4f0364ca4 1176 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
mluis 0:45c4f0364ca4 1177 ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size );
mluis 0:45c4f0364ca4 1178
mluis 0:45c4f0364ca4 1179 if( this->settings.LoRa.RxContinuous == false )
mluis 0:45c4f0364ca4 1180 {
mluis 0:45c4f0364ca4 1181 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1182 }
mluis 0:45c4f0364ca4 1183 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1184
mluis 0:45c4f0364ca4 1185 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
mluis 0:45c4f0364ca4 1186 {
mluis 0:45c4f0364ca4 1187 this->RadioEvents->RxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
mluis 0:45c4f0364ca4 1188 }
mluis 0:45c4f0364ca4 1189 }
mluis 0:45c4f0364ca4 1190 break;
mluis 0:45c4f0364ca4 1191 default:
mluis 0:45c4f0364ca4 1192 break;
mluis 0:45c4f0364ca4 1193 }
mluis 0:45c4f0364ca4 1194 break;
mluis 0:45c4f0364ca4 1195 case RF_TX_RUNNING:
mluis 0:45c4f0364ca4 1196 txTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1197 // TxDone interrupt
mluis 0:45c4f0364ca4 1198 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1199 {
mluis 0:45c4f0364ca4 1200 case MODEM_LORA:
mluis 0:45c4f0364ca4 1201 // Clear Irq
mluis 0:45c4f0364ca4 1202 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
mluis 0:45c4f0364ca4 1203 // Intentional fall through
mluis 0:45c4f0364ca4 1204 case MODEM_FSK:
mluis 0:45c4f0364ca4 1205 default:
mluis 0:45c4f0364ca4 1206 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1207 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) )
mluis 0:45c4f0364ca4 1208 {
mluis 0:45c4f0364ca4 1209 this->RadioEvents->TxDone( );
mluis 0:45c4f0364ca4 1210 }
mluis 0:45c4f0364ca4 1211 break;
mluis 0:45c4f0364ca4 1212 }
mluis 0:45c4f0364ca4 1213 break;
mluis 0:45c4f0364ca4 1214 default:
mluis 0:45c4f0364ca4 1215 break;
mluis 0:45c4f0364ca4 1216 }
mluis 0:45c4f0364ca4 1217 }
mluis 0:45c4f0364ca4 1218
mluis 0:45c4f0364ca4 1219 void SX1272::OnDio1Irq( void )
mluis 0:45c4f0364ca4 1220 {
mluis 0:45c4f0364ca4 1221 switch( this->settings.State )
mluis 0:45c4f0364ca4 1222 {
mluis 0:45c4f0364ca4 1223 case RF_RX_RUNNING:
mluis 0:45c4f0364ca4 1224 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1225 {
mluis 0:45c4f0364ca4 1226 case MODEM_FSK:
mluis 0:45c4f0364ca4 1227 // FifoLevel interrupt
mluis 0:45c4f0364ca4 1228 // Read received packet size
mluis 0:45c4f0364ca4 1229 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
mluis 0:45c4f0364ca4 1230 {
mluis 0:45c4f0364ca4 1231 if( this->settings.Fsk.FixLen == false )
mluis 0:45c4f0364ca4 1232 {
mluis 0:45c4f0364ca4 1233 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
mluis 0:45c4f0364ca4 1234 }
mluis 0:45c4f0364ca4 1235 else
mluis 0:45c4f0364ca4 1236 {
mluis 0:45c4f0364ca4 1237 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
mluis 0:45c4f0364ca4 1238 }
mluis 0:45c4f0364ca4 1239 }
mluis 0:45c4f0364ca4 1240
mluis 0:45c4f0364ca4 1241 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
mluis 0:45c4f0364ca4 1242 {
mluis 0:45c4f0364ca4 1243 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
mluis 0:45c4f0364ca4 1244 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
mluis 0:45c4f0364ca4 1245 }
mluis 0:45c4f0364ca4 1246 else
mluis 0:45c4f0364ca4 1247 {
mluis 0:45c4f0364ca4 1248 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1249 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1250 }
mluis 0:45c4f0364ca4 1251 break;
mluis 0:45c4f0364ca4 1252 case MODEM_LORA:
mluis 0:45c4f0364ca4 1253 // Sync time out
mluis 0:45c4f0364ca4 1254 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1255 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1256 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
mluis 0:45c4f0364ca4 1257 {
mluis 0:45c4f0364ca4 1258 this->RadioEvents->RxTimeout( );
mluis 0:45c4f0364ca4 1259 }
mluis 0:45c4f0364ca4 1260 break;
mluis 0:45c4f0364ca4 1261 default:
mluis 0:45c4f0364ca4 1262 break;
mluis 0:45c4f0364ca4 1263 }
mluis 0:45c4f0364ca4 1264 break;
mluis 0:45c4f0364ca4 1265 case RF_TX_RUNNING:
mluis 0:45c4f0364ca4 1266 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1267 {
mluis 0:45c4f0364ca4 1268 case MODEM_FSK:
mluis 0:45c4f0364ca4 1269 // FifoLevel interrupt
mluis 0:45c4f0364ca4 1270 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
mluis 0:45c4f0364ca4 1271 {
mluis 0:45c4f0364ca4 1272 WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
mluis 0:45c4f0364ca4 1273 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
mluis 0:45c4f0364ca4 1274 }
mluis 0:45c4f0364ca4 1275 else
mluis 0:45c4f0364ca4 1276 {
mluis 0:45c4f0364ca4 1277 // Write the last chunk of data
mluis 0:45c4f0364ca4 1278 WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1279 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
mluis 0:45c4f0364ca4 1280 }
mluis 0:45c4f0364ca4 1281 break;
mluis 0:45c4f0364ca4 1282 case MODEM_LORA:
mluis 0:45c4f0364ca4 1283 break;
mluis 0:45c4f0364ca4 1284 default:
mluis 0:45c4f0364ca4 1285 break;
mluis 0:45c4f0364ca4 1286 }
mluis 0:45c4f0364ca4 1287 break;
mluis 0:45c4f0364ca4 1288 default:
mluis 0:45c4f0364ca4 1289 break;
mluis 0:45c4f0364ca4 1290 }
mluis 0:45c4f0364ca4 1291 }
mluis 0:45c4f0364ca4 1292
mluis 0:45c4f0364ca4 1293 void SX1272::OnDio2Irq( void )
mluis 0:45c4f0364ca4 1294 {
mluis 0:45c4f0364ca4 1295 switch( this->settings.State )
mluis 0:45c4f0364ca4 1296 {
mluis 0:45c4f0364ca4 1297 case RF_RX_RUNNING:
mluis 0:45c4f0364ca4 1298 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1299 {
mluis 0:45c4f0364ca4 1300 case MODEM_FSK:
mluis 0:45c4f0364ca4 1301 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
mluis 0:45c4f0364ca4 1302 {
mluis 0:45c4f0364ca4 1303 rxTimeoutSyncWord.detach( );
mluis 0:45c4f0364ca4 1304
mluis 0:45c4f0364ca4 1305 this->settings.FskPacketHandler.SyncWordDetected = true;
mluis 0:45c4f0364ca4 1306
mluis 0:45c4f0364ca4 1307 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
mluis 0:45c4f0364ca4 1308
mluis 0:45c4f0364ca4 1309 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
mluis 0:45c4f0364ca4 1310 ( uint16_t )Read( REG_AFCLSB ) ) *
mluis 0:45c4f0364ca4 1311 ( double )FREQ_STEP;
mluis 0:45c4f0364ca4 1312 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
mluis 0:45c4f0364ca4 1313 }
mluis 0:45c4f0364ca4 1314 break;
mluis 0:45c4f0364ca4 1315 case MODEM_LORA:
mluis 0:45c4f0364ca4 1316 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 1317 {
mluis 0:45c4f0364ca4 1318 // Clear Irq
mluis 0:45c4f0364ca4 1319 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
mluis 0:45c4f0364ca4 1320
mluis 0:45c4f0364ca4 1321 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
mluis 0:45c4f0364ca4 1322 {
mluis 0:45c4f0364ca4 1323 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 0:45c4f0364ca4 1324 }
mluis 0:45c4f0364ca4 1325 }
mluis 0:45c4f0364ca4 1326 break;
mluis 0:45c4f0364ca4 1327 default:
mluis 0:45c4f0364ca4 1328 break;
mluis 0:45c4f0364ca4 1329 }
mluis 0:45c4f0364ca4 1330 break;
mluis 0:45c4f0364ca4 1331 case RF_TX_RUNNING:
mluis 0:45c4f0364ca4 1332 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1333 {
mluis 0:45c4f0364ca4 1334 case MODEM_FSK:
mluis 0:45c4f0364ca4 1335 break;
mluis 0:45c4f0364ca4 1336 case MODEM_LORA:
mluis 0:45c4f0364ca4 1337 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 1338 {
mluis 0:45c4f0364ca4 1339 // Clear Irq
mluis 0:45c4f0364ca4 1340 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
mluis 0:45c4f0364ca4 1341
mluis 0:45c4f0364ca4 1342 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
mluis 0:45c4f0364ca4 1343 {
mluis 0:45c4f0364ca4 1344 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 0:45c4f0364ca4 1345 }
mluis 0:45c4f0364ca4 1346 }
mluis 0:45c4f0364ca4 1347 break;
mluis 0:45c4f0364ca4 1348 default:
mluis 0:45c4f0364ca4 1349 break;
mluis 0:45c4f0364ca4 1350 }
mluis 0:45c4f0364ca4 1351 break;
mluis 0:45c4f0364ca4 1352 default:
mluis 0:45c4f0364ca4 1353 break;
mluis 0:45c4f0364ca4 1354 }
mluis 0:45c4f0364ca4 1355 }
mluis 0:45c4f0364ca4 1356
mluis 0:45c4f0364ca4 1357 void SX1272::OnDio3Irq( void )
mluis 0:45c4f0364ca4 1358 {
mluis 0:45c4f0364ca4 1359 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1360 {
mluis 0:45c4f0364ca4 1361 case MODEM_FSK:
mluis 0:45c4f0364ca4 1362 break;
mluis 0:45c4f0364ca4 1363 case MODEM_LORA:
mluis 0:45c4f0364ca4 1364 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
mluis 0:45c4f0364ca4 1365 {
mluis 0:45c4f0364ca4 1366 // Clear Irq
mluis 0:45c4f0364ca4 1367 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
mluis 0:45c4f0364ca4 1368 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
mluis 0:45c4f0364ca4 1369 {
mluis 0:45c4f0364ca4 1370 this->RadioEvents->CadDone( true );
mluis 0:45c4f0364ca4 1371 }
mluis 0:45c4f0364ca4 1372 }
mluis 0:45c4f0364ca4 1373 else
mluis 0:45c4f0364ca4 1374 {
mluis 0:45c4f0364ca4 1375 // Clear Irq
mluis 0:45c4f0364ca4 1376 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
mluis 0:45c4f0364ca4 1377 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
mluis 0:45c4f0364ca4 1378 {
mluis 0:45c4f0364ca4 1379 this->RadioEvents->CadDone( false );
mluis 0:45c4f0364ca4 1380 }
mluis 0:45c4f0364ca4 1381 }
mluis 0:45c4f0364ca4 1382 break;
mluis 0:45c4f0364ca4 1383 default:
mluis 0:45c4f0364ca4 1384 break;
mluis 0:45c4f0364ca4 1385 }
mluis 0:45c4f0364ca4 1386 }
mluis 0:45c4f0364ca4 1387
mluis 0:45c4f0364ca4 1388 void SX1272::OnDio4Irq( void )
mluis 0:45c4f0364ca4 1389 {
mluis 0:45c4f0364ca4 1390 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1391 {
mluis 0:45c4f0364ca4 1392 case MODEM_FSK:
mluis 0:45c4f0364ca4 1393 {
mluis 0:45c4f0364ca4 1394 if( this->settings.FskPacketHandler.PreambleDetected == false )
mluis 0:45c4f0364ca4 1395 {
mluis 0:45c4f0364ca4 1396 this->settings.FskPacketHandler.PreambleDetected = true;
mluis 0:45c4f0364ca4 1397 }
mluis 0:45c4f0364ca4 1398 }
mluis 0:45c4f0364ca4 1399 break;
mluis 0:45c4f0364ca4 1400 case MODEM_LORA:
mluis 0:45c4f0364ca4 1401 break;
mluis 0:45c4f0364ca4 1402 default:
mluis 0:45c4f0364ca4 1403 break;
mluis 0:45c4f0364ca4 1404 }
mluis 0:45c4f0364ca4 1405 }
mluis 0:45c4f0364ca4 1406
mluis 0:45c4f0364ca4 1407 void SX1272::OnDio5Irq( void )
mluis 0:45c4f0364ca4 1408 {
mluis 0:45c4f0364ca4 1409 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1410 {
mluis 0:45c4f0364ca4 1411 case MODEM_FSK:
mluis 0:45c4f0364ca4 1412 break;
mluis 0:45c4f0364ca4 1413 case MODEM_LORA:
mluis 0:45c4f0364ca4 1414 break;
mluis 0:45c4f0364ca4 1415 default:
mluis 0:45c4f0364ca4 1416 break;
mluis 0:45c4f0364ca4 1417 }
mluis 0:45c4f0364ca4 1418 }